Strategic pause for quantum state leakage mitigation

Abstract

Systems and techniques are provided that facilitate strategic pauses of quantum state leakage mitigation. In different embodiments, a system can include a detection component that can detect quantum state leakage associated with one or more qubits. In various aspects, the system can further include a pause component that can generate a temporal pause prior to execution of a quantum circuit on the one or more qubits in response to detecting the quantum state leakage. In different embodiments, the pause component can generate a pause time after execution of a previous quantum circuit on the one or more qubits, where the quantum state leakage occurred during execution of the previous quantum circuit. In some cases, the quantum state leakage can decay during the temporal pause.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to quantum state leakage, and more specifically to strategic pausing for quantum state leakage mitigation. SUMMARY

[0002] The following presents a summary to provide a basic understanding of one or more embodiments of the application. This summary is not intended to identify key or critical elements, or delineate any scope of certain embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, apparatuses, systems, computer-implemented methods, devices, and / or computer program products that can facilitate strategic pausing for quantum state leakage mitigation are described.

[0003] According to one or more embodiments, a system is provided. The system can include a memory that can store computer executable components. The system can further include a processor that can be operatively coupled to the memory and that can execute the computer executable components stored in the memory. In various embodiments, the computer executable components can include a detection component that can detect quantum state leakage associated with one or more qubits. In various aspects, the computer executable components can further include a pausing component that can generate a temporal pause prior to execution of a quantum circuit on the one or more qubits in response to detecting the quantum state leakage. In different embodiments, the pausing component can generate a temporal pause after execution of a previous quantum circuit on the one or more qubits, wherein the quantum state leakage occurred during execution of the previous quantum circuit. In some cases, the quantum state leakage can decay during the temporal pause.

[0004] According to one or more embodiments, the system described above can be implemented as a computer-implemented method and / or a computer program product. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 A block diagram illustrating an example, non-limiting system that facilitates strategic pausing for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown.

[0006] Figure 2 A block diagram illustrating an example, non-limiting system that includes quantum state leakage that facilitates strategic pausing for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown.

[0007] Figure 3A block diagram of an example, non-limiting qubit is shown illustrating various possible quantum states in accordance with one or more embodiments described herein.

[0008] Figure 4 A block diagram of an example, non-limiting system including a strategic time pause that facilitates strategic pauses for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown.

[0009] Figure 5 A block diagram of an example, non-limiting timeline illustrating strategic pauses for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown.

[0010] Figure 6 A block diagram of an example, non-limiting system including a decay lookup table that facilitates strategic pauses for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown.

[0011] Figure 7 A block diagram of an example, non-limiting system including a next quantum circuit that facilitates strategic pauses for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown.

[0012] Figure 8 A block diagram of an example, non-limiting system including a strategic pause quantum state measurement that facilitates strategic pauses for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown.

[0013] Figures 9 to 11 A flow diagram of an example, non-limiting computer-implemented method that facilitates strategic pauses for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown.

[0014] Figure 12 A block diagram of an example, non-limiting operating environment in which one or more embodiments described herein can be facilitated is shown.

[0015] Figure 13 An example, non-limiting cloud computing environment in accordance with one or more embodiments described herein is shown.

[0016] Figure 14 An example, non-limiting abstraction model layer in accordance with one or more embodiments described herein is shown. DETAILED DESCRIPTION

[0017] The following detailed description is merely illustrative and is not intended to limit or restrict the embodiments and / or the application or uses of such embodiments in any way. Furthermore, this Detailed Description does not intend to limit or restrict the scope or application of any preceding or following claims in any way.

[0018] One or more embodiments will now be described, by way of example, with reference to the accompanying drawings, in which like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding. It is apparent, however, that one or more embodiments can be practiced without these specific details.

[0019] In a quantum computer, information is carried and / or represented via qubits (e.g., quantum binary digits). While a classical bit can be in one of two basis states (e.g., the state of the bit can be 0 or 1), a qubit can be in a superposition of multiple basis states (e.g., the state of the qubit can be represented as a |0> + β |1>, where |0> represents the ground state of the qubit, where |1> represents a first excited state of the qubit, and where a and β represent complex probability amplitudes). Qubits can be implemented on atomic scales (e.g., photon polarizations can exhibit quantum behavior, electron spins can exhibit quantum behavior, nuclear spins can exhibit quantum behavior, quantum dots can exhibit quantum behavior) and / or on macroscopic scales (e.g., Josephson junctions can exhibit quantum behavior).

[0020] During quantum computation and / or quantum information processing, one or more quantum circuits can be executed on a set of qubits (e.g., a set of qubits can include one or more qubits). A quantum circuit can be a string of one or more quantum gates that operate on and / or transform the state of the set of qubits. Specifically, the set of qubits can be initialized with a known state, a quantum circuit can be executed on the set of qubits, thereby transforming their state, and the transformed state of the set of qubits can be measured by any suitable quantum readout technique. The transformed state of the set of qubits can then be reset (e.g., reinitialized) before another quantum circuit is executed on the set of qubits. To increase the rate of execution of these quantum circuits and, thus, the rate of sampling of these outputs, it can be desirable to execute two or more quantum circuits in close temporal proximity on the set of qubits; i.e., to increase the repetition rate of the quantum circuits. To facilitate this increased repetition rate, quantum state reset can be performed, e.g., via microwave sideband techniques and / or via measurement and feedforward techniques.

[0021] In general, in quantum computing and / or quantum information processing, a qubit can be assumed to have two basis states: a ground state and a first excited state. However, in reality, a qubit can sometimes have more than two basis states: a ground state, a first excited state, and one or more higher-order excited states (e.g., a second excited state, a third excited state, an mth excited state for any suitable integer m > 1). In such cases, the ground state and the first excited state of the qubit can be considered as computational basis states (e.g., states used to perform quantum computations), while the higher-order excited states can be considered as leakage states (e.g., states not used to perform quantum computations). That is, quantum state leakage can be said to occur when a qubit is in a state other than the ground state or the first excited state. Although the disclosure herein primarily discusses embodiments in which the computational basis states include only the ground state and the first excited state and the leakage states include excited states of higher order than the first excited state, such embodiments are non-limiting examples. In other various embodiments, the computational basis states can include any suitable number of states (e.g., the ground state, the first excited state, the second excited state, up to a pth excited state for any suitable positive integer p), while the leakage states can include the remaining possible states of the qubit (e.g., a (p+1)th excited state, a (p+2)th excited state, up to an mth excited state, where m > p, and where m represents the total number of possible states of the qubit). Note that quantum state leakage is different from physical charge leakage (e.g., quantum state leakage involves the state of a qubit; it does not involve the permeation of charge and / or current beyond some physical barrier used in the physical structure of the qubit).

[0022] During execution of a quantum circuit and / or quantum readout, quantum state leakage can occur (e.g., a qubit can become leaked). When quantum state leakage occurs, it can corrupt the execution of subsequent quantum circuits, which can be undesirable. In particular, when quantum state leakage occurs, reset techniques (e.g., such as microwave sidebands and / or measurement and feedforward) can not fully reinitialize the states of a set of qubits, which can cause subsequent quantum circuits to be inaccurately and / or inappropriately executed on the set of qubits. Such issues can become more severe at high repetition rates; in particular, as the repetition rate increases, quantum state leakage is more likely to negatively impact subsequent quantum circuits, resulting in a decrease in fidelity. Thus, systems and / or techniques that can ameliorate the technical problems of quantum state leakage can be desirable.

[0023] Some systems and / or techniques attempt to actively prevent and / or mitigate the formation of quantum state leakage by applying auxiliary electronic pulses to a set of qubits before, during, and / or after the execution of a quantum circuit and / or before, during, and / or after the measurement of the state of the set of qubits. However, such pulses increase the overhead cost, require frequent calibration to ensure proper operation, and inject additional noise that can negatively impact the coherence and / or fidelity of the set of qubits. In other words, systems and / or techniques that utilize pulses to actively prevent and / or mitigate quantum state leakage introduce a number of drawbacks on their own.

[0024] Various embodiments of the present invention can address one or more of these technical problems. In particular, various embodiments of the present invention can provide systems and / or techniques that can facilitate strategic pauses to mitigate quantum state leakage. In other words, various embodiments of the present invention can be viewed as a quantum computing tool (e.g., computer-implemented software) that can facilitate high repetition rates of quantum circuits on a set of qubits while also helping to prevent quantum state leakage in the set of qubits from disrupting the subsequent execution of the quantum circuit. In different aspects, such a quantum computing tool can measure the state of the set of qubits via any suitable quantum readout technique to detect quantum state leakage related to the set of qubits. If the quantum computing tool detects quantum state leakage (e.g., if the quantum computing tool determines that at least one qubit in the set of qubits is in a state other than the ground state or the first excited state), the quantum computing tool can produce a strategic time pause before executing the next quantum circuit on the set of qubits. In aspects, the quantum state leakage can decay back to a non-leaking state (e.g., the ground state and / or the first excited state) during the strategic time pause. In various cases, once the strategic time pause has elapsed, the quantum computing tool can execute, cause to execute, and / or otherwise facilitate the execution of the next quantum circuit. In various cases, if the quantum computing tool does not detect quantum state leakage (e.g., if the quantum computing tool determines that no qubit in the set of qubits is in a state other than the ground state or the first excited state), the quantum computing tool can not produce a strategic time pause and can immediately (e.g., without a pause) execute, cause to execute, and / or otherwise facilitate the execution of the next quantum circuit.

[0025] In various instances, the strategic pauses as described herein can prevent fidelity loss associated with quantum state leakage. Specifically, if the quantum computing tool determines that at least one qubit of the set of qubits is in a leaked state, the quantum computing tool can pause execution of the next quantum circuit on the set of qubits so that the leaked state has time to naturally decay back to a non-leaked state. Thus, after the leaked state decays back to a non-leaked state, the next quantum circuit can be executed on the set of qubits, which means that the next quantum circuit can not be affected by the leaked state. Because the leaked state is no longer present when the next quantum circuit is executed (e.g., the leaked state can decay during the strategic time pause), the fidelity of the next quantum circuit can not be affected by the leaked state.

[0026] Further, in various aspects, the strategic pauses described herein can further result in increased quantum circuit repetition rates. Intuitively, it can suggest the opposite: waiting for a leaked state to decay before executing the next quantum circuit will decrease the repetition rate. After all, a high repetition rate can be achieved by executing quantum circuits on the set of qubits sequentially as close in time as possible, and thus inserting a pause between the execution of sequential quantum circuits would thus be expected to decrease the repetition rate. However, the inventors of various embodiments of the present invention have recognized that such a pause need not be inserted before executing each quantum circuit in a sequence of quantum circuits. Rather, the inventors of various embodiments of the present invention have recognized that by inserting a pause upon detecting quantum state leakage and not inserting a pause when quantum state leakage is not detected (e.g., the pause can allow a leaked state to decay back to a non-leaked state; if quantum state leakage is not detected, the pause can not be necessary because there is no leaked state to decay), the average repetition rate associated with a sequence of quantum circuits can increase without a corresponding loss in fidelity.

[0027] In different instances, a quantum computing tool according to various embodiments of the present invention can be electronically integrated with a set of qubits and can include a detection component, a pause component, and an execution component.

[0028] In various aspects, the previous quantum circuit can be executed on the set of qubits. In different instances, the detection component of the quantum computing tool can measure the state of the set of qubits (e.g., can determine what state each qubit in the set of qubits is currently in). In various aspects, the detection component can facilitate such measurement by any suitable quantum state readout technique and / or apparatus. For example, in some cases, the detection component can be integrated with any suitable number of microwave readout resonators that can measure and / or detect the state of a superconducting qubit in the set of qubits. As another example, in some cases, the detection component can be integrated with any suitable number of photonic sensors that can measure and / or detect the state of a spin-based qubit in the set of qubits. It will be appreciated that these are merely examples of quantum state readout apparatuses / techniques and are non-limiting. In various aspects, any suitable combination of any other suitable quantum state readout apparatus / technique can be implemented by the detection component.

[0029] Further, as will be appreciated by one of ordinary skill in the art, some quantum state readout apparatuses / techniques can distinguish between a ground state and an excited state in a binary fashion (e.g., a measurement of a first excited state will yield the same result as a measurement of a higher order excited state when implementing such apparatuses / techniques), while other quantum state readout apparatuses / techniques can distinguish between different excited state levels granularly (e.g., a measurement of a first excited state will yield a different result than a measurement of a higher order excited state when implementing such apparatuses / techniques). In different embodiments, any such quantum state readout apparatus / technique can be implemented by the detection component. In various aspects, if the implemented quantum state readout apparatus / technique can distinguish between different levels of excited states, if any qubit in the set of qubits is in an excited state higher than the first excited state, it can be determined / inferred that quantum state leakage has occurred. In different instances, if the implemented quantum state readout apparatus / technique is only able to distinguish between a ground state and an excited state (e.g., a non-ground state) in a binary fashion, it can be determined / inferred that quantum state leakage has occurred if any qubit is in an excited state (e.g., a non-ground state). In different other instances, if the implemented quantum state readout apparatus / technique is only able to distinguish between a ground state and an excited state (e.g., a non-ground state) in a binary fashion, one or more reset operations can be performed after execution of the previous quantum circuit and before measurement by the detection component, and if any qubit is in an excited state (e.g., a non-ground state) after execution of the one or more reset operations, it can be determined / inferred that quantum state leakage has occurred (e.g., if the one or more reset operations fail to return the set of qubits to a ground state, it can be inferred that quantum state leakage has occurred).

[0030] In various instances, the pause component of the quantum computing tool can take action and / or can refrain from taking action based on the quantum state measurements obtained by the detection component. For example, if the detection component determines and / or infers that there is quantum state leakage in the set of qubits, the pause component can generate a strategic time pause before the set of qubits on the next quantum circuit, thereby stopping execution of the next quantum circuit. On the other hand, if the detection component determines and / or infers that there is no quantum state leakage in the set of qubits, the pause component can refrain from generating the strategic time pause, thereby not stopping execution of the next quantum circuit. In various aspects, the strategic time pause can be a span of time in which the next quantum circuit is not executed. During this span of time, the quantum state leakage detected by the detection component can naturally decay and / or relax back to a non-leaking state (e.g., decay and / or relax from a higher order excited state back to a first excited state or ground state). In various cases, the strategic time pause can have any suitable duration and / or length that allows the quantum state leakage to decay and / or relax back to a non-leaking state. In various aspects, the duration of the strategic time pause can be greater than and / or equal to a coherence time associated with the set of qubits, where the coherence time of a qubit can be an amount of time that a quantum state can persist before being altered due to interaction with an external environment of the qubit (e.g., it can be on the order of milliseconds and / or microseconds). In various cases, the strategic time pause can have the same order of magnitude as the coherence time associated with the set of qubits (e.g., where the order of magnitude can be similar to powers of 10). Thus, for example, if the set of qubits has a coherence time of T microseconds for any suitable positive number T, the duration of the strategic time pause can be greater than and / or equal to T and can be less than and / or equal to 10T (e.g., can be up to an order of magnitude greater than T). However, in various cases, the strategic time pause can be more than an order of magnitude greater than the coherence time associated with the set of qubits.

[0031] As noted above, in various aspects, the detection component of the quantum computing tool can distinguish between different levels of excited states. In such cases, the pause component can vary and / or modulate the length of the strategic time pause based on the size, order, and / or level of the largest excited state detected by the detection component. In particular, the time required for an excited state to naturally decay and / or relax to the ground state or a first excited state can increase with the size, order, and / or level of the excited state (e.g., a third excited state can require a longer time to decay / relax than a second excited state, a fourth excited state can require a longer time to decay / relax than a third excited state). In various aspects, the pause component can have any suitable electronic access to a decay lookup table that can correlate different sizes, orders, and / or levels of excited states to different decay times. In various aspects, such decay times can be obtained through conventional experimentation (e.g., a quantum bit can be placed in a second excited state in a laboratory setting, and the time required for the quantum bit to decay back to a first excited state and / or ground state can be recorded; likewise, a quantum bit can be placed in a third excited state in a laboratory setting, and the time required for the quantum bit to decay back to a first excited state and / or ground state can be recorded). In this way, the pause component can adjust the length / duration of the strategic time pause based on the extent of quantum state leakage detected by the detection component (e.g., the more severe the quantum state leakage, the longer the time required for the quantum state leakage to dissipate).

[0032] In various aspects, the execution component of the quantum computing tool can execute, cause to execute, and / or otherwise facilitate execution of a next quantum circuit on the set of quantum bits after the strategic time pause. As noted above, the detection component can determine and / or infer that there is quantum state leakage associated with the set of quantum bits (e.g., can determine and / or infer that at least one quantum bit in the set of quantum bits is in a leakage state). In such cases, the pause component can determine an amount of time that will allow the quantum state leakage to naturally decay and / or relax to a non-leakage state, and this amount of time can be considered the strategic time pause. In various cases, the pause component can implement the strategic time pause by transmitting an electronic command to the execution component, where the electronic command instructs the execution component to prevent and / or refrain from execution of the next quantum circuit during the strategic time pause. In various aspects, the electronic command can instruct the execution component to execute, cause to execute, and / or otherwise facilitate execution of the next quantum circuit as soon as the strategic time pause has elapsed. At such time, the quantum state leakage can have naturally decayed and / or relaxed to a non-leakage state, and thus execution of the next quantum circuit on the set of quantum bits can not be disturbed by the quantum state leakage. If the detection component determines and / or infers that there is no quantum state leakage associated with the set of quantum bits, the pause component can transmit an electronic command to the execution component that instructs the execution component to execute, cause to execute, and / or otherwise facilitate execution of the next quantum circuit on the set of quantum bits without waiting / pausing.

[0033] To summarize some of the above, the detection component can measure the state of the set of qubits to determine whether quantum state leakage has occurred. If the detection component concludes that quantum state leakage has occurred, the pause component can generate a strategic time pause and the execution component can be instructed to wait for the duration of the strategic time pause before executing the next quantum circuit on the set of qubits. Once the strategic time pause has passed, the execution component can proceed to execute the next quantum circuit. If the detection component concludes that no quantum state leakage has occurred, the pause component can not generate a strategic time pause and the execution component can proceed to execute the next quantum circuit immediately. By pausing upon detecting a leakage state and not pausing upon not detecting a leakage state (e.g., thus referred to as a "strategic pause"), the quantum circuit can be executed on the set of qubits at a high / fast average repetition rate without being disrupted by a leakage state. This is certainly advantageous compared to pausing before executing every quantum circuit. Moreover, this strategic pause does not require implementation and / or calibration of leakage mitigation pulses, thus providing further advantages.

[0034] To help clarify these advantages, consider the following non-limiting example. It should be understood that any numerical values presented in the following example are illustrative and non-limiting. Consider a 20-qubit device with a 100-microsecond coherence time (e.g., although in the real world the coherence time is more complex, for the purposes of this example assume that the coherence time is the same for all levels / states of the qubits). Further, assume a 0.1% leakage rate when performing a quantum state measurement and a 0.01% leakage rate when performing an entangling gate (e.g., a 2-qubit gate such as a Controlled-NOT). Assume a quantum circuit is executed on the 20-qubit device that involves all 20 qubits and involves a depth of 10 entangling gates, and assume that a quantum state measurement is performed on all 20 qubits afterwards. In this case, the probability that any given qubit leaks during the execution of the circuit and the measurement can be approximately 0.2% (e.g., the probability that the qubit leaks only during the measurement, by 0.001 * (1 - 0.0001) 10 Given, plus the probability that the qubit leaks during the measurement and all entangling gates, by 0.001 * 0.0001 10 Given, plus the probability that the qubit leaks only during certain combinations of entangling gates, by Given, for a total of approximately 0.002 or 0.2%). Thus, the probability that none of the 20 qubits leak while running the circuit and measurement can be approximately 96% (e.g., (1 - 0.002) 20about 4% of the executions, meaning that at least one of the 20 qubits can leak after about 4% of the executions. Assuming that the execution of an entangling gate takes 200 nanoseconds, and assuming that measuring the state of 20 qubits takes a total of 10 microseconds. Thus, the sequential execution of the circuit and the measurement takes a total of 12 microseconds (e.g., 200 nanoseconds for each of the 10 entangling gates, plus the 10 microseconds for the measurement). In other words, if the execution of multiple such circuits and measurements is performed back-to-back, this can result in a repetition rate of 12 microseconds. Since each qubit can have a coherence time of 100 microseconds, any qubit that is in a leaked state can remain in the leaked state for about 8 repetitions (e.g., about 8 repetitions of the circuit and measurement, each taking 12 microseconds, can be performed within a 100-microsecond time window). Thus, when the leaked state is not addressed in some manner, many subsequent repetitions of the circuit and measurement are corrupted (e.g., in some cases, as many as 30% of the runs are contaminated by the leaked state), which is problematic.

[0035] Various embodiments of the present invention can address this problem with strategic pauses. Specifically, after performing a measurement that determines a leaked state and before performing a subsequent circuit, a time pause that is longer than the coherence time (e.g., greater than and on the same order of magnitude as the coherence time) can be inserted. For a coherence time of 100 microseconds, in some cases, the time pause can be 500 microseconds. During such a time pause, any detected leaked state can naturally decay and / or relax to a non-leaked state, such that the execution of the subsequent circuit is not corrupted by the leaked state. As noted above, this example can involve about 4% of the runs having a leaked state. Thus, the 500-microsecond time pause can be added to about 4% of the runs, and can not be added to the remaining 96% of the runs, which can result in an average repetition rate of about 32 microseconds (e.g., 96% of the circuit and measurement repetitions in this example do not involve a leaked state, and thus can take 12 microseconds, and 4% of the circuit and measurement repetitions in this example involve a leaked state, and thus can take 512 microseconds, where 0.96*12 + 0.04*512 = 32). Note that an average repetition rate of 32 microseconds is very fast, in comparison to a 512-microsecond average repetition rate that would result from pausing before each individual circuit. Also, note that while the average repetition rate of 32 microseconds is slightly slower than the repetition rate of 12 microseconds that can be achieved without any pauses, the implementation of the strategic pauses improves the problem of circuit corruption and / or contamination due to quantum state leakage (e.g., the implementation of the time pauses allows detected leakage to decay and / or relax to a non-leaked state, such that the leakage does not contaminate the execution of subsequent circuits). Moreover, as noted above, the strategic pauses do not require the implementation and / or calibration of any additional electronic pulses, which would otherwise increase the cost of overhead, noise, and / or decoherence.

[0036] Various embodiments of the present invention can be used to solve technically strong problems (e.g., facilitating policy pauses to mitigate quantum state leakage) using hardware and / or software that are not abstract and cannot be performed as a set of mental acts by a human. Moreover, some of the processes performed can be performed by a specialized computer (e.g., detecting quantum state leakage related to one or more qubits by a device operatively coupled to a processor; and generating a time pause before execution of a quantum circuit on the one or more qubits by the device and in response to detecting the quantum state leakage, where generating the time pause occurs after execution of a previous quantum circuit on the one or more qubits, where the quantum state leakage occurred during execution of the previous quantum circuit, and where the quantum state leakage decays during the time pause). Such defined tasks are not typically performed manually by a human. Moreover, neither a human brain nor a human holding a pen and paper can detect a leaking quantum state of a set of qubits and produce a time pause during which the leaking quantum state relaxes to a non-leaking state. Rather, various embodiments of the present invention are inextricably bound to computer technology and cannot be implemented outside of a computing environment (e.g., quantum state leakage degrades the fidelity of a quantum computer, and quantum computing technology that is capable of ameliorating such fidelity loss cannot be utilized in any workable fashion outside of a quantum computing environment).

[0037] In various instances, embodiments of the present invention can integrate the disclosed teachings regarding suspending strategies for mitigating quantum state leakage into practical applications. Indeed, as described herein, various embodiments of the present invention, which can take the form of a system and / or computer-implemented method, can be viewed as a quantum computing tool that measures the state of a set of qubits to detect quantum state leakage (e.g., to determine whether any of the qubits are in a leakage state). If the quantum computing tool determines that quantum state leakage has occurred, the quantum computing tool can suspend execution of a subsequent quantum circuit on the set of qubits for a particular period of time (e.g., for the duration of the strategy time suspension). During such a period of time, the quantum state leakage can naturally dissipate back to the ground state or first excited state, at which point the quantum state leakage no longer exists (e.g., at which point the qubits are no longer in a leakage state). The quantum computing tool can then execute and / or otherwise cause execution of the subsequent quantum circuit on the set of qubits. Because the quantum state leakage no longer exists when the subsequent quantum circuit is executed, the subsequent quantum circuit can be unaffected by the quantum state leakage. By inserting such a time suspension when quantum state leakage is detected, and not inserting such a time suspension when quantum state leakage is not detected, quantum circuits can be executed on a set of qubits at an increased average repetition rate without a corresponding decrease in fidelity and / or accuracy due to a leaking state. In other words, various embodiments of the present invention can improve the performance of a quantum computing device (e.g., can increase the repetition rate, and can decrease the loss of fidelity). A system and / or technique that is capable of facilitating an increased repetition rate while also ameliorating quantum state leakage issues clearly constitutes a specific and tangible technical improvement in the field of quantum computing and / or quantum information processing.

[0038] Furthermore, various embodiments of the present invention can control tangible, hardware-based, and / or software-based devices based on the disclosed teachings. For example, embodiments of the present invention can measure / probe the state of a tangible qubit device, can determine whether at least one of the tangible qubit device is currently in a leakage state based on such measurement / probing, can prevent execution of a quantum circuit on such a tangible qubit device if at least one of the tangible qubit device is in a leakage state, and / or can facilitate execution of a quantum circuit on such a tangible qubit device if none of the tangible qubit device is in a leakage state. In other words, various embodiments of the present invention can control and improve the performance of real-world and tangible qubit devices. Accordingly, embodiments of the present invention constitute a specific and tangible technical improvement in the field of quantum computing and / or quantum information processing.

[0039] It should be understood that the drawings and disclosed herein describe non-limiting examples of various embodiments of the present invention.

[0040] Figure 1A block diagram of a non-limiting system 100 that can facilitate strategic pauses for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown. As shown, in various embodiments, a strategic pause system 102 can be coupled to a set of qubits 104 by any suitable electronic connection (e.g., wired and / or wireless). The set of qubits 104 can include any suitable number of qubits (e.g., qubit 1, qubit 2,..., qubit n, as shown for any suitable positive integer n). In different aspects, the set of qubits 104 can include any suitable combination of any suitable type of qubit (e.g., superconducting qubits, spin-based qubits, quantum dots). In various cases, the qubits in the set of qubits 104 can have multiple states: a ground state and a first excited state (which can be referred to as a computational ground state) and higher order excited states (which can be referred to as leakage states and / or leakage states). In various cases, it can be desirable to perform quantum computations and / or quantum information processing by executing quantum circuits on the set of qubits 104 and measuring the resulting states of the set of qubits 104 accordingly. In various cases, it can be desirable to perform such quantum circuits on the set of qubits 104 more quickly (e.g., faster and / or higher repetition rates). However, due to quantum state leakage associated with the set of qubits 104, such faster performance can be accompanied by a loss of fidelity and / or accuracy (e.g., when one or more qubits of the set of qubits 104 are in a leakage state, reset techniques can become ineffective and / or the execution of subsequent quantum circuits can be corrupted). In aspects, the strategic pause system 102 can facilitate such faster performance of quantum circuits on the set of qubits 104 without such corresponding loss of fidelity and / or accuracy by implementing strategic pauses.

[0041] In different embodiments, the strategic pause system 102 can include a processor 106 (e.g., a computer processing unit, a microprocessor) and a computer-readable memory 108 operably connected to the processor 106. The memory 108 can store computer-executable instructions that, when executed by the processor 106, can cause the processor 106 and / or other components of the strategic pause system 102 (e.g., a detection component 110, a pause component 112, an execution component 114) to perform one or more actions. In different embodiments, the memory 108 can store computer-executable components (e.g., the detection component 110, the pause component 112, the execution component 114), and the processor 106 can execute the computer-executable components.

[0042] In different embodiments, the strategic pause system 102 can include an execution component 114. In various aspects, the execution component 114 can execute, cause to be executed, and / or otherwise assist in executing one or more quantum circuits on the set of qubits 104 in any suitable manner. In different instances, as described above, the quantum circuits can be a sequence of quantum gates (e.g., represented by matrices) that can operate on and / or transform the state of the set of qubits 104. The quantum circuits can be sequentially combined via matrix multiplication and / or can be combined in parallel via a tensor product (e.g., a Kronecker product). In some cases, the execution component 114 can execute, cause to be executed, and / or otherwise assist in executing the quantum circuits on the set of qubits 104 by driving the set of qubits 104 with controlled and / or tuned electromagnetic signals (e.g., the execution component 114 can be integrated with any suitable quantum computing devices, such as waveguides and / or signal generators / modulators, to generate and / or propagate such electromagnetic signals).

[0043] In different embodiments, the strategic pause system 102 can include a detection component 110. In various aspects, the detection component 110 can read, measure, detect, and / or otherwise sense the state of the set of qubits 104. In different instances, the detection component 110 can facilitate such reading, measuring, detecting, and / or otherwise sensing by implementing and / or electronically integrating with any suitable combination of quantum readout devices (e.g., the detection component 110 can have a dedicated quantum readout device for each qubit in the set of qubits 104). For example, in different cases, the detection component 110 can implement and / or electronically integrate with any suitable microwave readout resonators, which can read, measure, detect, and / or otherwise sense the state of superconducting qubits included in the set of qubits 104. As another example, in different cases, the detection component 110 can implement and / or electronically integrate with any suitable photonic sensors, which can read, measure, detect, and / or otherwise sense the state of spin-based qubits included in the set of qubits 104. Those of ordinary skill in the art will recognize that these are merely non-limiting examples of possible quantum readout devices that can be incorporated in different embodiments. In different cases, any other suitable quantum readout devices and / or quantum readout techniques can be implemented by the detection component 110.

[0044] By reading, measuring, detecting, and / or otherwise sensing the state of the set of qubits 104, the detection component 110 can determine whether there is quantum state leakage associated with the set of qubits 104. In various aspects, if the detection component 110 determines that at least one qubit in the set of qubits 104 is in a leaked state (e.g., is in a state other than the ground state or the first excited state), the detection component 110 can conclude and / or infer that there is quantum state leakage associated with the set of qubits 104.

[0045] In some cases, as described above, the detection component 110 can implement quantum readout devices and / or techniques that can distinguish between different levels of excited states. As will be appreciated by one of ordinary skill in the art, for any suitable positive integers x and y, and where x≠y, such quantum readout devices and / or techniques can distinguish between the ground state and any excited state, can distinguish between the first excited state and the second excited state, can distinguish between the second excited state and the third excited state, and / or can distinguish between the xth excited state and the yth excited state. In such cases, when at least one qubit in the set of qubits 104 has a state that is neither the ground state nor the first excited state, the detection component 110 can conclude and / or infer that there is quantum state leakage associated with the set of qubits 104. Conversely, when each qubit in the set of qubits 104 is in either the ground state or the first excited state (e.g., the set of qubits 104 can all be in the ground state, the set of qubits 104 can all be in the first excited state, and / or some of the set of qubits 104 can be in the ground state while the remainder of the set of qubits 104 can be in the first excited state), the detection component 110 can conclude and / or infer that there is no quantum state leakage associated with the set of qubits 104.

[0046] In other cases, as described above, the detection component 110 can implement a quantum readout device and / or technique capable of binary distinguishing between a ground state and an excited state. As those skilled in the art will understand, for any suitable positive integers x and y, where x ≠ y, such a quantum readout device and / or technique can distinguish the ground state from any excited state, but cannot distinguish between a first excited state and a second excited state, cannot distinguish between a second excited state and a third excited state, and / or cannot distinguish between the x-th excited state and the y-th excited state, where... In such cases, when at least one qubit in the qubit set 104 has a state that is not in the ground state, the detection component 110 can determine and / or infer, in various instances, a quantum state leakage associated with the qubit set 104. In various other instances, when the quantum readout device and / or technology implemented by the detection component 110 cannot distinguish between different levels of excited states, one or more reset operations may be performed on the qubit set 104 before the detection component 110 can read, measure, detect, and / or otherwise sense them. Figure 1 (not shown in the diagram), and when at least one qubit in the qubit set 104 is not in the ground state after the one or more reset operations, the detection component 110 can determine and / or infer a quantum state leakage associated with the qubit set 104. Conversely, in each respect, when every qubit in the qubit set 104 is in the ground state, the detection component 110 can determine and / or infer that there is no quantum state leakage associated with the qubit set 104.

[0047] In various embodiments, the strategic pause system 102 can include a pause component 112. In various aspects, the pause component 112 can initiate operations and / or can refrain from initiating operations based on determinations of the detection component 110. As explained above, the execution component 114 can execute, cause to execute, and / or otherwise assist in executing a first quantum circuit on the set of qubits 104, and the detection component 110 can read, measure, detect, and / or otherwise sense a resulting state of the set of qubits 104 after execution of the first quantum circuit. In other words, the execution component 114 can execute a quantum computation on the set of qubits 104, and the detection component 110 can read the result. In various aspects, it can be desirable for the execution component 114 to execute, cause to execute, and / or otherwise assist in executing a second quantum circuit on the set of qubits 104. However, if quantum state leakage occurs during execution of the first quantum circuit, such quantum state leakage can corrupt and / or contaminate execution of the second quantum circuit. In various aspects, the pause component 112 can address and / or handle such quantum state leakage. Specifically, if the detection component 110 determines and / or infers that there is quantum state leakage associated with the set of qubits 104, the pause component 112 can produce a strategic temporal pause during which such quantum state leakage can decay and / or relax back to a non-leaking state (e.g., a qubit in a leaking state can naturally dissipate back to a ground state and / or a first excited state over time). In various aspects, the pause component 112 can implement the strategic temporal pause by transmitting an electronic command to the execution component 114 instructing the execution component 114 to wait to execute, cause to execute, and / or otherwise assist in executing the second quantum circuit on the set of qubits 104 until after the strategic temporal pause has elapsed. Because the quantum state leakage can decay and / or relax during the strategic temporal pause, the quantum state leakage is no longer present at the time of execution of the second quantum circuit, which means that execution of the second quantum circuit can not be corrupted by the quantum state leakage (e.g., due to the strategic temporal pause, a loss of fidelity associated with execution of the second quantum circuit can be avoided). If the detection component 110 determines and / or infers that there is no quantum state leakage associated with the set of qubits 104, the pause component 112 can refrain from producing the strategic temporal pause. As such, the execution component 114 can execute, cause to execute, and / or otherwise assist in executing the second quantum circuit on the set of qubits 104 immediately after the detection component 110 reads, measures, detects, and / or otherwise senses the state of the set of qubits 104 resulting from execution of the first quantum circuit. In this way, the pause component 112 can generate strategic temporal pauses only when needed (e.g., when quantum state leakage is detected, but not when quantum state leakage is not detected).The result can be that the quantum circuit can be executed by the execution component 114 on the set of qubits 104 at a high average repetition rate and without any corresponding drop in fidelity due to quantum state leakage corruption.

[0048] In various aspects, the duration of the strategic time pause can be greater than and / or of the same order of magnitude as a coherence time associated with the set of qubits 104. For example, if the qubits in the set of qubits 104 have a coherence time of T microseconds for any appropriate positive number T, then the duration of the strategic time pause can be greater than and / or equal to T and can be less than and / or equal to 10T. In some cases, each qubit in the set of qubits 104 can have its own corresponding coherence time (e.g., the qubits can have different coherence times), and the duration of the strategic time pause can be greater than and / or of the same order of magnitude as a maximum coherence time of the set of qubits 104.

[0049] In various embodiments, if the detection component 110 can distinguish between different levels of excited states, then the pause component 112 can vary, adjust, and / or modulate the duration of the strategic time pause based on the maximum excited state detected by the detection component 110. For example, if the maximum excited state detected by the detection component 110 is the fourth excited state, then the pause component 112 can cause the strategic time pause to have a first duration, and if the maximum excited state detected by the detection component 110 is the fifth excited state, then the pause component 112 can cause the strategic pause time to have a second duration that is greater than the first duration (e.g., the fifth excited state can take longer to dissipate back to the ground state and / or back to the first excited state than the fourth excited state). In this way, the pause component 112 can tailor the duration of the strategic pause to the particular state of the set of qubits 104.

[0050] Figure 2 A block diagram illustrating an example, non-limiting system 200 including quantum state leakage that can facilitate strategic pausing for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown. As shown, in some cases, the system 200 can include the same components as the system 100 and can also include quantum state leakage 202.

[0051] In various aspects, the detection component 110 can read, measure, detect, and / or otherwise sense the state of the set of qubits 104 by any suitable quantum readout apparatus / technique (e.g., microwave readout resonators, photonic sensors). Specifically, since the set of qubits 104 can include n qubits, the detection component 110 can read, measure, detect, and / or otherwise sense n states. In cases where the detection component 110 can distinguish between different levels of excited states, if the detection component 110 determines that any of such n states is a leakage state (e.g., any of such n states is neither the ground state nor the first excited state), the detection component 110 can infer and / or conclude that the quantum state leakage 202 is present in the set of qubits 104. In cases where the detection component 110 can distinguish between different levels of excited states, if the detection component 110 determines that none of such n states is a leakage state (e.g., none of such n states is neither the ground state nor the first excited state), the detection component 110 can infer and / or conclude that the quantum state leakage 202 is not present in the set of qubits 104. In cases where the detection component 110 can only make a binary distinction between the ground state and excited states, if the detection component 110 determines that any of such n states is a non-ground state, the detection component 110 can infer and / or conclude that the quantum state leakage 202 is present in the set of qubits 104. In cases where the detection component 110 can only make a binary distinction between the ground state and excited states, if the detection component 110 determines that none of such n states is a non-ground state, the detection component 110 can infer and / or conclude that the quantum state leakage 202 is not present in the set of qubits 104.

[0052] Figure 3A block diagram of an example, non-limiting qubit with various possible quantum states is shown in accordance with one or more embodiments described herein. As shown, qubit 302 can have different possible states 304. Specifically, qubit 302 can have a ground state, a first excited state, a second excited state,..., and an mth excited state (for any suitable positive integer m > 1). In various aspects, the ground state and the first excited state can be considered computational states 306 because those two states are generally and / or frequently used to perform quantum computations and / or quantum information processing (e.g., the ground state can be represented as |0> and the first excited state can be represented as |1>). In different cases, these higher order excited states (e.g., second excited state, mth excited state) can be considered leakage states 308 because these states are generally and / or frequently not used to perform quantum computations and / or quantum information processing. When qubit 302 is in one of the leakage states 308, execution of a quantum circuit on qubit 302 can be corrupted and / or contaminated (e.g., can produce inaccurate results). Thus, it can be beneficial to ensure that qubit 302 is in one of the computational states 306 and not in one of the leakage states 308 when executing a quantum circuit on qubit 302. As explained herein, strategic pause system 102 can ensure that this is the case.

[0053] Although Figure 3 Although the computational states 306 are depicted as including only the ground state and the first excited state, this is merely a non-limiting example. In some cases, the computational states 306 can include the ground state, the first excited state, and any suitable number of higher order excited states (e.g., the second excited state can be considered a computational state in some cases rather than a leakage state). In such cases, the leakage states 308 can include the higher order excited states that are not included in the computational states 306. Thus, although the disclosure herein primarily discusses embodiments in which the leakage states are any states that are neither the ground state nor the first excited state, such discussion is non-limiting.

[0054] Figure 4 A block diagram of an example, non-limiting system 400 that includes a strategic time pause that can facilitate strategic pausing for quantum state leakage mitigation is shown in accordance with one or more embodiments described herein. As shown, in some cases, system 400 can include the same components as system 200 and can also include a strategic time pause 402.

[0055] In various aspects, the pause component 112 can generate a strategic time pause 402 if the detection component 110 infers and / or infers that the quantum state leakage 202 is present in the set of qubits 104. On the other hand, the pause component 112 can refrain from generating the strategic time pause 402 if the detection component 110 infers and / or infers that the quantum state leakage 202 is not present in the set of qubits 104. In various aspects, the strategic time pause 402 can be a span of time in which no quantum circuit is executed on the set of qubits 104. Thus, the quantum state leakage 202 can decay and / or relax during the strategic time pause 402. Once this decay and / or relaxation is complete, the quantum state leakage 202 is no longer present in the set of qubits 104. In other words, any leaked states in the set of qubits 104 can dissipate back to non-leaked states during the strategic time pause 402. Note that this dissipation can occur naturally over time and does not require exposing the set of qubits 104 to different calibration pulses (e.g., pulses that are separate and / or different from the pulses used to execute a quantum circuit or measure a quantum state), which can otherwise introduce additional noise and / or cost.

[0056] Figure 5 A block diagram illustrating an example, non-limiting timeline showing a strategic pause for quantum state leakage mitigation is shown in accordance with one or more embodiments described herein. Specifically, Figure 5The timeline 502 and the timeline 516 are described. The timeline 502 can represent quantum computing operations performed on the set of qubits 104 over time when the strategic time pause 402 is not implemented. In contrast, the timeline 516 can represent quantum computing operations performed on the set of qubits 104 over time when the strategic time pause 402 is implemented. First, consider the timeline 502. As shown, a circuit execution 504 can first be performed on the set of qubits 104 (e.g., a first quantum circuit can be performed on the set of qubits 104), and then a state measurement 506 can be performed on the set of qubits 104 to determine a result of the circuit execution 504. Similarly, a circuit execution 508 can next be performed on the set of qubits 104 (e.g., a second quantum circuit can be performed on the set of qubits 104), and then a state measurement 510 can be performed on the set of qubits 104 to determine a result of the circuit execution 508. Likewise, a circuit execution 512 can then be performed on the set of qubits 104 (e.g., a third quantum circuit can be performed on the set of qubits 104), and then a state measurement 514 can be performed on the set of qubits 104 to determine a result of the circuit execution 512. In other words, the timeline 502 shows that three quantum circuits can be performed on the set of qubits 104, with each quantum circuit followed by a measurement operation. In various aspects, as shown, a quantum state leakage 202 can occur (e.g., can occur accidentally) during the circuit execution 508. In other words, at least one qubit in the set of qubits 104 can enter a leakage state in the course of the circuit execution 508. Unfortunately, the quantum state leakage 202 can persist through the state measurement 510 and into the circuit execution 512 (e.g., in practice, in some cases, the quantum state leakage 202 can persist for several circuit and measurement iterations, if left unresolved). As such, the quantum state leakage 202 can negatively affect the circuit execution 512 (e.g., and / or other subsequent circuit executions), which can result in a loss of fidelity.

[0057] In various aspects, this loss of fidelity can be avoided by implementing a strategic time pause 402. Consider timeline 516. As with timeline 502, in timeline 516, circuit execution 504 can be performed first, followed by state measurement 506, followed by circuit execution 508, followed by state measurement 510. However, instead of performing circuit execution 512 immediately after state measurement 510, a strategic time pause 402 can be inserted between state measurement 510 and circuit execution 512 in response to state measurement 510 detecting quantum state leakage 202. As such, quantum state leakage 202 can decay and / or relax back to a non-leaking state during strategic time pause 402. Once strategic time pause 402 has elapsed, circuit execution 512 can be performed, followed by state measurement 514. Because quantum state leakage 202 can decay and / or relax during strategic time pause 402, quantum state leakage 202 is no longer present at the time of circuit execution 512, meaning that circuit execution 512 can not be corrupted and / or contaminated by quantum state leakage 202.

[0058] Note that no pause is inserted between state measurement 506 and circuit execution 508. This can be due to the fact that no quantum state leakage 202 arose during circuit execution 504. In other words, strategic time pause 402 can be inserted and / or implemented when needed (e.g., when a leaking state is detected) and can not be inserted and / or implemented when not needed (e.g., when no leaking state is detected). The result can be an increased average repetition rate without a corresponding loss of fidelity due to leakage.

[0059] Those of ordinary skill in the art will appreciate that Figure 5 The figures are illustrative, non-limiting, and are not necessarily drawn to scale.

[0060] Figure 6 A block diagram of an example, non-limiting system 600 including a decay lookup table that can facilitate strategic pause for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown. As shown, in some cases, system 600 can include the same components as system 400 and can also include a decay lookup table 602.

[0061] In various embodiments, if the detection component 110 can distinguish between different levels of excited states, the pause component 112 can vary the duration of the strategic time pause 402 based on the maximum excited state detected by the detection component 110. In different scenarios, to facilitate this variation of the duration of the strategic time pause 402, the pause component 112 can have electronic access to any suitable form of an attenuation lookup table 602. In various aspects, the attenuation lookup table 602 can be any appropriate data structure (e.g., a relational data structure, a graph data structure, a hybrid data structure) that can be centralized and / or distributed and that can map and / or correlate different levels of excited states of a qubit to corresponding attenuation times. In other words, the attenuation lookup table 602 can indicate how long it takes for a particular leakage state to naturally relax back to a non-leakage state (e.g., to relax back to a ground state and / or to a first excited state). For example, the attenuation lookup table 602 can indicate that a second excited state of a qubit in the set of qubits 104 can relax back to the first excited state within q microseconds for any appropriate positive integer q, can indicate that a third excited state of a qubit in the set of qubits 104 can relax back to the first excited state within r microseconds for any appropriate positive integer r, where r > q, and / or can indicate that a fourth excited state of a qubit in the set of qubits 104 can relax back to the first excited state within s microseconds for any appropriate positive integer s, where s > r. From this, if the detection component 110 determines that at least one qubit in the set of qubits 104 is in the fourth excited state and that no qubit in the set of qubits 104 is in an excited state higher than the fourth excited state, the pause component 112 can cause the strategic time pause 402 to have a duration of s microseconds. If the detection component 110 determines that at least one qubit in the set of qubits 104 is in the third excited state and that no qubit in the set of qubits 104 is in an excited state higher than the third excited state, the pause component 112 can cause the strategic time pause 402 to have a duration of r microseconds. If the detection component 110 determines that at least one qubit in the set of qubits 104 is in the second excited state and that no qubit in the set of qubits 104 is in an excited state above the second excited state, the pause component 112 can cause the strategic time pause 402 to have a duration of q microseconds. In this way, the pause component 112 can tailor and / or customize the duration of the strategic time pause 402 based on the magnitude of the quantum state leakage 202.

[0062] In various aspects, the attenuation lookup table 602 can be obtained and / or generated in any suitable manner (e.g., can be obtained through routine experimentation in a laboratory setting in which a controlled qubit is forced into a leakage state and in which the time it takes for the controlled qubit to naturally attenuate back to the first excited state and / or to attenuate back to the ground state is recorded).

[0063] Figure 7 A block diagram illustrating an example, non-limiting system 700 including a next quantum circuit that can facilitate strategic pauses for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown. As shown, in some aspects, system 700 can include the same components as system 600 and can further include a next quantum circuit 702.

[0064] In various embodiments, after the strategic time pause 402 has elapsed, the execution component 114 can perform, cause to be performed, and / or otherwise facilitate execution of the next quantum circuit 702 on the set of qubits 104. In other words, the pause component 112 can instruct and / or command the execution component 114 to stop execution of the next quantum circuit 702 until after the strategic time pause 402 has elapsed. As described above, the quantum state leakage 202 can decay and / or relax during the strategic time pause 402. Thus, when the next quantum circuit 702 is executed, the quantum state leakage 202 can no longer be present, meaning that the fidelity and / or accuracy associated with execution of the next quantum circuit 702 can not be affected by the quantum state leakage 202. In various aspects, if the strategic time pause 402 is not produced by the pause component 112, the execution component 114 can perform, cause to be performed, and / or otherwise facilitate execution of the next quantum circuit 702 on the set of qubits 104 immediately after the detection component 110 reads, measures, detects, and / or otherwise senses the state of the set of qubits 104. That is, the pause component 112 can instruct and / or command the execution component 114 not to stop execution of the next quantum circuit 702. Again, this can result in an increased average repetition rate without a corresponding decrease in fidelity.

[0065] Figure 8 A block diagram illustrating an example, non-limiting system 800 including a mid-pause quantum state measurement that can facilitate strategic pauses for quantum state leakage mitigation in accordance with one or more embodiments described herein is shown. As shown, in some aspects, system 800 can include the same components as system 700 and can further include a mid-pause quantum state measurement 802.

[0066] In various aspects, the detection component 110 can perform one or more intermediate pause quantum state measurements 802. That is, in some cases, the detection component 110 can read, measure, detect, and / or otherwise sense the state of the set of qubits 104 during the strategic time pause 402 (e.g., before the strategic time pause 402 has elapsed). In different instances, if the intermediate pause quantum state measurements 802 indicate that the quantum state leakage 202 has been dissipated before the strategic time pause 402 has elapsed, the execution component 114 can end the stopping of the execution of the next quantum circuit 702 (e.g., if the quantum state leakage 202 has decayed, as can be the case if the duration of the strategic time pause 402 is longer than needed, the next quantum circuit 702 can be executed on the set of qubits 104 before the strategic time pause 402 ends). On the other hand, if the intermediate pause quantum state measurements 802 indicate that the quantum state leakage 202 has not been dissipated, the execution component 114 can continue the stopping of the execution of the next quantum circuit 702 (e.g., since the quantum state leakage 202 has not decayed, the next quantum circuit 702 should not be executed on the set of qubits 104). In different instances, any suitable number of intermediate pause quantum state measurements 802 can be implemented during the strategic time pause 402. In different cases where multiple intermediate pause quantum state measurements 802 are implemented, they can be performed at any suitable regular and / or irregular intervals (e.g., at intervals separated by the coherence time of the set of qubits 104).

[0067] Figures 9 to 11 Flowcharts illustrating example non-limiting computer-implemented methods 900, 1000, and 1100 that can facilitate strategic pauses for quantum state leakage mitigation in accordance with one or more embodiments described herein are shown.

[0068] Consider Figure 9 and computer-implemented method 900. As shown, in different embodiments, act 902 can include executing, by a device (e.g., 114) operatively coupled to a processor, a quantum circuit (e.g., 508) on a set of qubits (e.g., 104).

[0069] In various aspects, act 904 can include measuring, by the device (e.g., 110), a state of the set of qubits.

[0070] In different instances, act 906 can include determining, by the device (e.g., 110), whether any qubit in the set of qubits is in a leakage state (e.g., 202 and / or 308). If not, the computer-implemented method 900 can return to act 902. If so, the computer-implemented method 900 can proceed to act 908.

[0071] In various instances, action 908 can include pausing, by the apparatus (e.g., 112), prior to performing any other circuitry (e.g., 512 and / or 702) on the set of qubits, where the duration of the pause (e.g., 402) is greater than and on the order of the coherence time associated with the set of qubits. In various aspects, computer-implemented method 900 can then return to action 902.

[0072] In summary, computer-implemented method 900 can include performing a quantum circuit on a set of qubits, measuring quantum states of the set of qubits, determining whether there are leaked quantum states, and if there are leaked quantum states, stopping execution of a next quantum circuit until after any leaked quantum states decay. If there are no leaked quantum states, the next quantum circuit can be executed immediately without waiting / stopping.

[0073] In some aspects, as shown, computer-implemented method 900 can sometimes proceed from action 908 to Label A, which is shown in Figure 10

[0074] Consider Figure 10 and computer-implemented method 1000. As shown, in various aspects, Label A can proceed to action 1002, which can include measuring, by the apparatus (e.g., 110) and during the pause, states of the set of qubits (e.g., 802).

[0075] In various instances, action 1004 can include determining, by the apparatus (e.g., 110), whether any qubits in the set of qubits are in a leaked state. If not, computer-implemented method 1000 can proceed to action 1006. If so, computer-implemented method 1000 can proceed to action 1008.

[0076] In various instances, action 1006 can include immediately continuing back to action 902; i.e., without waiting for the pause time to elapse.

[0077] In various aspects, action 1008 can include continuing back to action 902 after the pause, thereby allowing any detected leaked states to decay.

[0078] In summary, computer-implemented method 1000 shows how to implement intermediate pause quantum state measurement 802 (e.g., if quantum state leakage 202 has decayed before the end of the policy time pause 402, the execution component 114 need not stall for the entire duration of the policy time pause 402).

[0079] Consider Figure 11 ​and computer-implemented method 1100. In various embodiments, act 1102 can include detecting, by a device (e.g., 110) operatively coupled to a processor, quantum state leakage (e.g., 202) associated with one or more qubits (e.g., 104).

[0080] In various aspects, act 1104 can include generating, by a device (e.g., 112) and in response to the detected quantum state leakage, a time pause (e.g., 402) prior to execution of a quantum circuit (e.g., 702 and / or 512) on the one or more qubits. In some cases, generating the time pause can occur after execution of a previous quantum circuit (e.g., 508) on the one or more qubits. In some cases, the quantum state leakage can have occurred during execution of the previous quantum circuit. In certain cases, the quantum state leakage can decay during the time pause.

[0081] Although not shown in Figure 11 , in some cases, computer-implemented method 1100 can further include: performing, by the device (e.g., 110) during the time pause, one or more quantum state measurements (e.g., 802) on the one or more qubits, wherein the one or more quantum state measurements binarily distinguish between the ground state and the excited state; and performing, by the device (e.g., 114), the quantum circuit on the one or more qubits if the one or more quantum state measurements indicate that the one or more qubits are in the ground state.

[0082] Although not shown in Figure 11 , in some cases, computer-implemented method 1100 can further include: performing, by the device (e.g., 110) during the time pause, one or more quantum state measurements (e.g., 802) on the one or more qubits, wherein the one or more quantum state measurements distinguish between different levels of the excited state; and performing, by the device (e.g., 114), the quantum circuit on the one or more qubits if the one or more quantum state measurements indicate that the one or more qubits are in the ground state, the first excited state, or a combination of the ground state and the first excited state.

[0083] Although not shown in Figure 11 , in some cases, computer-implemented method 1100 can further include changing, by the device (e.g., 112), a duration of the time pause based on a maximum excited state detected during the detecting.

[0084] Although embodiments are discussed herein in which the execution component 114 executes and / or causes execution of quantum circuits on the set of qubits 104 and the detection component 110 measures the state of the set of qubits 104, this is illustrative and non-limiting. In some embodiments, the execution component 114 can execute and / or cause execution of quantum circuits that operate only on a subset of the set of qubits 104. In this case, the detection component 110 can measure the state of this subset of the set of qubits 104, rather than measuring the state of the entire set of qubits 104.

[0085] Various embodiments of the present invention can address the problem of quantum state leakage. Specifically, when a qubit is in a leaked state, it can corrupt and / or pollute the execution of subsequent quantum circuits involving that qubit. In different aspects, embodiments of the present invention can address this problem by inserting a temporal pause before executing a quantum circuit upon detecting quantum state leakage. The temporal pause can allow the quantum state leakage to naturally relax to a non-leaked state, at which point the subsequent quantum circuit can be executed without loss of fidelity. Moreover, the average repetition rate of such quantum circuits can be increased by various embodiments of the present invention, as the temporal pause can not be inserted when no quantum state leakage is detected. Thus, embodiments of the present invention can speed up the repetition rate of quantum circuit execution without the corresponding drop in fidelity that typically accompanies quantum state leakage. Furthermore, various embodiments of the present invention can facilitate this benefit without the need to implement specially-tuned leakage mitigation pulses, which would otherwise add noise and cost to quantum computing.

[0086] To provide additional context for various implementations described herein, Figure 12 And the following discussion is intended to provide a brief, general description of a suitable computing environment 1200 in which various embodiments of the implementations described herein can be implemented. While the above has been described in the general context of computer-executable instructions of a computer program that runs on a computer, those skilled in the art will recognize that the embodiments also can be implemented in combination with other program modules and / or as a combination of hardware and software.

[0087] Generally, program modules include routines, programs, components, data structures, etc., that perform particular tasks or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputers, mainframe computers, Internet of Things (IoT) devices, distributed computing systems, as well as personal computers, hand-held computing devices, microprocessor-based or programmable consumer electronics, and the like, each of which can be operatively coupled to one or more associated devices.

[0088] The illustrated embodiments of the embodiments herein can also be implemented in a distributed computing environment, where certain tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

[0089] Computing devices typically include a variety of media, which can include computer-readable storage media, machine-readable storage media, and / or communications media, which two terms are used herein differently from one another. Computer-readable storage media or machine-readable storage media can be any available storage media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media. By way of example, and not limitation, computer-readable storage media or machine-readable storage media can be implemented in connection with any method or technology for storage of information such as computer-readable or machine-readable instructions, program modules, program data, or

[0090] Computer-readable storage media can include, but are not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD ROM), digital versatile disk (DVD), Blu-ray disc (BD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, solid state drives or other solid state storage devices, or other tangible and / or non-transitory media that can be used to store desired information. In this regard, the terms “tangible” or “non-transitory” herein as applied to storage, memory or computer-readable media, are to be understood to exclude only propagating transitory signals per se as modifiers and do not negate the

[0091] Computer-readable storage media can be accessed by one or more local or remote computing devices, such as via access requests, queries or other data retrieval protocols, for various operations with respect to the information stored on the media.

[0092] Communication media typically embody computer-readable instructions, data structures, program modules or other structured or unstructured data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery or transport media. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media.

[0093] Referring again to Figure 12The example environment 1200 for implementing various embodiments of the aspects described herein includes a computer 1202, which includes a processing unit 1204, a system memory 1206, and a system bus 1208. The system bus 1208 couples system components including, but not limited to, the system memory 1206 to the processing unit 1204. The processing unit 1204 can be any of various commercially available processors. Dual microprocessors and other multi-processor architectures can also be employed as the processing unit 1204.

[0094] The system bus 1208 can be any of several types of bus structures including an address bus, a data bus, a control bus, and a memory bus (with or without a memory controller), a peripheral bus, and a local bus using any of a variety of commercially available bus architectures. The system memory 1206 includes ROM 1210 and RAM 1212. A basic input / output system (BIOS) can be stored in a non-volatile memory such as ROM, erasable programmable read-only memory (EPROM), EEPROM, flash memory, or the like, which BIOS contains the basic routines that help to transfer information between elements within the computer 1202, such as during startup. The RAM 1212 can also include a high-speed RAM such as static RAM for caching data.

[0095] The computer 1202 further includes an internal hard disk drive (HDD) 1214 (e.g., EIDE, SATA), one or more external storage devices 1216 (e.g., a magnetic floppy disk drive (FDD) 1216, a memory stick or flash drive reader, a memory card reader, etc.), and a drive 1220, such as a solid state drive, an optical drive, which can read or write from a disk 1222, such as a CD-ROM disk, a DVD, a BD, etc. Alternatively, in cases involving a solid state drive, the disk 1222 would not be included unless separate. While the internal HDD 1214 is illustrated as being within the computer 1202, the internal HDD 1214 can also be configured for external use in an appropriate chassis (not shown). Additionally, while not shown in the environment 1200, a solid state drive (SSD) can be used in addition to or in place of the HDD 1214. The HDD 1214, external storage devices 1216, and drive 1220 can be connected to the system bus 1208 by a HDD interface 1224, an external storage interface 1226, and a drive interface 1228, respectively. The interface 1224 for external drive implementations can include at least one or both of Universal Serial Bus (USB) and Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technologies. Other external drive connection technologies are within the contemplation of the embodiments described herein.

[0096] The drive and its associated computer-readable storage medium provide non-volatile storage of data, data structures, computer-executable instructions, etc. For computer 1202, the drive and storage medium accommodate any data stored in a suitable digital format. Although the above description of computer-readable storage media refers to a corresponding type of storage device, those skilled in the art will understand that other types of computer-readable storage media (whether currently existing or developed in the future) may also be used in the example operating environment, and further, any such storage medium may contain computer-executable instructions for performing the methods described herein.

[0097] Multiple program modules can be stored in the drive and RAM 1212, including the operating system 1230, one or more application programs 1232, other program modules 1234, and program data 1236. All or part of the operating system, application programs, modules, and / or data may also be cached in RAM 1212. The systems and methods described herein can be implemented using different commercially available operating systems or combinations of operating systems.

[0098] Computer 1202 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary may emulate the hardware environment used for operating system 1230, and the emulated hardware may optionally be compatible with... Figure 12 The hardware shown is different. In this embodiment, the operating system 1230 may include one of a plurality of virtual machines (VMs) hosted at the computer 1202. Furthermore, the operating system 1230 may provide a runtime environment for the application 1232, such as the Java Runtime Environment or the .NET Framework. A runtime environment is a consistent execution environment that allows the application 1232 to run on any operating system that includes a runtime environment. Similarly, the operating system 1230 may support containers, and the application 1232 may be in the form of a container, which is a lightweight, standalone executable package that includes, for example, code, runtime, system tools, system libraries, and settings for the application.

[0099] Furthermore, computer 1202 can enable security modules, such as a Trusted Processing Module (TPM). For example, with TPM, before loading the next boot component, the boot component hashes the next boot component in time and waits for the result to match a security value. This process can occur at any layer of the computer 1202's code execution stack, for example, at the application execution level or at the operating system (OS) kernel level, thereby achieving security at any code execution level.

[0100] A user can enter commands and information into the computer 1202 through one or more wire / wireless input devices, e.g., a keyboard 1238, a touch screen 1240, and a pointing device, e.g., a mouse 1242. Other input devices (not shown) can include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control, an other remote control, a joystick, a virtual reality controller and / or virtual reality headset, a gamepad, a stylus, an image input device, e.g., a camera, a gesture sensor input device, a visual movement sensor input device, an emotion or facial detection device, a biometric input device, e.g., a fingerprint or iris scanner, or the like. These and other input devices are often connected to the processing unit 1204 through an input device interface 1244 that can be coupled to the system bus 1208, but can be connected by other interfaces, such as a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR interface, a Bluetooth® interface, etc.

[0101] A monitor 1246 or other type of display device can also be connected to the system bus 1208 via an interface, such as a video adapter 1248. In addition to the monitor 1246, a computer typically includes other peripheral output devices (not shown), such as speakers, printers, etc.

[0102] The computer 1202 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer(s) 1250. The remote computer(s) 1250 can be a workstation, a server computer, a router, a personal computer, portable computer, microprocessor-based entertainment appliance, a peer device or other common network node, and typically includes many or all of the elements described relative to the computer 1202, although, for purposes of brevity, only a memory / storage device 1252 is illustrated. The logical connections depicted include wire / wireless connectivity to a local area network (LAN) 1254 and / or larger networks, e.g., a wide area network (WAN) 1256. Such LAN and WAN networking environments are commonplace in offices and companies and facilitate enterprise-wide computer networks, such as intranets, all of which can connect to a global communications network, e.g., the Internet.

[0103] When used in a LAN networking environment, the computer 1202 can be connected to the local network 1254 through a wire / wireless communication network interface or adapter 1258. The adapter 1258 can facilitate wire or wireless communication to the LAN 1254, which can also include a wireless access point (AP) disposed therein for communicating with the adapter 1258 in wireless mode.

[0104] When used in a LAN-networking environment, the computer 1202 can be connected to the LAN 1254 through a network adapter 1258. When used in a WAN-networking environment, the computer 1202 can typically include a modem 1260 or other means for establishing communications over the WAN 1256, such as by telephone

[0105] When used in a LAN or WAN networking environment, the computer 1202 can access cloud storage systems or other network-based storage systems, in addition to or in place of external storage devices 1216 as described above, such as but not limited to network virtual machines providing one or more aspects of storage or processing of information. Generally speaking, connections between the computer 1202 and a cloud storage system can be established, for example, by the adapter 1258 or the modem 1260 over the LAN 1254 or the WAN 1256, respectively. In connecting the computer 1202 to an associated cloud storage system, the external storage interface 1226 can manage storage provided by the cloud storage system by means of the adapter 1258 and / or the modem 1260, as with other types of external storage. For example, the external storage interface 1226 can be configured to provide access to cloud storage sources as if those sources were physically connected to the computer 1202.

[0106] The computer 1202 can be operable to communicate with any wireless devices or entities operatively disposed in wireless communication, e.g., printers, scanners, desktop and / or portable computers, portable data assistants, communications satellites, any devices or effects associated with a wireless detectable tag (e.g., a kiosk, a news stand, a vendor cart, and / or the like), and telephones. This can include Wireless Fidelity (Wi-Fi) and BLUETOOTH® wireless technology. Thus, the communication can be a predefined structure as with a conventional network or simply an ad hoc communication between at least two devices.

[0107] Referring now to Figure 13, an illustrative cloud computing environment 1300 is described. As shown, cloud computing environment 1300 includes one or more cloud computing nodes 1302 with which a cloud consumer can engage with to use the cloud computing resources. Cloud computing nodes 1302 can communicate with one another. They can be grouped (not shown) physically or virtually, in one or more networks, such as Private, Community, Public, or Hybrid clouds as described hereinabove, or a combination thereof. This allows cloud computing environment 1300 to offer infrastructure, platforms and / or software as services with Figure 13 The types of computing devices 1304-1310 shown in

[0108] Referring now to Figure 14 , a set of functional abstraction layers provided by cloud computing environment 1300 Figure 13 is shown. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity. Figure 14 The components, layers, and functional abstraction layers shown in

[0109] Hardware and software layer 1402 includes hardware and software components. Examples of hardware components include: mainframes 1404; RISC (Reduced Instruction Set Computer) architecture based servers 1406; servers 1408; blade servers 1410; storage devices 1412; and networks and networking components 1414. In some embodiments, software components include network application server software 1416 and database software 1418.

[0110] Virtualization layer 1415 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual servers 1422; virtual storage 1424; virtual networks 1426, including virtual private networks; virtual applications and operating systems 1428; and virtual clients 1430.

[0111] In one example, management layer 1432 can provide the functions described below. Resource provisioning 1434 provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment. Metering and Pricing 1436 provide cost tracking as resources are utilized within the cloud computing environment, and billing or invoicing for consumption of these resources. In one example, these resources can include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal 1438 provides access to the cloud computing environment for consumers and system administrators. Service level management 1440 provides cloud computing resource allocation and management such that required service levels are met. Service Level Agreement (SLA) planning and fulfillment 1442 provide pre-arrangement for, and procurement of, cloud computing resources for which a future requirement is anticipated in accordance with an SLA.

[0112] Workloads layer 1444 provides examples of functionality for which the cloud computing environment can be utilized. Examples of workloads and functions which can be provided from this layer include: mapping and navigation 1446; software development and lifecycle management 1448; virtual classroom education delivery 1450; data analytics processing 1452; transaction processing 1454; and differential private federated learning processing 1456. Various embodiments of the present invention can utilize the cloud computing environment described with reference to Figure 13 and Figure 14 to perform one or more differential private federated learning processes in accordance with the different embodiments described herein.

[0113] The present application can be a system, a method, an apparatus and / or a computer program product at any possible technical detail level of integration. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present application. The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non- exhaustive list of more specific examples of the computer readable storage medium can also include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0114] The computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to external computers or external storage devices via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device. Computer readable program instructions for carrying out operations of the present application can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and a conventional procedural programming language such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computing / processing device, partly on the user's computing / processing device, as a stand-alone software package, partly on the user's computing / processing device and partly on a remote computing / processing device or entirely on the remote computing / processing device or server. In the latter scenario, the remote computing / processing device can be connected to the user's computing / processing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present application.

[0115] The present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operations to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0116] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0117] While the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on a computer and / or computer systems, those skilled in the art will recognize that the disclosure also can be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive computer-implemented methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputers, mainframe computers, as well as computers, hand-held computing devices (e.g., PDA, phone), microprocessor-based or programmable consumer or industrial electronics, etc. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. However, some if not all aspects of the application can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

[0118] As used in this application, the terms "component," "system," "platform," "interface," and the like can refer to and / or can include a computer-related entity or an entity that is related to an operational machine with one or more specific functionalities. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, co-resident, and / or distributed amongst one computer and / or across multiple computers. In another example, a component can execute from various computer readable media having various data structures stored thereon. The components can communicate via local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal). As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, which is operated by a software or firmware application running in a processor. In such a case, the processor can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts, wherein the electronic components can include a processor or other means to execute at least a portion of an software or firmware application that provides the component's functionality. In an aspect, a component can emulate the electronic components as a virtual machine(s) within a cloud computing system.

[0119] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied under any of the foregoing instances. Moreover, articles "a" and "an" as used in the subject specification and annexed drawings should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. As used herein, the terms "instance" and / or "exemplary" are used to mean as an example, instance, or illustration. For the avoidance of doubt, the subject matter of the present disclosure is not limited to the examples described herein. In addition, any aspect or design described herein as "instance" and / or "exemplary" is not necessarily meant to convey that it is the best or only design or implementation. Also, descriptions of examples using "comprising," "including," "containing," "carrying," "adapting," "configuring," or "plugging" to recite lists of elements are not meant to be exhaustive of other methods that can be substituted for the listed elements, as these methods are merely examples and are not to be seen as limiting.

[0120] As employed in this specification, the term "processor" can refer to substantially any computing processing unit or device comprising, but not limited to, a single-core processor; a single processor with software multithread execution capability; a multi-core processor; a multi-core processor with software multithread execution capability; a multi-core processor with hardware multithread technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field- programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a processor can utilize nano- scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. A processor can also be implemented as a combination of computing processing units. In the present disclosure, terms such as "store," "storage," "data store," data storage," "database," and substantially any other information storage component relevant to operation and functionality of a component are utilized to refer to "memory components," entities embodied in a "memory," or components comprising a memory. It is to be appreciated that memory and / or memory components described herein can be volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and without limitation, nonvolatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory can include, for example, RAM that can act as external cache memory. By way of illustration and not limitation, RAM can be available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), and Rambus dynamic RAM (RDRAM). Additionally, memory components of systems or computer-implemented methods disclosed herein are intended to comprise, without being limited to, these and any other suitable types of memory.

[0121] The above-described examples merely include examples of systems and computer-implemented methods. Of course, it is impossible to describe every conceivable combination or computer-implemented method of components for the purposes of describing the present disclosure, but one of ordinary skill in the art can recognize that many further combinations and permutations of the disclosure are possible. Moreover, to the extent that the terms "including", "having", "possessing", and the like are used in the detailed description, the claims, the appendices, and the drawings, they are intended to be inclusive and to the exclusion of equivalents thereof.

[0122] The description of the different embodiments has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technology found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A system for facilitating strategic pauses in quantum state leakage mitigation, comprising: a processor that executes computer-executable components stored in a computer- readable memory, the computer-executable components comprising: a detection component that detects quantum state leakage associated with one or more qubits; a pause component that generates a temporal pause prior to execution of a quantum circuit on the one or more qubits in response to detecting the quantum state leakage, wherein the detection component performs one or more quantum state measurements on the one or more qubits during the temporal pause, wherein the one or more quantum state measurements make a binary distinction between a ground state and an excited state; and an execution component that initiates execution of the quantum circuit on the one or more qubits during the temporal pause in response to the one or more quantum state measurements indicating that the one or more qubits are in the ground state.

2. The system of claim 1, wherein, the pause component generates the temporal pause after execution of a previous quantum circuit on the one or more qubits, wherein the quantum state leakage occurs during execution of the previous quantum circuit, and wherein the quantum state leakage decays during the temporal pause.

3. The system of claim 1 or 2, wherein, the one or more quantum state measurements further distinguish between different levels of the excited state having a lowest level of the different levels.

4. The system of claim 1 or 2, wherein, the execution component initiates the execution of the quantum circuit on the one or more qubits during the temporal pause in response to the one or more quantum state measurements indicating that the one or more qubits are in the ground state, a first excited state, or a combination of the ground state and the first excited state.

5. The system of claim 1 or 2, wherein, the pause component varies a duration of the temporal pause as a function of a maximum excited state detected by the detection component.

6. The system of claim 1 or 2, wherein, the duration of the temporal pause is greater than a coherence time of the one or more qubits.

7. The system of claim 6, wherein, the duration of the temporal pause is of the same order of magnitude as the coherence time of the one or more qubits.

8. A computer-implemented method for facilitating strategic pauses in quantum state leakage mitigation, comprising: detecting, by a device operatively coupled to a processor, quantum state leakage associated with one or more qubits; generating, by the device and prior to execution of a quantum circuit on the one or more qubits, a temporal pause in response to detecting the quantum state leakage; performing, by the device, one or more quantum state measurements on the one or more qubits during the temporal pause, wherein the one or more quantum state measurements make a binary distinction between a ground state and an excited state; and initiating, by the device, execution of the quantum circuit on the one or more qubits during the temporal pause in response to the one or more quantum state measurements indicating that the one or more qubits are in the ground state.

9. The computer-implemented method of claim 8, wherein, The temporal pause occurs after execution of a previous quantum circuit on the one or more qubits, wherein the quantum state leakage occurs during execution of the previous quantum circuit, and wherein the quantum state leakage decays during the temporal pause.

10. The computer-implemented method of claim 8 or 9, wherein, The one or more quantum state measurements further distinguish between the excited states having a first excited state of a lowest level of different levels.

11. The computer-implemented method of claim 8 or 9, wherein, The initiating includes initiating, by the processor, the execution of the quantum circuit on the one or more qubits during the temporal pause in response to the one or more quantum state measurements indicating that the one or more qubits are in the ground state, a first excited state, or a combination of the ground state and the first excited state.

12. The computer-implemented method of claim 8 or 9, further comprising: changing, by the device, a duration of the temporal pause based on a maximum excited state detected during the detecting.

13. The computer-implemented method of claim 8 or 9, wherein, The duration of the temporal pause is greater than a coherence time of the one or more qubits.

14. The computer-implemented method of claim 13, wherein, The duration of the temporal pause is of the same order of magnitude as a coherence time of the one or more qubits.

15. A computer program product for facilitating policy pause of quantum state leakage mitigation, the computer program product comprising a computer readable memory having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to: detect, by the processor, quantum state leakage associated with one or more qubits; generate, by the processor and in response to detecting the quantum state leakage, a temporal pause prior to execution of a quantum circuit on the one or more qubits; during the time pause, one or more quantum state measurements are performed by the processor on the one or more qubits, wherein, The one or more quantum state measurements further distinguish between the excited states having a first excited state of a lowest level of different levels. initiate, by the processor, execution of the quantum circuit on the one or more qubits during the temporal pause in response to the one or more quantum state measurements indicating that the one or more qubits are in the ground state.

16. The computer program product of claim 15, wherein, The processor generates the temporal pause after execution of a previous quantum circuit on the one or more qubits, wherein the quantum state leakage occurs during execution of the previous quantum circuit, and wherein the quantum state leakage decays during the temporal pause.

17. The computer program product of claim 15 or 16, wherein, The one or more quantum state measurements further distinguish between the excited states having a first excited state of a lowest level of different levels.

18. The computer program product of claim 15 or 16, wherein, The program instructions are further executable to cause the processor to: initiate, by the processor, the execution of the quantum circuit on the one or more qubits during the temporal pause in response to the one or more quantum state measurements indicating that the one or more qubits are in the ground state, a first excited state, or a combination of the ground state and the first excited state.

19. The computer program product of claim 15 or 16, wherein, The program instructions are further executable to cause the processor to: change, by the processor, a duration of the temporal pause based on a maximum excited state detected by the processor. The duration of the temporal pause is greater than a coherence time of the one or more qubits. The duration of the temporal pause is of the same order of magnitude as a coherence time of the one or more qubits.

20. The computer program product of claim 15 or 16, wherein, the duration of the temporal pause is greater than a coherence time of the one or more qubits, and wherein the duration of the temporal pause has the same order of magnitude as the coherence time of the one or more qubits.

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