A verification method for DMI-JTAG dual-end communication based on UVM

Abstract

The present invention discloses a kind of verification method of DMI-JTAG dual-end communication based on UVM, based on stimulus generation module, multiple driver modules, multiple monitors, comparator and DMI-JTAG module;The stimulus generation module generates the random instruction with constraint that meets JTAG protocol, produces the stimulus of JTAG terminal input, and when detecting that the generated JTAG terminal input is a read instruction, the response stimulus of DMI terminal is automatically generated and has been read back by JTAG terminal;Multiple driver modules drive the JTAG port and DMI port of DMI-JTAG module with the timing that meets JTAG protocol by the generated JTAG terminal input stimulus and DMI terminal input stimulus;Multiple monitors monitor the input and output of DMI-JTAG module and JTAG terminal;Comparator stores the input and output data of JTAG terminal and DMI terminal, and compares respectively.The present invention can verify DMI-JTAG module more conveniently, obtains the original stimulus with higher coverage, and supports input and output simultaneously at both ends of DMI-JTAG module under test.

Description

Technical Field

[0001] The present invention relates to the technical field of digital integrated circuit verification, and in particular to a UVM-based DMI-JTAG two-end communication verification method. Background Art

[0002] With the continuous development of the integrated circuit design field, the amount of code is increasing, the circuit scale is gradually expanding, and various bugs are more likely to appear in the circuit. The debugging time has become the most important part of the circuit design process for designers, greatly slowing down the tape-out progress of the integrated circuit.

[0003] Verification technology permeates the entire circuit design and tape-out process; verification continues even after tape-out, right up to customer delivery. Verification encompasses many different types, with RTL hardware logic functional verification being only a small part. A variety of verification languages ​​have emerged specifically for RTL verification alone. Currently, SystemVerilog is the most widely used verification language in the market. As verification has become increasingly systematized, verification methodologies integrating multiple functions have been developed based on these foundational languages. Initially, OVM and VMM became popular, but UVM has now become the mainstream verification method.

[0004] Shorter verification times can significantly increase tape-out speed, placing higher demands on the verification platform. As designs become increasingly complex, high coverage becomes increasingly difficult to achieve. Automated stimulus generation can reduce the time spent manually programming stimulus conditions. Currently, a basic UVM platform includes a sequencer, driver, monitor, RFmodel, and scoreboard. These platforms are typically only suitable for DUTs with single-ended input and output. Furthermore, when the DUT's input timing requirements are complex, traditional UVM platforms struggle to simulate the actual circuit timing. Their reusability is also poor, making it difficult to simulate the actual use of DUTs with multiple inputs and outputs under multiple clocks. Therefore, a highly reusable verification platform capable of implementing multiple timing logics is needed to address these issues. Summary of the Invention

[0005] The object of the present invention is to provide a verification method for DMI-JTAG two-end communication based on UVM, to solve the problem that the existing UVM platform cannot meet the complex timing of DMI-JTAG and the incentive generation coverage is low.

[0006] To solve the above technical problems, the present invention provides a UVM-based DMI-JTAG two-end communication verification method, based on an incentive generation module, multiple driver modules, multiple monitors, a comparator and a DMI-JTAG module;

[0007] The stimulus generation module generates random instructions with constraints that comply with the JTAG protocol. It not only generates the stimulus input by the JTAG end, but also automatically generates the response stimulus of the DMI end when it detects that the generated JTAG end input is a read instruction.

[0008] The plurality of driver modules are used to drive the jtag port and the dmi port of the dmi-jtag module with the generated jtag end input stimulus and the dmi end input stimulus in a timing sequence that complies with the jtag protocol;

[0009] Multiple monitors monitor the input and output of the DMI and JTAG terminals of the DMI-JTAG module;

[0010] The comparator stores the input and output data of the jtag end and the dmi end and compares them respectively.

[0011] In one embodiment, the stimulus generated by the stimulus generation module is specified in the data format of the jtag protocol and consists of an address field, an operation type field, and a data field.

[0012] In one embodiment, the comparator includes four FIFOs, which respectively store the input of the JTAG terminal, the output of the JTAG terminal, the input of the DMI terminal, and the output of the DMI terminal; the comparator compares the input of the JTAG terminal and the output of the DMI terminal, and compares the output of the JTAG terminal and the input of the DMI terminal through two comparison logics.

[0013] In one embodiment, the monitor samples input and output signals according to valid signals of input and output ports.

[0014] In one embodiment, the monitor integrates the sampled signals according to the format specified by the jtag protocol and then sends them to the comparator, rather than directly transmitting the sampled serial signals to the comparator.

[0015] In one embodiment, the driving timing of the driving module is specified according to the timing format of the jtag protocol.

[0016] In one embodiment, since the inputs at both ends have different clks, in order to drive the timing at the two input ends of the module with the correct sending timing, the driving timing is implemented by a mailbox mechanism.

[0017] The present invention provides a UVM-based DMI-JTAG two-end communication verification method with a more complete structure, more realistically simulating the characteristics of dual clocks of a DMI-JTAG module and simultaneous communication of both ends; and can autonomously generate a stimulus that complies with JTAG timing and specifications to drive a DUT under test, thereby reducing the manpower and time for stimulus writing and obtaining a higher verification coverage rate. In addition, the platform structure of the method is relatively clear, the method has strong reusability, and is compatible with the verification of various two-end input and output modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The present invention is a schematic diagram of a verification platform based on a verification method of UVM-based DMI-JTAG two-end communication.

[0019] Figure 2 A schematic diagram of the implementation sequence of a UVM-based DMI-JTAG two-end communication verification method proposed in the present invention. DETAILED DESCRIPTION

[0020] Below in conjunction with accompanying drawing and specific embodiment, the verification method of a kind of DMI-JTAG dual-end communication based on UVM proposed by the present invention is described in further detail.According to the following description, the advantages and features of the present invention will be clearer.It should be noted that the accompanying drawings all adopt very simplified form and all use non-precise scale, only for the purpose of conveniently and clearly assisting in explaining the embodiment of the present invention.

[0021] The present invention provides a UVM-based DMI-JTAG dual-end communication verification method, which mainly includes a stimulus generation module for generating constrained random instructions that comply with the JTAG protocol. The stimulus generation module does not generate a DMI-end input stimulus when the randomly generated JTAG-end stimulus is a write instruction; when the randomly generated JTAG-end stimulus is a read instruction, it simultaneously generates a DMI-end response stimulus to be read back by the JTAG end, thereby simulating the actual usage of the DMI-JTAG module in an integrated kernel system; when the JTAG-end instruction is a read instruction, the stimulus generation module can also be configured to generate an erroneous DMI-end response stimulus to simulate the unexpected situation of a JTAG end reading error in the kernel.

[0022] The system also includes more than one driver module for driving the generated stimulus to the input port of the DMI-JTAG module. When the instruction from the JTAG end is a write instruction, the driver module will drive the DMI end with a response of data 0 and status success to simulate the feedback of the JTAG end correctly writing in the actual kernel; when the instruction from the JTAG end is a read instruction, the driver module will drive the input stimulus of the JTAG end and the response stimulus of the DMI end at the appropriate time in a timing that complies with the JTAG protocol to simulate the actual usage timing of the DMI-JTAG module in the entire kernel system, and perform data feedback and read-back successful status feedback; this timing simulation will be implemented using a mailbox to ensure that the response stimulus of the DMI end is later than the input stimulus of the JTAG end, so as to ensure strict compliance with the timing requirements of the JTAG protocol, solving the problem of difficult timing control under multiple driver modules.

[0023] In addition, more than one monitor is included for monitoring the input and output of the DMI end and the JTAG end. The monitor will use the valid signals of the input and output of the two ports as the starting point of sampling to ensure the accuracy of sampling. Since the DMI end and the JTAG end can input and output each other, the present invention will use two sets of monitors to simultaneously monitor the input and output signals of the DMI end and the JTAG end. Each set of monitors includes an input monitor and an output monitor, and sends the monitored signals to the comparator. Since the data transmission mode of the JTAG end is serial transmission and the data transmission mode of the DMI end is parallel transmission, when the monitor detects the input signal of the JTAG end, it will not directly transmit it to the comparator. The monitor will integrate the monitored JTAG end signal in accordance with the timing and format requirements of the JTAG protocol, integrate the serial data into parallel data, and then send it to the comparator so that the comparator can perform direct comparison. The comparator contains four FIFOs, which store the input and output data of the JTAG end and the DMI end respectively. The write instruction driven from the JTAG end is compared with the instruction monitored from the DMI end. When the driving instruction of the JTAG end is a read instruction, the response data driven from the DMI end is compared with the data read back from the JTAG end.

[0024] like Figure 2 As shown, the specific implementation steps of using the method of the present invention to verify the DMI-JTAG module are as follows:

[0025] Step 1: Instantiate the DMI-JTAG module under test at the top layer and connect the DUT under test to the interface;

[0026] Step 2: Use the interface to connect the DMI-JTAG module's DMI-end signal to the first set of input and output monitors, connect the JTAG-end signal of the DMI-JTAG module to the second set of input and output monitors, and connect other modules that need to be connected in the platform;

[0027] Step 3: Adjust the timing of the input and output monitors according to the timing required by the JTAG protocol, use the valid signal of the input and output ports as the data receiving starting point, and format the data to be monitored in preparation for sending it to the comparator;

[0028] Step 4: According to the timing and specifications specified by the JTAG protocol, the format and timing of the stimulus generation module are constrained, and the number of times the stimulus is generated is set;

[0029] In step 5, use the makefile script to start the simulation, wait for the comparison results, and obtain the code coverage. If the coverage is not ideal, repeat step 4 to adjust the constraints and increase the number of times to improve the coverage. At the same time, in order to verify the wrong use case, you can adjust the constraints in step 4 or manually add wrong stimuli to ensure complete coverage of the entire verification process.

[0030] In summary, the UVM-based DMI-JTAG two-end communication verification method proposed in the present invention can effectively verify the DMI-JTAG module with data transmission between the two ends, strictly follows the JTAG protocol requirements, truly simulates the application of the DMI-JTAG module in the system, effectively saves manpower, and obtains complete coverage; at the same time, the present invention also has good code reusability, and can complete the verification of different types of multi-clock multi-terminal input and output modules.

[0031] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A UVM-based DMI-JTAG dual-end communication verification method, characterized in that: Based on stimulus generation module, multiple driver modules, multiple monitors, comparators and DMI-JTAG modules; The stimulus generation module generates random instructions with constraints that comply with the JTAG protocol. It not only generates the stimulus input by the JTAG end, but also automatically generates the response stimulus of the DMI end when it detects that the generated JTAG end input is a read instruction, which is read back by the JTAG end. Multiple driver modules are used to drive the JTAG port and DMI port of the DMI-JTAG module with the generated JTAG input stimulus and DMI input stimulus in a timing sequence that complies with the JTAG protocol; when the instruction from the JTAG end is a write instruction, the driver module will drive the DMI end with a response of data 0 and status success to simulate the feedback of the JTAG end correctly performing the write in the actual core; When the instruction from the jtag end is a read instruction, the driver module drives the input stimulus of the jtag end and the response stimulus of the dmi end in a timing sequence that complies with the jtag protocol, so as to simulate the actual usage timing of the dmi-jtag module in the entire core system, and perform data feedback and read-back success status feedback. The mailbox is used to complete the timing simulation to ensure that the response stimulus of the dmi end is later than the input stimulus of the jtag end, so as to ensure that the timing requirements of the jtag protocol are strictly met. Multiple monitors monitor the input and output of the DMI and JTAG ends of the DMI-JTAG module. The monitors use the valid input and output signals of the two ports as the start of sampling to ensure the accuracy of sampling. The DMI and JTAG ends input and output each other, and two sets of monitors are used to simultaneously monitor the input and output signals of the DMI and JTAG ends. Each set of monitors includes an input monitor and an output monitor, and sends the monitoring signals to the comparator. The data transmission mode of the JTAG end is serial transmission, and the data transmission mode of the DMI end is parallel transmission. When the monitor detects the input signal of the JTAG end, it integrates the monitored JTAG end signal in accordance with the timing and format requirements of the JTAG protocol, integrates the serial data into parallel data, and then sends it to the comparator for direct comparison. The comparator stores the input and output data of the jtag end and the dmi end and compares them respectively.

2. the verification method of the dmi-jtag double-ended communication based on UVM as claimed in claim 1, is characterized in that, The stimulus generated by the stimulus generation module is in accordance with the data format of the jtag protocol and consists of an address field, an operation type field and a data field.

3. the verification method of the dmi-jtag double-ended communication based on UVM as claimed in claim 1, is characterized in that, The comparator includes four fifos, which respectively store the input of the jtag end, the output of the jtag end, the input of the dmi end, and the output of the dmi end; the comparator compares the input of the jtag end and the output of the dmi end, and compares the output of the jtag end and the input of the dmi end through two comparison logics.

4. the verification method of the dmi-jtag double-ended communication based on UVM as claimed in claim 1, is characterized in that, Since the inputs at both ends have different clks, in order to drive the timing at the two input ends of the module with the correct sending timing, the driving timing is implemented by the mailbox mechanism.

Images