A deep neural network hardware accelerator device

Abstract

The application discloses a deep neural network hardware accelerator device, which comprises a matrix calculation core module, a vector calculation core module, an on-chip cache module, a direct memory access (DMA) data transmission controller module and a configurable interconnection network module; wherein the matrix calculation core module and the vector calculation core module support different reconfigurable options; the matrix calculation core module and the vector calculation core module are connected with a plurality of on-chip cache modules through the configurable interconnection network module; the reconfigurable options include a weight fixed data stream and an output fixed data stream; the reconfiguration modes include a reconfigurable data stream accelerator (RDA), a reconfigurable function accelerator (RFA) and a heterogeneous multi-data stream accelerator (HDA). The application can realize multiple reconfiguration modes at the same time and realize efficient processing of different DNN networks.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of deep neural network hardware accelerator, in particular to a reconfigurable neural network hardware accelerator hardware device. BACKGROUND

[0002] With the rapid growth of deep neural network (DNN) models and applications, many new deep neural network models not only broaden the application range, but also achieve better results in different technical fields. At the same time, with the breakthrough of DNN algorithm and network model architecture, the algorithm type and data transfer mode become more diversified. For example, light DNN network models such as Mobilenet (Sandler, Mark, et al. "Mobilenetv2: Inverted residuals and linear bottlenecks." Proceedings of the IEEE conference on computer vision and pattern recognition. 2018.) can perform network processing on low-power edge devices, which reduce the amount of calculation by using deep separable convolution. The recurrent neural network (RNN) model expands the network application to the language field, including speech and text processing tasks. The transformer network model uses new algorithms such as softmax and layer normalization (Layer Norm), and is superior to RNN and traditional CNN (convolutional neural network) models in multiple scenarios.

[0003] To efficiently process DNN models, researchers have designed various DNN hardware accelerators, targeting devices including ASIC, FPGA, CGRA, and other embedded devices. The typical hardware architecture of a DNN accelerator contains a large array of processing elements (PEs), some additional logic for activation and post-processing, and a large on-chip buffer for better data locality. Compared with traditional CPU and GPU architectures, DNN accelerators can achieve orders-of-magnitude performance and energy efficiency improvements. The PE array has a dedicated dataflow for DNN-related algorithms (e.g., matrix multiplication, convolution, activation function, etc.), and the accelerator hardware can use different spatial dataflow to achieve efficient data reuse, including systolic arrays (TPU (Norman P Jouppi et al. In-datacenter performance analysis of a tensor processing unit. In ISCA, 2017) and the like), multicast networks (Shidiannao (Z. Du, R. Fasthuber, T. Chen, P. Ienne, L. Li, T. Luo, X. Feng, Y. Chen, and O. Temam, “Shidiannao: shifting vision processing closer to the sensor,” in Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015) and the like), and tree-based structures (MAERI (H. Kwon, A. Samajdar, and T. Krishna, “MAERI: enabling flexible dataflow mapping over DNN accelerators via reconfigurable interconnects,” in Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018) and the like).

[0004] From the perspective of DNN hardware accelerator, one major challenge is how to implement high-performance algorithms for various DNN models and guarantee the ease of programming. The most basic DNN hardware accelerator uses fixed data flow and functions, and can only be applied to standard CNN models, making it difficult to handle various complex and diverse network models. In recent years, researchers have proposed many reconfigurable DNN accelerator hardware to support different network models using reconfiguration. Such accelerators can be divided into three types according to the method of reconfiguration: reconfigurable data flow accelerator (RDA), reconfigurable function accelerator (RFA), and heterogeneous multi-data flow accelerator (HDA). Reconfigurable data flow accelerator uses configurable switches to configure different data flows for different computing modes, such as Flexflow (Lu, Wenyan, et al. "Flexflow: A flexible dataflow accelerator architecture for convolutional neural networks." 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2017.) and MAERI. Reconfigurable function accelerator uses multiple computing units with variable functions, which are scheduled by a unified global controller to process DNN models. Configuration is achieved through a dedicated instruction set architecture (ISA), such as Cambricon, VTA, Brainwave. Heterogeneous multi-data flow accelerator integrates multiple accelerators (sub-cores) with different data flows or functions on a single chip. HDA (Kwon, Hyoukjun, et al. "Heterogeneous dataflow accelerators for multi-DNN workloads." 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, 2021.) and DNPU (Shin, Dongjoo, et al. "DNPU: An energy-efficient deep-learning processor with heterogeneous multi-core architecture." IEEE Micro 38.5 (2018): 85-93.) use this method. Different DNN layers use different data flows, and they can be scheduled to specific sub-cores with better performance.

[0005] However, existing reconfigurable DNN accelerators can only implement one of the three aforementioned reconfiguration schemes. A single reconfiguration approach is insufficient to address diverse DNN processing requirements. For example, RDA struggles with various types of convolutions, and RFA's performance is significantly lower than that of traditional fixed-dataflow accelerators. Therefore, current deep learning applications urgently require a DNN hardware accelerator that can simultaneously implement multiple reconfiguration methods, enabling the simultaneous processing of diverse deep neural network models. Summary of the Invention

[0006] In order to overcome the shortcomings of the above-mentioned prior art, the present invention proposes a deep neural network accelerator hardware device, which can simultaneously implement the above-mentioned three reconstruction methods (reconfigurable data flow accelerator (RDA), reconfigurable function accelerator (RFA) and heterogeneous multi-data flow accelerator (HDA)) of the neural network accelerator, so as to overcome the singleness of the reconstruction method implemented by the existing reconfigurable DNN accelerator hardware. It is a DNN hardware accelerator that can simultaneously implement multiple reconstruction methods and can simultaneously process various deep neural network model calculations.

[0007] For convenience, the following definitions are used in this invention:

[0008] RDA (Reconfigurable Dataflow Accelerator) Reconfigurable Dataflow Accelerator

[0009] RFA (Reconfigurable Functionality Accelerator)

[0010] HDA (Heterogeneous Multi-Dataflow Accelerator)

[0011] ALU (Arithmetic Logic Unit)

[0012] VALU vector calculation unit

[0013] PE (Processing Element) computing unit

[0014] IO (Input-Output)

[0015] WS (Weight Stationary) weighted fixed data flow

[0016] OS (Output Stationary) outputs fixed data stream

[0017] DMA(Direct Memory Access) directly memory access

[0018] RTL(Register Transistor Level) register transistor level circuit

[0019] AXI(Advanced eXtensible Interface) AXI bus protocol

[0020] MAC(Multiply Accumulation) multiply accumulation operation

[0021] ISA(Instruction Set Architecture) instruction set architecture

[0022] DDR double data rate synchronous dynamic random access memory

[0023] The technical scheme provided by the application is:

[0024] A deep neural network accelerator hardware device, comprising: a matrix calculation core module, a vector calculation core module, an on-chip cache module, a direct memory access (DMA) data transmission controller module and a configurable interconnection network module; wherein the matrix calculation core module and the vector calculation core module support different reconfigurable options; the reconfigurable options include weight fixed data flow and output fixed data flow; the reconfiguration mode includes reconfigurable data flow accelerator (RDA), reconfigurable function accelerator (RFA) and heterogeneous multi-data flow accelerator (HDA); the hardware reconfiguration characteristics of data flow, function and multi-module can be realized at the same time, and various types of neural network calculations can be processed.

[0025] The matrix calculation core module is constructed by using a standard systolic array architecture, the hardware structure is an N*N systolic array, and N^2 calculation units (PE) are included; the data flow changes between weight fixed data flow and output fixed data flow, and different matrix formats are supported; the matrix calculation core module can be used to directly run standard matrix multiplication, transpose matrix multiplication and convolution operation based on standard matrix multiplication and transpose matrix multiplication;

[0026] The vector calculation core module is formed by connecting M vector calculation units (VALU) in series, each VALU is composed of N parallel arithmetic logic units (ALU); each ALU has an output register; the ALU has a configurable vector operation function, and is configured for various data reuse modes through ALU interconnection; the vector calculation core module includes three input ports and one output port; the input port and the output port are connected with the cache; the vector calculation core module is used to execute unary operation, binary operation and ternary operation; the vector calculation core module supports reconfiguration of different reconfigurable data flows and various different operands.

[0027] The DMA data transmission controller module comprises a memory access address generator and an AXI bus protocol interface, which are used for communication between the accelerator and external storage, and realize data exchange in the on-chip cache and the off-chip DDR at the same time.

[0028] The reconfigurable interconnection network module is used for controlling the data movement mode between the on-chip cache module and the two computing core modules, and sending corresponding configuration information to each of the other modules; the matrix computing core module and the vector computing core module are connected with a plurality of on-chip cache modules through the reconfigurable interconnection network module.

[0029] The on-chip cache module comprises a plurality of on-chip cache groups; each on-chip cache group (BUFG) comprises three cache units; the cache units are used for saving matrix data loaded from outside the accelerator; each cache unit has a plurality of storage areas corresponding to a plurality of data ports in each computing core and the DMA data transmission controller.

[0030] Compared with the prior art, the beneficial effects of the present application are as follows:

[0031] The existing reconfigurable DNN accelerator can only realize one of three reconfiguration schemes of a reconfigurable data flow accelerator (RDA), a reconfigurable function accelerator (RFA) and a heterogeneous multi-data flow accelerator (HDA). However, a single reconfiguration mode is difficult to cope with various DNN processing requirements. The deep neural network accelerator hardware device provided by the present application comprises a matrix computing core module, a vector computing core module, an on-chip cache module, a direct memory access (DMA) data transmission controller module and a reconfigurable interconnection network module; different reconfiguration options are supported by designing the matrix computing core module and the vector computing core module, so that multiple reconfiguration modes can be realized at the same time, and various deep neural network model calculations can be processed at the same time. The present application supports multiple reconfiguration schemes, and realizes efficient processing of different DNN networks. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 The structure block diagram of the deep neural network hardware accelerator provided by the present application is shown.

[0033] Figure 2 The hardware structure block diagram of the matrix computing core module of the deep neural network hardware accelerator is shown.

[0034] Figure 3 The internal data path schematic diagram of two data streams is shown; Reg B and Reg C are registers for saving fixed data.

[0035] Figure 4 The hardware structure block diagram of the computing core module is shown; PA, PB and PC are input ports, and PD is an output port.

[0036] Figure 5 Figure 2 is a schematic diagram of data flow supported by the vector calculation core module; where Elem represents data element, ALU represents arithmetic logic unit. DETAILED DESCRIPTION

[0037] The application will be further described by examples with reference to the accompanying drawings, but the scope of the application is not limited in any way.

[0038] The application provides a deep neural network hardware accelerator structure device. The overall hardware structure of the deep neural network hardware accelerator includes five main modules, namely a matrix calculation core module, a vector calculation core module, an on-chip cache module, a direct memory access (DMA) data transmission controller module, and a configurable interconnection network module. Each calculation core (matrix calculation core, vector calculation core) supports different reconfigurable options. Among them, the matrix calculation core supports two data flow reconfigurable options, including a weight fixed data flow WS and an output fixed data flow OS. The vector calculation core supports reconfiguration of different data flows and a plurality of different operands (supports reconfiguration of four different data flows and eleven different operands).

[0039] Among them, the matrix calculation core module requires less reconfigurability, but also requires smaller overhead to achieve high performance, while the vector calculation core module requires higher reconfigurability to achieve operation diversity. The matrix calculation core module is constructed using a standard systolic array architecture, but the data flow can be changed between the weight fixed data flow WS and the output fixed data flow OS to support different matrix formats. The vector calculation core module includes a plurality of vector arithmetic logic units (ALU units), the ALU units have configurable vector operation functions, and the ALU unit interconnections can be configured for a plurality of data reuse modes. The two calculation cores run simultaneously in different configurations. In addition, the DMA data transmission controller module can also exchange data between the on-chip cache and the off-chip DDR (main memory). The reconfigurable interconnection network module is used to control the data movement between the on-chip cache module and the two calculation cores, and sends corresponding configuration information to each module. The overall hardware structure is shown in the accompanying Figure 1 Figure 1 : The matrix calculation core module and the vector calculation core module are connected to a plurality of on-chip cache modules through a configurable interconnection network. At the same time, the DMA data transmission controller is used for communication between the accelerator and the external storage. The specific structure of each module is introduced below.

[0040] 1) Hardware structure of the matrix calculation core module.

[0041] The hardware structure of the matrix calculation core module is an N*N systolic array, containing N^2 PEs, and supporting OS and WS data streams simultaneously; used for calculating matrix multiplication and addition operations, including running standard matrix multiplication, transposed matrix multiplication, and convolution operation based on the two kinds of matrix multiplication;

[0042] Figure 2 The hardware structure of the matrix calculation core module is shown. It is an N*N systolic array, containing N^2 PEs, and supporting OS and WS data streams simultaneously. It is used for calculating matrix multiplication and addition operations D=A×B+C (A, B, C, and D are all matrices). A is an input matrix from the top side, B and C are input matrices from the left side, and D is an output matrix from the right side. Figure 3 The internal data path of the PE is shown (the pipeline register is omitted), wherein Reg B and Reg C are registers for storing fixed data. The code of the convolution algorithm represented by the 6-layer loop is as follows:

[0043]

[0044] Among them, taking the C_o, C_i, and W three loops, it can be expressed as D[co,w]=A[ci,w]×B[co,ci]+C[co,w] matrix multiplication and addition operation. Among them, C_o represents the output channel number, C_i represents the input channel number, and W represents the feature map width. When configured as a WS data stream, map C_o and C_i to the PE array in parallel execution, that is, when the C_o loop subscript is co and the C_i loop subscript is ci, the corresponding calculation is performed in the PE in the co row and the ci column. The matrix B (the weight matrix of C_o×C_i) is preloaded into the Reg B of each PE, and then the matrix A (the input matrix of C_i×W) flows vertically from top to bottom for W cycles to perform multiplication. The matrix D (the output matrix of C_o×W) is accumulated from left to right in each PE. When configured as an OS data stream, map C_o and W to the PE array in parallel calculation, that is, when the C_o loop subscript is co and the W loop subscript is w, the corresponding calculation is performed in the PE in the co row and the w column. The matrix D is accumulated in the PE, and the execution time becomes C_i. In this case, the matrix C is preloaded into the Reg C of each PE and is accumulated with the output of the multiplier. The shape of the matrix A is transposed as A^T, which flows vertically from top to bottom. The matrix B flows from left to right. When the accumulation is completed, the matrix D is output from the Reg C and saved to the on-chip cache module. At this time, the PE array performs transposed matrix multiplication D=A^T×B+C. T is the transpose symbol.

[0045] The reconstruction of data flow does not change the communication direction of each matrix between PEs, but only changes the data communication behavior inside each PE, so the hardware overhead is small. Standard convolution operation (using NHWC format) does not involve transpose matrix multiplication, but transpose matrix multiplication is used in NCHW format convolution and Attention calculation in Transformer network. Therefore, the matrix calculation core module proposed by us can directly run standard matrix multiplication, transpose matrix multiplication, and convolution operation based on the two kinds of matrix multiplication.

[0046] 2) Hardware structure of vector calculation core module.

[0047] The vector calculation core module is composed of M vector calculation units (VALU) in series, and each VALU is composed of N parallel arithmetic logic units (ALU); each ALU has an output register;

[0048] The vector calculation core module includes 3 input ports and 1 output port; the input port and the output port are connected with the cache;

[0049] The vector calculation core module is used to execute unary operation, binary operation and ternary operation; supports reconfigurable data flow, and realizes on-chip data reuse;

[0050] Figure 4 The hardware structure of the vector calculation core is shown. The hardware is composed of M vector calculation units (VALU) in series, and each VALU is composed of N parallel ALUs. Each VALU uses the immediate number provided by the unified operand and configuration file, but the input data comes from different positions of the length N vector. Each ALU contains a multifunctional calculation unit (MFU) which can execute unary operation (log, exp, sigmoid, etc. implemented by lookup table), binary operation (add, sub, mul, min, max, shr, shl, etc.) and ternary operation (MAC) configured by operands. The vector calculation core module has 3 input ports (PA, PB, PC) and 1 output port PD. The input ports PA, PB, PC take out the tensor data from the cache with the corresponding name in each cache group to the first VALU, and the output of the last VALU is written back to the cache connected with the port PD.

[0051] The architecture of the vector calculation core module can support flexible reconfigurable data flow to realize efficient on-chip data reuse, as shown in Figure 5 Each operand can select one data flow from the following four data flow options:

[0052] 2a) Horizontal pulsation. The input of each VALU is connected to the output of the previous VALU. It can be used for chain element operation or data transfer of systolic array.

[0053] 2b) Hold. Data is held in each ALU for a period of time. It can be used for weight holding data stream of input operand, or multi-cycle accumulation operation of output operand.

[0054] 2c) Horizontal broadcast. The input of M ALUs in a VALU is the same value broadcast from the input port, but each ALU in a VALU uses N different values.

[0055] 2d) Vertical broadcast. The same value is broadcast vertically to fill N ALUs in each VALU. Different VALUs receive M different values from the input port.

[0056] Horizontal pulsation and hold data stream also support two modes: update mode and bypass mode. Each ALU has an output register. In update mode, the output register is updated with the output value of the ALU and forwarded to the next ALU (horizontal pulsation data stream) or retained in the current ALU (hold data stream). In bypass mode, data is only sent to the ALU, but the result is not updated to the register. Horizontal or vertical broadcast data stream is only used for input operand, not for output operand, so they only support bypass mode.

[0057] 3) Hardware structure of on-chip cache module and DMA data transfer controller.

[0058] The on-chip cache module includes a plurality of on-chip cache groups; each on-chip cache group (BUFG) contains three cache units; for saving matrix data loaded from outside the accelerator; the DMA data transfer controller includes a memory access address generator and an AXI interface, for data exchange between the accelerator outside the DDR storage and the on-chip cache module.

[0059] The on-chip cache module is also composed of a plurality of cache groups. Each cache group (BUFG) contains three cache units (named BUFA, BUFB, BUFC), each cache unit has N storage areas corresponding to N data ports in each computing core and DMA data transfer controller. The DMA data transfer controller includes an AXI interface and a memory access address generator, which reads and writes data with the external DDR storage through the AXI interface, and generates the access address of the DDR and the access address of the accelerator cache unit through the memory access address generator, for writing the data of the corresponding address in the DDR storage to the accelerator, or writing the data of the accelerator back to the DDR. The internal finite state machine (FSM) is used in the memory access address generator, which can generate different address signals in each cycle.

[0060] The data transmission between the two computing cores, the DMA and the on-chip cache groups of the on-chip cache module is realized through a configurable crossbar switch. Each computing core generates cache read / write requests through data input tensor ports PA, PB, PC and output port PD, and sends the requests to the corresponding on-chip cache groups according to the crossbar switch configuration. In order to reduce the complexity of the multiplexer in the crossbar switch while maintaining the flexibility of the interconnection, the input tensor ports PA, PB, PC can only load data from any cache group with the same buffer name (for example, the input tensor port PA can only read data from the cache unit BUFA of each cache group), while the output port PD of each computing core and the port of the DMA data transmission controller can write to any cache unit of any cache group. The DMA and the two computing core modules can work in parallel to realize double buffering and producer-consumer reuse between computing units. The hardware configuration code must prevent concurrent read / write requests of different computing and DMA modules to the same buffer to avoid data conflicts in the storage area.

[0061] The present application is implemented by using Chisel hardware design language to realize the hardware register behavior description (RTL) code of each module, which can be used for configuration writing, simulation, synthesis and layout in chip design process.

[0062] It should be noted that the purpose of publishing the embodiments is to help further understand the present application, but those skilled in the art can understand that various replacements and modifications are possible without departing from the scope of the present application and the appended claims. Therefore, the present application should not be limited to the disclosed content of the embodiments, and the scope of protection claimed by the present application is defined by the scope of the claims.

Claims

1. A deep neural network hardware accelerator apparatus, characterized by, Comprise: a matrix calculation core module, a vector calculation core module, an on-chip cache module, a direct memory access (DMA) data transfer controller module, and a configurable interconnection network module; wherein the matrix calculation core module and the vector calculation core module support different reconfigurable options; the reconfigurable options include fixed weight data flow and fixed output data flow; the reconfiguration modes include reconfigurable data flow accelerator (RDA), reconfigurable function accelerator (RFA), and heterogeneous multi-data flow accelerator (HDA); The matrix calculation core module is constructed using a standard systolic array architecture, and the hardware structure is an N×N systolic array, including N^2 computing units (PEs); the data flow changes between fixed weight data flow and fixed output data flow, and supports different matrix formats; the matrix calculation core module is used to directly run standard matrix multiplication, transpose matrix multiplication, and convolution operation based on standard matrix multiplication and transpose matrix multiplication; The vector calculation core module is composed of M vector calculation units (VALU) in series, and each VALU is composed of N parallel arithmetic logic units (ALU); each ALU has an output register; the ALU has a configurable vector operation function, and is configured for multiple data reuse modes through ALU interconnection; the vector calculation core module includes 3 input ports and 1 output port; the input port and the output port are connected with the cache; the vector calculation core module is used to perform unary operation, binary operation and ternary operation; different reconfigurable data flows and multiple different operands are supported through the vector calculation core module; The DMA data transfer controller module includes a memory access address generator and an AXI bus protocol interface, which is used for communication between the accelerator and the external storage, and realizes simultaneous exchange of data in the on-chip cache and the off-chip DDR; The reconfigurable interconnection network module is used to control the data movement mode between the on-chip cache module and the two calculation core modules, and sends corresponding configuration information to each module; the matrix calculation core module and the vector calculation core module are connected with multiple on-chip cache modules through the reconfigurable interconnection network module; The on-chip cache module includes multiple on-chip cache groups (BUFG); each on-chip cache group includes three cache units; used to save the matrix data loaded from the outside of the accelerator; each cache unit has multiple storage areas corresponding to multiple data ports in each calculation core and the DMA data transfer controller.

2. The deep neural network hardware accelerator apparatus of claim 1, wherein, The vector calculation core module supports reconfiguration of 4 different data flows and 11 different operands.

3. The deep neural network hardware accelerator apparatus of claim 1, wherein, The matrix calculation core module and the vector calculation core module are configured and run at the same time.

4. The deep neural network hardware accelerator apparatus of claim 1, wherein, The matrix calculation core module is used to calculate the matrix multiplication operation D=A×B+C; wherein A is the input matrix from the top, B and C are the input matrices from the left, and D is the output matrix from the right.

5. The deep neural network hardware accelerator apparatus of claim 1, wherein, The reconfiguration of the data flow does not change the communication direction of the matrix between the PEs, only changes the data communication inside each PE, and the hardware overhead is small.

6. The deep neural network hardware accelerator apparatus of claim 1, wherein, In the hardware structure of the vector calculation core module, each ALU includes a multifunctional calculation unit (MFU) for performing unary operation, binary operation and ternary operation, which is configured by operands; the vector calculation core module includes 3 input ports and 1 output port; the input ports are used for taking out tensor data from the cache corresponding to the name in each cache group to the first VALU; the output of the last VALU is written back to the cache connected with the output port.

7. The deep neural network hardware accelerator apparatus of claim 1, wherein, In the vector calculation core module, each operand selects a data stream from the following data stream options: 2a) horizontal pulsation: the input of each VALU is connected to the output of the previous VALU, which is used for chain element operation or data transmission of the pulsation array; 2b) keep still: the data remains still in each ALU for a period of time, which is used for weight keeping data stream of the input operand or multi-cycle accumulation operation of the output operand; 2c) horizontal broadcast: the input of M VALUs is the same value broadcast from the input port, and each ALU in the VALU uses N different values; 2d) vertical broadcast: the same value is broadcast vertically to fill the ALU in each VALU; different VALUs receive M different values from the input port.

8. The deep neural network hardware accelerator apparatus of claim 7, wherein, The two data streams of horizontal pulsation and stillness support two modes: update mode and bypass mode; in the update mode, the output register is updated with the output value of the ALU, which is forwarded to the next ALU for the horizontal pulsation data stream; for the keep still data stream, it is kept in the current ALU; In the bypass mode, the data is only sent to the ALU without updating to the register.

9. The deep neural network hardware accelerator apparatus of claim 7, wherein, The horizontal broadcast or vertical broadcast data stream only supports the bypass mode.

10. The deep neural network hardware accelerator apparatus of claim 1, wherein, The DMA data transmission controller reads and writes data with the external DDR storage through the AXI interface, generates the access address of the DDR and the access address of the accelerator cache unit through the memory address generator, and is used for writing the data of the corresponding address in the DDR storage into the accelerator, or writing the data of the accelerator back to the DDR.

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