GOA Circuit, GOA Unit, Driving Method Thereof, and Array Substrate

Abstract

The present invention relates to a GOA circuit, a GOA unit, a driving method thereof, and an array substrate, belonging to the field of display technology. The GOA circuit is composed of N cascaded GOA units. The first-stage GOA unit is started by a start signal SIN, and the nth-stage GOA unit is started by an output signal Cout(n-1) of the (n-1)th-stage GOA unit. Among the cascaded GOA units, odd-stage GOA units are connected to a first clock signal SCLK1 and a second clock signal SCLK2 as control signals, and even-stage GOA units are connected to a third clock signal SCLK3 and a fourth clock signal SCLK4 as control signals. In the present invention, the GOA unit is paired with a specific driving timing, which can quickly charge the output signal, and at the same time can solve the problems of slow charging of the traditional GOA circuit in DC driving and inability to achieve full-swing output, as well as the problem of leakage of the output signal.

Description

Technical Field

[0001] The present invention belongs to the technical field of display, and relates to a GOA circuit, a GOA unit, a driving method thereof, and an array substrate. Background Art

[0002] GOA (Gate Driver on Array) technology is a technology that uses the existing thin-film transistor array manufacturing process to fabricate a gate driver circuit on an array substrate to achieve progressive scanning of scan lines. However, the output module of the existing GOA circuit uses DC drive and cannot output with a full swing due to the slow charging speed. After long-term operation, the threshold voltage of the thin-film transistor drifts easily, resulting in leakage, and then causing the GOA circuit to malfunction.

[0003] Therefore, there is an urgent need for a new GOA circuit to solve the problems of slow charging in DC drive and leakage in the traditional GOA circuit after the threshold voltage of the thin-film transistor drifts. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a GOA circuit, a GOA unit, a driving method thereof, and an array substrate, so as to solve the problems that the traditional circuit cannot output with a full swing due to slow charging in DC drive and leakage of the output signal.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] Solution 1: A GOA unit includes thin-film transistors T1 to T12 and capacitors C1 to C3;

[0007] The gate of thin-film transistor T1 is connected to a clock signal, and its source is connected to a start signal. Its drain is respectively connected to the source of thin-film transistor T2 and the drain of T3. The gate of thin-film transistor T2 is connected to a clock signal, and its drain is connected to the third node Q0. The gate and source of thin-film transistor T3 are both connected to the drain of thin-film transistor T9. The source of thin-film transistor T4 is connected to a clock signal, its gate is connected to the third node Q0, and its drain is connected to the fourth node Q1. The gate of thin-film transistor T5 is connected to the second node QB, its source is connected to a voltage signal, and its drain is connected to the fourth node Q1. The gate of thin-film transistor T6 is connected to the second node QB, its source is connected to a voltage signal, and its drain is connected to the first node Q. The gate of thin-film transistor T7 is connected to the third node Q0, its source is connected to a start signal, and its drain is connected to the second node QB. The gate of thin-film transistor T8 is connected to a clock signal, its source is connected to a voltage signal, and its drain is connected to the second node QB. The gate of thin-film transistor T9 is connected to the first node Q, its source is connected to a voltage signal, and its drain is connected to the drain of thin-film transistor T10. The gate of thin-film transistor T10 is connected to the second node QB, and its source is connected to a voltage signal. The gate of thin-film transistor T11 is connected to the first node Q, its source is connected to a voltage signal, and its drain is connected to the drain of thin-film transistor T12. The gate of thin-film transistor T12 is connected to the second node QB, and its source is connected to a voltage signal. One end of capacitor C1 is connected to the third node Q0, and the other end is connected to the fourth node Q1. One end of capacitor C2 is connected to the fourth node Q1, and the other end is connected to the first node Q. One end of capacitor C3 is connected to the second node QB, and the other end is connected to the source of thin-film transistor T10.

[0008] Among them, the timing signal, voltage signal, and start signal are all provided by the timing controller.

[0009] Optionally, the thin-film transistor can be replaced by a field-effect transistor or other devices with the same characteristics. The source and drain of the transistor used here are symmetric, and the source and drain can be interchanged. The middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.

[0010] Solution 2: A GOA circuit includes N GOA units arranged in cascade, where N is a positive integer. The first-stage GOA unit is started by the start signal SIN, and the nth-stage GOA unit is started by the output signal Cout(n - 1) of the (n - 1)th-stage GOA unit, where n is a positive integer and 1 < n < N - 1.

[0011] In the cascade-connected GOA units, the odd-stage GOA units are connected to the first clock signal SCLK1, the second clock signal SCLK2, the constant high-voltage signal VGH, the first constant low-voltage signal VGL1, and the second constant low-voltage signal VGL2.

[0012] The even-level GOA units are connected to a third clock signal SCLK3, a fourth clock signal SCLK4, a constant high-voltage signal VGH, a first constant low-voltage signal VGL1, and a second constant low-voltage signal VGL2.

[0013] In the nth-level GOA unit, the source of the thin-film transistor T1 is connected to a start signal Cout(n - 1), and the Cout(n - 1) signal is the output signal of the previous-level GOA unit; the sources of the thin-film transistors T5 and T10 are connected to the first constant low-voltage signal VGL1; the sources of the thin-film transistors T6 and T12 are connected to the second constant low-voltage signal VGL2; the sources of the thin-film transistors T8, T9, and T11 are connected to the constant high-voltage signal VGH.

[0014] Optionally, in the odd-level GOA units, the gates of the thin-film transistors T1, T2, and T8 are all connected to a first clock signal SCLK1, and the source of the thin-film transistor T4 is connected to a second clock signal SCLK2; in the even-level GOA units, the gates of the thin-film transistors T1, T2, and T8 are all connected to a third clock signal SCLK3, and the source of the thin-film transistor T4 is connected to a fourth clock signal SCLK4.

[0015] Optionally, the driving timing of the nth-level GOA unit sequentially includes:

[0016] (1) Stage t1: The clock signal SCLK1(n) and the start signal Cout(n - 1) provide high potentials, and the clock signal SCLK2(n) provides a low potential;

[0017] (2) Stage T2: The clock signal SCLK2(n) provides a high potential, and the clock signal SCLK1(n) and the start signal Cout(n - 1) provide low potentials;

[0018] (3) Stage T3: The clock signal SCLK1(n) provides a high potential, and the clock signal SCLK2(n) and the start signal Cout(n - 1) provide low potentials;

[0019] (4) Stage T4: The clock signal SCLK2(n) provides a high potential, and the clock signal SCLK1(n) and the start signal Cout(n - 1) provide low potentials.

[0020] Among them, when n is odd, the clock signal SCLK1(n) represents the first clock signal SCLK1, and the clock signal SCLK2(n) represents the second clock signal SCLK2; when n is even, the clock signal SCLK1(n) represents the third clock signal SCLK3, and the clock signal SCLK2(n) represents the fourth clock signal SCLK4.

[0021] Solution 3, a driving method for a GOA unit, includes the following steps:

[0022] S1. Enter the t1 stage: The clock signal SCLK1(n) and the start signal Cout(n - 1) provide high potentials, the clock signal SCLK2(n) provides a low potential, turning on thin-film transistors T1, T2, T4, T5, T6, T7, T8, T10, and T12, and turning off thin-film transistors T3, T9, and T11; The third node Q0 is charged to a high level VGH - Vth1 - Vth2 through thin-film transistors T1 and T2, where Vth1 and Vth2 represent the on-voltages of thin-film transistors T1 and T2 respectively; The second node QB is charged to a high level through thin-film transistors T7 and T8; The first node Q is discharged to a low level VGL2 through thin-film transistor T6; The fourth node Q1 is discharged to a low level VGL1 through thin-film transistor T6;

[0023] S2. Enter the t2 stage: The clock signal SCLK2(n) provides a high potential, the clock signals SCLK1(n) and the start signal Cout(n - 1) provide low potentials, turning on thin-film transistors T3, T4, T7, T9, and T11, and turning off thin-film transistors T1, T2, T5, T6, T8, T10, and T12; The third node Q0 rises to a potential higher than VGH, 2VGH - VGL - Vth1 - Vth7 - Vth8, through the capacitive coupling effect of capacitor C1, and makes thin-film transistors T4 and T7 fully turn on, where Vth7 and Vth8 represent the on-voltages of thin-film transistors T7 and T8 respectively; The fourth node Q1 is charged to a high level through thin-film transistor T4, and under the capacitive coupling effect of capacitor C2, the first node Q rises to a potential higher than VGH, VGH - VGL1 + VGL2; The second node QB is discharged to a low level VGL1 through thin-film transistor T7;

[0024] S3. Enter the t3 stage: The clock signal SCLK1(n) provides a high potential, the clock signals SCLK2(n) and the start signal Cout(n - 1) provide low potentials, turning on thin-film transistors T1, T2, T5, T6, T8, T10, and T12, and turning off thin-film transistors T3, T4, T7, T9, and T11; The third node Q0 is discharged to a low level VGL1 through thin-film transistors T1 and T2; The fourth node Q1 is discharged to a low level VGL1 through thin-film transistor T5; The first node Q is discharged to a low level VGL2 through thin-film transistor T6; The VGH signal is transmitted to the second node QB through thin-film transistor T8 and charges capacitor C3; The voltage of the second node QB is equal to VGH - Vth8;

[0025] S4. Enter the t4 stage: The clock signal SCLK2(n) provides a high potential, and the clock signals SCLK1(n) and the start signal Cout(n - 1) provide low potentials, turning on thin film transistors T5, T6, T10, and T12 and turning off thin film transistors T1, T2, T3, T4, T7, T8, T9, and T11; the first node Q maintains a low level VGL2; the second node QB maintains a high level VGH - Vth8.

[0026] Solution 4. An array substrate includes a display area and a non - display area, and a GOA circuit is provided in the non - display area.

[0027] Solution 5. A display device includes an array substrate.

[0028] The beneficial effects of the present invention are as follows: The present invention can use the coupling effect of capacitor C2 to pull up the potential of the first node in the t2 stage, making the potential of the first node higher than the VGH level, fully turning on thin film transistors T9 and T11, and quickly charging the output signal; at the same time, pulling down the voltage of the second node to the VGL1 level lower than VGL2, completely turning off the pull - down output thin film transistor, suppressing the leakage of the output signal to the pull - down output thin film transistor, solving the problems of slow charging in the traditional circuit's DC drive and inability to achieve full - swing output, as well as the problem of output signal leakage, ensuring that the GOA circuit realizes full - swing output and still can work normally after the threshold voltage drifts due to the long - term operation of the thin film transistors. In addition, the circuit also adopts a DC output module, reducing the dynamic power consumption caused by large - size pull - up transistors, which is beneficial to reducing the power consumption of the GOA circuit.

[0029] Other advantages, objectives, and features of the present invention will be described to some extent in the following description, and to some extent, will be obvious to those skilled in the art based on the study of the following text, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. Description of the Drawings

[0030] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described in detail and preferably with reference to the accompanying drawings, where:

[0031] Figure 1 is a schematic structural diagram of the display device provided by the present invention;

[0032] Figure 2 is a timing diagram of the GOA circuit;

[0033] Figure 3 is a circuit structure diagram of the 12T3C GOA unit;

[0034] Figure 4It is a timing diagram of a 12T3C GOA unit. Specific implementation manners

[0035] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0036] Among them, the attached drawings are only for illustrative purposes, showing only schematic diagrams, not physical diagrams, and should not be construed as a limitation to the present invention; in order to better illustrate the embodiments of the present invention, some components in the attached drawings will be omitted, enlarged or reduced, and do not represent the dimensions of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the attached drawings may be omitted.

[0037] In the attached drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship, it is based on the orientation or positional relationship shown in the attached drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the attached drawings are only for illustrative purposes and should not be construed as a limitation to the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0038] As Figure 1 shown is a schematic structural diagram of a display device proposed by the present invention. The display device includes a display area and a non-display area, and the GOA circuit is arranged in the non-display area.

[0039] Among them, the GOA circuit includes N - stage cascaded GOA units, and the N - stage GOA units can be distributed on one side or two opposite sides of the display device. Among the N - stage GOA units, the odd - numbered GOA units are connected to the first clock signal SCLK1, the second clock signal SCLK2, the constant high - voltage signal VGH, the first constant low - voltage signal VGL1, and the second constant low - voltage signal VGL2; the even - numbered GOA units are connected to the third clock signal SCLK3, the fourth clock signal SCLK4, the constant high - voltage signal VGH, the first constant low - voltage signal VGL1, and the second constant low - voltage signal VGL2. Among the N - stage GOA units, except that the first - stage GOA unit is started by the start signal SIN, the remaining GOA units are all started by the output signal Cout of the previous - stage GOA unit, that is, the output signal Cout(n - 1) of the (n - 1) - th stage GOA unit serves as the start signal of the n - th stage GOA unit. The driving timing of the GOA circuit is as Figure 2 shown.

[0040] It should be noted that for the n - th stage GOA unit, when n is even, SCLK1(n) is the same signal as the first clock signal SCLK1, and SCLK2(n) is the same signal as the second clock signal SCLK2; when n is odd, SCLK1(n) is the same signal as the third clock signal SCLK3, and SCLK2(n) is the same signal as the fourth clock signal SCLK4. Here, n is a positive integer.

[0041] In this embodiment, a GOA unit with a 12T3C structure is adopted, and its structure is as Figure 3 shown, including thin - film transistors T1~T12 and capacitors C1~C3. The specific connection method is:

[0042] The gate of thin-film transistor T1 is connected to the first clock signal SCLK1(n), its source is connected to the start signal Cout(n - 1), and its drain is electrically connected to the source of thin-film transistor T2. The Cout(n - 1) signal is the output signal of the previous-stage GOA unit. If it is the first-stage GOA unit, the start signal connected to the source of thin-film transistor T1 should be SIN. The gate of thin-film transistor T2 is connected to the first clock signal SCLK1(n), its drain is electrically connected to the third node Q0, and its source is electrically connected to the drain of thin-film transistor T1. The gate and source of thin-film transistor T3 are both electrically connected to the drain of thin-film transistor T9, and its drain is electrically connected to the drain of thin-film transistor T1. The gate of thin-film transistor T4 is electrically connected to the drain of thin-film transistor T2, its drain is electrically connected to the drain of thin-film transistor T5, and its source is connected to the second clock signal SCLK2(n). The gate of thin-film transistor T5 is electrically connected to the second node QB, its drain is electrically connected to the drain of thin-film transistor T4, and its source is connected to the first constant low-level signal VGL1. The gate of thin-film transistor T6 is electrically connected to the second node QB, its drain is electrically connected to the first node Q, and its source is connected to the second constant low-level signal VGL2. The gate of thin-film transistor T7 is electrically connected to the third node Q0, its drain is electrically connected to the second node QB, and its source is connected to the start signal. The gate of thin-film transistor T8 is connected to the first clock signal SCLK1(n), its drain is electrically connected to the second node QB, and its source is connected to the constant high-level signal VGH. The gate of thin-film transistor T9 is electrically connected to the first node Q, its drain is electrically connected to the drain of thin-film transistor T10, and its source is connected to the constant high-level signal VGH. The gate of thin-film transistor T10 is electrically connected to the second node QB, its drain is electrically connected to the drain of thin-film transistor T9, and its source is connected to the first constant low-level signal VGL1. The gate of thin-film transistor T11 is electrically connected to the first node Q, its drain is electrically connected to the drain of thin-film transistor T12, and its source is connected to the constant high-level signal VGH. The gate of thin-film transistor T12 is electrically connected to the second node QB, its drain is electrically connected to the drain of thin-film transistor T11, and its source is connected to the second constant low-level signal VGL2. One end of capacitor C1 is electrically connected to the third node Q0, and the other end is electrically connected to the fourth node Q1; one end of capacitor C2 is electrically connected to the fourth node Q1, and the other end is electrically connected to the first node Q; one end of capacitor C3 is electrically connected to the second node QB, and the other end is electrically connected to the source of thin-film transistor T10.

[0043] Among them, the thin film transistors T1 to T12 can be field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used in this embodiment are symmetrical, their source and drain can be interchanged. It is stipulated that the middle terminal of the switching transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. The start signal SIN, the first clock signal SCLK1, the second clock signal SCLK2, the third clock signal SCLK3, the fourth clock signal SCLK4, the constant voltage high level signal VGH, the first constant voltage low level signal VGL1, and the second constant voltage low level signal VGL2 are all provided by an external timing controller.

[0044] In this embodiment, the driving method of the nth stage GOA unit is as follows:

[0045] Step 1: Enter the t1 stage:

[0046] As Figure 4 shown, the clock signal SCLK1(n) and the start signal Cout(n - 1) provide a high potential, and the clock signal SCLK2(n) provides a low potential; the thin film transistors T1, T2, T4, T5, T6, T7, T8, T10, T12 are turned on, and the thin film transistors T3, T9, T11 are turned off; the third node Q0 is charged to the high level VGH - Vth1 - Vth2 through the thin film transistors T1 and T2; the second node QB is charged to the high level through the thin film transistors T7 and T8; the first node Q is discharged to the low level VGL2 through the thin film transistor T6; the fourth node Q1 is discharged to the low level VGL1 through the thin film transistor T6.

[0047] It should be noted that at this time, the voltage of the capacitor C1 is the difference between the voltage of the third node and the voltage of the fourth node, which is equal to VGH - Vth1 - Vth2 - VGL1; the voltage of the capacitor C2 is the difference between the voltage of the fourth node and the voltage of the first node, which is equal to VGL1 - VGL2. The output signal at this stage is the constant voltage low level VGL2.

[0048] Step 2, enter the t2 stage:

[0049] As Figure 4As shown, the clock signal SCLK2(n) provides a high potential, the clock signals SCLK1(n) and the start signal Cout(n - 1) provide low potentials, the thin-film transistors T3, T4, T7, T9, and T11 are turned on, and the thin-film transistors T1, T2, T5, T6, T8, T10, and T12 are turned off; the third node Q0 rises to a potential higher than VGH, 2VGH - VGL - Vth1 - Vth7 - Vth8, through the capacitive coupling effect of the capacitor C1, and makes the thin-film transistors T4 and T7 fully turned on; the fourth node Q1 changes to a high level through the thin-film transistor T4, and under the capacitive coupling effect of the capacitor C2, the first node Q rises to a potential higher than VGH, VGH - VGL1 + VGL2; at the same time, the second node QB discharges to a low level VGL1 through the thin-film transistor T7; where VGL1 < VGL2. This makes Vgs_T12 < 0, fully turning off the thin-film transistor T12, thereby suppressing the leakage of the output signal through the thin-film transistor T12; therefore, the 12T3C GOA unit solves the problems of slow charging in DC drive and inability to achieve full-swing output, as well as the problem of output signal leakage. The GOA circuit can achieve full-swing output. At the same time, the circuit adopts a DC output module, reducing the dynamic power consumption caused by large-size pull-up transistors, which is beneficial to reducing power consumption. The output signal at this stage is a constant high potential VGH.

[0050] Step 3, enter the t3 stage:

[0051] As Figure 4 shown, the clock signal SCLK1(n) provides a high potential, the clock signals SCLK2(n) and the start signal Cout(n - 1) provide low potentials; the thin-film transistors T1, T2, T5, T6, T8, T10, T12 are turned on, and the thin-film transistors T3, T4, T7, T9, T11 are turned off; the third node Q0 discharges to a low level VGL1 through the thin-film transistors T1 and T2, the fourth node Q1 discharges to a low level VGL1 through the thin-film transistor T5, the first node Q discharges to a low level VGL2 through the thin-film transistor T6, and the VGH signal is transmitted to the second node QB through the thin-film transistor T8. The output signal at this stage is a constant low potential VGL2.

[0052] Step 4, enter the t4 stage:

[0053] As Figure 4 shown, the clock signal SCLK2(n) provides a high potential, the clock signals SCLK1(n) and the start signal Cout(n - 1) provide low potentials; the thin-film transistors T5, T6, T10, T12 are turned on, and the thin-film transistors T1, T2, T3, T4, T7, T8, T9, T11 are turned off. The first node Q remains at a low level VGL2, and the second node QB has no discharge path and remains at a high level VGH - Vth8. The output signal at this stage is still a constant low potential VGL2.

[0054] In the above driving method, the capacitor C2 between the fourth node Q1 and the first node Q can convert the fourth node Q1 to a high level in the t2 stage, and use the coupling effect of the capacitor C2 to pull up the first node Q to a level higher than VGH; the thin-film transistor T3 feeds back the output signal to suppress the leakage of the first node and maintain the voltage of the first node; thus, in the T2 stage, the thin-film transistors T9 and T11 are fully turned on, and the output signal can be quickly charged. The third node Q0 controls the thin-film transistor T7, and can pull down the potential of the second node QB to a low level VGL1 lower than VGL2 in the t2 stage, so that the thin-film transistor T12 is completely turned off, suppressing the leakage of the thin-film transistor T12; by suppressing the leakage of the thin-film transistor T12, when the GOA circuit is in the output stage, the leakage of the output signal is suppressed. Thus, the problems that the DC driving and charging of the traditional GOA circuit are slow and the full swing output cannot be achieved and the leakage of the output signal are solved, and the GOA circuit can achieve the full swing output, ensuring that the GOA circuit can still work normally after the threshold voltage of the transistor drifts.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the present technical solution, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A GOA unit, characterized in that: It includes thin film transistors T1 to T12 and capacitors C1 to C3; The gate of thin film transistor T1 is connected to a clock signal, the source is connected to a start signal, and its drain is respectively connected to the source of thin film transistor T2 and the drain of T3; The gate of thin film transistor T2 is connected to a clock signal, and its drain is connected to the third node Q0; Both the gate and the source of thin film transistor T3 are connected to the drain of thin film transistor T9; The source of thin film transistor T4 is connected to a clock signal, its gate is connected to the third node Q0, and its drain is connected to the fourth node Q1; The gate of thin film transistor T5 is connected to the second node QB, its source is connected to a voltage signal, and its drain is connected to the fourth node Q1; The gate of thin film transistor T6 is connected to the second node QB, its source is connected to a voltage signal, and its drain is connected to the first node Q; The gate of thin film transistor T7 is connected to the third node Q0, its source is connected to a start signal, and its drain is connected to the second node QB; The gate of thin film transistor T8 is connected to a clock signal, its source is connected to a voltage signal, and its drain is connected to the second node QB; The gate of thin film transistor T9 is connected to the first node Q, its source is connected to a voltage signal, and its drain is connected to the drain of thin film transistor T10; The gate of thin film transistor T10 is connected to the second node QB, and its source is connected to a voltage signal; The gate of thin film transistor T11 is connected to the first node Q, its source is connected to a voltage signal, and its drain is connected to the drain of thin film transistor T12; The gate of thin film transistor T12 is connected to the second node QB, and its source is connected to a voltage signal; One end of capacitor C1 is connected to the third node Q0, and the other end is connected to the fourth node Q1; one end of capacitor C2 is connected to the fourth node Q1, and the other end is connected to the first node Q; one end of capacitor C3 is connected to the second node QB, and the other end is connected to the source of thin film transistor T10; The thin film transistors T1, T2, and T8 are connected to the same kind of clock signal, and the thin film transistor T4 is connected to another clock signal; the voltage signals connected to the thin film transistors T5 and T10 are the first constant low-level signal; the voltage signals connected to the thin film transistors T6 and T12 are the second constant low-level signal; the voltage signals connected to the thin film transistors T8, T9, and T11 are the constant high-level signal.

2. The GOA unit according to claim 1, wherein: The clock signal, voltage signal, and start signal are all provided by a timing controller.

3. A GOA circuit, characterized in that: It includes N GOA units cascaded as claimed in claim 1 or 2, where N is a positive integer; among them, the first-stage GOA unit is started by the start signal SIN, and the nth-stage GOA unit is started by the output signal Cout(n - 1) of the (n - 1)th-stage GOA unit, where n is a positive integer and 1 < n < N - 1; In the cascaded GOA units, the odd-stage GOA units are connected to the first clock signal SCLK1, the second clock signal SCLK2, the constant high-level signal VGH, the first constant low-level signal VGL1, and the second constant low-level signal VGL2; The even - level GOA units are connected to the third clock signal SCLK3, the fourth clock signal SCLK4, the constant high - voltage signal VGH, the first constant low - voltage signal VGL1, and the second constant low - voltage signal VGL2.

4. The GOA circuit according to claim 3, wherein: In the odd - level GOA units, the gates of thin - film transistors T1, T2, and T8 are all connected to the first clock signal SCLK1, and the source of thin - film transistor T4 is connected to the second clock signal SCLK2; In the even - level GOA units, the gates of thin - film transistors T1, T2, and T8 are all connected to the third clock signal SCLK3, and the source of thin - film transistor T4 is connected to the fourth clock signal SCLK4.

5. The driving method for the GOA circuit according to claim 3, characterized in that: This driving method includes the following steps: S1. Enter the t1 stage: The clock signal SCLK1(n) and the start signal Cout(n - 1) provide high potential, and the clock signal SCLK2(n) provides low potential, turning on thin - film transistors T1, T2, T4, T5, T6, T7, T8, T10, and T12, and turning off thin - film transistors T3, T9, and T11; The third node Q0 is charged to the high level VGH - Vth1 - Vth2 through thin - film transistors T1 and T2, where Vth1 and Vth2 are the conduction voltages of thin - film transistors T1 and T2 respectively; The second node QB is charged to the high level through thin - film transistors T7 and T8; The first node Q is discharged to the low level VGL2 through thin - film transistor T6; The fourth node Q1 is discharged to the low level VGL1 through thin - film transistor T6; S2. Enter the t2 stage: The clock signal SCLK2(n) provides high potential, and the clock signal SCLK1(n) and the start signal Cout(n - 1) provide low potential, turning on thin - film transistors T3, T4, T7, T9, and T11, and turning off thin - film transistors T1, T2, T5, T6, T8, T10, and T12; The third node Q0 rises to a potential higher than VGH, 2VGH - VGL - Vth1 - Vth7 - Vth8, due to the capacitive coupling effect of capacitor C1, and makes thin - film transistors T4 and T7 fully turn on, where Vth7 and Vth8 are the conduction voltages of thin - film transistors T7 and T8 respectively; The fourth node Q1 is charged to the high level through thin - film transistor T4, and due to the capacitive coupling effect of capacitor C2, the first node Q rises to a potential higher than VGH, VGH - VGL1+VGL2; The second node QB is discharged to the low level VGL1 through thin - film transistor T7; S3. Enter the t3 stage: The clock signal SCLK1(n) provides a high potential, and the clock signals SCLK2(n) and the start signal Cout(n - 1) provide low potentials, turning on thin film transistors T1, T2, T5, T6, T8, T10, and T12, and turning off thin film transistors T3, T4, T7, T9, and T11; The third node Q0 is discharged to the low level VGL1 through the thin film transistors T1 and T2; The fourth node Q1 is discharged to the low level VGL1 through the thin film transistor T5; The first node Q is discharged to the low level VGL2 through the thin film transistor T6; The VGH signal is transmitted to the second node QB through the thin film transistor T8 and charges the capacitor C3; The voltage of the second node QB is equal to VGH - Vth8; S4. Enter the t4 stage: The clock signal SCLK2(n) provides a high potential, and the clock signals SCLK1(n) and the start signal Cout(n - 1) provide low potentials, turning on thin film transistors T5, T6, T10, and T12, and turning off thin film transistors T1, T2, T3, T4, T7, T8, T9, and T11; The first node Q maintains the low level VGL2; The second node QB maintains the high level VGH - Vth8; Among them, when n is odd, the clock signal SCLK1(n) represents the first clock signal SCLK1, and the clock signal SCLK2(n) represents the second clock signal SCLK2; When n is even, the clock signal SCLK1(n) represents the third clock signal SCLK3, and the clock signal SCLK2(n) represents the fourth clock signal SCLK4.

6. An array substrate includes a display area and a non-display area, characterized in that: The GOA circuit described in claim 3 is provided in the non-display area.

7. A display device, characterized in that: It includes the array substrate described in claim 6.

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