In-memory multi-bit adder and in-memory operation method

Abstract

The present invention provides an in-memory multi-bit adder and an in-memory operation method, wherein the in-memory multi-bit adder includes multiple non-volatile memory arrays; two adjacent non-volatile memory arrays are connected via an inter-column transfer module; each non-volatile memory array includes a precharge amplifier read module PCSA, a write driver circuit module WR, a first three-terminal device MTJ, and a second three-terminal device MTJ. The present invention optimizes the array operation steps by combining optimized Brent-Kung addition and an in-memory multi-bit adder to achieve multi-bit addition, targeting the unipolar flip characteristics of SOT-MRAM. The present invention can minimize the impact of the long recovery time required after the state flip of the SOT-MRAM device, and achieve in-memory multi-bit addition with fewer steps and less area overhead.

Description

Technical Field

[0001] The present invention belongs to the technical field of non-volatile memory design, and in particular relates to an in-memory multi-bit adder and an in-memory operation method. Background Art

[0002] Storage technology is widely used in in-memory computing. Non-volatile memory offers the following advantages over volatile memory: 1. Non-volatility, meaning data is not lost after a power outage; 2. Fast read and write speeds; and 3. Low static power consumption. Therefore, non-volatile memory is widely used in in-memory computing.

[0003] Magnetic random access memory (MRAM), a non-volatile memory technology, is widely used in in-memory computing. It is primarily divided into two types: spin-transfer torque magnetic random access memory (STT-MRAM) and spin-orbit torque magnetic random access memory (SOT-MRAM). The latest unipolar switching spin-orbit torque magnetic random access memory (US-SOT-MRAM) offers the following advantages over traditional SOT-MRAM and STT-MRAM: 1. Fast switching speed, with sub-nanosecond switching times; 2. Symmetrical switching currents for writing 1 and writing 0, eliminating source degeneration; 3. Current flows through the oxide layer only during read operations, preventing oxide penetration during write operations; 4. Switching can be achieved without external magnetic field assistance by adjusting the ratio of field torque to damping torque, reducing implementation complexity.

[0004] Current theoretical algorithms for multi-bit addition, including ripple carry, carry lookahead, and parallel prefix, fail to consider in-memory computation. Most in-memory multi-bit addition implementations based on various non-volatile devices lack consideration for achieving high parallelism and fast, reliable inter-column operations within the memory array while maintaining the integrity of the memory array structure and minimizing the overhead of peripheral circuitry and array units.

[0005] In US-SOT-MRAM devices, the free layer magnetization switching process is determined by the magnetic anisotropy field, damping torque, and fieldlike torque. Setting the fieldlike torque weight coefficient to 3.5 times the damping torque achieves unipolar switching without external magnetic field assistance. Under this setting, the final equilibrium state of the free layer magnetization is primarily determined by the perpendicular magnetic anisotropy field and the horizontal fieldlike torque. Therefore, the final equilibrium position for the switching is not completely perpendicular, but rather at a certain angle. The switching equilibrium state requires a relaxation period after the switching process (in the presence of only the perpendicular magnetic anisotropy field) for the free layer magnetization to be pulled to the perpendicular direction and the MTJ resistance to reach a completely parallel / antiparallel state. If this relaxation period occurs between the two steps of a multi-bit addition operation, it significantly increases the time required for the entire logic operation, resulting in a significant speed difference compared to other non-volatile memory technologies for in-memory operations. Therefore, optimizing the relaxation time for the free layer magnetization switching is a critical issue. Summary of the Invention

[0006] The present invention aims to solve the deficiencies in the prior art and provides an in-memory multi-bit adder and an in-memory operation method.

[0007] In a first aspect, the present invention provides an in-memory multi-bit adder, comprising a plurality of non-volatile memory arrays; two adjacent non-volatile memory arrays are connected via an inter-column transfer module; each non-volatile memory array comprises a pre-charge amplifier read module PCSA, a write driver circuit module WR, a first three-terminal device MTJ, and a second three-terminal device MTJ;

[0008] The upper end of the first three-terminal device MTJA0 is connected to the drain of the first read control transistor, the right end is connected to the drain of the first write control transistor, and the left end is connected to the left end of the second three-terminal device MTJ B0 and the source of the first column select transistor; the upper end of the second three-terminal device MTJ is connected to the drain of the second read control transistor, and the right end is connected to the drain of the second write control transistor;

[0009] The source of the first read control transistor serves as the input terminal of the precharge amplifier read module PCSA and is connected to the source of the second read control transistor; the precharge amplifier read module PCSA has an output terminal Vout and an output terminal !Vout; the output terminal Vout is connected to the gate of the first NMOS transistor; the source of the first NMOS transistor is connected to the 0V control signal, and the drain is connected to the source of the second NMOS transistor, the drain of the first PMOS transistor, the gate of the second column selection transistor, and the gate of the second PMOS transistor; the source of the first write control transistor is connected to the source of the second write control transistor, the source of the second column selection transistor, and the drain of the second PMOS transistor; the source of the second PMOS transistor, the first read control transistor, and the source of the second read control transistor are connected to the write drive circuit module WR; the drain of the second column selection transistor, the drain of the first column selection transistor, and the drain of the second NMOS transistor are all connected to GND; the source of the first PMOS transistor is connected to VDD.

[0010] Furthermore, the inter-column transfer module includes a third PMOS transistor and a third NMOS transistor; the source of the third PMOS transistor is connected to the source of the third NMOS transistor and serves as the source of the inter-column transfer module; the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor and serves as the drain of the inter-column transfer module; the source of the inter-column transfer module is connected to the drain of the first NMOS transistor in one non-volatile memory array, and the drain is connected to the drain of the first NMOS transistor in another non-volatile memory array.

[0011] In a second aspect, the present invention provides an in-memory operation method, which is applied to the in-memory multi-bit adder described in the first aspect, comprising: performing a read operation on a first three-terminal device MTJA0 in a first column of a non-volatile memory array, and turning on a second NMOS transistor, a first read control transistor, and a first column select transistor respectively during a cycle using a control signal; a precharge amplifier read module PCSA outputting a read result and storing it at an output terminal 0Vout and an output terminal 0!Vout;

[0012] In the second column of the non-volatile memory array, a read operation is performed on the first three-terminal device MTJA1, and the third NMOS transistor, the third PMOS transistor, the first write control transistor and the first column select transistor are respectively turned on by control signals within a cycle;

[0013] The 0V control signal in the first column of the non-volatile memory array is set to a high level. When the initial logic of the first three-terminal device MTJA0 is "0", 0Vout outputs a low level, so that the first NMOS transistor in the first column of the non-volatile memory array is turned off, and the source and drain of the inter-column transfer module are kept at a low level, so as to turn on the second PMOS transistor in the second column of the non-volatile memory array; wherein the logic "0" corresponds to a high resistance value of the MRAM, and the logic "1" corresponds to a low resistance value of the MRAM;

[0014] The first three-terminal device MTJA1 is written to logic "1"; when the initial logic of the first three-terminal device MTJA0 is "1", 0Vout outputs a high level, turning on the first NMOS transistor in the first column of the non-volatile memory array, so that the source and drain signals of the inter-column transfer module are pulled high to turn off the second PMOS transistor in the second column of the non-volatile memory array. The first three-terminal device MTJA1 does not perform a write operation and remains at logic "0" to achieve a 1-bit shift operation between columns.

[0015] Furthermore, the second aspect also includes:

[0016] In the first column of the non-volatile memory array, a read operation is performed on the first three-terminal device MTJA0. During a cycle, the second NMOS transistor, the first read control transistor, and the first column select transistor are respectively turned on by control signals. The precharge amplifier read module PCSA outputs the read result and stores it on the output terminals 0Vout and 0!Vout.

[0017] In the second column of the non-volatile memory array, an XOR operation is performed on the first three-terminal device MTJA1, and the third NMOS transistor, the third PMOS transistor, the first read control transistor and the second write control transistor are respectively turned on by the control signal within the cycle;

[0018] The 0V control signal in the first column of the non-volatile memory array is set to a high level. When the initial logic of the first three-terminal device MTJA0 is "1", 0Vout outputs a high level, turning on the first NMOS transistor in the first column of the non-volatile memory array, so that the signals at the source and drain of the inter-column transfer module are pulled high, thereby turning on the second column selection transistor in the second column of the non-volatile memory array; current flows from the first read control transistor in the second column of the non-volatile memory array to the left end of the first three-terminal device MTJA1, then flows through the heavy metal layer at the bottom of the second three-terminal device MTJ B1 in the second column of the non-volatile memory array to the second write control transistor in the second column of the non-volatile memory array, and finally flows to the GND connected to the drain of the first column selection transistor in the first column of the non-volatile memory array, thereby realizing an exclusive OR operation;

[0019] When the initial logic of the first three-terminal device MTJA0 is "0", 0Vout outputs a low level, turning off the first NMOS transistor in the first column of the non-volatile memory array, so that the source and drain of the inter-column transfer module remain at a low level, thereby turning off the second column selection transistor in the second column of the non-volatile memory array. Current flows from the first read control transistor in the second column of the non-volatile memory array to the left end of the first three-terminal device MTJA1. There is no current in the path through the second three-terminal device MTJ B1 and the second write control transistor in the second column of the non-volatile memory array to GND, and there is no impact on the resistance value of the second three-terminal device MTJ B1, thereby realizing an inter-column XOR operation.

[0020] The present invention provides an in-memory multi-bit adder and an in-memory operation method that optimizes Brent-Kung addition. This method, combined with the proposed optimized Brent-Kung addition and an in-memory multi-bit adder, addresses the unipolar flip characteristics of SOT-MRAM and implements multi-bit addition by optimizing array operation steps. This method minimizes the impact of the long recovery time required after a state flip in SOT-MRAM devices, achieving in-memory multi-bit addition with fewer steps and less area overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A circuit diagram of an in-memory multi-bit adder provided by an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of an 8-bit optimized Brent-Kung addition provided in an embodiment of the present invention;

[0024] Figure 3 An 8-bit addition flowchart according to the algorithm theory and an 8-bit addition flowchart after step optimization provided by an embodiment of the present invention;

[0025] Figure 4 This is a current flow diagram for the read operation, write operation, and XOR operation provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0027] In one embodiment, the present invention provides an in-memory multi-bit adder, comprising a plurality of non-volatile memory arrays; two adjacent non-volatile memory arrays are connected via an inter-column transfer module; each non-volatile memory array comprises a pre-charge amplifier read module PCSA, a write driver circuit module WR, a first three-terminal device MTJA0, and a second three-terminal device MTJB0.

[0028] like Figure 1 As shown, in the first column of the non-volatile memory array, the upper end of the first three-terminal device MTJA0 is connected to the drain of the first read control transistor N10, the right end is connected to the drain of the first write control transistor N8, and the left end is connected to the left end of the second three-terminal device MTJB0 and the source of the first column selection transistor N1; the upper end of the second three-terminal device MTJB0 is connected to the drain of the second read control transistor N6, and the right end is connected to the drain of the second write control transistor N4.

[0029] In the first column of the nonvolatile memory array, the source of the first read control transistor N10 serves as the input terminal of the precharge amplifier read module PCSA and is connected to the source of the second read control transistor N6; the precharge amplifier read module PCSA has an output terminal 0Vout and an output terminal 0! Vout; the output terminal 1Vout is connected to the gate of the first NMOS transistor N14; the source of the first NMOS transistor N14 is connected to the 0V control signal, and the drain is connected to the source of the second NMOS transistor N12, the drain of the first PMOS transistor P2, the gate of the second column selection transistor N0 and the gate of the second PMOS transistor P0; the source of the first write control transistor N8 is connected to the source of the second write control transistor N4, the source of the second column selection transistor N0 and the drain of the second PMOS transistor P0; the source of the second PMOS transistor P0, the source of the first read control transistor N10 and the source of the second read control transistor N6 are connected to the write drive circuit module WR; the drain of the second column selection transistor N0, the drain of the first column selection transistor N1 and the drain of the second NMOS transistor N12 are all connected to GND; the source of the first PMOS transistor P2 is connected to VDD.

[0030] In the second column of the non-volatile memory array, the upper end of the first three-terminal device MTJA1 is connected to the drain of the first read control transistor N11, the right end is connected to the drain of the first write control transistor N9, and the left end is connected to the left end of the second three-terminal device MTJ B1 and the source of the first column selection transistor N3; the upper end of the second three-terminal device MTJ B1 is connected to the drain of the second read control transistor N7, and the right end is connected to the drain of the second write control transistor N5.

[0031] In the second column of the nonvolatile memory array, the source of the first read control transistor N11 serves as the input terminal of the precharge amplifier read module PCSA and is connected to the source of the second read control transistor N7; the precharge amplifier read module PCSA has an output terminal 1Vout and an output terminal 1! Vout; the output terminal 1Vout is connected to the gate of the first NMOS transistor N15; the source of the first NMOS transistor N15 is connected to the 1V control signal, and the drain is connected to the source of the second NMOS transistor N13, the drain of the first PMOS transistor P3, the gate of the second column selection transistor N2 and the gate of the second PMOS transistor P1; the source of the first write control transistor N9 is connected to the source of the second write control transistor N5, the source of the second column selection transistor N2 and the drain of the second PMOS transistor P1; the source of the second PMOS transistor P1, the source of the first read control transistor N11 and the source of the second read control transistor N7 are connected to the write drive circuit module WR; the drain of the second column selection transistor N2, the drain of the first column selection transistor N3 and the drain of the second NMOS transistor N13 are all connected to GND; the source of the first PMOS transistor P3 is connected to VDD.

[0032] For example, Figure 1 As shown, the inter-column transfer module includes a third PMOS transistor P4 and a third NMOS transistor N16; the source of the third PMOS transistor is connected to the source of the third NMOS transistor N16, and serves as the source of the inter-column transfer module; the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor N16, and serves as the drain of the inter-column transfer module; the source of the inter-column transfer module is connected to the drain of the first NMOS transistor N14 in one non-volatile memory array, and the drain is connected to the drain of the first NMOS transistor N15 in another non-volatile memory array.

[0033] In the design of multi-bit addition, four basic operations in the array are used: read operation, write operation, XOR operation and read delay operation. The current flow direction of read and write operation is as follows: Figure 4 As shown in sub-graphs (1) and (2) of ; the current flow direction of the XOR operation is as follows Figure 4As shown in sub-figure (3), the resistance of MTJ C corresponding to different logics is used to generate two currents of different magnitudes under a given voltage to control the flipping of MTJ D, thus realizing XOR logic. The read delay operation uses the latch structure in the read circuit to save the read operation result.

[0034] In another embodiment, the present invention provides an in-memory operation method for an in-memory multi-bit adder, implementing inter-column 1-bit shift operations and inter-column XOR operations. Assuming that the inverted resistance value of MTJA0 is transferred to the resistance value of MTJA1, and that MTJA1 is initially at logic "0," it is assumed that logic "0" corresponds to a high resistance value of the MRAM, and logic "1" corresponds to a low resistance value of the MRAM.

[0035] The in-memory operation method includes performing a read operation on a first three-terminal device MTJA0 in a first column of a non-volatile memory array. Within a cycle, control signals Ognd2, RWL0, and BLS0 are used to respectively turn on a second NMOS transistor N12, a first read control transistor N10, and a first column select transistor N1. A precharge amplifier read module PCSA outputs a read result and stores it at output terminals 0Vout and 0!Vout.

[0036] In the second column of the nonvolatile memory array, a read operation is performed on the first three-terminal device MTJA1. In the cycle, the third NMOS transistor N16, the third PMOS transistor P4, the first write control transistor N9 and the first column select transistor N3 are turned on respectively by the control signals O1en, O1!en, WWL0 and BLS1.

[0037] The 0V control signal in the first column of the non-volatile memory array is set to a high level. When the initial logic of the first three-terminal device MTJA0 is "0", 0Vout outputs a low level, so that the first NMOS transistor N14 in the first column of the non-volatile memory array is turned off, so that the source (0SL) and drain (1SL) of the inter-column transfer module remain at a low level, thereby turning on the second PMOS transistor P1 in the second column of the non-volatile memory array.

[0038] The first three-terminal device MTJA1 is written to logic "1"; when the initial logic of the first three-terminal device MTJA0 is "1", 0Vout outputs a high level, turning on the first NMOS transistor in the first column of the non-volatile memory array, so that the source and drain signals of the inter-column transfer module (0SL and 1SL respectively) are pulled high to turn off the second PMOS transistor P1 in the second column of the non-volatile memory array. The first three-terminal device MTJA1 does not perform a write operation and remains at logic "0"; to achieve a 1-bit shift operation between columns.

[0039] Illustratively, the inter-column XOR operation includes performing a read operation on the first three-terminal device MTJA0 in the first column of the non-volatile memory array. Within a cycle, the second NMOS transistor N12, the first read control transistor N10, and the first column select transistor N1 are respectively turned on by control signals Ognd2, RWL0, and BLS0. The pre-charge amplifier read module PCSA outputs the read result and stores it at the output terminals 0Vout and 0!Vout.

[0040] In the second column of the non-volatile memory array, an exclusive OR operation is performed on the first three-terminal device MTJA1. During the cycle, the third NMOS transistor N16, the third PMOS transistor P4, the first read control transistor N11, and the second write control transistor N5 are turned on respectively by the control signals O1en, O1!en, RWL0, and WWL1.

[0041] The 0V control signal in the first column of the non-volatile memory array is set to a high level. When the initial logic of the first three-terminal device MTJA0 is "1", 0Vout outputs a high level, turning on the first NMOS transistor N14 in the first column of the non-volatile memory array, so that the signals at the source and drain of the inter-column transfer module are pulled high, thereby turning on the second column selection transistor N2 in the second column of the non-volatile memory array; current flows from the first read control transistor N11 in the second column of the non-volatile memory array to the left end of the first three-terminal device MTJA1, then flows through the heavy metal layer at the bottom of the second three-terminal device MTJ B1 in the second column of the non-volatile memory array to the second write control transistor N5 in the second column of the non-volatile memory array, and finally flows to the GND connected to the drain of the first column selection transistor N1 in the first column of the non-volatile memory array, realizing the A1⊕B1→B1 operation.

[0042] When the initial logic of the first three-terminal device MTJA0 is "0", 0Vout outputs a low level, turning off the first NMOS transistor N14 in the first column of the non-volatile memory array, so that the source and drain of the inter-column transfer module remain at a low level, thereby turning off the second column select transistor N2 in the second column of the non-volatile memory array. Current flows from the first read control transistor N11 in the second column of the non-volatile memory array to the left end of the first three-terminal device MTJA1. There is no current in the path through the second three-terminal device MTJ B1 and the second write control transistor N5 in the second column of the non-volatile memory array to GND, and there is no impact on the resistance value of the second three-terminal device MTJB1, thereby realizing an inter-column XOR operation.

[0043] Through the in-memory multi-bit adder, the basic operations that can be implemented in the array include: read operation, write operation, XOR operation, 1-bit shift operation between columns and XOR operation between columns. On this basis, combined with Brent-Kung addition, the normal process of implementing 8-bit addition is as follows Figure 3As shown in the neutron diagram (1), a small box in the figure represents a memory cell in the memory array, that is, a non-volatile MRAM cell. The resistance values ​​of MTJA0-A7 and MTJ B0-B7 represent the 8-bit addend and augend respectively. The implementation process is as follows:

[0044] Step 1: Generate P and G.

[0045] 1. Generate P (the XOR result of MTJA and MTJ B) (requires 1 step)

[0046] 1) A⊕B→B(P), perform an XOR operation on the resistance values ​​of MTJA and MTJ B in columns 0-7, and store the XOR result in the resistance value of MTJ B (store the P result of the optimized BK algorithm in the resistance value of MTJ B).

[0047] 2. Generate G (the AND result of MTJA and MTJ B) (requires 2 steps)

[0048] 1) Read A: The resistance values ​​of the MTJAs in columns 0-7 are read using the PCSA read circuits in each column, and the read results are stored at the output terminals Vout / !Vout of the PCSAs in each column.

[0049] 2) When A = "1", B ⊕ A → A(G); when A = "0", no operation is performed. The transistors in each column Ni (i = 0, 2, 3, ...) are selected and enabled based on the Vout reading results stored in each column in the previous step. When the MTJA reading result in columns 0-7 is high (corresponding to a logical "1"), the resistance values ​​of the MTJA in columns 0-7 and MTJ B are XORed, and the XOR result is stored in the MTJA resistance value. When the MTJA reading result in columns 0-7 is low (corresponding to a logical "0"), the MTJA resistance value is not affected. Finally, the G result of the optimized Brent-Kung algorithm is stored in the MTJA resistance value.

[0050] Step 2: P shift.

[0051] 3. Move the P logic in columns 0, 2, and 4 to columns 1, 3, and 5 of row M, and move the P logic in columns 2, 4, and 6 to columns 1, 3, and 5 of row N (requires 3 steps)

[0052] 1) Read P (0, 2, 4, 6). Use the read circuit to read the MTJ resistance values ​​of columns 0, 2, 4, and 6 of row P and store the read results in Vout / !Vout of the corresponding columns.

[0053] 2) When P = "1", no operation is performed; when P = "0", M(1,3,5,_) is written. Based on the Vout reading result stored in columns 0, 2, and 4 in the previous step, the Pi (i = 0, 2, 3, ...) transistors in columns 0, 2, and 4 are enabled. When the MTJ P reading result in columns 0, 2, and 4 is high (corresponding to a logic "1"), the corresponding Pi transistor is turned off, which has no effect on the resistance of MTJ M. When the MTJ P reading result in columns 0, 2, and 4 is low (corresponding to a logic "0"), the corresponding Pi transistor is turned on, and a write operation is performed on the MTJ M in columns 0, 2, and 4. The inverted resistance values ​​of the MTJ P in columns 0, 2, and 4 are transferred to the MTJ M in columns 1, 3, and 5.

[0054] 3) When P = "1", no operation is performed; when P = "0", N(_,1,3,5) is written. Based on the read result of Vout stored in columns 2, 4, and 6 in the first step, the Pi transistors in columns 2, 4, and 6 are enabled. When the read result of MTJ P in columns 2, 4, and 6 is high (corresponding to a logic "1"), the corresponding Pi transistor is turned off, which has no effect on the resistance of MTJN. When the read result of MTJ P in columns 2, 4, and 6 is low (corresponding to a logic "0"), the corresponding Pi transistor is turned on, and a write operation is performed on MTJ N in columns 2, 4, and 6. The inverted resistance of MTJ P in columns 2, 4, and 6 is transferred to MTJN in columns 1, 3, and 5.

[0055] 4. Move the MTJ P in columns 1, 3, 5, and 7 to columns 0, 2, 4, and 6 in row N (requires 2 steps)

[0056] 1) Read P(1,3,5,7). Use the read circuit to read the MTJ resistance values ​​of columns 1, 3, 5, and 7 of row P and store the read results in Vout / !Vout of the corresponding columns.

[0057] 2) When P = "1", no operation is performed; when P = "0", N (0, 2, 4, 6) is written. Based on the read result of Vout stored in columns 1, 3, 5, and 7 in the first step, the Pi transistors in columns 1, 3, 5, and 7 are enabled. When the read result of the MTJ P in columns 1, 3, 5, and 7 is high (corresponding to a logic "1"), the corresponding Pi transistor is turned off, which has no effect on the resistance of the MTJN. When the read result of the MTJ P in columns 1, 3, 5, and 7 is low (corresponding to a logic "0"), the corresponding Pi transistor is turned on, and a write operation is performed on the MTJN in columns 0, 2, 4, and 6. The inverted resistance values ​​of the MTJ P in columns 1, 3, 5, and 7 are transferred to the MTJN in columns 0, 2, 4, and 6.

[0058] Step 3: Calculate the first-level PG of the optimized Brent-Kung addition.

[0059] 5. Calculate the first level G (Gi=Gi+PiGi-1) (requires 2 steps)

[0060] 1) Read G(0,2,4): Use the read circuit to read the MTJ resistance values ​​of columns 0, 2, and 4 of row G and store the read results in Vout / !Vout of the corresponding columns.

[0061] 2) When G = "1", P ⊕ G → G(1, 3, 5); when G = "0", no operation is performed. Based on the Vout reading results stored in columns 0, 2, and 4 in the previous step, transistors 01en and 01!en are turned on, passing the reading results to the next column, selectively enabling the Ni transistors in columns 1, 3, and 5. When the MTJ G reading results in columns 0, 2, and 4 are high (corresponding to a logical "1"), the resistance values ​​of MTJ P and MTJ G in columns 1, 3, and 5 are XORed, and the XOR result is stored in the MTJ G resistance value. When the MTJ G reading results in columns 0, 2, and 4 are low (corresponding to a logical "0"), the resistance values ​​of MTJ G in columns 1, 3, and 5 are not affected. Finally, the G result of the first stage of the optimized Brent-Kung addition is stored in the MTJ G resistance values ​​in columns 1, 3, and 5.

[0062] 6. Calculate the first level P (Pi = PiPi-1) (requires 2 steps)

[0063] 1) Read P(1,3,5). Use the read circuit to read the MTJ resistance values ​​of columns 1, 3, and 5 of row P and store the read results in Vout / !Vout of the corresponding columns.

[0064] 2) When P = "1", M ⊕ P → P(1, 3, 5); when P = "0", no operation is performed. Based on the Vout reading results stored in columns 1, 3, and 5 in the previous step, the Ni transistors in columns 1, 3, and 5 are enabled. When the MTJ P reading result in columns 1, 3, and 5 is high (corresponding to a logical "1"), the resistance values ​​of MTJ M and MTJ P in columns 1, 3, and 5 are XORed, and the XOR result is stored in the MTJ P resistance value. When the MTJ P reading result in columns 1, 3, and 5 is low (corresponding to a logical "0"), the resistance values ​​of MTJ P in columns 1, 3, and 5 are not affected. Finally, the P result of the first stage of the optimized BK algorithm is stored in the MTJ P resistance values ​​in columns 1, 3, and 5.

[0065] Step 4: Calculate the 2nd to 5th levels G (Gi=Gi+PiGi-1) of the optimized Brent-Kung addition.

[0066] 7-10. Calculate and optimize the Brent-Kung addition method for levels 2-5 G (8 steps required)

[0067] 1) Read G (1): Use the read circuit to read the MTJ resistance of the first column of row G and store the read result in Vout / !Vout of the corresponding column.

[0068] 2) When G = "1", P ⊕ G → G (3); when G = "0", no operation is performed. Based on the read result stored in column 1 Vout in the previous step, transistors 01en and 01!en are turned on, and the read result is transferred to column 3, selecting to enable the Ni transistor in column 3. When the read result of MTJ G in column 1 is high (corresponding to logic "1"), the resistance values ​​of MTJ P and MTJ G in column 3 are XORed, and the XOR result is stored in the resistance value of MTJ G; when the read result of MTJ G in column 1 is low (corresponding to logic "0"), it will not affect the resistance value of MTJ G in column 3. Finally, the G result of the second stage of the optimized Brent-Kung addition is stored in the resistance value of MTJ G in column 3.

[0069] 3) Read G (3): Use the read circuit to read the MTJ resistance value of the third column of row G and store the read result in Vout / !Vout of the corresponding column.

[0070] 4) When G = "1", P ⊕ G → G (5); when G = "0", no operation. According to the reading result stored in the 3rd column Vout in the previous step, turn on transistors 01en and 01!en, pass the reading result to the 5th column, and select N to enable the 5th column. i Transistor. When the read result of MTJ G in the third column is high (corresponding to a logic "1"), the resistance values ​​of MTJ P and MTJ G in the fifth column are XORed, and the XOR result is stored in the resistance value of MTJ G. When the read result of MTJ G in the third column is low (corresponding to a logic "0"), it has no effect on the resistance value of MTJ G in the fifth column. Finally, the G result of the third level of the optimized BK algorithm is stored in the resistance value of MTJ G in the fifth column.

[0071] 5) Read G(1,3,5). Use the read circuit to read the MTJ resistance values ​​of columns 1, 3, and 5 of row G and store the read results in Vout / !Vout of the corresponding columns.

[0072] 6) When G = "1", P ⊕ G → G (2, 4, 6); when G = "0", no operation. According to the reading result stored in the 1st, 3rd, and 5th columns Vout in the previous step, turn on transistors 01en and 01!en, pass the reading result to the 2nd, 4th, and 6th columns, and select N to enable the 2nd, 4th, and 6th columns. iTransistors. When the MTJ G reading result in columns 1, 3, and 5 is high (corresponding to a logic "1"), the resistance values ​​of MTJ P and MTJ G in columns 2, 4, and 6 are XORed, and the XOR result is stored in the MTJ G resistance value. When the MTJ G reading result in columns 1, 3, and 5 is low (corresponding to a logic "0"), it has no effect on the resistance values ​​of MTJ G in columns 2, 4, and 6. Finally, the G result of the fourth level of the optimized BK algorithm is stored in the MTJ G resistance values ​​in columns 2, 4, and 6.

[0073] 7) Read G (6): Use the read circuit to read the MTJ resistance value of the 6th column of row G and store the read result in Vout / !Vout of the corresponding column.

[0074] 8) When G = "1", P ⊕ G → G (7); when G = "0", no operation. According to the read result stored in the 6th column Vout in the previous step, transistors 01en and 01!en are turned on, and the read result is passed to the 7th column, and the Ni transistor in the 7th column is selected and enabled. When the read result of MTJ G in the 6th column is high (corresponding to logic "1"), the resistance values ​​of MTJ P and MTJ G in the 7th column are XORed, and the XOR result is stored in the MTJ G resistance value; when the read result of MTJ G in the 6th column is low (corresponding to logic "0"), it will not affect the resistance value of MTJ G in the 7th column. Finally, the G result of the 5th level of the optimized BK algorithm is stored in the MTJ G resistance value in the 7th column.

[0075] Step 5: Calculate SUM.

[0076] 11. Invert the resistance of the MTJN in columns 0-6 (requires 1 step)

[0077] 1) Write N (0-6), turn on the corresponding write transistor, and perform a write operation on the MTJN of columns 0-6.

[0078] 12. Calculate the SUM result (SUMi=Pi⊕Ci-1) (requires 1 step)

[0079] 1) G⊕N→N(0, 1, 2, 3, 4, 5, 6), turn on the transistor corresponding to the XOR operation, perform an XOR operation on the resistance values ​​of MTJ G and MTJ N in columns 0-6, and store the XOR result in the resistance value of MTJ N. Finally, the addition result of bits 1-7 is stored in MTJN0-N6, the addition result of bit 0 is stored in MTJ P0, and the carry information is stored in MTJ G7.

[0080] like Figure 3As shown in sub-figure (2), after the steps, when an MTJ is flipped, there is at least one read operation and one XOR / write operation time to relax the direction of the free layer magnetization intensity.

[0081] The present invention optimizes the traditional Brent-Kung addition to obtain an optimized Brent-Kung addition which only needs to calculate P (the result of XOR of A and B) and G (the result of AND of A and B) in the first stage and calculate G in the remaining stages. The number of stages is (N / 2+1). The optimization algorithm is as follows: Figure 2 As shown. For the inter-column calculation in the algorithm, combined with the read amplifier circuit of the memory array, a multi-bit adder in memory with low area overhead is proposed, which does not affect the operation of the memory array and the inter-column operation in the matching algorithm logic, as shown in Figure 1 As shown, an in-memory multi-bit adder is used to implement inter-column shift operations and inter-column XOR operations (selectively performing XOR operations on any column based on the data in a certain column). This inter-column XOR operation fully complies with the logic for calculating G in the optimized Brent-Kung addition. Simultaneously, the logic for calculating P in the optimized Brent-Kung addition is implemented using an inter-column 1-bit shift operation.

[0082] Multi-bit addition logic is implemented by four basic logic operations in memory, including read operation, write operation, XOR operation and read result delay operation. Among them, write operation and XOR operation will flip the resistance value of the memory cell, and there will be a recovery time problem of the magnetization direction flipping of the free layer, while read operation and read delay operation will not cause this problem. Figure 3 As shown, by optimizing the steps of multi-bit addition, after the write operation / XOR operation, the corresponding flipped MTJ has at least two operation cycles to relax and recover.

[0083] The present invention has been described in detail above with reference to specific embodiments and exemplary examples. However, these descriptions should not be construed as limiting the present invention. Those skilled in the art will appreciate that various equivalent substitutions, modifications, or improvements may be made to the technical solutions and implementations of the present invention without departing from the spirit and scope of the present invention, all of which fall within the scope of the present invention. The scope of protection of the present invention shall be determined by the appended claims.

Claims

1. An in-memory multi-bit adder, characterized in that: It includes multiple non-volatile memory arrays; two adjacent non-volatile memory arrays are connected through an inter-column transfer module; each non-volatile memory array includes a pre-charge amplifier read module PCSA, a write driver circuit module WR, a first three-terminal device MTJ and a second three-terminal device MTJ; The upper end of the first three-terminal device MTJ is connected to the drain of the first read control transistor, the right end is connected to the drain of the first write control transistor, and the left end is connected to the left end of the second three-terminal device MTJ and the source of the first column select transistor; the upper end of the second three-terminal device MTJ is connected to the drain of the second read control transistor, and the right end is connected to the drain of the second write control transistor; The source of the first read control transistor serves as an input terminal of the precharge amplifier read module PCSA and is connected to the source of the second read control transistor; the precharge amplifier read module PCSA has an output terminal Vout and an output terminal !Vout; the output terminal Vout is connected to the gate of the first NMOS transistor; the source of the first NMOS transistor is connected to a 0V control signal, and the drain is connected to the source of the second NMOS transistor, the drain of the first PMOS transistor, the gate of the second column select transistor, and the gate of the second PMOS transistor; the source of the first write control transistor is connected to the source of the second write control transistor, the source of the second column select transistor, and the drain of the second PMOS transistor; the source of the second PMOS transistor, the first read control transistor, and the source of the second read control transistor are connected to the write driver circuit module WR; the drain of the second column select transistor, the drain of the first column select transistor, and the drain of the second NMOS transistor are all connected to GND; the source of the first PMOS transistor is connected to VDD; The inter-column transfer module includes a third PMOS transistor and a third NMOS transistor; the source of the third PMOS transistor is connected to the source of the third NMOS transistor and serves as the source of the inter-column transfer module; the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor and serves as the drain of the inter-column transfer module; The source of the inter-column transfer module is connected to the drain of the first NMOS transistor in one non-volatile memory array, and the drain is connected to the drain of the first NMOS transistor in another non-volatile memory array.

2. An in-memory operation method, said method being applied to the in-memory multi-bit adder according to claim 1, characterized in that: include: In the first column of the non-volatile memory array, a read operation is performed on the first three-terminal device MTJ A0, and the second NMOS transistor, the first read control transistor and the first column selection transistor are respectively turned on by control signals within a cycle; The pre-charge amplifier read module PCSA outputs the read result and stores it on the output terminal 0Vout and the output terminal 0!Vout; In the second column of the non-volatile memory array, a read operation is performed on the first three-terminal device MTJ A1, and the third NMOS transistor, the third PMOS transistor, the first write control transistor and the first column select transistor are respectively turned on by control signals within a cycle; The 0V control signal in the first column of the non-volatile memory array is set to a high level. When the first three-terminal device MTJ A0 initially has a logic "0", 0Vout outputs a low level, turning off the first NMOS transistor in the first column of the non-volatile memory array. This causes the source and drain of the inter-column transfer module to maintain a low level, thereby turning on the second PMOS transistor in the second column of the non-volatile memory array. A logic "0" corresponds to a high resistance value of the MRAM, and a logic "1" corresponds to a low resistance value of the MRAM. The first three-terminal device MTJ A1 is written to logic "1"; when the first three-terminal device MTJ A0 is initially logic "1", 0Vout outputs a high level, turning on the first NMOS transistor in the first column of the non-volatile memory array, so that the source and drain signals of the inter-column transfer module are pulled high, thereby turning off the second PMOS transistor in the second column of the non-volatile memory array. The first three-terminal device MTJA1 does not perform a write operation and remains at logic "0", thereby realizing a 1-bit shift operation between columns.

3. The in-memory computing method according to claim 2, wherein: Also includes: In the first column of the non-volatile memory array, a read operation is performed on the first three-terminal device MTJ A0. During a cycle, the second NMOS transistor, the first read control transistor, and the first column select transistor are respectively turned on by control signals. The precharge amplifier read module PCSA outputs the read result and stores it on the output terminals 0Vout and 0!Vout. In the second column of the non-volatile memory array, an XOR operation is performed on the first three-terminal device MTJ A1, and the third NMOS transistor, the third PMOS transistor, the first read control transistor and the second write control transistor are respectively turned on by the control signal within the cycle; The 0V control signal in the first column of the non-volatile memory array is set to a high level. When the first three-terminal device MTJ A0 initially has a logic "1," 0Vout outputs a high level, turning on the first NMOS transistor in the first column of the non-volatile memory array. This pulls the source and drain signals of the inter-column transfer module high, turning on the second column select transistor in the second column of the non-volatile memory array. Current flows from the first read control transistor in the second column of the non-volatile memory array to the left end of the first three-terminal device MTJ A1, then flows through the heavy metal layer at the bottom of the second three-terminal device MTJ B1 in the second column of the non-volatile memory array to the second write control transistor in the second column of the non-volatile memory array, and finally flows to the GND connected to the drain of the first column select transistor in the first column of the non-volatile memory array, thereby realizing an exclusive OR operation; When the first three-terminal device MTJ A0 initially has a logic "0," 0Vout outputs a low level, turning off the first NMOS transistor in the first column of the non-volatile memory array. This causes the source and drain of the inter-column transfer module to remain at a low level, turning off the second column select transistor in the second column of the non-volatile memory array. Current then flows from the first read control transistor in the second column of the non-volatile memory array to the left end of the first three-terminal device MTJ A1. Current flows through the second three-terminal device MTJ B1 and the second write control transistor in the second column of the non-volatile memory array to GND, leaving no current in the path. This path does not affect the resistance value of the second three-terminal device MTJ B1, thereby achieving an inter-column exclusive-OR operation.

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