A method and apparatus for reducing polar code encoding of a storage resource

Abstract

The application provides a polar code encoding method and device for reducing storage resources, and the method comprises the following steps: only using one memory, and adopting address two-level mapping to perform polar code encoding, wherein the address two-level mapping to perform polar code encoding refers to that when performing one column encoding, input data of the column is read from an address in the memory, and after the encoding is completed, the input data is written back to the original address in the memory, and the read address and the write address are the same. The polar code encoding device is constructed on the basis of the address two-level mapping scheme, and compared with a traditional encoding device, the hardware resource consumption can be effectively reduced, and the area required by the storage unit is reduced by half. The address two-level mapping scheme in the application can be used to realize the polar code encoding device for any code length polar code, as long as the mother code length N and the parallel degree P of the calculation unit are powers of two.

Description

TECHNICAL FIELD

[0001] The present application relates to a method and apparatus for polar code encoding of a storage resource. BACKGROUND

[0002] Since Shannon proposed the channel coding theorem, various codes that can approach the Shannon limit have been proposed. Low-density parity-check (LDPC) codes and parallel concatenated convolution (Turbo) codes can approach the Shannon channel capacity infinitely as the code length tends to infinity, but it has always been unable to prove that it can reach the Shannon limit. Polar codes (reference: E. Arikan, "Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," in IEEE Transactions on Information Theory, vol. 55, no. 7, pp. 3051-3073, July 2009, doi: 10.1109 / TIT.2009.2021379.) are a new coding method proposed in recent years, which is the only error correction code that can theoretically achieve the Shannon limit. Polar codes are considered a major breakthrough in the field of coding, and have wide application prospects in source coding, channel coding, key agreement and network security, etc. Polar codes were identified as the control channel coding scheme for 5G enhanced mobile broadband scenarios in 2016.A large number of researches have been conducted on the construction, encoding and decoding of polar codes by domestic and foreign scholars (Reference: E. Arikan, "Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," in IEEE Transactions on Information Theory, vol. 55, no. 7, pp. 3051-3073, July 2009, doi: 10.1109 / TIT.2009.2021379, R. Mori and T. Tanaka, "Performance of Polar Codes with the Construction using Density Evolution," in IEEE Communications Letters, vol. 13, no. 7, pp. 519-521, July 2009, doi: 10.1109 / LCOMM.2009.090428, D. Wu, Y. Li and Y. Sun, "Construction and Block Error Rate Analysis of Polar Codes Over AWGN Channel Based on Gaussian Approximation," in IEEE Communications Letters, vol. 18, no. 7, pp. 1099-1102, July 2014, doi: 10.1109 / LCOMM.2014.2325811).

[0003] The document "E. Arikan, "Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," in IEEE Transactions on Information Theory, vol. 55, no. 7, pp. 3051-3073, July 2009, doi: 10.1109 / TIT.2009.2021379" proposes a full parallel polar code encoder based on fast Fourier transform structure, but its hardware complexity O(N.log N) will increase significantly as the code length increases. The document "M. S. Oommen and S. Ravishankar, "FPGA implementation of an advanced encoding and decoding architecture of polar codes," 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), Bengaluru, India, 2015, pp. 1-6, doi: 10.1109 / VLSI-SATA.2015.7050456" reduces the use of resources such as registers by reducing the number of N bits to N-R' bits for encoding, where R' is the number of fixed bits 0. This structure reduces the resource usage to some extent, but there is still a lot of optimization space. The document "H. Yoo and I.-C. Park, "Partially Parallel Encoder Architecture for Long Polar Codes," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 3, pp. 306-310, March 2015, doi: 10.1109 / TCSII.2014.2369131" proposes a semi-parallel encoding method that can improve the throughput and reduce the hardware complexity, but increases the use of memory, and the occupied register resources will increase with the increase of the code length.

[0004] When the mother code length used by the polar code is N = 2 nThere are n columns of encoding processes, recorded as 0, 1, ..., n-1 columns; the calculation parallelism is set to P (P is a power of 2), and a serial structure encoding method is adopted. In the encoding calculation of each column, P coding bits form a coding unit. In the polar code encoding structure diagram, each column from top to bottom is 0 to Coding unit.

[0005] During the encoding process, a "ping-pong memory" reading and storage mechanism is used, where data is read from one memory block and written to another memory block at the same time. Generally, a polar code with a mother code length of N requires two N-bit memories for storage. When the parallelism of the computing unit is P, the structure of each memory is words, each word is P bits wide.

[0006] The input values ​​of column 0 are stored in the memory block 0 (hereinafter referred to as mem0) in order. When the encoding of the two encoding units 0 and 1 of column 0 is completed, the encoding of the two encoding units 0 and 1 of column 1 is generated. The input data of the two coding units. When the 2nd and 3rd coding units of the 0th column complete the coding, the 1st and 2nd coding units of the 1st column are generated. The input data of the two encoding units. Correspondingly, the operation of the circuit is to read mem0 address 0, encode, read mem0 address 1, encode, and the output of the two encodings is interleaved to generate the 0th and 1st columns. Input data of two encoding units. These two sets of input data need to be stored in memory. Prepare another block of memory for the input data of column 1, called block 1 memory (hereinafter referred to as mem1). The operation on the circuit is to write mem1 address 0 and write mem1 address Similarly, read mem0 address 2, read mem0 address 3, write mem1 address 1, write mem1 address And so on until the column has finished calculating the The encoding unit is used to complete the encoding of column 0. At this time, all the input data of the encoding of column 1 are stored in mem1 in order, and the data in mem0 is no longer used. Mem0 is used to store the output of the encoding of column 1, that is, the encoding input of column 2. According to the encoding architecture diagram, the encoding of each column is completed from column 0 to column n-1. When the calculation of the first column n-1 is completed, Coding unit, encoding ends.

[0007] Two blocks of memory are used here, which are called ping-pong memory. When encoding a column, the input data of the column is always read from one block of memory, and the result is written to another block of memory after the encoding is completed. When reading data from one block of memory, the memory address is always in the order of However, when writing data to another memory block, the addresses may not be generated in the natural order, and there may be address interleaving. SUMMARY

[0008] The application aims at the architecture of a polar code encoder, and a storage mechanism called "ping-pong storage" is usually used in the encoding process, which requires two pieces of storage to store the input and output of the XOR operation, respectively; the application uses address two-level mapping, and only one piece of storage is needed to complete the polar code encoding process, thereby saving half of the storage resources.

[0009] The application specifically provides a polar code encoding method for reducing storage resources, which comprises: using only one piece of memory and using address two-level mapping to perform polar code encoding.

[0010] The address two-level mapping polar code encoding further comprises: setting the polar code length as any, and the mother code length used is N=2 n , calculating the parallel degree as P, and having n column encoding processes, which are denoted as 0, 1,..., n-1 columns.

[0011] The address two-level mapping polar code encoding further comprises: reading out the data in the 0th and 1st addresses in the 0th piece of memory mem0, calculating the 0th and 1st encoding units in the 0th column to generate the 0th and 1st addresses in the 1st column, The input of the two encoding units is stored in the 0th and 1st addresses. The input of the two encoding units is stored in the 0th and 1st addresses. The polar code basic encoding unit processes two-bit data, and the encoding unit processes P-bit data in parallel, that is, the size of the encoding unit is times that of the polar code basic encoding unit.

[0012] The address two-level mapping polar code encoding further comprises: reading out the data in the 2nd and 3rd addresses and storing them back to the original addresses after the calculation is completed, so that the 2nd and 3rd addresses respectively store the input of the 1st and 2nd encoding units in the 1st column, The input of the two encoding units is stored in the 0th and 1st addresses. The input of the two encoding units is stored in the 0th and 1st addresses. The input of the two encoding units is stored in the 0th and 1st addresses.

[0013] The address two-level mapping polar code encoding further comprises: when the 1st column is encoded, the input of the 0th and 1st encoding units in the 1st column is first obtained, the input of the 0th and 1st encoding units in the 1st column is located in the 0th and 2nd addresses in the 0th piece of memory mem0, and the 0th and 1st encoding units in the 2nd column are obtained after the XOR operation is completed, The input of two encoding units is stored in the 0th and 2nd addresses;

[0014] Then the input of the 2nd and 3rd encoding units in the 1st column is obtained, the input of the 2nd and 3rd encoding units in the 1st column is respectively located in the 4th and 6th addresses in the 0th memory mem0, and the 1st, The input of two encoding units is stored in the 4th and 6th addresses, and so on, until the 1st column is calculated.

[0015] From the 0th column to the n-1th column, each column is sequentially encoded, and after the 1st, The encoding is completed.

[0016] The application also provides a polar code encoding device for reducing storage resources, which adopts address two-level mapping for polar code encoding, and reduces the storage resources of half of the storage units of the polar code encoder.

[0017] The device comprises a storage unit, a calculation unit and a control unit.

[0018] The number of the storage unit is one block (herein referred to as the storage unit mem0), the width of the storage unit is P bits of the calculation parallelism of the polar code encoding device, and the depth is The storage unit is used for storing the calculation result value of each column in the calculation process of the polar code encoding device, and storing the new calculation result after the next calculation is completed.

[0019] The calculation unit can process P-bit data in parallel, and the calculation unit comprises P polar code basic encoding units; the polar code basic encoding unit is used for realizing XOR operation, and after two-bit input data passes through an XOR gate, the first bit of two-bit output data is obtained, and the second bit of the two-bit input data is directly output as the second bit of the two-bit output data; in the encoding, the The calculation unit is multiplexed for times in each column, and the calculation unit is multiplexed for times in the n-column encoding process. The part of the calculation unit in each multiplexing is referred to as an encoding unit, and the entire encoding process has encoding units.

[0020] The control unit is used for generating various enable signals of the entire polar code encoding device, including the read enable, write enable, read address and write address signals related to the storage unit, and the column number control signal and the encoding unit control signal of each column related to the calculation unit.

[0021] ​Use i to represent the column number control signal, the counter counts from 0 to n-1 in the encoding process, and the counting result is transmitted to i, which represents the current encoding column number in the encoding process, and the mother code length N=2 n Polar code encoding satisfies 0≤i≤n-1;

[0022] Use j to represent the encoding unit control signal in each column, and the counter counts from 0 to

[0023] The calculation unit is used for calculating the data read from the storage unit, and the parallelism of the data is P, that is, P bits of data are input, and the calculation unit writes the result into the storage unit after the calculation is completed, that is, P bits of data are output.

[0024] The calculation unit further comprises an interleaving module, a register and a selector;

[0025] The The data calculated by the basic polar code encoding unit is first stored in the register, and the data calculated by the basic polar code encoding unit in the next period and the data in the register are transmitted into the interleaving module for processing, and the obtained data is selected by the selector and then output as the final result;

[0026] The device specifically comprises the following steps during the polar code encoding: first, determining polar code encoding parameters according to requirements, wherein the polar code encoding parameters comprise a mother code length N, information bits K and a calculation unit data parallelism P, K<N, P<N, and the reliability order of polar sub-channels is determined according to the polar code construction mode; then, mapping N-K frozen bits to N-K polar sub-channels with the worst reliability; mapping K information bits to K polar sub-channels with the best reliability; storing N bits of data in a storage unit; starting encoding, and there are n column encoding processes, starting from the 0th column, and each column of encoding needs to traverse encoding units from top to bottom, and after the encoding unit in each column completes encoding, the encoding of the next column is performed, and then the encoding of the last encoding unit in the n-1th column is completed, and then the encoding is completed; the encoding of each group of encoding units needs to read corresponding data from the storage unit, and the calculation unit stores the result in the corresponding position in the storage unit after the calculation is completed, wherein various control signals (such as read enable, write enable, read address, write address and the like) are given by the control unit.

[0027] In the present application, the method of using ping-pong storage, reading data from one memory in natural order, and writing data to another memory in a special interleaving manner in the prior art is referred to as address-level mapping.​

[0028] The ping-pong storage and the address one-level mapping in the prior art are a simple and conventional scheme, but the feature of requiring double memory will greatly increase the power consumption and resources of the circuit.

[0029] Beneficial effects:

[0030] The address two-level mapping scheme is used to replace the original address one-level mapping scheme, the scheme can replace the original two pieces of storage with one piece of storage on the hardware circuit, and half of the storage resources are saved; the hardware circuit implementation under the address two-level mapping scheme is provided; the polar code coding device is constructed on the basis of the address two-level mapping scheme, compared with the traditional coding device, the hardware resource consumption can be effectively reduced, and here, the area required by the storage unit is reduced by half; for any code length of the polar code, as long as the mother code length N and the parallel degree P of the calculation unit are powers of 2, the address two-level mapping scheme in the application can be used to realize the polar code coding device. BRIEF DESCRIPTION OF DRAWINGS

[0031] The above and other aspects of the application will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings.

[0032] Figure 1 is a polar code coding structure diagram of N=16 and P=2.

[0033] Figure 2 is a polar code coding structure diagram of N=16 and P=2.

[0034] Figure 3 is a polar code coding structure diagram of N=16 and P=2.

[0035] Figure 4 is a polar code coding structure diagram of N=16 and P=2.

[0036] Figure 5 is a polar code coding structure diagram of N=16 and P=2. DETAILED DESCRIPTION

[0037] The application specifically provides a polar code coding method for reducing storage resources, comprising: using only one piece of memory, and using address two-level mapping to perform polar code coding, wherein the address two-level mapping comprises: reading input data of a column from a memory address when performing coding on the column, and writing the input data back to the original address in the memory after coding is completed, and the read address and the write address are the same.

[0038] The address two-level mapping further comprises: setting the polar code length to be arbitrary, and the mother code length used is N=2n , the computational parallelism is P, and there are n columns of encoding processes, recorded as 0, 1, ..., n-1 columns.

[0039] The polar code encoding using the address two-level mapping further includes: reading data at addresses 0 and 1 from the memory block 0 mem0, and calculating the data at addresses 0 and 1 by the encoding units 0 and 1 in the 0th column to generate the data at addresses 0 and 1 in the 1st column. The input of the two encoding units is the 0th and The inputs of the two coding units are stored in addresses 0 and 1. The polar code basic coding unit processes two bits of data, and the coding unit processes P bits of data in parallel, that is, the size of the coding unit is the size of the polar code basic coding unit. times.

[0040] The polar code encoding using address two-level mapping also includes: after the data in the second and third addresses are read out and calculated, they are stored back to the original address. Then, the data stored in the second and third addresses are the first and second addresses of the first column respectively. The input of the two encoding units is calculated in this way, and finally The addresses are stored in the first column. Input to the encoding unit.

[0041] The polar code encoding using the address two-level mapping further includes: when encoding the first column, first obtaining the inputs of the 0th and 1st encoding units of the first column, the inputs of the 0th and 1st encoding units of the first column are respectively located at the 0th and 2nd addresses in the 0th block memory mem0, and after the exclusive OR operation is completed, obtaining the 0th and 2nd addresses of the second column. The inputs of the two encoding units are stored back in addresses 0 and 2;

[0042] Then get the input of the 2nd and 3rd coding units in the 1st column. The input of the 2nd and 3rd coding units in the 1st column are located at the 4th and 6th addresses in the 0th block of memory mem0 respectively. After the calculation, get the 1st and 2nd columns. The input of the two encoding units is stored back in the 4th and 6th addresses, and so on, until the first column calculates the coding units;

[0043] Complete the encoding of each column from column 0 to column n-1 in sequence. When the calculation of column n-1 is completed, After encoding units, the encoding ends.

[0044] The present invention also provides a polar code encoding device that reduces storage resources. The device uses two-level address mapping to perform polar code encoding, reducing the storage resources of a polar code encoder storage unit by half.

[0045] The device includes a storage unit, a computing unit (such asFigure 5 a control unit;

[0046] The number of the storage units is one (denoted as mem0 in the figure), the width of the storage unit is P bits, and the depth is The storage unit is used to store the calculation result value of each column in the calculation process of the polar code encoding device, and store the new calculation result after the next calculation is completed.

[0047] The calculation unit can process P-bit data in parallel, and the calculation unit comprises a polar code basic encoding unit; the polar code basic encoding unit is used to realize XOR operation, and after two-bit input data passes through an XOR gate, the first bit of two-bit output data is obtained, and the second bit of the two-bit input data is directly output as the second bit of the two-bit output data; in the encoding, each column needs to be calculated times of multiplexing of the calculation unit, and n columns of encoding process are times of multiplexing of the calculation unit; the part of the calculation unit in each multiplexing is called an encoding unit, that is, the entire encoding process has encoding units.

[0048] The control unit is used to generate various enable signals of the entire polar code encoding device, including read enable, write enable, read address and write address signals related to the storage unit, and column number control signals and each column encoding unit control signal related to the calculation unit;

[0049] Let i represent the column number control signal, the counter counts from 0 to n-1 in the encoding process, and the counting result is transmitted to i, which represents the current encoding column number in the encoding process, and the mother code length N=2 n satisfies 0≤i≤n-1 when the polar code encoding is used;

[0050] Let j represent the column encoding unit control signal, and the counter counts from 0 to under the condition of parallelism P in each column encoding process of the polar code, and the counting result is transmitted to j, which represents that the current jth encoding unit is being encoded in the ith column encoding process,

[0051] The calculation unit is used to calculate the data read from the storage unit, and the parallelism of the data is P, that is, P-bit data is input, and after the calculation unit completes the calculation, the result is written into the storage unit, that is, P-bit data is output.

[0052] The calculation unit further comprises an interleaving module, a register and a selector.

[0053] The The data calculated by the polar code basic coding unit is first stored in a register, and the data calculated by the polar code basic coding unit in the next period and the data in the register are transmitted into an interleaving module for processing, and the obtained data is selected by a selector and then output as a final result.

[0054] The device comprises the following steps when performing polar code encoding: first, determining polar code encoding parameters according to requirements, wherein the polar code encoding parameters comprise a mother code length N, information bits K, and a calculation unit data parallel degree P, K < N, P < N, and the reliability order of polar sub-channels is determined by a polar code construction method; then, mapping N-K frozen bits to N-K polar sub-channels with the worst reliability; mapping K information bits to K polar sub-channels with the best reliability; storing N bits of data in a storage unit; starting encoding, and performing n column encoding processes, starting from the 0th column, and performing encoding on each column from top to bottom each group of coding units, and storing the results in the storage unit after the calculation unit completes calculation. each group of coding units, and storing the results in the storage unit after the calculation unit completes calculation.

[0055] Embodiment

[0056] The polar code length is set to be arbitrary, the mother code length used is N = 2 n , the calculation parallel degree is P, and there are n column encoding processes, which are denoted as 0, 1,..., n-1 columns. Data in the 0, 1 addresses of the 0th memory mem0 is read out, calculated by the 0th and 1st coding units in the 0th column, and the input of the 0th and 1st coding units in the 1st column is generated. According to the prior art, they should be stored in the 0, addresses of the 1st memory mem1. However, if they are directly stored in the 0, addresses of the 0th memory mem0, the data in the 0, addresses that have not been processed will be overwritten. Since the data in the 0, 1 addresses has been processed, it is no longer needed, and the input of the 0th and 1st coding units in the 1st column can be stored in the 0, 1 addresses. Similarly, the data in the 2, 3 addresses needs to be read out and calculated and then stored back in the original addresses, and the input of the 1st and 2nd coding units in the 1st column is stored in the 2, 3 addresses, respectively. Similarly, the input of the coding units is calculated in turn, addresses of the 1st column, respectively. Similarly, the input of the coding units is calculated in turn, addresses of the 1st column, respectively. Similarly, the input of the coding units is calculated in turn, addresses of the 1st column, respectively. Similarly, the input of the coding units is calculated in turn, The input of two encoding units. When encoding the first column, the input of the 0th and 1st encoding units of the first column is obtained first, which is located in the 0th and 2nd addresses in the memory. After XOR operation, the 0th and 4th encoding units of the second column are obtained, The input of two encoding units is stored in the 0th and 2nd addresses. Then the input of the 2nd and 3rd encoding units of the first column is obtained, which is located in the 4th and 6th addresses in the memory. After calculation, the 1st and 5th encoding units of the second column are obtained, The input of two encoding units is stored in the 4th and 6th addresses. In this way, the calculation of the encoding units of the column is completed. From the 0th column to the (n-1)th column, the encoding of each column is completed in turn. When the 0th encoding unit of the (n-1)th column is calculated, the encoding is completed.

[0057] The present application only uses one memory. When encoding a column, the input data of the column is read from a certain address in the memory. After encoding, the data is written back to the original address in the memory. The read address and the write address are the same. This method is called address two-level mapping.

[0058] According to the above description, the encoding of the polar code can be completed by using only one memory.

[0059] Taking the case of N=16 and P=2 as an example, the encoding structure is shown in Figure 1 The specific mapping is shown in Figure 2 After the calculation of the first column is completed, the 0th, 4th, 1st, 5th, 2nd, 6th, 3rd and 7th encoding units of the second column are stored in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th and 7th addresses in the memory respectively.

[0060] Table 1 shows the reading and writing of each memory during the entire encoding process under the condition of address two-level mapping. The characteristic of address two-level mapping is that the two addresses written this time are the same as the two addresses read two periods ago, that is, the data is read from where it is written back.

[0061] Table 1

[0062]

[0063] The generation of address two-level mapping in hardware circuit is described as follows.

[0064] The counter col_cnt counts the column number from 0 to n-1. Each column has its own address mapping scheme. The original address counter addr_original counts from 0 to ​​count; addr_map represents the address after the address two-level mapping, i.e. the address index where each group of calculation results is stored. When N=16, P=2, the storage address is 0-7, each address is represented by 3 bits in the hardware circuit, from high to low as addr_original[2], addr_original[1], addr_original[0]. As can be seen from Table 2, the rule of address two-level mapping. When the encoding process is the 0th column, the original address and the address after two-level mapping are the same, the result of address two-level mapping is addr_map[2]=addr_original[2], addr_map[1]=addr_original[1], addr_map[0]=addr_original[0]; when the encoding process is the 1st column, the mapped address is obtained by cyclically left shifting the original address once, the result of address two-level mapping is addr_map[2]=addr_original[1], addr_map[1]=addr_original[0], addr_map[0]=addr_original[2]; when the encoding process is the 2nd column, the mapped address is obtained by cyclically left shifting the original address twice and reversing the lowest two bits, the result of address two-level mapping is addr_map[2]=addr_original[0], addr_map[1]=addr_original[1], addr_map[0]=addr_original[2]; when the encoding process is the 3rd column, the mapped address is obtained by cyclically left shifting the original address three times and reversing the lowest three bits, the result of address two-level mapping is addr_map[2]=addr_original[0], addr_map[1]=addr_original[1], addr_map[0]=addr_original[2].

[0065] Table 2

[0066]

[0067] More generally, when N and P are both powers of 2, there are n columns of encoding processes, denoted as 0, 1,..., n-1; the storage unit of the encoder has addresses, denoted as The address is represented by bits in the hardware circuit, denoted as The lowest bit of the address is the 0th bit, and the highest bit of the address is the (a-1)th bit. When the encoding process is in the ith column (0≤i≤a), the address is cyclically left shifted for i times, and the result of the address two-level mapping is obtained by inversely ordering the bits from the 0th bit to the (i-1)th bit; when the encoding process is in the jth column (a<j≤n-1), the result of the address two-level mapping is the same as the result of the address two-level mapping when the encoding process is in the a-th column.

[0068] The storage scheme in the polar code encoding architecture to be implemented adopts the address two-level mapping described above. The entire encoder device design flowchart is shown in Figure 3 When the device performs polar code encoding, first, polar code encoding parameters are determined according to requirements, the polar code encoding parameters include a mother code length N, information bits K, and a data parallel degree P of a calculation unit, K<N, P<N, and the reliability order of polar sub-channels is determined according to the polar code construction method; then, N-K frozen bits are mapped to N-K polar sub-channels with the worst reliability; K information bits are mapped to K polar sub-channels with the best reliability; N bits of data are stored in a storage unit; the encoding is started, there are n columns of encoding processes, the encoding of each column is performed on the encoding unit from top to bottom, and after the encoding of the encoding unit in each column is completed, the encoding of the next column is performed, until the encoding of the last encoding unit in the (n-1)th column is completed, and then the encoding is completed; the encoding of each group of encoding units is performed by reading corresponding data from the storage unit, and the calculation unit stores the result in the corresponding position in the storage unit after the calculation is completed, wherein various control signals such as read enable, write enable, read address, and write address are given by the control unit. According to the above flow, the main architecture of the polar code encoder is shown in Figure 4 , which includes a storage unit, a calculation unit, and a control unit.

[0069] The modules are introduced as follows.

[0070] The storage unit only needs one storage (here, mem0 represents the storage unit), the width of the storage unit is the calculation parallel degree P bits of the polar code encoding device, and the depth is The storage unit is used to store the calculation result value of each column in the calculation process of the polar code encoding device, and store the new calculation result after the next calculation is completed;

[0071] The control unit is used for generating various enable signals of the whole polar code coding device, including read enable, write enable, read address, write address and the like signals related to the storage unit, column number control signal and each column coding unit control signal related to the calculation unit; i represents the column number control signal, the counter counts from 0 to n-1 during the coding process, and the counting result is transmitted to i, which represents the column number during the coding process, and the mother code length N=2 n Polar code coding satisfies 0≤i≤n-1; j represents the each column coding unit control signal, and the counter counts from 0 to P during the coding process of each column of the polar code, and the counting result is transmitted to j, which represents the column number during the coding process, and the mother code length N=2

[0072] The calculation unit is used for calculating the data read from the storage unit, and the data parallelism is P, that is, P-bit data is input, and the calculation unit writes the result into the storage unit after the calculation is completed, that is, P-bit data is output. The calculation unit includes a polar code basic coding unit, an interleaving module, a register, a selector and the like, and the polar code basic coding unit is composed of an exclusive or gate element and a connection line.

[0073] As long as the mother code length N and the calculation unit parallelism P used by the polar code of any code length are powers of 2, the address two-level mapping scheme in the application can be used to realize the polar code coding device.

[0074] The application provides a polar code coding method and device for reducing storage resources, and there are many methods and approaches for specifically realizing the technical scheme, and the above description is only the preferred embodiment of the application, and it should be pointed out that, for ordinary skilled in the art, some improvements and refinements can be made without departing from the principle of the application, and these improvements and refinements should also be regarded as the protection scope of the application. The components not explicitly described in the embodiment can be realized by using the prior art.

Claims

1. A polar code encoding method for reducing storage resources, characterized in that: include: Only one memory block is used, and polar code encoding is performed using two-level address mapping. This means that when encoding a column, the input data for that column is read from an address in the memory, and after encoding, it is written back to the original address in the memory. The read address and the write address are the same. The polar code encoding using the address two-level mapping further includes: setting the polar code length to be arbitrary, and the mother code length N used is 2 n , the computational parallelism is P, there are n columns of encoding processes, recorded as 0, 1, ..., n-1 columns; The polar code encoding using the address two-level mapping further includes: reading data at addresses 0 and 1 from the memory block 0 mem0, and calculating the data at addresses 0 and 1 by the encoding units 0 and 1 in the 0th column to generate the data at addresses 0 and 1 in the 1st column. The input of the two encoding units is the 0th and The inputs of the two coding units are stored in addresses 0 and 1; the polar code basic coding unit processes two bits of data, and the coding unit processes P bits of data in parallel, that is, the size of the coding unit is the size of the polar code basic coding unit. times.

2. The method according to claim 1, characterized in that The polar code encoding using address two-level mapping also includes: after the data in the second and third addresses are read out and calculated, they are stored back to the original address. Then, the data stored in the second and third addresses are the first and second addresses of the first column respectively. The input of the two encoding units is calculated in this way, and finally The addresses are stored in the first column. Input to the encoding unit.

3. The method according to claim 2, characterized in that The polar code encoding using the address two-level mapping further includes: when encoding the first column, first obtaining the inputs of the 0th and 1st encoding units of the first column, the inputs of the 0th and 1st encoding units of the first column are respectively located at the 0th and 2nd addresses in the 0th block memory mem0, and after the exclusive OR operation is completed, obtaining the 0th and 2nd addresses of the second column. The inputs of the two encoding units are stored back in addresses 0 and 2; Then get the input of the 2nd and 3rd coding units in the 1st column. The input of the 2nd and 3rd coding units in the 1st column are located at the 4th and 6th addresses in the 0th block of memory mem0 respectively. After the calculation, get the 1st and 2nd columns. The input of the two encoding units is stored back in the 4th and 6th addresses, and so on, until the first column calculates the coding units; Complete the encoding of each column from column 0 to column n-1 in sequence. When the calculation of column n-1 is completed, After encoding units, the encoding ends.

4. A polar code encoding device for reducing storage resources implemented by the method according to any one of claims 1 to 3, characterized in that: The device adopts address two-level mapping to perform polar code encoding.

5. The polar code encoding device for reducing storage resources according to claim 4, characterized in that: The device includes a storage unit, a computing unit, and a control unit; The number of the storage units is one, denoted as mem0. The width of the storage unit is the computational parallelism P bits of the polar code encoding device, and the depth is The storage unit is used to store the calculation result value of each column during the calculation process of the polar code encoding device, and store the new calculation result after the next calculation is completed; The computing unit is capable of processing P-bit data in parallel, and the computing unit includes Polar code basic coding unit; the polar code basic coding unit is used to implement exclusive OR operation, two bits of input data pass through an exclusive OR gate to obtain the first bit of the two bits of output data, and the second bit of the two bits of input data is directly output as the second bit of the two bits of output data; in the encoding, each column is to be The multiplexing of the computing units is done in a total of n columns. Reuse of secondary computing units; The part of the multiplexing calculation unit each time is called the coding unit, that is, the whole coding process has coding units.

6. The polar code encoding device for reducing storage resources according to claim 5, characterized in that: The control unit is used to generate various enable signals for the entire polar code encoding device, including read enable, write enable, read address, and write address signals related to the storage unit, as well as column number control signals and per-column encoding unit control signals related to the calculation unit; Use i to represent the column number control signal. During the encoding process, the counter counts from 0 to n-1, and the counting result is passed to i. Use i to represent the current number of encoding columns during the encoding process. The mother code length N=2 is used. n The polar code encoding satisfies 0≤i≤n-1; Let j represent the control signal of each column coding unit. In the process of polar code encoding, the counter is counted from 0 to Count, the counting result is passed to j, indicating that the jth encoding unit in the i-th column encoding process is currently encoding, 7. The polar code encoding device for reducing storage resources according to claim 6, characterized in that: The calculation unit is used to calculate the data read from the storage unit. The parallelism of the data is P, which means that P bits of data are input. After the calculation is completed, the calculation unit writes the result into the storage unit, that is, outputs P bits of data.

8. The polar code encoding device for reducing storage resources according to claim 7, characterized in that: The computing unit further includes an interleaving module, a register and a selector; described The data calculated by each polar code basic coding unit is first stored in a register. In the next cycle, the data calculated by the polar code basic coding unit is transmitted to the interleaving module together with the data in the register for processing. The obtained data is selected by the selector and the final result is output. When the device performs polar code encoding, it specifically includes: First, determine the parameters of polar code encoding according to requirements. The parameters of polar code encoding include the mother code length N, the information bit K, and the data parallelism P of the calculation unit. K < N, P < N. Determine the reliability order of polar sub-channels according to the polar code construction method; then map N - K frozen bits to N - K polar sub-channels with the worst reliability; map K information bits to K polar sub-channels with the best reliability; then store N bits of data in the storage unit; start encoding. There are n columns of encoding processes. Start from the 0th column. For each column, traverse the encoding units from top to bottom. After the encoding unit of each column finishes encoding, start encoding the next column until the encoding of the last encoding unit in the (n - 1)th column ends, then the encoding is completed; for the encoding of each group of encoding units, read the corresponding data from the storage unit, and after the calculation unit calculates, store the result in the corresponding position in the storage unit. Various control signals are given by the control unit.

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