Clock synchronization system, method, electronic device and computer readable storage medium

Abstract

The application relates to the technical field of integrated circuits, and discloses a clock synchronization system and method, electronic equipment and a computer readable storage medium. The system is integrated in an SOC chip and comprises a first timing module and a second timing module. The first timing module is used for counting based on a first clock corresponding to a standard mode when a terminal is in the standard mode. The second timing module is used for counting based on a second clock corresponding to a low-power mode after the terminal is switched from the standard mode to the low-power mode, and the counting value of the first timing module is used as an initial counting value. The second timing module is also used for determining a current system time of the terminal based on the initial counting value and a running counting value after the terminal is switched from the low-power mode to the standard mode, the counting value of the second timing module being used as the running counting value, and the current system time is sent to the first timing module for clock synchronization by the first counting module, so that the sleep duration of the terminal is obtained, and the power consumption is low.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a clock synchronization system, method, electronic device, and computer-readable storage medium. Background Technology

[0002] Narrow Band Internet of Things (NBIoT) is an emerging technology in the Internet of Things (IoT) field. It supports low-power transmission modes such as Power Saving Mode (PSM), Discontinuous Reception (DRX), and Extended Discontinuous Reception (eDRX), which can reduce the power consumption of terminals. However, in these low-power modes, the system may be prematurely woken up due to external events. After waking up, the terminal needs to search for the network again and synchronize with the base station in order to communicate, resulting in increased system response time and power consumption.

[0003] To address this issue, the system can employ an external microcontroller unit (MCU) to detect whether the terminal needs to be woken up. The MCU then wakes the terminal and simultaneously uses a counting circuit to obtain the terminal's sleep duration (i.e., the duration of low-power mode) and informs the terminal, thus achieving synchronization between the terminal and the base station. However, this method of obtaining sleep duration requires an additional MCU module, resulting in higher system power consumption. Furthermore, the MCU module requires significant software involvement, and the software implementation itself is complex, making it difficult to implement. Summary of the Invention

[0004] The purpose of this application is to provide a clock synchronization system, method, electronic device, and computer-readable storage medium that can accurately calculate the duration of a terminal in low-power mode, thereby achieving synchronization between the terminal and the base station, and with low power consumption and easy implementation.

[0005] To address the aforementioned technical problems, embodiments of this application provide a clock synchronization system integrated within a SOC chip, comprising: a first timing module and a second timing module, wherein the first timing module is connected to the second timing module; the first timing module is used to count based on a first clock corresponding to the standard mode when the terminal is in standard mode; the second timing module is used to use the count value of the first timing module as an initial count value and to count based on a second clock corresponding to the low-power mode after the terminal switches from the standard mode to a low-power mode; the second timing module is further used to use the count value of the second timing module as a running count value after the terminal switches from the low-power mode to the standard mode, and to determine the current system time of the terminal based on the initial count value and the running count value, and to send the current system time to the first timing module for clock synchronization.

[0006] An embodiment of this application also provides a clock synchronization method applied to the aforementioned clock synchronization system, comprising the following steps: when the terminal is in standard mode, counting is performed based on a first clock corresponding to the standard mode; after the terminal switches from the standard mode to a low-power mode, the count value obtained based on the first clock is used as an initial count value, and counting is performed based on a second clock corresponding to the low-power mode; after the terminal switches from the low-power mode to the standard mode, the count value obtained based on the second clock is used as a running count value, and the current system time of the terminal is determined based on the initial count value and the running count value; clock synchronization is performed according to the current system time of the terminal.

[0007] Embodiments of this application also provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the clock synchronization method described above.

[0008] Embodiments of this application also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described clock synchronization method.

[0009] The clock synchronization system of this application includes a first timing module and a second timing module. The first timing module counts based on a first clock corresponding to the standard mode when the terminal is in standard mode, i.e., in a mode where normal communication is possible. The second timing module uses the count value of the first timing module as an initial count value after the terminal switches from standard mode to low-power mode. The system time when the terminal switches from standard mode to low-power mode can be determined by the initial count value. The second timing module also uses the count value of the second timing module as a running count value after the terminal switches from low-power mode to standard mode. The duration of the terminal in low-power mode can be determined by the running count value. Therefore, based on the initial count value and the running count value, the current system time of the terminal can be determined. Finally, the current system time is sent to the first timing module for clock synchronization, i.e., synchronization of the first clock, which is also synchronization between the terminal and the base station, so that the terminal can resume normal communication with the base station. Since the clock synchronization system of this application is integrated into the SOC chip, no additional MCU module is required, thus reducing the power consumption of the system. Furthermore, the entire clock synchronization process is implemented in hardware without the need for software intervention, making it easy to implement.

[0010] In addition, the clock synchronization system also includes a control module, which is connected to the second timing module. The control module is used to control the terminal to switch from standard mode to low power mode and inform the second timing module. The control module is also used to control the terminal to switch from low power mode to standard mode and inform the second timing module, so as to flexibly realize the adjustment of the terminal between standard mode and low power mode.

[0011] In addition, the clock synchronization system further includes a clock switching module connected to the control module. The control module is further configured to, upon receiving a first mode switching instruction, send a first clock switching instruction to the clock switching module according to the first mode switching instruction, and upon receiving a second mode switching instruction, send a second clock switching instruction to the clock switching module according to the second mode switching instruction. The first mode switching instruction instructs the terminal to switch from the standard mode to the low-power mode, and the second mode switching instruction instructs the terminal to switch from the low-power mode back to the standard mode. The clock switching module is configured to, according to the first clock switching instruction, turn off the first clock and turn on the second clock to instruct the second timing module to count based on the second clock, and according to the second clock switching instruction, turn off the second clock and turn on the first clock to instruct the first timing module to count based on the first clock, thereby enabling the system to use only the timing module and the clock switching module in low-power mode, reducing system power consumption.

[0012] In addition, the clock synchronization system also includes a communication module connected to the control module; the control module is further configured to disable the communication module after the terminal switches from the standard mode to the low-power mode, so as to prevent the terminal from communicating with the base station, and to enable the communication module after the terminal switches from the low-power mode to the standard mode, so as to allow the terminal to communicate with the base station.

[0013] In addition, the second timing module is also used to calibrate the current system time according to the first clock and the second clock, and send the calibrated system time to the first timing module to improve the accuracy of the synchronization clock.

[0014] In addition, the precision of the first clock is greater than that of the second clock, so as to further reduce the power consumption of the system in low-power mode.

[0015] In addition, the first clock is a micro-digitally controlled crystal oscillator (DCXO). Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0017] Figure 1 This is a schematic diagram of a clock synchronization system according to an embodiment of this application. Figure 1 ;

[0018] Figure 2 This is a schematic diagram of a clock synchronization system according to an embodiment of this application. Figure 2 ;

[0019] Figure 3 This is a schematic diagram of a clock synchronization system according to an embodiment of this application. Figure 3 ;

[0020] Figure 4 This is a flowchart of a clock synchronization method according to an embodiment of this application;

[0021] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this application to help readers better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0023] One embodiment of this application relates to a clock synchronization system. The implementation details of the clock synchronization system in this embodiment are described in detail below. The following content is only for the convenience of understanding and is not necessary for implementing this solution.

[0024] The specific structure of the clock synchronization system in this embodiment can be as follows: Figure 1 As shown, it includes: a first timing module 11 and a second timing module 12, the first timing module 11 and the second timing module 12 are connected, and the connection between the first timing module 11 and the second timing module 12 is a hardware module.

[0025] Specifically, the first timing module 11 is used to count based on a first clock corresponding to the standard mode when the terminal is in standard mode. In other words, the system clock used at this time is the first clock.

[0026] Understandably, in standard mode, the terminal can maintain normal communication with the base station or other devices and process services normally. However, in idle state, to avoid increasing system power consumption, it is necessary to control the terminal to switch from standard mode to low-power mode (i.e., sleep mode). In low-power mode, the terminal cannot communicate with the outside world. The second timing module 12 is used to count based on the second clock corresponding to the low-power mode after the terminal switches from standard mode to low-power mode. That is, after the terminal switches from standard mode to low-power mode, the first timing module 11 is turned off, and the system clock used at this time switches from the first clock to the second clock, and the second timing module 12 starts counting based on the second clock. After the terminal switches from standard mode to low-power mode, the second timing module 12 also obtains the count value of the first timing module 11 as the initial count value of the second timing module 12. That is, the second timing module 12 obtains the system time when the terminal switches from standard mode to low-power mode and uses the system time when the terminal switches from standard mode to low-power mode as the initial time for counting.

[0027] The duration of a terminal's low-power mode can usually be set by the user. Under normal circumstances, the terminal can be woken up from low-power mode within a specified time according to the set duration. However, in some cases, the terminal may be woken up by an external event while in low-power mode, i.e., the terminal switches from low-power mode to standard mode. The second timing module 12 is also used as a running count value after the terminal switches from low-power mode to standard mode, that is, to obtain the duration the terminal will be in low-power mode. Therefore, the second timing module 12 can determine the terminal's current system time based on the initial count value and the running count value, i.e., based on the system time when the terminal switches from standard mode to low-power mode and the duration the terminal is in low-power mode, and send the current system time to the first timing module 11 for clock synchronization. That is, the first timing module 11 synchronizes the first clock corresponding to the standard mode based on the current system time, so that the terminal can synchronize with the base station in standard mode.

[0028] In other examples, if the terminal is woken up from low power mode at a specified time according to the set duration, since the duration of the terminal in low power mode is known, the system clock, i.e. the first timing module 11, can be clock synchronized based on this duration.

[0029] In this embodiment, the clock synchronization system includes a first timing module and a second timing module. The first timing module counts based on a first clock corresponding to the standard mode when the terminal is in standard mode, i.e., in a mode capable of normal communication. The second timing module uses the count value of the first timing module as an initial count value after the terminal switches from standard mode to low-power mode. The system time when the terminal switches from standard mode to low-power mode can be determined using the initial count value. The second timing module also uses the count value of the second timing module as a running count value after the terminal switches from low-power mode to standard mode. The duration of the terminal in low-power mode can be determined using the running count value. Therefore, based on the initial count value and the running count value, the current system time of the terminal can be determined. Finally, the current system time is sent to the first timing module for clock synchronization, i.e., synchronization of the first clock, which is also the synchronization between the terminal and the base station, thereby enabling the terminal to resume normal communication with the base station. Since the clock synchronization system of this application is integrated into the SOC chip, no additional MCU module is required, thus reducing system power consumption. Furthermore, the entire clock synchronization process is implemented in hardware without the need for software intervention, making it easy to implement.

[0030] In some embodiments, the clock synchronization system further includes a control module 23, such as Figure 2As shown, the first timing module 21 and the second timing module 22 are the same as the first timing module 11 and the second timing module 12 in the above embodiment, and will not be described again here.

[0031] In this embodiment, the control module 23 is connected to the second timing module 22. The control module 23 controls the terminal to switch from standard mode to low-power mode and informs the second timing module 22. Upon receiving this information, the second timing module 22 uses the count value of the first timing module 21 as its initial count value and counts based on the second clock corresponding to the low-power mode. Correspondingly, the control module 23 also controls the terminal to switch from low-power mode to standard mode and informs the second timing module 22. Upon receiving this information, the second timing module 22 uses its own count value as its running count value and, based on the initial and running count values, determines the terminal's current system time and sends this time to the first timing module 21. In this embodiment, by promptly informing the second timing module of the terminal's current mode, the control module enables the second timing module to take appropriate actions, thus improving response speed.

[0032] In one example, the control module 23 is only used to control the terminal to switch between standard mode and low power mode. However, the specific mode that the terminal should switch to is determined by the upper-layer application software or the user. Therefore, the control module 23 will only control the terminal to switch from standard mode to low power mode after receiving an instruction to instruct the terminal to switch from standard mode to low power mode. Correspondingly, the control module 23 will only control the terminal to switch from low power mode to standard mode after receiving an instruction to instruct the terminal to switch from low power mode to standard mode.

[0033] In some embodiments, since the switching between standard mode and low-power mode by the terminal is essentially due to a switch in their respective system clocks, the switching between standard mode and low-power mode can be achieved by switching between a first clock and a second clock. Therefore, the clock synchronization system also includes, for example, Figure 2 The clock switching module 24 shown is connected to the control module 23, so that the control module 23 can switch between the first clock and the second clock through the clock switching module 24.

[0034] Specifically, control module 23 is also used to receive a first mode switching instruction, which instructs the terminal to switch from standard mode to low-power mode. After receiving the first mode switching instruction, control module 23 sends a first clock switching instruction to clock switching module 24 according to the first mode switching instruction, so that clock switching module 24 turns off the first clock and turns on the second clock according to the first clock switching instruction, that is, switches the system clock from the first clock to the second clock, so as to instruct the second timing module to count based on the second clock, thereby realizing the switching process of the terminal from standard mode to low-power mode. Correspondingly, control module 23 is also used to receive a second mode switching instruction, which instructs the terminal to switch from low-power mode to standard mode. After receiving the second mode switching instruction, control module 23 sends a second clock switching instruction to clock switching module 24 according to the second mode switching instruction, so that clock switching module 24 turns off the second clock and turns on the first clock according to the second clock switching instruction, that is, switches the system clock from the second clock to the first clock, so as to instruct the first timing module to count based on the first clock, thereby realizing the switching process of the terminal from low-power mode to standard mode.

[0035] In one example, to improve the flexibility of clock switching, a switch can be set for the first clock and the second clock respectively. The clock switching module 24 realizes the switching of the first clock and the second clock by controlling the closing of the respective switches of the first clock and the second clock.

[0036] The precision of the first clock is greater than that of the second clock, which enables the system power consumption to be further reduced when the terminal is in low power mode. The first clock can be a micro digitally controlled crystal oscillator (DCXO).

[0037] In some embodiments, due to the difference in accuracy between the first clock and the second clock, the current system time of the terminal determined by the second timing module 22 is deviated. Therefore, the second timing module 22 also includes a compensation mechanism, which enables the second timing module 22 to calibrate the current system time according to the first clock and the second clock, and send the calibrated system time to the first timing module to improve the accuracy of the final clock synchronization.

[0038] In some embodiments, the clock synchronization system further includes a communication module 25, which is connected to the control module 23. When the terminal is in standard mode, it can communicate with the base station through the communication module; when it is in low-power mode, it does not need to communicate with the base station. Therefore, the control module 23 is also used to disable the communication module 25 after the terminal switches from standard mode to low-power mode, thereby preventing the terminal from communicating with the base station. Correspondingly, the control module 23 is also used to enable the communication module 25 after the terminal switches from low-power mode to standard mode, thereby allowing the terminal to communicate with the base station.

[0039] Understandably, in order to ensure normal communication between the base station and the terminal, the clock synchronization system also includes a phase-locked loop circuit connected to the communication module 25.

[0040] In one example, since the first timing module 21, communication module 25, and phase-locked loop are all turned on when the terminal is in standard mode and turned off when the terminal is in low-power mode, in order to improve the flexibility of terminal mode switching, a master switch can be set for the first timing module 21, communication module 25, and phase-locked loop. When the terminal switches from standard mode to low-power mode, the first timing module 21, communication module 25, and phase-locked loop are turned off, and when the terminal switches from low-power mode to standard mode, the first timing module 21, communication module 25, and phase-locked loop are turned on.

[0041] In one embodiment, the clock synchronization system of this application is as follows: Figure 3 As shown, it includes: a first timing module 301, a second timing module 302, a control module 303, a clock switching module 304, a communication module 305, a first clock 306, a second clock 307, a first switch 308, a second switch 309, a phase-locked loop (PLL) 310, and a third switch 311.

[0042] Specifically, when the terminal is in standard mode, if the control module 303 receives a first mode switching command, it controls the first switch 308 to open via the clock switching module 304 and controls the second switch 309 to close, thereby switching the terminal's system clock from the first clock 306 to the second clock 307. Simultaneously, the control module 303 controls the third switch 311 to open, thereby shutting down the first timing module 301, the communication module 305, and the phase-locked loop (PLL) 310. At this point, the terminal has switched from standard mode to low-power mode.

[0043] After the terminal switches from standard mode to low power mode, the second timing module 302 obtains the count value of the first timing module 301, loads it into the second timing module 302 as the initial count value, and at the same time the second timing module 302 starts counting based on the second clock corresponding to the low power mode.

[0044] When the control module 303 receives the second mode switching command, it controls the second switch 309 to open via the clock switching module 304 and controls the first switch 308 to close, thereby switching the terminal's system clock from the second clock 307 to the first clock 306. Simultaneously, the control module 303 controls the third switch 311 to close, thereby opening the first timing module 301, the communication module 305, and the phase-locked loop (PLL) 310. At this time, the second timing module 302 has stopped counting, so its count value is used as the running count value. Based on the initial count value and the running count value, the terminal's current system time is determined and sent to the first timing module 301.

[0045] The first timing module 301 synchronizes the first clock 306 with the current system time of the terminal sent by the second timing module 302, thereby synchronizing the terminal with the base station.

[0046] The clock synchronization system in any of the above embodiments is integrated into the terminal's SOC chip, so there is no need to provide an additional MUX module, which reduces power consumption. Unlike MUX, which requires software cooperation, the entire clock synchronization process can be achieved solely through hardware, reducing the complexity of user operation.

[0047] It should be noted that the examples described above in this embodiment are merely illustrative for ease of understanding and do not constitute a limitation on the technical solution of the present invention.

[0048] It is worth mentioning that all modules involved in this embodiment are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units are absent in this embodiment.

[0049] Another embodiment of this application relates to a clock synchronization method. The implementation details of the clock synchronization method in this embodiment are described below. The following content is only for ease of understanding and is not essential for implementing this solution. The flowchart of the clock synchronization method in this embodiment can be seen as follows: Figure 4 As shown, it includes:

[0050] Step 401: When the terminal is in standard mode, count based on the first clock corresponding to the standard mode.

[0051] Step 402: After the terminal switches from standard mode to low power mode, the count value obtained by counting based on the first clock is used as the initial count value, and counting is performed based on the second clock corresponding to the low power mode.

[0052] Step 403: After the terminal switches from low power mode to standard mode, the count value obtained by counting based on the second clock is used as the running count value, and the current system time of the terminal is determined based on the initial count value and the running count value.

[0053] Step 404: Synchronize the clock according to the current system time of the terminal.

[0054] Specifically, the first clock is synchronized based on the terminal's current system time.

[0055] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0056] It is not difficult to see that this embodiment is a method embodiment corresponding to the above method embodiments, and this embodiment can be implemented in conjunction with the above system embodiments. The relevant technical details and technical effects mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0057] Another embodiment of this application relates to an electronic device, such as... Figure 5 As shown, it includes: at least one processor 501; and a memory 502 communicatively connected to the at least one processor 501; wherein the memory 502 stores instructions executable by the at least one processor 501, the instructions being executed by the at least one processor 501 to enable the at least one processor 501 to perform the clock synchronization methods in the above embodiments.

[0058] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and memories. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.

[0059] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0060] Another embodiment of this application relates to a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the method embodiments described above.

[0061] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0062] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A clock synchronization system, characterized by, Integrated in an SOC chip, comprising: a first timing module and a second timing module, the first timing module being connected with the second timing module; The first timing module is configured to count based on a first clock corresponding to a standard mode when a terminal is in the standard mode; The second timing module is configured to take a count value of the first timing module as an initial count value and count based on a second clock corresponding to a low-power mode after the terminal switches from the standard mode to the low-power mode; The second timing module is further configured to take a count value of the second timing module as a running count value and determine a current system time of the terminal based on the initial count value and the running count value after the terminal switches from the low-power mode to the standard mode, send the current system time to the first timing module for clock synchronization of the first timing module; The clock synchronization system further comprises a control module connected with the second timing module; The control module is configured to control the terminal to switch from the standard mode to the low-power mode and inform the second timing module, and control the terminal to switch from the low-power mode to the standard mode and inform the second timing module; The clock synchronization system further comprises a communication module connected with the control module; The control module is further configured to close the communication module to prohibit the terminal from communicating with a base station after the terminal switches from the standard mode to the low-power mode, and open the communication module to allow the terminal to communicate with the base station after the terminal switches from the low-power mode to the standard mode.

2. The clock synchronization system of claim 1, wherein, The clock synchronization system further comprises a clock switching module connected with the control module; The control module is further configured to send a first clock switching instruction to the clock switching module according to a first mode switching instruction after receiving the first mode switching instruction, and send a second clock switching instruction to the clock switching module according to a second mode switching instruction after receiving the second mode switching instruction; the first mode switching instruction is used to indicate the terminal to switch from the standard mode to the low-power mode, and the second mode switching instruction is used to indicate the terminal to switch from the low-power mode to the standard mode; The clock switching module is configured to close the first clock and open the second clock according to the first clock switching instruction to indicate the second timing module to count based on the second clock, and close the second clock and open the first clock according to the second clock switching instruction to indicate the first timing module to count based on the first clock.

3. The clock synchronization system of claim 1, wherein, The second timing module is further configured to calibrate the current system time according to the first clock and the second clock, and send the calibrated system time to the first timing module.

4. The clock synchronization system of any one of claims 1 to 3, wherein, The first clock has a higher precision than the second clock.

5. The clock synchronization system of any one of claims 1 to 3, wherein, The first clock is a micro digital control crystal oscillator (DCXO).

6. A clock synchronization method characterized by, The method is applied to the clock synchronization system as claimed in any one of claims 1 to 5, and the method comprises: counting based on a first clock corresponding to a standard mode when the terminal is in the standard mode; after the terminal switches from the standard mode to a low-power-consumption mode, taking a count value obtained by counting based on the first clock as an initial count value, and counting based on a second clock corresponding to the low-power-consumption mode; after the terminal switches from the low-power-consumption mode to the standard mode, taking a count value obtained by counting based on the second clock as a running count value, and determining a current system time of the terminal based on the initial count value and the running count value; performing clock synchronization according to the current system time of the terminal.

7. An electronic device, comprising: comprise: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the clock synchronization method as claimed in claim 6.

8. A computer readable storage medium storing a computer program, characterized in that, The computer program is executed by the processor to implement the clock synchronization method as claimed in claim 6.

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