Display substrate, pixel circuit, driving method and display device

Abstract

A display substrate, a pixel circuit, a driving method and a display device, the display substrate comprising: a substrate (10) and a plurality of repeating units arranged in an array on one side of the substrate (10), each repeating unit comprising: at least two light emitting elements (12) and at least two pixel circuits, each pixel circuit comprising: a first transistor (T1), a second transistor (T2) and a third transistor (T3), the third transistor (T3) being configured to drive the light emitting element (12) to emit light, each repeating unit further comprising: a first region (100), a second region (200) and a third region (300) arranged continuously along a first direction, the first region (100) comprising: at least two first transistors (T1), the third region (300) comprising: at least two third transistors (T3), wherein the type of the first transistor (T1) and the type of the third transistor (T3) are different.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate, pixel circuit, driving method, and display device. Background Technology

[0002] Organic light-emitting diode (OLED) display devices offer advantages such as thinness, light weight, wide viewing angle, active emission, continuously adjustable emission color, low cost, fast response speed, low driving voltage, wide operating temperature range, simple manufacturing process, and flexible display capabilities, leading to their increasingly widespread application in displays for mobile phones, tablets, and digital cameras. However, pixel circuits often occupy a large area, which is detrimental to achieving optimal display effects in OLED devices. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, embodiments of this disclosure provide a display substrate, including: a substrate and a plurality of repeating units arranged in an array on one side of the substrate. Each repeating unit includes: at least two light-emitting elements and at least two pixel circuits. Each pixel circuit includes: a first transistor, a second transistor, and a third transistor. The third transistor is configured to drive the light-emitting elements to emit light. Each repeating unit further includes: a first region, a second region, and a third region continuously disposed along a first direction. The first region includes: at least two first transistors. The third region includes: at least two third transistors. The types of the first transistors and the third transistors are different.

[0005] On the other hand, this disclosure also provides a pixel circuit, including: a first transistor, a second transistor, and a third transistor, wherein the control electrode of the first transistor is connected to a scan signal line, the first electrode of the first transistor is connected to a data signal line, and the second electrode of the first transistor is connected to a first node; the control electrode of the second transistor is connected to a reference signal line, the first electrode of the second transistor is connected to a second node, and the second electrode of the second transistor is connected to a first electrode of a light-emitting element; the control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to a first power supply line, and the second electrode of the third transistor is connected to the second node;

[0006] The first transistor is configured to provide a data signal line signal to the third transistor under the control of a scan signal line signal; the second transistor is configured to provide a second node signal to the first electrode of the light-emitting element under the control of a reference signal line signal; and the third transistor is configured to provide a first power line signal to the second node under the control of a data signal line signal.

[0007] In another aspect, embodiments of this disclosure also provide a driving method, including: a data writing stage and a light emission stage, wherein, in the data writing stage, under the control of the signal of the scan signal line, the signal of the data signal line is provided to the control electrode of the third transistor; in the light emission stage, under the control of the signal of the data signal line, the third transistor is turned on, and under the control of the signal of the reference signal line, the second transistor is turned on, and through the third transistor and the second transistor, the signal of the first power line is provided to the first electrode of the light emission element to drive the light emission element to emit light.

[0008] In another aspect, embodiments of this disclosure also provide a driving method, including: a first testing phase, wherein, under the control of a test enable signal line, the connection state of the third transistor is switched from a first connection state to a second connection state, a fixed voltage output by the fourth power line is provided to the third transistor, and the third transistor is controlled to be in a forward bias state; wherein, the first connection state is that the substrate end of the third transistor is connected to the third power line, and the second connection state is that the substrate end of the third transistor is connected to the fourth power line; under the control of a reference signal line, a fixed voltage output by the fourth power line is provided to the first electrode of the light-emitting element to make the light-emitting element emit light.

[0009] In another aspect, embodiments of this disclosure also provide a driving method, including: a second testing phase, wherein, under the control of a switch signal line, the connection state of the fourth transistor is switched between a third connection state and a fourth connection state, and a signal of a monochrome test signal line or a signal of a fourth power supply line is provided to the fourth transistor; wherein, the third connection state is that the second terminal of the fourth transistor is connected to the monochrome test signal line, and the fourth connection state is that the second terminal of the fourth transistor is connected to the fourth power supply line; under the control of a monochrome enable signal line, a light-emitting element connected to the monochrome enable signal line is controlled to emit monochrome light corresponding to the signal of the monochrome enable signal line; the monochrome enable signal line includes one of: a first enable signal line connected to a light-emitting element emitting a first emission color, a second enable signal line connected to a light-emitting element emitting a second emission color, and a third enable signal line connected to a light-emitting element emitting the first emission color.

[0010] In another aspect, embodiments of this disclosure also provide a display device, including: the display substrate described in the above embodiments and the pixel circuit described in the above embodiments.

[0011] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings.

[0012] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects will become clear. Attached Figure Description

[0013] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure, but do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0014] Figure 1A This is a schematic diagram of a display substrate structure in an exemplary embodiment of the present disclosure;

[0015] Figure 1B This is a schematic diagram of a first arrangement of transistors in a display substrate according to an exemplary embodiment of the present disclosure;

[0016] Figure 1C This is a schematic diagram of a second arrangement of transistors in a display substrate according to an exemplary embodiment of the present disclosure;

[0017] Figure 1D This is a schematic diagram of a third arrangement of transistors in a display substrate according to an exemplary embodiment of the present disclosure;

[0018] Figure 1E This is a schematic diagram of a fourth arrangement of transistors in a display substrate according to an exemplary embodiment of the present disclosure;

[0019] Figure 1F This is a schematic diagram of a fifth arrangement of transistors in a display substrate according to an exemplary embodiment of the present disclosure;

[0020] Figure 2 This is a schematic diagram of another structure of the display substrate in an exemplary embodiment of the present disclosure;

[0021] Figure 3 This is a first circuit diagram of a pixel circuit in an exemplary embodiment of the present disclosure;

[0022] Figure 4A This is a signal timing diagram of a pixel circuit in an exemplary embodiment of the present disclosure;

[0023] Figure 4B This is another signal timing diagram of the pixel circuit in an exemplary embodiment of the present disclosure;

[0024] Figure 5 This is a second circuit diagram of the pixel circuit in an exemplary embodiment of the present disclosure;

[0025] Figure 6 This is a third circuit diagram of the pixel circuit in an exemplary embodiment of the present disclosure;

[0026] Figure 7 This is a fourth circuit diagram of the pixel circuit in an exemplary embodiment of the present disclosure;

[0027] Figure 8A This is a fifth circuit diagram of a pixel circuit in an exemplary embodiment of the present disclosure;

[0028] Figure 8B for Figure 8A A schematic diagram of the signal lines and light-emitting elements of the pixel circuit shown;

[0029] Figure 9 This is a schematic diagram of the structure of the active layer and the first conductive layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0030] Figure 10 This is a schematic diagram of the structure of the active layer, the first conductive layer, and the first insulating layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0031] Figure 11 This is a schematic diagram of the structure of the second conductive layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0032] Figure 12This is a schematic diagram of the structure after the formation of the second conductive layer in an exemplary embodiment of this disclosure;

[0033] Figure 13 This is a schematic diagram of the structure of the second conductive layer and the second insulating layer in the display substrate of the exemplary embodiments of this disclosure;

[0034] Figure 14 This is a schematic diagram of the structure of the third conductive layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0035] Figure 15 This is a schematic diagram showing the formation of the third conductive layer in an exemplary embodiment of this disclosure;

[0036] Figure 16 This is a schematic diagram of the structure of the third conductive layer and the third insulating layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0037] Figure 17 This is a schematic diagram of the structure of the fourth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0038] Figure 18 This is a schematic diagram showing the formation of the fourth conductive layer in an exemplary embodiment of this disclosure;

[0039] Figure 19 This is a schematic diagram of the structure of the fourth conductive layer and the fourth insulating layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0040] Figure 20 This is a schematic diagram of the structure of the fifth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0041] Figure 21 This is a schematic diagram of the fourth conductive layer, the fourth insulating layer, and the fifth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0042] Figure 22 This is a schematic diagram of the structure of the sixth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0043] Figure 23 This is a schematic diagram of the structure of the fifth conductive layer, the sixth conductive layer, and the fifth insulating layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0044] Figure 24 This is a schematic diagram of the structure of the seventh conductive layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0045] Figure 25 This is a schematic diagram of the structure of the fifth conductive layer, the sixth conductive layer, the fifth insulating layer, and the seventh conductive layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0046] Figure 26This is a schematic diagram of the structure of the seventh conductive layer and the sixth insulating layer in a display substrate according to an exemplary embodiment of the present disclosure.

[0047] Figure 27 This is a schematic diagram of the structure of the eighth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0048] This document describes several embodiments, but these descriptions are exemplary and not limiting. Many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the accompanying drawings and discussed in exemplary embodiments, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment may be used in conjunction with, or substitute for, any other feature or element of any other embodiment.

[0049] In describing representative embodiments, the specification may have presented a method or process as a specific sequence of steps. However, the method or process should not be limited to a specific order of steps to the extent that it is independent of this specific order. Other orders of steps are possible, as will be understood by those skilled in the art. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Furthermore, the claims relating to the method or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders may be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0050] In the accompanying drawings, the size of each component, the thickness of a layer, or the area are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of each part in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0051] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0052] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or element referred to has a specific orientation, or is constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0053] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0054] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on the "elements that have a certain electrical function," as long as they enable the transmission and reception of electrical signals between the connected components. Examples of "elements that have a certain electrical function" include electrodes or wiring, switching elements such as transistors, or other functional elements such as resistors, inductors, or capacitors.

[0055] In this specification, a transistor is a device comprising at least three terminals: a gate electrode (also called a gate or control electrode), a drain electrode (also called a drain terminal, drain region, or drain), and a source electrode (also called a source terminal, source region, or source). A transistor has a channel region between the drain and source electrodes, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0056] In this specification, to distinguish the two terminals of a transistor other than the control terminal, one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0057] In this specification, the term "co-layer configuration" refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple co-layer configurations may be made of the same material, while the final materials may be the same or different.

[0058] The transistors in this disclosure can all be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. For example, the thin-film transistors used in this disclosure can include, but are not limited to, oxide TFTs or low-temperature poly-silicon TFTs (LTPS TFTs). For example, the thin-film transistor can be a bottom-gate structure thin-film transistor or a top-gate structure thin-film transistor, as long as it can achieve the switching function. Here, this disclosure does not limit this. In addition, according to the characteristics of the transistor, transistors can be divided into N-type transistors and P-type transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltage); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltage).

[0059] OLED displays have small pixel sizes (e.g., less than 100 micrometers), making them suitable for microdisplay applications, such as virtual reality (VR) and augmented reality (AR) near-eye displays. However, pixel circuits typically include multiple transistors and capacitors. Due to limitations in fabrication precision and layout design, pixel circuits often occupy a large area within sub-pixels, hindering pixel size reduction, high-resolution (Pixel Per Inch, PPI) displays, and high-brightness and high-contrast displays. This can lead to reduced pixel circuit performance and reliability, consequently deteriorating display uniformity and reliability. Therefore, higher demands are placed on the structural design of the display substrate, such as the arrangement of pixels and signal lines. Furthermore, when an individual OLED pixel experiences a short circuit between its anode and cathode, a latch-up effect occurs. This latch-up effect can lead to further failure or damage to the pixel circuit, causing defects across the entire display area and severely impacting the user experience.

[0060] This disclosure provides a display substrate. In one exemplary embodiment, the display substrate may be an OLED display substrate. Figure 1A This is a schematic diagram of a display substrate structure in an embodiment of the present disclosure, such as... Figure 1A As shown, in a direction perpendicular to the display device, the OLED display substrate may include: a substrate 10, a pixel circuit layer 11 disposed on the substrate 10, and a plurality of light-emitting elements 12 disposed on the side of the pixel circuit layer 11 away from the substrate 10. For example, the pixel circuit layer 11 may include a plurality of pixel circuits, each configured to drive a plurality of light-emitting elements (i.e., OLED pixels). The circuit structure and layout of the pixel circuits can be designed according to actual conditions, and this disclosure does not limit this aspect. For clarity and brevity, Figure 1A The diagram only schematically shows one transistor in each pixel circuit of the pixel circuit layer 11, configured to be coupled to a subsequently formed light-emitting element. For example, the pixel circuit layer 11 may also include various traces such as scan signal lines and data signal lines, which are not limited in this embodiment. For example, the substrate 10 may be a silicon-based substrate, which may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. For example, the pixel circuits may be fabricated on the silicon-based substrate using silicon semiconductor processes (e.g., CMOS processes), while the light-emitting elements may be fabricated on the silicon-based substrate having the pixel circuits.

[0061] In one exemplary embodiment, such as Figure 1A As shown, taking a transistor as an example, the transistor in the pixel circuit layer 11 may include a gate electrode G, a source electrode S, and a drain electrode D. For example, these three electrodes are electrically connected to three electrode connection portions, such as through tungsten metal-filled vias (i.e., tungsten vias, W-vias); furthermore, these three electrodes can be electrically connected to other electrical structures (e.g., transistors, traces, or light-emitting elements) through their respective electrode connection portions.

[0062] In one exemplary embodiment, such as Figure 1AAs shown, the light-emitting element 12 may include a first electrode 121 (e.g., as an anode), an organic light-emitting functional layer 122, and a second electrode 123 (e.g., as a cathode) stacked sequentially. For example, the first electrode 121 may be electrically connected to the source electrode S of the corresponding transistor via a tungsten via (via a connection portion corresponding to the source electrode S). Here, the positions of the source electrode S and the drain electrode D may be interchanged, i.e., the first electrode 121 may be electrically connected to the drain electrode D. For example, the organic light-emitting functional layer 122 may include an emitted-light (EL) layer, and may also include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the second electrode 123 may be a transparent electrode. For example, the second electrode 123 may be a common electrode, i.e., multiple light-emitting elements (i.e., sub-pixels) in the light-emitting element 12 may share an entire surface of the second electrode 123.

[0063] In one exemplary embodiment, such as Figure 1A As shown, in a direction perpendicular to the display device, the OLED display device may further include: a first encapsulation layer 13, a color filter layer 15, a second encapsulation layer 14, and a cover plate 16 sequentially disposed on a plurality of light-emitting elements 12. For example, the color filter layer 15 may include: a color filter (CF) 151 and a black matrix (BM) 152 located between adjacent color filters 151, wherein the color filter 151 corresponds to the light-emitting element 12 and is configured to allow light emitted by the light-emitting element to pass through, and one color filter 151 and its corresponding light-emitting element can be divided into a sub-pixel. For example, the color filter 151 may include a red (R) filter unit, a green (G) filter unit, and a blue (B) filter unit. The red (R) filter unit, green (G) filter unit, and blue (B) filter unit may correspond to a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, respectively. For example, the material of the color filter 151 can be color photoresist (also known as color adhesive), but is not limited to this. For example, the first encapsulation layer 13 and the second encapsulation layer 14 can be any one or more of polymer and thin film encapsulation (TFE) layers, but are not limited to this. For example, the cover plate 16 can be a glass cover plate, but is not limited to this.

[0064] In one exemplary embodiment, the first direction DR1 can be the extension direction of a scan signal line, and the second direction DR2 can be the extension direction of a data signal line. For example, the first direction DR1 can be the row direction of the array, and the second direction DR2 can be the column direction of the array. For example, the second direction DR2 intersects the first direction DR1 (e.g., the second direction DR2 is perpendicular to the first direction DR1).

[0065] This disclosure provides a display substrate, which may include: a substrate and a plurality of repeating units arranged in an array on one side of the substrate. Each repeating unit may include: at least two light-emitting elements and at least two pixel circuits. Each pixel circuit may include: a first transistor, a second transistor, and a third transistor, wherein the third transistor is configured to drive the light-emitting elements to emit light. Each repeating unit may also include: a first region, a second region, and a third region continuously disposed along a first direction DR1. The first region may include: at least two first transistors, and the third region may include: at least two third transistors. The types of the first transistors and the third transistors are different.

[0066] In one exemplary embodiment, the second region may include at least two second transistors, wherein the first transistor and the second transistor are of the same type.

[0067] In one exemplary embodiment, the size of the third transistor is larger than the size of the first transistor and also larger than the size of the second transistor. For example, multiple third transistors in the third region can be arranged in an array. In this way, by placing relatively large transistors in the same region in an array, the transistor arrangement can be optimized, space can be saved, and thus the area occupied by the pixel circuit in the sub-pixel can be reduced.

[0068] In one exemplary embodiment, each repeating unit may include: six first transistors, six second transistors, and six third transistors.

[0069] The following description, using a repeating unit comprising six first transistors T1, six second transistors T2, and six third transistors T3 as an example, illustrates the transistor arrangement in the repeating unit of the display substrate in the embodiments of this disclosure, in conjunction with the accompanying drawings.

[0070] In one exemplary embodiment, such as Figures 1B to 1F As shown, each repeating unit may include: a first region 100, a second region 200, and a third region 300 continuously disposed along the first direction DR1. The transistor arrangement in the display substrate of this disclosure embodiment may include, but is not limited to, the following:

[0071] In one exemplary embodiment, such as Figure 1BAs shown, in the first region 100, six first transistors T1 are arranged sequentially along the second direction DR2; and in the second region 200, six second transistors T2 are arranged sequentially along the second direction DR2; and in the third region 300, six third transistors T3 are arranged in an array. Thus, by placing identical transistors in the same region, arranging relatively smaller transistors in a column, and relatively larger transistors in an array, the transistor arrangement can be optimized, resulting in a smaller layout area, reducing the area occupied by pixel circuits in sub-pixels, facilitating pixel size reduction, and achieving a higher PPI and better display effect.

[0072] In one exemplary embodiment, such as Figure 1C As shown, in the first region 100, three first transistors T1 and three second transistors T2 are alternately arranged along the second direction DR2; and in the second region 200, three first transistors T1 and three second transistors T2 are alternately arranged along the second direction DR2; and in the third region 300, six third transistors T3 are arranged in an array.

[0073] In one exemplary embodiment, such as Figure 1D As shown, both the first region 100 and the second region 200 may include: a first sub-region 100-1 and a second sub-region 100-2 arranged sequentially along the second direction DR2. In each first sub-region 100-1, three first transistors T1 are arranged sequentially along the second direction DR2. In each second sub-region 100-2, three second transistors T2 are arranged sequentially along the second direction DR2. Furthermore, in the third region 300, six third transistors T3 are arranged in an array.

[0074] In one exemplary embodiment, such as Figure 1E As shown, both the first region 100 and the second region 200 may include: a third sub-region 100-3, a fourth sub-region 100-4, and a fifth sub-region 100-5 arranged sequentially along the second direction DR2. In each third sub-region 100-3, two first transistors T1 are arranged sequentially along the second direction DR2. In each fourth sub-region 100-4, two second transistors T2 are arranged sequentially along the second direction DR2. In each fifth sub-region 100-5, one second transistor T2 and one first transistor T1 are alternately arranged along the second direction DR2. Furthermore, in the third region 300, six third transistors T3 are arranged in an array.

[0075] In one exemplary embodiment, such as Figure 1FAs shown, the first region 100 may include: a sixth sub-region 100-6, a seventh sub-region 100-7, and an eighth sub-region 100-8 arranged sequentially along the second direction DR2. In the sixth sub-region 100-6, two first transistors T1 are arranged sequentially along the second direction DR2. In the seventh sub-region 100-7, two second transistors T2 are arranged sequentially along the second direction DR2. In the eighth sub-region 100-8, two first transistors T1 are arranged sequentially along the second direction DR2. Furthermore, the second region 200 may include: along the second direction DR2... The ninth sub-region 100-9, the tenth sub-region 100-10, and the eleventh sub-region 100-11 are arranged sequentially along the second direction DR2 in the ninth sub-region 100-9. In the tenth sub-region 100-10, two first transistors T1 are arranged sequentially along the second direction DR2. In the eleventh sub-region 100-11, two second transistors T2 are arranged sequentially along the second direction DR2. Furthermore, in the third region 300, six third transistors T3 are arranged in an array.

[0076] Of course, in addition to the arrangement methods listed above, other suitable arrangement methods are also possible, and this disclosure does not limit such arrangements.

[0077] Thus, the display substrate provided in at least one embodiment of this disclosure, based on the pixel circuit structure, can achieve optimized layout and wiring by reasonably optimizing the transistor arrangement, making full use of the layout space, achieving a smaller layout area, reducing the area occupied by the pixel circuit in the sub-pixels, facilitating the reduction of pixel size (for example, achieving a pixel area of ​​4.2μm (micrometers) × 3.15μm = 13.23μm2), achieving a higher PPI and better display effect. Optimized layout and wiring can achieve optimized arrangement of the pixel circuit array, achieving a sub-pixel area of ​​4.2μm × 3.15μm, achieving a higher resolution (PPI), and having a better display effect.

[0078] For example, this display substrate can be used in virtual reality devices or augmented reality devices. For example, the display substrate can be a silicon-based OLED display substrate, or a quantum-dot light-emitting diode (QLED) display substrate, or other types of display substrates. This disclosure does not limit the scope of the application.

[0079] For example, consider a repeating unit comprising six first transistors T1, six second transistors T2, and six third transistors T3. Figure 1B Taking the transistor arrangement shown as an example, Figure 2 This is a schematic diagram of another structure of the display substrate in an exemplary embodiment of this disclosure, as shown below. Figure 2 As shown, the display substrate may include: a substrate (not shown) and a plurality of repeating units arranged in an array on one side of the substrate. Each repeating unit may include: six light-emitting elements (not shown) and six pixel circuits. Each pixel circuit may include: a first transistor T1, a second transistor T2, and a third transistor T3. Each repeating unit may also include: a first region 100, a second region 200, and a third region 300 continuously arranged along a first direction DR1. The first region 100 may include: six first transistors T1 arranged side by side along a second direction DR2. The second region 200 may include: six second transistors T2 arranged side by side along a second direction DR2. The third region 300 may include: six third transistors T3 arranged in a three-row, two-column array along the first direction DR1 and the second direction DR2. The second direction DR2 intersects the first direction DR1 (for example, the second direction DR2 is perpendicular to the first direction DR1). In this embodiment, "side by side" may refer to being arranged in a line. Figure 2 The following is an illustration using a repeating unit as an example.

[0080] In one exemplary embodiment, a light-emitting element and a pixel circuit for driving the light-emitting element can be divided into a sub-pixel, three sub-pixels can be divided into a pixel, and two pixels can be divided into a repeating unit, that is, six light-emitting elements and six pixel circuits for driving the light-emitting elements can be divided into a repeating unit. Here, the embodiments of this disclosure do not limit this.

[0081] The pixel circuit in the display substrate of the present disclosure embodiment will now be described with reference to the accompanying drawings.

[0082] This disclosure also provides a pixel circuit, which may include: an input sub-circuit, a storage sub-circuit, a driving sub-circuit, and a transmission sub-circuit. The input sub-circuit is connected to a data signal line Vdata, a scan signal line Scan, and a first node N1, and is configured to store the data signal line Vdata in the storage sub-circuit and provide a signal for the data signal line Vdata to the driving sub-circuit under the control of the signal from the scan signal line Scan. The storage sub-circuit is connected to the first node N1 and a second power line VSS. The driving sub-circuit is connected to the first node N1, a first power line VDD, a second node N2, and a third power line Vsub, and is configured to provide a signal from the first power line VDD to the second node N2 under the control of the signal from the data signal line Vdata. The transmission sub-circuit is connected to the second node N2, a reference signal line Vref, and a first electrode (e.g., anode) of the light-emitting element L, and is configured to provide a signal from the second node N2 to the first electrode of the light-emitting element L under the control of the signal from the reference signal line Vref. The second electrode (e.g., cathode) of the light-emitting element L is connected to the second power line VSS.

[0083] In one exemplary embodiment, taking an input sub-circuit comprising a first transistor T1, a driving sub-circuit comprising a third transistor T3, and a transmission sub-circuit comprising a second transistor T2 as an example, Figure 3 As shown, the control electrode of the first transistor T1 is connected to the scan signal line Scan, the first electrode of the first transistor T1 is connected to the data signal line Vdata, and the second electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 is configured to provide the data signal line Vdata to the third transistor T3 under the control of the signal from the scan signal line Scan. The control electrode of the third transistor T3 is connected to the first node N1 (i.e., the first control electrode of the third transistor T3 is connected to the first plate of the storage capacitor Cst), the substrate of the third transistor T3 is connected to the third power supply line Vsub, the first electrode of the third transistor T3 is connected to the first power supply line VDD, and the second electrode of the third transistor T3 is connected to the second node N2 (i.e., the second electrode of the third transistor T3 is connected to the first electrode of the second transistor T2). The control electrode of the second transistor T2 is connected to the reference signal line Vref, the first electrode of the second transistor T2 is connected to the second node N2 (i.e., the first electrode of the second transistor T2 is connected to the second electrode of the third transistor T3), the second electrode of the second transistor T2 is connected to the first electrode (e.g., anode) of the light-emitting element L, and the second electrode (e.g., cathode) of the light-emitting element L is connected to the second power supply line VSS.

[0084] In one exemplary embodiment, taking the storage sub-circuit as an example, the pixel circuit may further include a storage capacitor Cst. The storage capacitor Cst may include a first electrode plate and a second electrode plate disposed opposite to each other, wherein the first electrode plate of the storage capacitor Cst is connected to the first node N1, and the second electrode plate of the storage capacitor Cst is connected to the second power line VSS.

[0085] For example, the first transistor T1, the second transistor T2, the third transistor T3, and the storage capacitor Cst can be formed in the area corresponding to the display area of ​​the display substrate.

[0086] In one exemplary embodiment, the pixel circuit may further include: a reset sub-circuit connected to the discharge signal line Discharge, the second node N2 and the initial signal line INIT, configured to provide the initial signal line INIT to the second node N2 under the control of the signal of the discharge signal line Discharge.

[0087] For example, the reset sub-circuit may include: the fourth transistor T4, as shown in the example. Figure 3 As shown, the control electrode of the fourth transistor T4 is connected to the discharge signal line Discharge, the first electrode of the fourth transistor T4 is connected to the second node N2, and the second electrode of the fourth transistor T4 is connected to the initial signal line INIT. For example, the fourth transistor T4 can be formed in a region corresponding to the non-display area of ​​the display substrate.

[0088] In one exemplary embodiment, the first node N1 and the second node N2 do not necessarily represent components that must actually exist, but rather represent the junction of related electrical connections in the circuit diagram.

[0089] In one exemplary embodiment, a first transistor is configured to store a data signal line Vdata to a storage capacitor Cst and provide a signal for the data signal line Vdata to a third transistor T3 under the control of a scan signal line Scan; a second transistor T2 is configured to provide a signal for the second node N2 to a first electrode of the light-emitting element L under the control of a reference signal line Vref; and a third transistor T3 is configured to provide a signal for the first power supply line VDD to the second node N2 under the control of the data signal line Vdata to drive the light-emitting element L to emit light; and a fourth transistor T4 is configured to provide a signal for the initial signal line INIT to the second node N2 under the control of a discharge signal line Discharge.

[0090] In one exemplary embodiment, the first power line VDD can continuously provide a high-level signal.

[0091] In one exemplary embodiment, the second power line VSS can continuously provide a low-level signal. For example, the second power line VSS can provide zero voltage or ground voltage.

[0092] In one exemplary embodiment, the third power line Vsub can continuously provide a low-level signal or can provide a variable voltage signal. For example, the third power line Vsub can provide zero voltage or ground voltage. For example, the third power line Vsub can provide a variable voltage signal from 0V to 5V.

[0093] In one exemplary embodiment, the initial signal line INIT can continuously provide a reset voltage signal, which can be zero voltage or ground voltage, or other fixed levels, such as low voltage, etc. The embodiments of this disclosure are not limited in this regard.

[0094] In one exemplary embodiment, the light-emitting element may include any one of OLED, QLED, and inorganic light-emitting diode. For example, the light-emitting element L may be a micron-scale light-emitting element, such as a micro light-emitting diode (Micro LED), a sub-millimeter light-emitting diode (MiniLED), or a micro organic light-emitting diode (Micro OLED), etc., and this disclosure does not limit the specific application of the light-emitting element.

[0095] In one exemplary embodiment, the storage capacitor Cst can be a capacitor device fabricated through a process, for example, by fabricating dedicated capacitor electrodes. The multiple capacitor electrodes can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. Alternatively, the storage capacitor Cst can be a parasitic capacitance between multiple devices, implemented through the transistor itself and other devices or circuits. The connection method of the storage capacitor Cst includes, but is not limited to, the methods described above; other applicable connection methods can be used, as long as they can store the voltage level of the corresponding node. Here, the exemplary embodiments of this disclosure do not limit this.

[0096] For example, the first transistor T1 and the second transistor T2 can be P-type metal-oxide-semiconductor transistors (PMOS), and the third transistor T3 and the fourth transistor T4 can be N-type metal-oxide-semiconductor transistors (NMOS).

[0097] Figure 4A A signal timing diagram of a pixel circuit provided as an exemplary embodiment of this disclosure. Figure 4B Another signal timing diagram of a pixel circuit provided for an exemplary embodiment of this disclosure. The following is an example... Figure 3 The circuit structure shown is for reference, combined with Figure 4Aand Figure 4B The signal timing diagram shown illustrates the operation of the pixel circuit provided in the exemplary embodiments of this disclosure. Figure 4A and Figure 4B The high and low potentials in the signal timing diagram shown are only schematic and do not represent actual potential values ​​or relative proportions. Corresponding to the embodiments of this disclosure, a low-level signal corresponds to the turn-on signal of a P-type transistor, while a high-level signal corresponds to the turn-off signal of a P-type transistor.

[0098] For example, such as Figure 4A As shown, the operation of the pixel circuit provided in the exemplary embodiment of this disclosure may include three stages: a first stage S1, a second stage S2, and a third stage S3. Figure 4A The timing waveforms of multiple signal lines (Scan signal line, Vdata signal line, Vref signal line, Discharge signal line, and first power supply line VDD) in each stage are shown.

[0099] In one exemplary embodiment, the operation of the pixel circuit in this disclosure may include:

[0100] The first stage, S1, can be called the reset stage or the initialization stage.

[0101] At this stage, such as Figure 4A As shown, the Scan signal line is high in the first stage S1, the Data signal line Vdata is low in the first stage S1, the Reference signal line Vref is low in the first stage S1, the Discharge signal line Discharge is high in the first stage S1, and the First Power Supply line VDD is low in the first stage S1.

[0102] During this stage, because the discharge signal line Discharge is high in stage S1, the fourth N-type transistor T4 is turned on. Therefore, the initial signal line INIT is supplied to the second node N2 via the turned-on fourth transistor T4. Because the reference signal line Vref is low in stage S1, the second P-type transistor T2 is turned on. With both transistors T4 and T2 on, the signal output from the initial signal line INIT is supplied to the first electrode of the OLED via the turned-on fourth transistor T4, the second node N2, and the turned-on second transistor T2, initializing (or resetting) the OLED. The first electrode of the OLED is pulled to 0 potential, quickly discharging (clearing) the charge stored in the first electrode, ensuring the OLED does not emit light, thus achieving better dynamic contrast. The scan signal line Scan is high in stage S1, causing the first P-type transistor T1 to turn off.

[0103] The second stage, S2, can be called the data writing stage.

[0104] At this stage, such as Figure 4A As shown, the Scan signal line is low in the second stage S2, the Data signal line Vdata is high in the second stage S2, the Reference signal line Vref is low in the second stage S2, the Discharge signal line Discharge is low in the second stage S2, and the First Power Supply line VDD is low in the second stage S2.

[0105] During this stage, since the scan signal output by the scan signal line Scan in the second stage S2 is a low-level signal, the first P-type transistor T1 is turned on. Therefore, the signal of the data signal line Vdata is provided to the first node N1 through the turned-on first transistor T1, charging the storage capacitor Cst, so that the signal output by the data signal line Vdata is stored in the storage capacitor Cst. Because the signal of the data signal line Vdata passes through the turned-on first transistor T1 and the first node N1, the third N-type transistor T3 is turned on. Furthermore, since the control signal output by the reference signal line Vref in the second stage S2 is a low-level signal, the second P-type transistor T2 is turned on. Because the control signal output by the discharge signal line Discharge in the second stage S2 is a low-level signal, the fourth N-type transistor T4 is turned off.

[0106] The third stage, S3, is called the luminescence stage.

[0107] At this stage, such as Figure 4AAs shown, the Scan signal line is high in the third stage S3, the Data signal line Vdata is low in the third stage S3, the Reference signal line Vref is low in the third stage S3, the Discharge signal line Discharge is low in the third stage S3, and the First Power Supply line VDD is high in the third stage S3.

[0108] During this stage, because the scan signal line Scan provides a high-level signal in the third stage S3, the first P-type transistor T1 is turned off. Consequently, the storage capacitor Cst provides the signal output from the data signal line Vdata stored in the second stage S2 to the first node N1. Therefore, the third N-type transistor T3 is turned on under the control of the first node N1 (i.e., the signal output from the data signal line Vdata stored in the second stage S2 by the storage capacitor Cst in the data writing stage S2). Since the reference signal line Vref is a low-level signal in the third stage S3, the second P-type transistor T2 is turned on. Therefore, due to the conduction of the third transistor T3 and the second transistor T2, the high-level signal output from the first power line VDD is provided to the first electrode of the OLED through the turned-on third transistor T3, the second node N2, and the turned-on second transistor T2. Thus, under the influence of the high-level signal from the first power line VDD to the first electrode of the OLED and the low-level signal from the second power line VSS to the second electrode of the OLED, the OLED emits light. The discharge signal line Discharge provides a low-level signal in the third stage S3, causing the fourth N-type transistor T4 to turn off.

[0109] In one exemplary embodiment, the S2 data signal line Vdata in the second stage may begin providing a high-level signal with a delay of a certain period of time. For example, as... Figure 4B As shown, after a period of time t1 in the second stage S2, the data signal line Vdata begins to provide a high-level signal and can continue to provide a low-high level signal until the end of the fourth time period t4 in the second stage S2.

[0110] In one exemplary embodiment, the scan signal line Scan in the second stage S2 may begin providing a low-level signal with a delay and end providing a low-level signal a certain time earlier. For example, after the second stage S2 lasts for a period of t1+t2, the scan signal line Scan begins to provide a low-level signal and continues to provide a low-level signal until the end of the third time period t3 in the second stage S2, and then begins to provide a high-level signal in the fourth time period t4.

[0111] Of course, in addition to the two exemplary working sequences mentioned above, other working sequences can be set according to the actual working scenario of the pixel circuit. Here, this disclosure embodiment does not limit this.

[0112] In one exemplary embodiment, when the signal level provided by the data signal line Vdata is low, the gate-source voltage Vgs of the P-type second transistor T2 will be ≤|Vth|, where Vgs represents the gate-source voltage difference of the second transistor T2 (e.g., the voltage difference between the gate electrode and the first electrode of the second transistor T2), and Vth represents the threshold voltage of the second transistor T2. This results in a smaller current flowing through the light-emitting element L, achieving higher contrast. For example, when the signal provided by the data signal line Vdata is 0 grayscale, the current flowing through the light-emitting element L will be smaller, resulting in lower brightness for the 0 grayscale and achieving higher contrast.

[0113] In one exemplary embodiment, since the second electrode (e.g., cathode) of the light-emitting element L is connected to the second power line VSS, and the signal provided by the second power line VSS is a low voltage signal (e.g., negative voltage, which can be generated by the relevant circuit module), the voltage Vcom of the second electrode (e.g., cathode) of the light-emitting element L is a low voltage signal (e.g., negative voltage). Therefore, when a short circuit occurs between the second electrode (e.g., cathode) and the first electrode (e.g., anode) of the light-emitting element L, without the P-type second transistor T2, the voltage of the second node N2 would be pulled low, causing the first terminal (e.g., as the source) of the fourth transistor T4 to be pulled to a negative voltage. This would result in the parasitic PN junction of the fourth transistor T4 being in a forward biased state, thereby triggering a latch-up effect and causing further circuit failure or damage. However, when the P-type second transistor T2 is introduced, when a short circuit occurs between the second electrode (e.g., cathode) and the first electrode (e.g., anode) of the light-emitting element L, the parasitic PN junction of the second terminal (e.g., as the drain) of the P-type second transistor T2 can be in a reverse biased state, thus preventing the latch-up effect and avoiding further circuit failure or damage caused by the latch-up effect. Therefore, the pixel circuit in the exemplary embodiment of this disclosure can prevent malfunctions in the entire display area caused by short circuits between the anode and cathode of individual pixels.

[0114] Here, forward bias (simply referred to as forward bias) means that the gate-source voltage difference of the fourth transistor T4 is greater than the threshold voltage of the fourth transistor T4. At this time, the fourth transistor T4 is turned on and drives the transmission circuit. Reverse bias (simply referred to as reverse bias) means that the gate-source voltage difference of the second transistor T2 is less than 0. At this time, the fourth transistor T4 is turned off.

[0115] In one exemplary embodiment, by selecting a suitable voltage on the reference signal line Vref, the second transistor T2 can act as a clamp, thereby improving the display contrast. For example, when displaying a higher grayscale (e.g., a grayscale greater than a preset value G0 and less than the highest grayscale Gmax), the second transistor T2 has a higher turn-on degree under the control of the voltage on the reference signal line Vref and the second terminal of the third transistor T3, so that the light-emitting element L can have a higher luminous brightness; for example, when displaying a lower grayscale (e.g., a grayscale less than a preset value G0 and greater than the lowest grayscale Gmax), the second transistor T2 has a lower turn-on degree under the control of the voltage on the reference signal line Vref and the second terminal of the third transistor T3, so that the light-emitting element L can have a lower luminous brightness; for example, when displaying the lowest grayscale, the second transistor T2 has an extremely low turn-on degree (e.g., close to the off state) under the control of the voltage on the reference signal line Vref and the second terminal of the third transistor T3, so that the light-emitting element L basically does not emit light.

[0116] In one exemplary embodiment, during the pixel circuit driving process, the driving current flowing through the third transistor T3 (also referred to as the driving transistor) is determined by the voltage difference between the control electrode and the first electrode of the third transistor T3. The driving current of the third transistor T3 is:

[0117] I=K*(Vgs-Vth)2=K*[(Vdd-Vdata)-Vth]2

[0118] Wherein, symbol I represents the driving current flowing through the third transistor T3 (i.e., the driving current driving the OLED), symbol K represents a constant, symbol Vgs represents the voltage difference between the gate electrode and the first electrode (e.g., the source electrode) of the third transistor T3, symbol Vth represents the threshold voltage of the third transistor T3, symbol Vdata can represent both the data signal line and the level of the signal provided by the data signal line, and symbol Vdd represents the voltage of the signal output by the first power supply line VDD.

[0119] In one exemplary embodiment, such as Figure 5As shown, the pixel circuit may further include a substrate voltage control sub-circuit, connected to the substrate terminal of the third transistor T3 via a third power line Vsub, and configured to apply a voltage corresponding to the display mode to the substrate terminal of the third transistor T3 according to the display mode. For example, the display mode may include a high-brightness mode and a low-brightness mode, where the brightness parameter of the high-brightness mode is higher than a preset brightness threshold, and the brightness parameter of the low-brightness mode is not higher than the preset brightness threshold. Then, the substrate voltage control sub-circuit may be configured to apply a first voltage to the substrate terminals of the six third transistors T3 in each repeating unit in the high-brightness mode, or to apply a second voltage to the substrate terminals of the six third transistors T3 in each repeating unit in the low-brightness mode, wherein the absolute value of the first voltage is greater than the absolute value of the second voltage. Thus, by increasing the voltage at the substrate terminal of the third transistor T3 through the substrate voltage control sub-circuit 900 in the high-brightness mode, the threshold voltage of the third transistor T3 can be reduced, and the threshold loss of the maximum trans-voltage of the light-emitting element L can be reduced, which is beneficial for achieving high-brightness display. For example, the substrate voltage control sub-circuit may be formed in a region corresponding to the non-display area of ​​the display substrate.

[0120] In one exemplary embodiment, the second voltage may be zero voltage.

[0121] In one exemplary embodiment, the substrate voltage control subcircuit may include a low-dropout regulator (LDO), the output of which is connected to a third power supply line Vsub and a power source. Thus, the LDO can provide a variable voltage to the substrate of the third transistor T3 via the third power supply line Vsub.

[0122] In one exemplary embodiment, the voltage of the first electrode (e.g., anode) of the light-emitting element L is controlled by the signal of the data signal line Vdata. When the pixel circuit displays a high grayscale, the voltage drop of the second transistor T2 can be ignored, and the voltage of the first electrode (e.g., anode) of the light-emitting element L is Vdata - VGSN2. Therefore, when the light-emitting element L emits light, the voltage across the light-emitting element L is Vdata - VGSN2 - Vcom, where Vcom represents the voltage of the second electrode of the light-emitting element L, Vdata can represent both the data signal line and the level of the signal provided by the data signal line, and VGSN2 represents the threshold voltage (or Vth voltage) of the second transistor T2.

[0123] In one exemplary embodiment, the voltage of the signal provided by the third power line Vsub connected to the substrate of the third transistor T3 is adjustable. For example, the third power line Vsub provides a ground voltage (i.e., the signal level Vsub provided by the third power line Vsub = 0V), meaning the substrate of the third transistor T3 is grounded. Under this condition, when the voltage Vcom of the second electrode (e.g., cathode) of the light-emitting element L is -7.5V, the voltage of the signal provided by the data signal line Vdata can be from 8.0V to 0V. The effective range of the gamma voltage is 8V to 1V, and the voltage difference is 7V. At this time, the voltage of the first electrode (e.g., anode) of the light-emitting element L is at most about 5.0V. Therefore, the maximum voltage across the light-emitting element L can reach 12.5V, thus enabling the driving of the OLED display device. For example, if the signal level provided by the third power line Vsub is Vsub = 5V, that is, the substrate terminal of the third transistor T3 is connected to 5V, under this condition, when the voltage Vcom of the second electrode (e.g., cathode) of the light-emitting element L is -7.5V, the voltage of the signal provided by the data signal line Vdata can be from 8.0V to 0V. The effective range of the gamma voltage is 8V to 5V, and the voltage difference is 3V. At this time, the voltage of the first electrode (e.g., anode) of the light-emitting element L is at most about 6.4V. Therefore, the maximum voltage across the light-emitting element L can reach 13.9V. In this way, the brightness of the OLED can be maximized, and a high-brightness mode can be achieved.

[0124] In one exemplary embodiment, the substrate voltage control sub-circuit includes, for example, an LDO (Light Detector Doppler). The output terminal of the LDO is connected to the third power supply line Vsub, and the substrate terminal of the third transistor T3 is also connected to the third power supply line Vsub. That is, the substrate terminal of the third transistor T3 is connected to the LDO. The voltage of the LDO is adjustable between 0V and 5V, enabling the driving of high-brightness OLED devices. Furthermore, since the substrate terminal of the third transistor T3 is connected to the LDO, the matching and compatibility of OLED devices with different voltage ranges can be achieved by changing the voltage of the LDO.

[0125] In one exemplary embodiment, when the target display grayscale of the light-emitting element L is greater than a preset value G0 (i.e., the target display grayscale is between G0 and Gmax, with Gmax being the highest grayscale), the voltage of the signal output by the third power line Vsub can be increased to reduce the threshold voltage of the third transistor T3, thereby reducing the threshold loss of the maximum trans-voltage of the light-emitting element L (such as an OLED device), which is beneficial for achieving high brightness.

[0126] In one exemplary embodiment, such as Figure 6As shown, each pixel circuit may further include: a gate voltage control sub-circuit connected to the reference signal line Vref; in each repeating unit, the control electrodes of six first transistors T1 in the first transistor column are connected and connected to the gate voltage control sub-circuit; the control electrodes of six second transistors T2 in the second transistor column are connected and connected to the gate voltage control sub-circuit; the gate voltage control sub-circuit is configured to provide a variable voltage to one or more of the control electrodes of the six first transistors T1 and the six second transistors T2 in each repeating unit. For example, the gate voltage control sub-circuit may be formed in a region corresponding to the non-display area of ​​the display substrate.

[0127] Thus, the control electrodes of the first transistor T1 and the second transistor T2 are both connected to the reference signal line Vref, and the gate voltage control sub-circuit is also connected to the reference signal line Vref. In other words, the control electrodes of the first transistor T1 and the second transistor T2 are connected to the gate voltage control sub-circuit. In this way, by providing a variable voltage to the control electrodes of the first transistor T1 and the second transistor T2 through the gate voltage control sub-circuit, a sufficient range of values ​​for the data signal line Vdata can be guaranteed, improving contrast and enabling the driving of high-brightness OLED devices, thereby increasing the PPI of the OLED.

[0128] In one exemplary embodiment, the gate voltage control sub-circuit may include an LDO, the output of which is connected to a reference signal line Vref and a power supply. Thus, the LDO can provide a variable voltage to the control gate of the first transistor T1 and the control gate of the second transistor T2 via the reference signal line Vref.

[0129] In one exemplary embodiment, the control electrode of the first transistor T1 is connected to an LDO with a variable voltage, thereby ensuring a sufficient range of values ​​for the data signal line Vdata. For example, the voltage provided by the LDO can be -2.5V, meaning the voltage of the reference signal line Vref can be -2.5V. While ensuring normal operation of the display device, the voltage of the data signal line Vdata can reach a maximum of 5.5V. At this higher voltage, finer grayscale division and smoother transitions at lower grayscale levels are achieved. Furthermore, by connecting the control electrode of the P-type first transistor T1 to an LDO to ensure the range of values ​​for the data signal line Vdata, the use of P-type MOS transistors (also known as PMOS transistors) can be reduced. Compared to the transmission gate switch composed of a combination of P-type and N-type MOS transistors (also known as NMOS transistors) in some technologies, this maximizes the PPI (pixel density) within a limited pixel area.

[0130] In highly integrated and miniaturized silicon-based OLED display devices, in order to achieve minimum structural size matching and miniaturize the OLED display device, some technologies use NMOS transistors as driving transistors in pixel circuit structures. By applying a positive voltage to the substrate of the NMOS transistor, a positive voltage is applied to the anode of the OLED through the forward-biased parasitic PN junction, and a negative voltage is applied to the cathode to achieve the lighting of the entire OLED. However, this structure is not suitable for pixel circuit structures with PMOS transistors at the anode of the OLED.

[0131] In one exemplary embodiment, such as Figure 7 As shown, the pixel circuit may further include: a first test circuit, connected to the test enable signal line CE, the third transistor T3, the third power supply line Vsub, and the fourth power supply line GND, configured to switch the connection state of the third transistor T3 from a first connection state to a second connection state under the control of the test enable signal line CE, providing a fixed voltage output from the fourth power supply line GND to the third transistor T3, and controlling the third transistor T3 to be in a forward bias state; wherein, in the first connection state, the substrate end of the third transistor T3 is connected to the third power supply line, and in the second connection state, the substrate end of the third transistor T3 is connected to the fourth power supply line GND; a second transistor T2, configured to provide a fixed voltage output from the fourth power supply line GND to the first electrode of the light-emitting element under the control of the reference signal line Vref, so as to make the light-emitting element emit light. Thus, by switching the connection state of the third transistor T3 to achieve two-point testing, it is possible to eliminate the lighting modes of all driving circuits, clarify problems between the backplane and the light-emitting element (such as OLED), facilitate verification of the anode uniformity of the light-emitting element (such as OLED), and improve product yield. For example, the first test circuit can be formed in a region corresponding to the non-display area of ​​the display substrate.

[0132] For example, during normal display, the substrate of the third transistor T3 is switched to be connected to the third power line Vsub.

[0133] For example, when entering AOI (Automatic Optic Inspection) mode, the AOI_EN pin is pulled high to provide an electrical signal to the test enable signal line CE to enter AOI-1 mode. Under the control of the test enable signal line CE, the substrate of the third transistor T3 switches to be connected to the fourth power supply line GND. At this time, there is a parasitic diode (also called a PN junction) between the substrate of the third transistor T3 and its second terminal (e.g., as the source). When a positive voltage is applied to the fourth power supply line GND, the parasitic diode of the third transistor T3 (e.g., an NMOS transistor) will conduct, and a negative voltage will be applied to the reference signal line Vref, causing the second transistor T2 (e.g., an NMOS transistor) to conduct. For example, if a PMOS transistor is turned on, the positive voltage of the fourth power line GND can be transmitted to the first electrode of the light-emitting element L (e.g., the anode of an OLED) through the forward-biased parasitic diode. At this time, the current flows from the pin of the fourth power line GND through the parasitic diode to the second transistor T2 (e.g., a PMOS transistor), and then flows down to the first electrode of the light-emitting element L (e.g., the anode of an OLED), causing it to emit light. It does not pass through the third transistor T3 above (e.g., an NMOS transistor), which is equivalent to directly applying voltage between the anode and cathode of the light-emitting element L (such as an OLED), realizing the lighting of the light-emitting element L by simply applying voltage at two points. Therefore, through the first test circuit, the lighting mode of the driver sub-circuit (i.e., the third transistor T3) in the pixel circuit can be eliminated, which can accelerate the clarification of problems between the backplane and the light-emitting element L (such as an OLED), and can quickly locate the defect. Moreover, under this lighting method, the uniformity of light emission of the light-emitting element L (such as OLED) is related to the uniformity of the anode process. Therefore, it is convenient to verify the uniformity of the anode of the light-emitting element (such as OLED), improve the product yield, and play an important role in the testing and analysis of silicon-based OLED displays.

[0134] In one exemplary embodiment, such as Figure 7As shown, the first test circuit may include: a first switching device and a second switching device; the first terminal of the first switching device is connected to the substrate terminal of the third transistor T3, and the second terminal of the first switching device is connected to the third power supply line Vsub; the first terminal of the second switching device is connected to the substrate terminal of the third transistor T3, and the second terminal of the second switching device is connected to the fourth power supply line GND; the first test circuit is configured to switch the first switching device from an on state to an off state and switch the second switching device from an off state to an on state under the control of the test enable signal line CE. Thus, by connecting the third transistor T3 (i.e., the driving transistor) to the switch device controlled by the signal on the test enable signal line CE (i.e., the control signal for the switch), the voltage at the substrate of the third transistor T3 (i.e., the driving transistor) can switch between the voltage of the signal on the third power line Vsub and the signal on the fourth power line GND. In this way, when the second switch device switches to the on state, the substrate of the third transistor T3 switches to the connection with the fourth power line GND. A positive voltage is applied to the fourth power line GND, and a negative voltage is applied to the reference signal line Vref, causing the second transistor T2 (e.g., a PMOS transistor) to conduct. At this time, the positive voltage provided by the fourth power line GND can be transmitted to the first electrode of the light-emitting element (e.g., the anode of the OLED) through the forward-biased parasitic diode. This can eliminate the lighting mode of the pixel circuit, clarify the problem between the backplane and the light-emitting element (e.g., OLED), facilitate the verification of the uniformity of the anode of the light-emitting element (e.g., OLED), improve the product yield, and play an important role in the testing and analysis of silicon-based OLED displays.

[0135] In highly integrated and miniaturized silicon-based OLED display devices, in order to achieve minimum structural size matching and miniaturize the OLED display device, some pixel circuit structures using NMOS transistors as driving transistors cannot light up the OLED in monochrome, and are not suitable for pixel circuit structures with PMOS transistors added to the OLED anode.

[0136] Figure 8A This is a fifth schematic diagram of the pixel circuit of a display substrate according to an exemplary embodiment of the present disclosure. Wherein, Figure 8A Taking red as the first color, green as the second color, and blue as the third color as an example, Figure 8AAs shown, the pixel circuit may further include: a second test circuit; wherein, the control electrode of the fourth transistor T4 is connected to the monochrome enable signal line DIS_EN_R / G / B, and the fourth transistor T4 is further configured to control the light-emitting element L connected to the monochrome enable signal line DIS_EN_R / G / B to emit monochrome light corresponding to the signal of the monochrome enable signal line DIS_EN_R / G / B under the control of the signal of the monochrome enable signal line DIS_EN_R / G / B; the monochrome enable signal line DIS_EN_R / G / B includes: a first enable signal line DIS_EN_R connected to the light-emitting element L emitting red light, and a second enable signal line DIS_E connected to the light-emitting element L emitting green light. One of N_G and a third enable signal line DIS_EN_B connected to the light-emitting element L that emits blue light; a second test circuit, connected to a fourth transistor T4, a switch signal line, a monochrome test signal line IS_OPT, and a fourth power supply line GND, is configured to switch the connection state of the fourth transistor T4 between a third connection state and a fourth connection state under the control of the signal from the switch signal line, and to provide the fourth transistor T4 with either the signal from the monochrome test signal line IS_OPT or the signal from the fourth power supply line GND; wherein, in the third connection state, the second terminal of the fourth transistor T4 is connected to the monochrome test signal line IS_OPT, and in the fourth connection state, the second terminal of the fourth transistor T4 is connected to the fourth power supply line GND. Thus, by connecting the control electrode of the fourth transistor T4 to the monochrome enable signal line DIS_EN_R / G / B, the fourth transistor T4 can switch between the monochrome test signal line IS_OPT and the fourth power supply line GND to achieve monochrome two-point testing. This can eliminate the lighting modes of all driving circuits, clarify the problems between the backplane and the light-emitting element (such as OLED), facilitate the verification of the uniformity of the anode of the light-emitting element (such as OLED), and improve the product yield.

[0137] For example, the second test circuit can be formed in a region corresponding to the non-display area of ​​the display substrate.

[0138] For example, when entering the monochrome test mode of AOI mode, the second terminal of the fourth transistor T4 is connected to the monochrome test signal line IS_OPT. A positive voltage is applied to the monochrome test signal line IS_OPT, and a negative voltage is applied to the reference signal line Vref, causing the second transistor T2 (e.g., a PMOS transistor) to conduct. At this time, the positive voltage of the monochrome test signal line IS_OPT can be transmitted to the first electrode of the light-emitting element (e.g., the anode of an OLED) to make it emit light, without passing through the third transistor T3 above (e.g., an NMOS transistor). This is equivalent to directly applying voltage between the anode and cathode of the light-emitting element L (such as an OLED), realizing the lighting of the light-emitting element L by simply applying voltage at two points. Thus, through the second test circuit, a monochrome lighting mode that excludes the driving sub-circuit (i.e., the third transistor T3) in the pixel circuit can be realized, which can accelerate the clarification of problems between the backplane and the light-emitting element (such as an OLED). Moreover, under this lighting method, the uniformity of light emission of the light-emitting element L (such as OLED) is related to the uniformity of the anode process. Therefore, it is convenient to verify whether the anode of the light-emitting element (such as OLED) is adhered and uniform, improve the product yield, and play an important role in the testing and analysis of silicon-based OLED displays.

[0139] For example, such as Figure 8B As shown, the control electrode of the fourth transistor T4 controls the upper end of all light-emitting elements L (e.g., as R sub-pixels) emitting red light by switching to the connection of the first enable signal line DIS_EN_R; the control electrode of the fourth transistor T4 controls the upper end of all light-emitting elements L (e.g., as G sub-pixels) emitting green light by switching to the connection of the second enable signal line DIS_EN_G; and the control electrode of the fourth transistor T4 controls the upper end of all light-emitting elements L (e.g., as B sub-pixels) emitting blue light by switching to the connection of the third enable signal line DIS_EN_B. The upper end of the sub-pixel and the lower ends of all light-emitting elements L (including RGB sub-pixels) can be connected together and connected to the signal line DIS_OPT. The signal line DIS_OPT is connected to the switch signal outside the display area (also known as the AA area), and is connected to the monochrome test signal line IS_OPT and the fourth power line GND respectively. When normal display is achieved, the second terminal of the fourth transistor T4 is connected to the fourth power line GND. When performing monochrome RGB lighting test, the second terminal of the fourth transistor T4 is connected to the monochrome test signal line IS_OPT.

[0140] In one exemplary embodiment, the first color, the second color, and the third color can be one of red, green, and blue, and they are all different from each other.

[0141] In one exemplary embodiment, such as Figure 8AAs shown, the second test circuit may include: a third switching device and a fourth switching device; the first terminal of the third switching device is connected to the second terminal of the fourth transistor T4, and the second terminal of the third switching device is connected to the monochrome test signal line IS_OPT; the first terminal of the fourth switching device is connected to the second terminal of the fourth transistor T4, and the second terminal of the fourth switching device is connected to the fourth power supply line GND.

[0142] The following example uses a pixel circuit comprising a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor. Another example uses a repeating unit comprising six first transistors T1, six second transistors T2, and six third transistors T3. Figure 1B Taking the transistor arrangement shown as an example, combined with Figure 2 The layout of the display substrate shown is provided as an example to illustrate the layout and wiring of the display substrate provided in at least one embodiment of this disclosure. In this embodiment, a silicon substrate is used as an example for illustration.

[0143] In one exemplary embodiment, the display substrate may include, in a direction perpendicular to the substrate, an active layer, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, a fourth conductive layer, a fourth insulating layer, a fifth conductive layer, a sixth conductive layer, a fifth insulating layer, a seventh conductive layer, a sixth insulating layer, and an eighth conductive layer, which are sequentially stacked on the substrate. Here, in this embodiment, "sequentially stacked" means that the active layer, the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, the third conductive layer, the third insulating layer, the fourth conductive layer, the fourth insulating layer, the fifth conductive layer, the sixth conductive layer, the fifth insulating layer, the seventh conductive layer, the sixth insulating layer, and the eighth conductive layer are stacked in a direction away from the substrate, but does not necessarily mean that these layers are necessarily bonded together in pairs.

[0144] In one exemplary embodiment, the substrate can be a rigid substrate, such as a glass substrate or a silicon substrate; or, the substrate can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyaryl compounds, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymers (COP), or cyclic olefin copolymers (COC). The embodiments described herein all use a silicon substrate as an example; however, the embodiments of this disclosure are not limited thereto.

[0145] In one exemplary embodiment, the substrate may include monocrystalline silicon or high-purity silicon. The pixel circuit is formed on the substrate using CMOS semiconductor processes. For example, the active regions of transistors (including the channel region, first region, and second region of the transistor) are formed in the substrate through a doping process, and multiple insulating layers are formed through silicon oxidation or chemical vapor deposition (CVD), and multiple conductive layers are formed through a sputtering process to form a wiring structure. The active regions of the multiple transistors are located inside the substrate.

[0146] The following explanation uses the example of the first transistor T1 and the second transistor T2 being P-type transistors and the third transistor T3 being an N-type transistor in the pixel circuit of the display area to illustrate the layered structure of the display substrate.

[0147] The fabrication process of the display substrate according to exemplary embodiments of this disclosure may include the following steps.

[0148] (1) An active layer and a first conductive layer are formed on a substrate.

[0149] In one exemplary embodiment, a silicon substrate is provided, for example, whose material is P-type single-crystal silicon. For example, an N-type transistor (e.g., a third transistor T3) can be directly fabricated on this P-type silicon substrate, that is, the P-type silicon substrate serves as the channel region of the N-type transistor, which is beneficial to taking advantage of the high speed of NMOS devices and improving circuit performance. For example, N-type doping is performed on the P-type silicon substrate to form an N-type well region to serve as the substrate for P-type transistors (e.g., a first transistor T1 and a second transistor T2).

[0150] In one exemplary embodiment, a gate insulating layer is formed on the aforementioned substrate, and then a first conductive layer is formed on the gate insulating layer using a patterning process. For example, the gate insulating layer is formed on the substrate by thermal oxidation, and the material of the gate insulating layer can be a silicon nitride, oxide, or oxynitride. Then, a first conductive material layer is formed on the gate insulating layer by chemical vapor deposition (PVD), and the first conductive material layer is formed by photolithography. The material of the first conductive layer can be polycrystalline silicon, and the first conductive layer can be referred to as a polycrystalline silicon layer.

[0151] In one exemplary embodiment, the N-type doping process can be, for example, an ion implantation process, and the doping element can be, for example, boron. The P-type doping process can be, for example, an ion implantation process, and the doping element can be, for example, phosphorus.

[0152] In one exemplary embodiment, N-type doping and P-type doping can be performed separately during the doping process. For example, taking the formation of the first and second regions of an N-type transistor and the first and second regions of a P-type transistor as examples, during the N-type doping process, a barrier layer can be formed to shield the regions that are not N-type doped; during the P-type doping process, a barrier layer can be formed to shield the regions that are not P-type doped.

[0153] In one exemplary embodiment, during the doping process, such as using an ion implantation process, the pattern of the first conductive layer (e.g., a polysilicon layer) can act as a mask, ensuring that ion implantation into the silicon substrate occurs precisely on both sides of the polysilicon, thereby forming the first and second regions of multiple transistors and achieving self-alignment. Furthermore, the resistivity of the originally high-resistivity polysilicon decreases after the doping process, allowing the formation of control electrodes for multiple transistors. Therefore, using polysilicon as the control electrode material for multiple transistors offers several advantages and reduces process costs.

[0154] In one exemplary embodiment, Figure 9 This is a schematic diagram of the structure of the active layer and the first conductive layer in the display substrate of an exemplary embodiment of the present disclosure, as shown below. Figure 9 As shown, the active layer may include: the active region of the first transistor T1, the active region of the second transistor T2, the active region of the third transistor T3, a first contact region 410 in the P-type substrate, and a second contact region 420 in the N-type well region. For example, the active regions of the first transistor T1, the second transistor T2, and the third transistor T3 extend along a first direction DR1. For example, the active regions of the first transistor T1 and the second transistor T2 are arranged along a second direction DR2 on the same side of the active region of the third transistor T3.

[0155] In one exemplary embodiment, such as Figure 9 As shown, the active region of the first transistor T1 may include: a first region 101 and a second region 102 located on both sides of the active region of the first transistor T1, and a channel (not shown in the figure) located between the first region 101 and the second region 102; the active region of the second transistor T2 may include: a first region 201 and a second region 202 located on both sides of the active region of the second transistor T2, and a channel (not shown in the figure) located between the first region 201 and the second region 202; the active region of the third transistor T3 may include: a first region 301 and a second region 302 located on both sides of the active region of the third transistor T3, and a channel (not shown in the figure) located between the first region 301 and the second region 302.

[0156] In one exemplary embodiment, such as Figure 9As shown, in each repeating unit, the active regions of multiple first transistors T1 and multiple second transistors T2 can be located in the same doped region (P-type well region). Thus, compared to setting separate well regions, this arrangement allows for a more compact pixel arrangement while meeting design rules, contributing to improved resolution of the display substrate.

[0157] In one exemplary embodiment, such as Figure 9 As shown, in each repeating unit, along the first direction DR1, the active regions of two adjacent third transistors T3 can be an interconnected integral structure. That is, the active regions of the two third transistors T3 are located in the same doped region (N-type well region), and the first regions of the two third transistors T3 are interconnected integral structures, so that the first electrodes of the two third transistors T3 are interconnected integral structures to receive signals provided by the same first power line VDD. In this way, the active regions of two adjacent third transistors T3 can be formed in the same patterning process, thereby saving process time, reducing production costs, and reducing the total area occupied by the third transistors T3 in the pixel area. This helps to reduce the pixel area and thus achieve high resolution in the display product.

[0158] Here, "integrated structure" in the embodiments of this disclosure can refer to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, which are connected to each other and whose materials may be the same or different.

[0159] In one exemplary embodiment, such as Figure 9 As shown, the area of ​​the active region of the third transistor T3 is larger than that of the active regions of other transistors (e.g., at least one of the first transistor T1 and the second transistor T2), which can achieve a larger aspect ratio, thus helping to improve the driving capability of the third transistor T3 and thereby improve the display effect.

[0160] In one exemplary embodiment, such as Figure 9As shown, the active layer may include a first contact region 410 and a second contact region 420, wherein the first contact region 410 and the second contact region 420 are doped regions of different types. For example, the first contact region 410 is a heavily doped P-type region (P+). For example, the first contact region 410 is used to bias the P-type substrate where the third transistor T3 is located, thereby avoiding threshold voltage changes caused by parasitic effects such as substrate bias effects and improving circuit stability. For example, the second contact region 420 is a heavily doped N-type region (N+). For example, the second contact region 420 is used to bias the N-type well region where the third transistor T3 is located, thereby avoiding threshold voltage changes caused by parasitic effects such as substrate bias effects and improving circuit stability. For example, by connecting the first contact area 410 to the fourth power line GND (or the third power line Vsub) and the second contact area 420 to the fifth power line AVDD, the P-type substrate can be low-voltage biased and the N-type well region can be high-voltage biased. This allows the parasitic PN junction between the two to be reverse biased, electrically isolating the devices, reducing parasitic effects between devices, and improving circuit stability.

[0161] In one exemplary embodiment, such as Figure 9 As shown, the first conductive layer may include: the control electrode 103 of the first transistor T1, the control electrode 203 of the second transistor T2, and the control electrode 303 of the third transistor T3.

[0162] In one exemplary embodiment, such as Figure 9 As shown, in each repeating unit, the control electrodes 103 of two adjacent first transistors T1 on the second direction DR2 can be an integrated structure connected to each other. Thus, compared to separate arrangements, this arrangement allows for a more compact pixel arrangement while meeting design rules, contributing to improved resolution of the display substrate.

[0163] In one exemplary embodiment, such as Figure 9 As shown, in each repeating unit, the control electrodes 203 of two adjacent second transistors T2 on the second direction DR2 can be an integrated structure connected to each other. Thus, compared to separate arrangements, this arrangement allows for a more compact pixel arrangement while meeting design rules, contributing to improved resolution of the display substrate.

[0164] In one exemplary embodiment, in a plurality of repeating units, the control electrodes of corresponding transistors in two adjacent repeating units along a first direction DR1 are symmetrical about a symmetry axis along a second direction, which intersects the first direction. That is, the pattern of the first conductive layer (e.g., a polysilicon layer) can be a symmetrical pattern. For example, the display substrate may include: a first repeating unit, a second repeating unit, and a third repeating unit arranged sequentially along the first direction DR1, wherein the first repeating unit may include: a first transistor column, a second transistor column, and a third transistor array arranged sequentially along the first direction DR1; the second repeating unit may include: a third transistor array, a second transistor column, and a first transistor column arranged sequentially along the first direction DR1; and the third repeating unit may include: a first transistor column, a second transistor column, and a third transistor array arranged sequentially along the first direction DR1. Then, the control electrodes of corresponding transistors in the first and second repeating units can be symmetrical about a first symmetry axis along a second direction DR2, and the control electrodes of corresponding transistors in the second and third repeating units can be symmetrical about a second symmetry axis along the second direction DR2, which is parallel to the first symmetry axis. This symmetrical arrangement can maximize the uniformity of process errors, thereby improving the uniformity of the display substrate. Furthermore, this symmetrical arrangement allows some structures on the same layer of the substrate that can be connected to each other to be formed as a single unit. Compared with separate arrangements, this makes the pixel layout more compact, improves space utilization, and thus improves the resolution of the display substrate.

[0165] (2) A first insulating layer and a second conductive layer are sequentially formed on the substrate on which the aforementioned structure is formed.

[0166] In one exemplary embodiment, Figure 10 This is a schematic diagram of the structure of the active layer, the first conductive layer, and the first insulating layer in a display substrate according to an exemplary embodiment of the present disclosure, as shown below. Figure 10 As shown, a plurality of contact holes may be formed on the first insulating layer. These contact holes may include: a first contact hole V101, a second contact hole V102, a third contact hole V103, a fourth contact hole V201, a fifth contact hole V202, a sixth contact hole V203, a seventh contact hole V301, an eighth contact hole V302, a ninth contact hole V303, a tenth contact hole V410, and an eleventh contact hole V420. For example, the first insulating layer may also be referred to as a contact (CT) layer.

[0167] For example, one or more of the third contact hole V103, the sixth contact hole V203, the seventh contact hole V301, the eighth contact hole V302, the ninth contact hole V303, the tenth contact hole V410, and the eleventh contact hole V420 can be set to at least two to reduce contact resistance.

[0168] In one exemplary embodiment, the material of the second conductive layer can be a metallic material. The second conductive layer can also be referred to as the first metal layer.

[0169] In one exemplary embodiment, Figure 11 This is a schematic diagram of the structure of the second conductive layer in a display substrate according to an exemplary embodiment of the present disclosure, as shown below. Figure 11 As shown, the second conductive layer may include: a first electrode 104 of the first transistor T1, a second electrode 105 of the first transistor T1, a first electrode 204 of the second transistor T2, a second electrode 205 of the second transistor T2, a first electrode 304 of the third transistor T3, a second electrode 305 of the third transistor T3, a gate connection electrode 306, a scan signal line Scan, a reference signal line Vref, a first connection line L500 (also known as a Vref connection line), a first second connection line 411, and a first third connection line 421.

[0170] In one exemplary embodiment, such as Figure 11 As shown, the scan signal line Scan extends along the first direction DR1, the reference signal line Vref extends along the first direction DR1, and the scan signal line Scan and the reference signal line Vref are set on the same layer.

[0171] In one exemplary embodiment, such as Figure 11 As shown, the first electrode 104 of the first transistor T1, the second electrode 105 of the first transistor T1, the first electrode 204 of the second transistor T2, the second electrode 205 of the second transistor T2, the first electrode 304 of the third transistor T3, the second electrode 305 of the third transistor T3, the scan signal line Scan, and the reference signal line Vref are arranged on the same layer.

[0172] In one exemplary embodiment, Figure 12 This is a schematic diagram of the structure after the formation of the second conductive layer in an exemplary embodiment of this disclosure, as shown below. Figures 9 to 12As shown, the first electrode 104 of the first transistor T1 is electrically connected to the first region 101 of the active region of the first transistor T1 through the first contact hole V101, and the second electrode 105 of the first transistor T1 is electrically connected to the second region 102 of the active region of the first transistor T1 through the second contact hole V102. The first electrode 204 of the second transistor T2 is electrically connected to the first region 201 of the active region of the second transistor T2 through the fourth contact hole V201, and the second electrode 205 of the second transistor T2 is electrically connected to the second region 202 of the active region of the second transistor T2 through the fifth contact hole V202. The first electrode 304 of the third transistor T3 is electrically connected to the first region 301 of the active region of the third transistor T3 through the seventh contact hole V301, and the second electrode 305 of the third transistor T3 is electrically connected to the second region 302 of the active region of the third transistor T3 through the eighth contact hole V302. The gate connection electrode 306 is connected to the control electrode 303 of the third transistor T3 through the ninth contact hole V303.

[0173] In one exemplary embodiment, such as Figure 11 As shown, in each repeating unit, the first electrodes 304 of two adjacent third transistors T3 in the first direction are interconnected as a single structure. This simplifies the manufacturing process, reduces production costs, and decreases the total area occupied by the third transistors T3 in the pixel region, thus reducing the pixel area and achieving higher resolution in the display product.

[0174] In one exemplary embodiment, such as Figure 11 As shown, in each repeating unit, the first electrode 204 of the second transistor T2 and the second electrode 305 of the third transistor T3 are disposed on the same layer and are an integral structure interconnected. This simplifies the manufacturing process, reduces production costs, allows for a more compact pixel arrangement, and helps reduce the pixel area, thereby contributing to improved resolution of the display substrate.

[0175] In one exemplary embodiment, such as Figures 9 to 12 As shown, the scan signal line Scan is connected to the control electrode 103 of the first transistor T1 through the third contact hole V103. For example, the scan signal line Scan extends along the first direction DR1.

[0176] In one exemplary embodiment, such as Figures 9 to 12 As shown, the reference signal line Vref is connected to the control electrode 203 of the second transistor T2 through the sixth contact hole V203. For example, the reference signal line Vref extends along the first direction DR1.

[0177] In one exemplary embodiment, such as Figures 9 to 12As shown, in each repeating unit, the control electrodes 103 of multiple first transistors T1 are controlled by the same scan signal line Scan. This helps to save the layout area occupied by the scan signal line Scan, thereby improving the space utilization of the layout and helping to improve the resolution of the display substrate.

[0178] In one exemplary embodiment, such as Figures 9 to 12 As shown, in each repeating unit, the control electrodes 203 of multiple second transistors T2 are controlled by the same reference signal line Vref. This helps to save the layout area occupied by the reference signal line Vref, thereby improving the space utilization of the layout and contributing to the improvement of the display substrate's resolution.

[0179] In one exemplary embodiment, such as Figures 9 to 12 As shown, the first connecting line L500 (also known as the Vref connecting line) is used to connect to the reference signal line Vref through the subsequently formed connecting line, so as to bring out the reference signal line Vref for easy connection to the control electrode 203 of the second transistor T2 in another repeating unit.

[0180] In one exemplary embodiment, such as Figures 9 to 12 As shown, the first and second connecting lines 411 are connected to the first contact area 410 through the tenth contact hole V410, and the first and third connecting lines 421 are connected to the second contact area 420 through the eleventh contact hole V420. This allows for subsequent electrical isolation of the devices by applying low-voltage bias to the P-type substrate and high-voltage bias to the N-type well region, thereby reducing parasitic effects between devices and improving circuit stability.

[0181] (3) A second insulating layer and a third conductive layer are sequentially formed on the substrate on which the aforementioned structure is formed.

[0182] In one exemplary embodiment, Figure 13 This is a schematic diagram of the structure of the second conductive layer and the second insulating layer in the display substrate of the exemplary embodiments of this disclosure, as shown below. Figure 13 As shown, the second insulating layer may have multiple vias, which may include: a first via V104, a second via V105, a third via V205, a fourth via V304, a fifth via V306, a sixth via V411, a seventh via V421, an eighth via V500, a ninth via V510, and a tenth via V520. For example, the second insulating layer may also be referred to as a first via (Via1) layer.

[0183] In one exemplary embodiment, such as Figure 13As shown, one or more of the first and second vias V105, the first and third vias V205, the first and fourth vias V304, the first and fifth vias V306, the first and sixth vias V411, and the first and seventh vias V421 can be set to at least two.

[0184] In one exemplary embodiment, the material of the third conductive layer can be a metallic material. The third conductive layer can also be referred to as a second metal (Metal2) layer.

[0185] In one exemplary embodiment, Figure 14 This is a schematic diagram of the structure of the third conductive layer in a display substrate according to an exemplary embodiment of the present disclosure, as shown below. Figure 14 As shown, the third conductive layer may include: a data signal line Vdata, a fourth power supply line GND (also known as a ground line GND), a second first connection electrode L105, a second second connection electrode L205, a second third connection electrode L304, a second fourth connection electrode L306, a second first connection line L421, a second fifth connection electrode L422, a second sixth connection electrode L510, and a second seventh connection electrode L520. Here, taking the provision of a signal to the substrate of the NMOS transistor via the fourth power supply line GND as an example, the third conductive layer may include a portion of the third power supply line Vsub.

[0186] In one exemplary embodiment, such as Figure 14 As shown, the data signal line Vdata extends along the second direction DR2.

[0187] In one exemplary embodiment, the film layer containing the data signal line Vdata extending along the second direction DR2 is located between the film layer containing the scan signal line Scan extending along the first direction DR1 and the film layer containing the first power line VDD extending along the first direction DR1.

[0188] In one exemplary embodiment, such as Figure 14 As shown, the second connecting line L421 extends along the second direction DR2.

[0189] In one exemplary embodiment, such as Figure 14 As shown, in each repeating unit, the data signal line Vdata and the second connection line L421 are alternately arranged on the first direction DR1.

[0190] In one exemplary embodiment, Figure 15 This is a schematic diagram of the formation of the third conductive layer in an exemplary embodiment of this disclosure, as shown below. Figures 9 to 15 As shown, the data signal line Vdata is connected to the first electrode 104 of the first transistor T1 through the first via V104.

[0191] In one exemplary embodiment, such as Figures 9 to 15As shown, the fourth power line GND (also known as the ground line GND) is connected to the first second connection line 411 through the first six-via V411. Thus, the fourth power line GND is sequentially connected to the first contact area 410 through the first six-via V411, the first second connection line 411, and the tenth contact hole V410. Therefore, by providing a low-level signal through the fourth power line GND, a low-voltage bias can be achieved on the P-type substrate. This, in turn, improves the stability of the circuit.

[0192] In one exemplary embodiment, such as Figures 9 to 15 As shown, the second connecting line L421 and the second fifth connecting electrode L422 are connected to the first third connecting line 421 through the first seventh via V421. Thus, the second connecting line L421 and the second fifth connecting electrode L422 are sequentially connected to the second contact area 420 through the first seventh via V421, the first third connecting line 421, and the eleventh contact hole V420, so that the N-type well region can be subsequently subjected to high-voltage bias.

[0193] In one exemplary embodiment, such as Figures 9 to 15 As shown, the second connecting electrode L105 is connected to the second electrode 105 of the first transistor T1 through the first via V105.

[0194] In one exemplary embodiment, such as Figures 9 to 15 As shown, the second electrode L205 is connected to the second electrode 205 of the second transistor T2 through the first via V205.

[0195] In one exemplary embodiment, such as Figures 9 to 15 As shown, the second and third connecting electrodes L304 are connected to the first electrode 304 of the third transistor T3 through the first four vias V304. This is to connect the first electrode 304 of the third transistor T3 to the subsequently formed first power line VDD.

[0196] In one exemplary embodiment, such as Figures 9 to 15 As shown, the second fourth connection electrode L306 is connected to the gate connection electrode 306 through the first fifth via V306.

[0197] In one exemplary embodiment, such as Figures 9 to 15 As shown, the second sixth connection electrode L510 is connected to the reference signal line Vref through the first ninth via V510, and to the first first connection line L500 through the first eighth via V500. This connects the first first connection line L500 to the reference signal line Vref, allowing the reference signal line Vref in one repeating unit to be brought out for easy connection to the control electrode 203 of the second transistor T2 in another repeating unit.

[0198] In one exemplary embodiment, such as Figures 9 to 15As shown, the second fifth connection electrode L520 is connected to the scan signal line Scan through the first ten via V520. In this way, the scan signal line Scan in one repeating unit can be led out, which is convenient for connecting the control electrode 103 of the first transistor T1 in another repeating unit.

[0199] (4) A third insulating layer and a fourth conductive layer are sequentially formed on the substrate on which the aforementioned structure is formed.

[0200] In one exemplary embodiment, Figure 16 This is a schematic diagram of the structure of the third conductive layer and the third insulating layer in a display substrate according to an exemplary embodiment of the present disclosure, as shown below. Figure 16 As shown, the third insulating layer may have multiple vias, which may include: second via VL105, second via VL205, second via VL304, second via VL306, second via VL421, and second via V530. For example, the third insulating layer may also be referred to as the second via (Via2) layer.

[0201] In one exemplary embodiment, such as Figure 16 As shown, one or more of the second via VL105, the second via VL205, the second via VL304, the second via VL306, the second via VL421, and the second via V530 can be set to at least two.

[0202] In one exemplary embodiment, the material of the fourth conductive layer can be a metallic material. The fourth conductive layer can also be referred to as a third metal (Metal3) layer.

[0203] In one exemplary embodiment, Figure 17 This is a schematic diagram of the structure of the fourth conductive layer in the display substrate according to an exemplary embodiment of the present disclosure, as shown below. Figure 17 As shown, the fourth conductive layer may include: a first power line VDD, a fifth power line AVDD, a third first connecting line L2051, a third second connecting line L530, and a third third connecting line L600. For example, the first power line VDD, the fifth power line AVDD, the third first connecting line L2051, the third second connecting line L530, and the third third connecting line L600 all extend along the first direction DR1.

[0204] In one exemplary embodiment, such as Figure 17 As shown, the first power line VDD extends along the first direction DR1.

[0205] In one exemplary embodiment, such as Figures 9 to 18As shown, the first power line VDD extending along the first direction DR1 is disposed in a different layer from the scan signal line Scan extending along the first direction DR1 and the reference signal line Vref extending along the first direction DR1.

[0206] In one exemplary embodiment, such as Figures 9 to 18 As shown, the first power line VDD is connected to the second third connecting electrode L304 through the second third via VL304. Thus, the first power line VDD can be connected to the first electrode 304 of the third transistor T3 in sequence through the second third via VL304, the second third connecting electrode L304, and the first fourth via V304.

[0207] In one exemplary embodiment, such as Figures 9 to 18 As shown, the first power supply line VDD can be set to at least two. Thus, in each repeating unit, the first pole 304 of multiple third transistors T3 can be controlled by at least two first power supply lines VDD.

[0208] In one exemplary embodiment, the orthographic projection of the first power line VDD extending along the first direction DR1 onto the substrate can be located between the orthographic projection of the reference signal line Vref extending along the first direction DR1 onto the substrate and the orthographic projection of the scan signal line Scan extending along the first direction DR1 onto the substrate. Since the signal transmitted by the first power line VDD is a DC signal, while the signals transmitted by the scan signal line Scan and the reference signal line Vref are both transition signals, the above arrangement can effectively shield the mutual interference between the reference signal line Vref and the scan signal line Scan. Therefore, the stability of the circuit can be improved.

[0209] In one exemplary embodiment, such as Figures 9 to 18 As shown, the fifth power line AVDD is connected to the second first connection line L421 via the second fifth via VL421. Thus, the fifth power line AVDD is sequentially connected to the second contact area 420 via the second fifth via VL421, the second first connection line L421, the first seventh via V421, the first third connection line 421, and the eleventh contact hole V420. Therefore, the high-level signal provided by the fifth power line AVDD can achieve high-voltage biasing of the N-type well region, thereby improving circuit stability.

[0210] In one exemplary embodiment, the orthographic projection of the fifth power line AVDD extending along the first direction DR1 on the substrate at least partially overlaps with the orthographic projection of the reference signal line Vref extending along the first direction DR1 on the substrate.

[0211] In one exemplary embodiment, such as Figures 9 to 18As shown, the third connection line L2051 is connected to the second connection electrode L205 through the second via VL205. Thus, the third connection line L2051 is connected to the second electrode 205 of the second transistor T2 in sequence through the second via VL205, the second connection electrode L205, and the first via V205.

[0212] In one exemplary embodiment, such as Figures 9 to 18 As shown, the third connecting line L530 is connected to the fourth power line GND (also known as the ground line GND) through the second six via V530. This allows the fourth power line GND in one repeating unit to be brought out for easy connection to the fourth power line GND in another repeating unit.

[0213] In one exemplary embodiment, such as Figures 9 to 18 As shown, the third three-connection line L600 is connected to the second first connection electrode L105 through the second first via VL105, and to the second fourth connection electrode L306 through the second fourth via VL306. Thus, the third three-connection line L600 is sequentially connected to the second electrode 105 of the first transistor T1 through the second first via VL105, the second first connection electrode L105, and the first second via V105, and sequentially connected to the control electrode 303 of the third transistor T3 through the second fourth via VL306, the second fourth connection electrode L306, the first fifth via V306, the gate connection electrode 306, and the ninth contact hole V303. That is, the second electrode 105 of the first transistor T1 and the control electrode 303 of the third transistor T3 can be connected through the traces in the second, third, and fourth conductive layers.

[0214] (5) A fourth insulating layer, a fifth conductive layer and a sixth conductive layer are sequentially formed on the substrate on which the aforementioned structure is formed.

[0215] In one exemplary embodiment, Figure 19 This is a schematic diagram of the structure of the fourth conductive layer and the fourth insulating layer in the display substrate of an exemplary embodiment of the present disclosure, as shown below. Figure 19 As shown, multiple vias can be formed on the fourth insulating layer, including a third via VL2051 and a third via VL600. For example, the fourth insulating layer can also be referred to as a third via (Via3) layer.

[0216] In one exemplary embodiment, such as Figure 19 As shown, one or more of the third via VL2051 and the third via VL600 can be set to at least two.

[0217] In one exemplary embodiment, the fifth conductive layer may be made of a metallic material. The fifth conductive layer may also be referred to as a fourth metal layer (Metal4).

[0218] In one exemplary embodiment, Figure 20 This is a schematic diagram of the structure of the fifth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure. Figure 21 This is a schematic diagram of the fourth conductive layer, the fourth insulating layer, and the fifth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure, as shown below. Figure 20 and Figure 21 As shown, the fifth conductive layer may include: a portion of the first electrode plate 701 of the plurality of storage capacitors Cst, a fourth first connecting electrode L2052, and a fourth second connecting electrode L601.

[0219] In one exemplary embodiment, a portion of the first electrode plate 701 of the plurality of storage capacitors Cst is connected to a portion of the plurality of third vias VL600 through a portion of the third vias LL600. Thus, through the traces in the second, third, fourth, and fifth conductive layers, a portion of the second electrode 105 of the first transistor T1 and a portion of the control electrode 303 of the third transistor T3 can be connected to a portion of the first electrode plate 701 of the plurality of storage capacitors Cst.

[0220] In one exemplary embodiment, in each repeating unit, the orthographic projection of at least one of the first plates of the plurality of storage capacitors onto the substrate at least partially overlaps with the orthographic projection of the control electrode of the plurality of first transistors onto the substrate, and at least partially overlaps with the orthographic projection of the control electrode of the plurality of second transistors onto the substrate. Alternatively, the orthographic projection of at least one of the first plates of the plurality of storage capacitors onto the substrate at least partially overlaps with the orthographic projection of at least a portion of the control electrode of the plurality of third transistors onto the substrate. For example, as... Figures 9 to 21 As shown, the fifth conductive layer may include: a first electrode 701 of a first storage capacitor, a first electrode 701 of a second storage capacitor, and a first electrode 701 of a third storage capacitor arranged sequentially in a first direction. The orthographic projection of the first electrode 701 of the first storage capacitor onto the substrate at least partially overlaps with the orthographic projection of the control electrode 103 of the first transistor T1 onto the substrate, and at least partially overlaps with the orthographic projection of the control electrode 203 of the second transistor T2 onto the substrate. The orthographic projection of the first electrode 701 of the second storage capacitor onto the substrate at least partially overlaps with the orthographic projection of at least a portion of the control electrodes 303 of the plurality of third transistors T3 onto the substrate. The orthographic projection of the first electrode 701 of the third storage capacitor onto the substrate at least partially overlaps with the orthographic projection of at least a portion of the control electrodes 303 of the plurality of third transistors T3 onto the substrate.

[0221] In one exemplary embodiment, such as Figures 9 to 21As shown, the fourth connecting electrode L2052 is connected to the third connecting line L2051 through the third via VL2051. Thus, the fourth connecting electrode L2052 is sequentially connected to the second electrode 205 of the second transistor T2 through the third via VL2051, the third connecting line L2051, the second via VL205, the second connecting electrode L205, and the first via V205.

[0222] In one exemplary embodiment, such as Figures 9 to 21 As shown, the fourth two-connection electrode L601 is connected to another part of the multiple third two-vias VL600 through another part of the multiple third three-connection lines L600. In this way, another part of the second electrode 105 of the first transistor T1 and another part of the control electrode 303 of the third transistor T3 can be brought out.

[0223] In one exemplary embodiment, the fifth conductive layer may have a MIM (Metal-Insulator-Metal) structure. The fifth conductive layer may also be referred to as an MIM layer.

[0224] In one exemplary embodiment, Figure 22 This is a schematic diagram of the structure of the sixth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure, as shown below. Figure 22 As shown, the sixth conductive layer may include: the second electrode 702 of the storage capacitor Cst.

[0225] (6) A fifth insulating layer and a seventh conductive layer are sequentially formed on the substrate on which the aforementioned structure is formed.

[0226] In one exemplary embodiment, Figure 23 This is a schematic diagram of the structure of the fifth conductive layer, the sixth conductive layer, and the fifth insulating layer in a display substrate according to an exemplary embodiment of the present disclosure, as shown below. Figure 23 As shown, multiple vias can be formed on the fifth insulating layer. These vias may include: a fourth via VL2052, a fourth via VL601, and a fourth via V702. For example, the fifth insulating layer may also be referred to as a fourth via (Via4) layer.

[0227] In one exemplary embodiment, such as Figure 23 As shown, one or more of the fourth via VL2052, the fourth via VL601, and the fourth via V702 can be set to at least two.

[0228] In one exemplary embodiment, the material of the seventh conductive layer can be a metallic material. The seventh conductive layer can also be referred to as the fifth metal layer (Metal5).

[0229] In one exemplary embodiment, Figure 24 This is a schematic diagram of the structure of the seventh conductive layer in a display substrate according to an exemplary embodiment of the present disclosure, as shown below. Figure 24 As shown, the seventh conductive layer may include: a fifth first transition electrode 703, a fifth second transition electrode L602, and a fifth third transition electrode L2053.

[0230] In one exemplary embodiment, such as Figure 24 As shown, the fifth transfer electrode 703 is a planar electrode, which can serve as another part of the first plate 701 of the multiple storage capacitors Cst. The space between the fifth transfer electrode 703 and the second plate 702 of the storage capacitor Cst forms another part of the storage capacitor Cst.

[0231] In one exemplary embodiment, such as Figures 9 to 25 As shown, the fifth transfer electrode 703 is connected to the second plate 702 of the storage capacitor Cst through the fourth via V702.

[0232] In one exemplary embodiment, such as Figures 9 to 25 As shown, the fifth transition electrode L602 is connected to the fourth connection electrode L601 through the fourth via VL601. This is to bring out another part of the second electrode 105 of the first transistor T1 and another part of the control electrode 303 of the third transistor T3.

[0233] In one exemplary embodiment, such as Figures 9 to 25 As shown, the fifth third-transition electrode L2053 is connected to the fourth first-connection electrode L2052 through the fourth first via VL2052. Thus, the fifth third-transition electrode L2053 is sequentially connected to the second electrode 205 of the second transistor T2 through the fourth first via VL2052, the fourth first-connection electrode L2052, the third first via VL2051, the third first connecting line L2051, the second second via VL205, the second second connecting electrode L205, and the first third via V205.

[0234] (7) A sixth insulating layer and an eighth conductive layer are sequentially formed on the substrate on which the aforementioned structure is formed.

[0235] In one exemplary embodiment, Figure 26 This is a schematic diagram of the structure of the seventh conductive layer and the sixth insulating layer in a display substrate according to an exemplary embodiment of the present disclosure, as shown below. Figure 26 As shown, the sixth insulating layer may have multiple vias, which may include: the fifth via VL2053, the fifth via VL602, and the fifth via V703. For example, the sixth insulating layer may also be referred to as the fifth via (Via5) layer.

[0236] In one exemplary embodiment, such as Figure 26 As shown, one or more of the fifth via VL2053, the fifth via VL602, and the fifth via V703 can be set to at least two.

[0237] In one exemplary embodiment, the material of the eighth conductive layer can be a metallic material. The eighth conductive layer can also be referred to as the sixth metal layer (Metal6).

[0238] In one exemplary embodiment, Figure 27 This is a schematic diagram of the structure of the eighth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure, as shown below. Figure 27 As shown, the eighth conductive layer may include: the sixth-first adapter L2054 and the sixth-second adapter L603.

[0239] In one exemplary embodiment, such as Figure 2 as well as Figures 9 to 27 As shown, the sixth adapter line L2054 is connected to the fifth third adapter electrode L2053 through the fifth via VL2053. Thus, the sixth adapter line L2054 sequentially connects to the second electrode 205 of the second transistor T2 through the fifth via VL2053, the fifth third adapter electrode L2053, the fourth via VL2052, the fourth connecting electrode L2052, the third via VL2051, the third connecting line L2051, the second second via VL205, the second second connecting electrode L205, and the first third via V205. Therefore, through the traces in the second, third, fourth, fifth, seventh, and eighth conductive layers, the second electrode 205 of the second transistor T2 can be led out for connection to the first electrode of the subsequently formed light-emitting element.

[0240] In one exemplary embodiment, such as Figure 2 as well as Figures 9 to 27 As shown, the sixth-second adapter line L603 is connected to the fifth-second adapter electrode L602 through the fifth-second via VL602, and to the fifth-first adapter electrode 703 through the fifth-third via V703. Thus, the fifth-first adapter electrode 703 can serve as another part of the first electrode plate 701 of multiple storage capacitors Cst. Therefore, through the traces in the second, third, fourth, fifth, seventh, and eighth conductive layers, another part of the second electrode 105 of the first transistor T1 and another part of the control electrode 303 of the third transistor T3 can be connected to the fifth-first adapter electrode 703.

[0241] Thus, based on the pixel circuit structure, by optimizing and designing the layout, making full use of the layout space, and rationally optimizing the transistor arrangement, a smaller layout area can be achieved, which can reduce the area occupied by the pixel circuit in the sub-pixel, thus facilitating the reduction of pixel size (for example, a pixel area of ​​4.5μm*3.15μm=13.23μm2 can be achieved), resulting in a higher PPI and better display effect.

[0242] In one exemplary embodiment, the second, third, fourth, fifth, seventh, and eighth conductive layers may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the aforementioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc., and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Here, the exemplary embodiments of this disclosure do not limit this.

[0243] In one exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers. This exemplary embodiment does not limit the specific layers described herein.

[0244] In one exemplary embodiment, the planar shape of the hole (via or contact hole) can be rectangular (e.g., square) or circular. For example, the dimensions of multiple holes (via or contact holes) in each insulating layer can be the same. Here, the exemplary embodiments of this disclosure do not limit this.

[0245] In one exemplary embodiment, signal lines such as Scan, Vref, VDD, or GND can represent at least a portion (e.g., a portion located in the display area) of the trace that transmits the corresponding signal to the repeating unit.

[0246] (8) such as Figure 1A As shown, a pixel definition layer and a light-emitting element 12 are sequentially formed on the substrate on which the aforementioned structure is formed. The light-emitting element 12 may include a first electrode 121, an organic light-emitting functional layer 122, and a second electrode 123 stacked sequentially.

[0247] In one exemplary embodiment, a pixel definition film is coated on a substrate forming the aforementioned structure. A pixel definition layer (PDL) pattern is formed through a masking, exposure, and development process. The PDL is formed in the sub-pixels of the display area, and the pixel definition layer in the sub-pixels forms pixel openings that expose the first electrode 121. Subsequently, an organic light-emitting functional layer 122 is formed within the aforementioned pixel openings, and the organic light-emitting functional layer 122 is connected to the first electrode 121 of the light-emitting element 12. Subsequently, a second electrode 123 film is deposited, and the second electrode 123 film is patterned through a patterning process to form a cathode pattern. The second electrode 123 is connected to the organic light-emitting functional layer 122 and the second power line VSS, respectively.

[0248] In one exemplary embodiment, the pixel definition layer may be made of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). This exemplary embodiment does not limit the scope of the invention.

[0249] The structures and their fabrication processes shown in this disclosure are merely illustrative. In one exemplary embodiment, the corresponding structures and patterning processes can be modified and added or reduced according to actual circumstances.

[0250] The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can employ processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, which are not limited here. In the description of this disclosure, a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire fabrication process, it can also be called a "layer". If the "thin film" requires a patterning process or photolithography process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern". The phrase "A and B are set in the same layer" mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process.

[0251] This disclosure also provides a driving method. This driving method can be applied to the pixel circuit in one or more of the above exemplary embodiments. The driving method may include: a data writing stage and a light emission stage, wherein...

[0252] During the data writing phase, under the control of the scan signal line, the data signal line is stored in the storage capacitor and the data signal line is supplied to the control electrode of the third transistor.

[0253] During the light-emitting stage, the third transistor is turned on under the control of the data signal line, and the second transistor is turned on under the control of the reference signal line. Through the third and second transistors, the first power line signal is provided to the first electrode of the light-emitting element to drive the light-emitting element to emit light.

[0254] In one exemplary embodiment, the driving method may further include an initialization phase, wherein, during the initialization phase, under the control of a signal from a discharge signal line, a signal from an initial signal line is provided to the first electrode of the light-emitting element to initialize the light-emitting element.

[0255] This disclosure also provides a driving method. This driving method can be applied to the pixel circuit in one or more of the above exemplary embodiments. The driving method may include: a first testing phase, wherein, under the control of a test enable signal line, the connection state of a third transistor is switched from a first connection state to a second connection state, a fixed voltage output from a fourth power line is provided to the third transistor, and the third transistor is controlled to be in a forward bias state; wherein, the first connection state is that the third transistor is connected to the third power line, and the second connection state is that the third transistor is connected to the fourth power line; under the control of a reference signal line, a fixed voltage output from the fourth power line is provided to the first electrode of the light-emitting element to cause the light-emitting element to emit light.

[0256] This disclosure also provides a driving method. This driving method can be applied to the pixel circuit in one or more of the above exemplary embodiments. The driving method may include: a second testing phase, wherein, under the control of a switch signal line signal, the connection state of a fourth transistor is switched between a third connection state and a fourth connection state, and a signal from a monochrome test signal line or a fourth power supply line is provided to the fourth transistor; wherein, in the third connection state, the second terminal of the fourth transistor is connected to the monochrome test signal line, and in the fourth connection state, the second terminal of the fourth transistor is connected to the fourth power supply line; under the control of a monochrome enable signal line signal, a light-emitting element connected to the monochrome enable signal line is controlled to emit monochrome light corresponding to the signal of the monochrome enable signal line; the monochrome enable signal line includes one of: a first enable signal line connected to a light-emitting element emitting a first emission color, a second enable signal line connected to a light-emitting element emitting a second emission color, and a third enable signal line connected to a light-emitting element emitting the first emission color.

[0257] This disclosure also provides a display device, including: a display substrate as described in one or more of the above exemplary embodiments and a pixel circuit as described in one or more of the above exemplary embodiments.

[0258] In one exemplary embodiment, the display device may include, but is not limited to, an OLED display device, a MicroOLED display device, or a QLED display device. This disclosure does not limit the scope of the application.

[0259] In one exemplary embodiment, the display device may include, but is not limited to, any product or component with display functionality such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This disclosure does not limit the scope of the embodiment.

[0260] The description of the above display device embodiments is similar to the description of the above display substrate and pixel circuit embodiments, and has similar beneficial effects. For technical details not disclosed in the display device embodiments of this disclosure, those skilled in the art should refer to the descriptions in the display substrate and pixel circuit embodiments of this disclosure for understanding, and will not be repeated here.

[0261] While the embodiments disclosed herein are as described above, the above content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein, but the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The substrate and a plurality of repeating units arranged in an array on one side of the substrate, each repeating unit including at least two light-emitting elements and at least two pixel circuits, each pixel circuit including a first transistor, a second transistor and a third transistor, the third transistor being configured to drive the light-emitting elements to emit light, each repeating unit further including a first region, a second region and a third region continuously arranged along a first direction, the first region including a first transistor and a second transistor, the second region including a first transistor and a second transistor, the third region including at least two third transistors, the first transistor and the third transistor being of different types; the first transistor and the second transistor of the two pixel circuits are alternately distributed in the first region and the second region.

2. The display substrate according to claim 1, wherein, The second region includes at least two second transistors, wherein the first transistor and the second transistor are of the same type.

3. The display substrate according to claim 2, wherein, The size of the third transistor is larger than the size of the first transistor and larger than the size of the second transistor.

4. The display substrate according to claim 3, wherein, Each repeating unit includes: six of the first transistors, six of the second transistors, and six of the third transistors.

5. The display substrate according to claim 4, wherein, In the third region, the six third transistors are arranged in an array.

6. The display substrate according to claim 5, wherein, In the first region, six first transistors are arranged sequentially along the second direction, and in the second region, six second transistors are arranged sequentially along the second direction; Alternatively, in the first region, three first transistors and three second transistors are alternately arranged along a second direction, and in the second region, three first transistors and three second transistors are alternately arranged along a second direction; Alternatively, both the first region and the second region include: a first sub-region and a second sub-region arranged sequentially along a second direction, wherein three first transistors are arranged sequentially along the second direction in the first sub-region, and three second transistors are arranged sequentially along the second direction in the second sub-region; Alternatively, both the first region and the second region include: a third sub-region, a fourth sub-region, and a fifth sub-region arranged sequentially along the second direction, wherein in the third sub-region, two first transistors are arranged sequentially along the second direction, in the fourth sub-region, two second transistors are arranged sequentially along the second direction, and in the fifth sub-region, one second transistor and one first transistor are alternately arranged along the second direction; Alternatively, the first region includes: a sixth sub-region, a seventh sub-region, and an eighth sub-region arranged sequentially along a second direction, wherein in the sixth sub-region, two first transistors are arranged sequentially along the second direction; in the seventh sub-region, two second transistors are arranged sequentially along the second direction; and in the eighth sub-region, two first transistors are arranged sequentially along the second direction. Furthermore, the second region includes: a ninth sub-region, a tenth sub-region, and an eleventh sub-region arranged sequentially along a second direction, wherein in the ninth sub-region, two second transistors are arranged sequentially along the second direction; in the tenth sub-region, two first transistors are arranged sequentially along the second direction; and in the eleventh sub-region, two second transistors are arranged sequentially along the second direction. The second direction intersects with the first direction.

7. The display substrate according to any one of claims 1 to 6, wherein, In each repeating unit, the first electrodes of two adjacent third transistors in the first direction are interconnected in an integral structure.

8. The display substrate according to any one of claims 1 to 6, wherein, In each pixel circuit, the first electrode of the second transistor and the second electrode of the third transistor are interconnected in an integral structure.

9. The display substrate according to any one of claims 1 to 6, wherein, In the plurality of repeating units, the control electrodes of the transistors in two adjacent repeating units in the first direction are symmetrical about the axis of symmetry along the second direction, which intersects the first direction.

10. The display substrate according to any one of claims 1 to 6, wherein, In each repeating unit, the control poles of two adjacent first transistors in the second direction are interconnected in an integral structure.

11. The display substrate according to any one of claims 1 to 6, wherein, In each repeating unit, the control poles of two adjacent second transistors in the second direction are interconnected in an integral structure.

12. The display substrate according to any one of claims 1 to 6, further comprising: The control electrode of the first transistor is connected to the scan signal line, and the control electrode of the second transistor is connected to the reference signal line. In each repeating unit, the control electrodes of multiple first transistors are controlled by the same scan signal line, and the control electrodes of multiple second transistors are controlled by the same reference signal line.

13. The display substrate according to any one of claims 1 to 6, further comprising: The system includes a scan signal line, a data signal line, a reference signal line, and a first power supply line. The control electrode of the first transistor is connected to the scan signal line, the first electrode of the first transistor is connected to the data signal line, the control electrode of the second transistor is connected to the reference signal line, and the first electrode of the third transistor is connected to the first power supply line. The scan signal line and the reference signal line are arranged on the same layer, while the scan signal line, the data signal line, and the first power supply line are arranged on different layers.

14. The display substrate according to any one of claims 1 to 6, further comprising: A first power line, a reference signal line, and a scan signal line are provided. The control electrode of the first transistor is connected to the scan signal line, the control electrode of the second transistor is connected to the reference signal line, and the first electrode of the third transistor is connected to the first power line. The orthographic projection of the first power line extending in a first direction on the substrate is located between the orthographic projection of the reference signal line extending in the first direction on the substrate and the orthographic projection of the scan signal line extending in the first direction on the substrate.

15. The display substrate according to any one of claims 1 to 6, further comprising: The system includes a data signal line, a scan signal line, and a first power supply line. The control electrode of the first transistor is connected to the scan signal line, the first electrode of the first transistor is connected to the data signal line, and the first electrode of the third transistor is connected to the first power supply line. In a direction perpendicular to the substrate, the film layer containing the data signal line extending in a second direction is located between the film layer containing the scan signal line extending in a first direction and the film layer containing the first power supply line extending in the first direction. The second direction intersects the first direction.

16. The display substrate according to any one of claims 1 to 6, further comprising: The scan signal line and the reference signal line are provided. The control electrode of the first transistor is connected to the scan signal line, and the control electrode of the second transistor is connected to the reference signal line. The first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor, the second electrode of the second transistor, the first electrode of the third transistor, the second electrode of the third transistor, the scan signal line, and the reference signal line are arranged on the same layer.

17. The display substrate according to any one of claims 1 to 6, wherein, The first transistor and the second transistor are P-type metal-oxide-semiconductor transistors, and the third transistor is an N-type metal-oxide-semiconductor transistor.

18. The display substrate according to claim 1, wherein, Each pixel circuit further includes: a storage capacitor, a first plate of the storage capacitor connected to a first node, and a second plate of the storage capacitor connected to a second power line. In each repeating unit, the orthographic projection of at least one of the first plates of the plurality of storage capacitors on the substrate at least partially overlaps with the orthographic projection of the control electrode of the plurality of first transistors on the substrate, and at least partially overlaps with the orthographic projection of the control electrode of the plurality of second transistors on the substrate; or, the orthographic projection of at least one of the first plates of the plurality of storage capacitors on the substrate at least partially overlaps with the orthographic projection of at least a portion of the control electrode of the plurality of third transistors on the substrate.

19. The display substrate according to claim 18, wherein, In a direction perpendicular to the substrate, the display substrate includes at least: an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate; wherein, The active layer includes at least: the active region of the first transistor, the active region of the second transistor, and the active region of the third transistor; The first conductive layer includes at least: the control electrode of the first transistor, the control electrode of the second transistor, and the control electrode of the third transistor; The second conductive layer includes at least: a first electrode of the first transistor, a second electrode of the first transistor, a first electrode of the second transistor, a second electrode of the second transistor, a first electrode of the third transistor, a scan signal line, and a reference signal line; The third conductive layer includes at least: data signal lines; The fourth conductive layer includes at least: a first power line and a transfer wire for connecting the second electrode of the first transistor, the control electrode of the third transistor, and the first electrode plate of the storage capacitor; The fifth conductive layer includes at least the first electrode of the storage capacitor.

20. A pixel circuit, comprising: A first transistor, a second transistor, and a third transistor are provided, wherein the control electrode of the first transistor is connected to a scan signal line, the first electrode of the first transistor is connected to a data signal line, and the second electrode of the first transistor is connected to a first node; the control electrode of the second transistor is connected to a reference signal line, the first electrode of the second transistor is connected to a second node, and the second electrode of the second transistor is connected to a first electrode of a light-emitting element; the control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to a first power supply line, and the second electrode of the third transistor is connected to the second node. The first transistor is configured to provide a data signal line signal to the third transistor under the control of a scan signal line signal; the second transistor is configured to provide a second node signal to the first electrode of the light-emitting element under the control of a reference signal line signal; and the third transistor is configured to provide a first power line signal to the second node under the control of a data signal line signal. The substrate end of the third transistor is connected to the third power line. The pixel circuit further includes a substrate voltage control sub-circuit, connected to the third power line, configured to apply a first voltage to the substrate end of the third transistor in a high-brightness mode, or apply a second voltage to the substrate end of the third transistor in a low-brightness mode, wherein the absolute value of the first voltage is greater than the absolute value of the second voltage, the brightness parameter of the high-brightness mode is higher than a preset brightness threshold, and the brightness parameter of the low-brightness mode is not higher than the preset brightness threshold.

21. The pixel circuit according to claim 20, further comprising: A storage capacitor, wherein the first plate of the storage capacitor is connected to the first node, and the second plate of the storage capacitor is connected to the second power line.

22. The pixel circuit according to claim 20, further comprising: A fourth transistor, wherein the control electrode of the fourth transistor is connected to the discharge signal line, the first electrode of the fourth transistor is connected to the second node, and the second electrode of the fourth transistor is connected to the initial signal line; the fourth transistor is configured to provide the signal of the initial signal line to the second node under the control of the signal of the discharge signal line.

23. The pixel circuit according to claim 22, wherein, The second transistor is also configured to be in a reverse bias state when a short circuit occurs between the first electrode and the second electrode of the light-emitting element.

24. The pixel circuit according to claim 20 or 22, further comprising: A gate voltage control subcircuit, connected to the reference signal line, is configured to provide a variable voltage to the control electrode of the second transistor.

25. The pixel circuit according to claim 20 or 22, further comprising: A first test circuit, connected to a test enable signal line, the third transistor, a third power supply line, and a fourth power supply line, is configured to, under the control of a signal from the test enable signal line, switch the connection state of the third transistor from a first connection state to a second connection state, provide the third transistor with a fixed voltage output from the fourth power supply line, and control the third transistor to be in a forward bias state; wherein, in the first connection state, the substrate of the third transistor is connected to the third power supply line, and in the second connection state, the substrate of the third transistor is connected to the fourth power supply line; and... The second transistor is configured to provide a fixed voltage output from the fourth power line to the first electrode of the light-emitting element under the control of the signal on the reference signal line.

26. The pixel circuit according to claim 25, wherein, The first test circuit includes: a first switching device and a second switching device; a first terminal of the first switching device is connected to the substrate terminal of the third transistor, and a second terminal of the first switching device is connected to the third power line; a first terminal of the second switching device is connected to the substrate terminal of the third transistor, and a second terminal of the second switching device is connected to the fourth power line. The first test circuit is configured to switch the first switching device from an on state to an off state and the second switching device from an off state to an on state under the control of the test enable signal line.

27. The pixel circuit according to claim 22, further comprising: The second test circuit; wherein, The control electrode of the fourth transistor is connected to a monochrome enable signal line. The fourth transistor is also configured to control a light-emitting element connected to the monochrome enable signal line to emit monochrome light corresponding to the signal of the monochrome enable signal line, under the control of the signal of the monochrome enable signal line. The monochrome enable signal line includes one of the following: a first enable signal line connected to a light-emitting element emitting light of a first color, a second enable signal line connected to a light-emitting element emitting light of a second color, and a third enable signal line connected to a light-emitting element emitting light of a third color. The second test circuit, connected to the second terminal of the fourth transistor, the switch signal line, the monochrome test signal line, and the fourth power supply line, is configured to switch the connection state of the fourth transistor between a third connection state and a fourth connection state under the control of the signal from the switch signal line, and to provide the fourth transistor with either the signal from the monochrome test signal line or the signal from the fourth power supply line; wherein, the third connection state is that the second terminal of the fourth transistor is connected to the monochrome test signal line, and the fourth connection state is that the second terminal of the fourth transistor is connected to the fourth power supply line.

28. The pixel circuit according to claim 27, wherein, The second test circuit includes a third switching device and a fourth switching device; the first terminal of the third switching device is connected to the second terminal of the fourth transistor, and the second terminal of the third switching device is connected to the monochrome test signal line; the first terminal of the fourth switching device is connected to the second terminal of the fourth transistor, and the second terminal of the fourth switching device is connected to the fourth power supply line.

29. A driving method applied to a pixel circuit as described in any one of claims 20 to 24, the driving method comprising: The data writing stage and the light emission stage, among which, During the data writing phase, under the control of the signal of the scan signal line, the signal of the data signal line is provided to the control electrode of the third transistor; During the light-emitting phase, the third transistor is turned on under the control of the signal on the data signal line, and the second transistor is turned on under the control of the signal on the reference signal line. Through the third transistor and the second transistor, the signal of the first power line is provided to the first electrode of the light-emitting element to drive the light-emitting element to emit light.

30. A driving method applied to a pixel circuit as described in any one of claims 25 to 26, the driving method comprising: The first testing phase, in which... In the first testing phase, under the control of the test enable signal line, the connection state of the third transistor is switched from the first connection state to the second connection state, and a fixed voltage output by the fourth power line is provided to the third transistor to control the third transistor to be in a forward bias state; wherein, in the first connection state, the substrate end of the third transistor is connected to the third power line, and in the second connection state, the substrate end of the third transistor is connected to the fourth power line. Under the control of the signal on the reference signal line, a fixed voltage output from the fourth power line is provided to the first electrode of the light-emitting element so that the light-emitting element emits light.

31. A driving method applied to a pixel circuit as described in any one of claims 27 to 28, the driving method comprising: The second testing phase, in which... In the second testing phase, under the control of the switch signal line, the connection state of the fourth transistor is switched between the third connection state and the fourth connection state, and the signal of the monochrome test signal line or the signal of the fourth power line is provided to the fourth transistor; wherein, the third connection state is that the second terminal of the fourth transistor is connected to the monochrome test signal line, and the fourth connection state is that the second terminal of the fourth transistor is connected to the fourth power line; Under the control of the signal of the monochrome enable signal line, the light-emitting element connected to the monochrome enable signal line is controlled to emit monochrome light corresponding to the signal of the monochrome enable signal line; the monochrome enable signal line includes one of the following: a first enable signal line connected to the light-emitting element emitting a first emission color, a second enable signal line connected to the light-emitting element emitting a second emission color, and a third enable signal line connected to the light-emitting element emitting the first emission color.

32. A display device, comprising: The display substrate as claimed in any one of claims 1 to 19 and the pixel circuit as claimed in any one of claims 20 to 28.

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