A read-write controller, memory and electronic device

Abstract

A read-write controller, a memory and an electronic device are used to improve the write flexibility of the memory. The read-write controller comprises a clock generation circuit, a multi-state write circuit, a row decoding circuit and a column decoding circuit. The clock generation circuit provides a first clock signal for the multi-state write circuit and provides a second clock signal for the row decoding circuit and the column decoding circuit. By configuring a separate working clock for the multi-state write circuit, the read-write controller can flexibly configure the current working clock of the multi-state write circuit according to the current process deviation. This not only helps to improve the flexibility of the multi-state write operation, but also makes the write operation more match the current process deviation by adjusting the current working clock of the multi-state write circuit, thereby improving the ability of the read-write controller to cope with different process deviations. In addition, the multi-state write circuit can write at least two states to the memory array within one clock cycle of the first clock signal, thereby also helping to improve the write efficiency of the read-write controller.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a read / write controller, memory, and electronic device. Background Technology

[0002] In recent years, with the development and popularization of semiconductor technology, numerous new types of memory have emerged, such as ferroelectric random access memory (FeRAM), phase-change random access memory (PCRAM), magnetic random access memory (MRAM), and resistive random access memory (ReRAM). These new memories have smaller cell sizes and can achieve faster access speeds with lower power consumption, and are now being used more and more widely.

[0003] However, existing memory technologies use the same clock signal as the operating clock for all internal circuits. This effectively couples memory write operations with other operations, meaning the memory can only perform write operations and other operations according to the same operating clock, and cannot perform write operations according to its own required operating clock. This reduces the write flexibility of the memory.

[0004] In view of this, this application provides a read / write controller to improve the write flexibility of memory. Summary of the Invention

[0005] This application provides a read / write controller, a memory, and an electronic device to improve the write flexibility of the memory.

[0006] In a first aspect, this application provides a read / write controller, including a clock generation circuit, a multi-state write circuit, a row decoding circuit, and a column decoding circuit. The clock generation circuit includes a first clock output terminal and a second clock output terminal. The clock frequency of the first clock signal output by the first clock output terminal is higher than the clock frequency of the second clock signal output by the second clock output terminal. The first clock output terminal can be connected to the input terminal of the multi-state write circuit, and the output terminal of the multi-state write circuit can be connected to a memory array. Thus, the multi-state write circuit can write at least two states to the memory array within one clock cycle under the operating clock provided by the first clock signal output by the first clock output terminal. The second clock output terminal can be connected to the input terminals of both the row decoding circuit and the column decoding circuit. The output terminals of both the row decoding circuit and the column decoding circuit can be connected to the memory array. Thus, the row decoding circuit and the column decoding circuit can perform their respective decoding operations under the operating clock provided by the second clock signal.

[0007] In the above design, by configuring different operating clocks for the multi-state write circuit and other circuits in the read / write controller (such as row decoding and column decoding circuits), the read / write controller can use a separate operating clock to perform multi-state write operations. This decouples the multi-state write operation from other operations, which not only improves the flexibility of the multi-state write operation but also avoids affecting the normal operation of other circuits when adjusting the operating clock corresponding to the read / write operation. Furthermore, the multi-state write circuit in this method can write at least two states within one clock cycle, instead of writing one state per clock cycle, thus improving the write efficiency of the read / write controller. In addition, by providing a separate operating clock for the multi-state write circuit, the design can flexibly configure the current operating clock of the multi-state write circuit according to the current process deviation of the memory, making the write operation of the read / write controller more compatible with the current process deviation and improving the read / write controller's ability to cope with different process deviations.

[0008] In one possible design, the read / write controller may further include a sensitive amplifier. The clock control terminal of the sensitive amplifier can be connected to a first clock output terminal, the first input terminal of the sensitive amplifier can be connected to a reference cell in the memory array, the second input terminal of the sensitive amplifier can be connected to at least one memory cell in the memory array, and the output terminal of the sensitive amplifier can be connected to a read device. In the above design, configuring a separate operating clock for the sensitive amplifier allows the read / write controller to perform read operations using a separate operating clock. This decouples the read operation from other operations, improving the flexibility of the read operation. Furthermore, this design uses the same operating clock for the sensitive amplifier and the multi-state write circuit, instead of allocating separate operating clocks. Therefore, it can further reduce the complexity of the circuit structure and lower the circuit cost while independently controlling the read / write operations.

[0009] In one possible design, when the memory array is in read mode, if the first clock signal switches from a second level to a first level within one cycle of the first clock signal, the sensitive amplifier acquires the reference signal in the reference cell and the stored signal in at least one memory cell, and calculates the data stored in the memory cell based on the reference signal and the stored signal. This design can flexibly adjust the turn-on time of the sensitive amplifier by adjusting the level switching time of the clock signal. For example, the sensitive amplifier can be turned on earlier when the bit line charges and discharges quickly to improve read efficiency, or turned on later when the bit line charges and discharges slowly to improve read accuracy. This approach not only allows the read / write controller to adapt to different read scenarios, but also eliminates the need for additional components such as inverters, helping to reduce the cost of the read / write controller and the complexity of the circuit structure.

[0010] In this application, the clock generation circuit capable of generating two clock signals can have several possibilities, for example:

[0011] In one possible design, the clock generation circuit may further include a first clock generator and a frequency divider. The output of the first clock generator is connected to both a first clock output and the input of the frequency divider, and the output of the frequency divider is connected to a second clock output. Thus, the first clock generator can generate a first clock signal and provide it to both the first clock output and the frequency divider. On one hand, the first clock signal can be provided to the multi-state write circuit (and sensitive amplifier) ​​through the first clock output; on the other hand, it can be divided by the frequency divider into a lower-frequency second clock signal and provided to the second clock output, which in turn provides it to the row decoding circuit and the column decoding circuit. This design can obtain two clock signals of different frequencies using one clock generator and one frequency divider.

[0012] In another possible design, the clock generation circuit can also include a second clock generator and a frequency multiplier. The output of the second clock generator is connected to both the second clock output and the input of the frequency multiplier, while the output of the frequency multiplier is connected to the first clock output. In this way, the second clock generator can generate a second clock signal and provide it to both the second clock output and the frequency multiplier. On one hand, the second clock signal can be provided to the row and column decoding circuits through the second clock output; on the other hand, it can be divided by the frequency multiplier into a higher-frequency first clock signal and then provided to the first clock output, which in turn provides it to the multi-state write circuit (and the sensitive amplifier). This design can obtain two clock signals of different frequencies using a single clock generator and a frequency multiplier.

[0013] In another possible design, the clock generation circuit can also include a third clock generator and a fourth clock generator. The output of the third clock generator is connected to the first clock output, and the output of the fourth clock generator is connected to the second clock output. Thus, the third clock generator can generate a first clock signal and provide it to the first clock output, which is then supplied to the multi-state write circuit (and the sensitive amplifier). The fourth clock generator can generate a second clock signal and provide it to the second clock output, which is then supplied to the row and column decoding circuits. This design can obtain two clock signals of different frequencies using two clock generators.

[0014] In one possible design, the multi-state write circuit may include an inverter, a first metal-oxide-semiconductor (MOS) transistor, and a second MOS transistor. The input of the inverter and the gate of the second MOS transistor are respectively connected to the input of the multi-state write circuit. The output of the inverter is connected to the gate of the first MOS transistor. The source of the first MOS transistor is connected to a first power supply, and the source of the second MOS transistor is connected to a second power supply. The drains of the first and second MOS transistors are connected to the memory array. This design can achieve continuous writing of at least two states to the memory cell within one clock cycle using only one inverter and two MOS transistors. This not only simplifies the circuit structure but also allows the two MOS transistors to be in opposite states at the same clock signal level. Thus, the read / write controller can switch the write state by controlling the level switching of the clock signal.

[0015] In one possible design, when the memory array is in write mode, within one cycle of the first clock signal, if the first clock signal switches from a first level to a second level, the multi-state write circuit writes the first state to the memory array; if the first clock signal switches from a second level to a first level, the multi-state write circuit writes the second state to the memory array. This design, by adjusting the timing of the first clock signal's level transition, allows the multi-state write circuit to begin writing the second state precisely after the write duration corresponding to the process deviation, thus accurately tracking the memory's process deviations and improving the read / write controller's ability to withstand the effects of various process deviations.

[0016] Secondly, this application provides a memory including a memory array and a read / write controller as described in any of the first aspects above. The read / write controller can be connected to the memory array, the memory array can be used to store data, and the read / write controller can write data to the memory array or read data from the memory array.

[0017] Thirdly, this application provides an electronic device including a printed circuit board (PCB) and the memory provided in the second aspect above, the memory being disposed on the surface of the PCB.

[0018] Specifically, the electronic device includes, but is not limited to: smartphones, smartwatches, tablets, virtual reality (VR) devices, augmented reality (AR) devices, in-vehicle devices, desktop computers, personal computers, handheld computers, or personal digital assistants.

[0019] The foregoing or other aspects of this application will be described in detail in the following embodiments. Attached Figure Description

[0020] Figure 1 An exemplary schematic diagram of the internal structure of a memory to which this application embodiment applies is shown;

[0021] Figure 2 An exemplary schematic diagram of a read / write controller provided in an embodiment of this application is shown;

[0022] Figure 3 An exemplary schematic diagram of another read / write controller provided in an embodiment of this application is shown;

[0023] Figure 4 An exemplary schematic diagram of a multi-state write scheme provided in an embodiment of this application is shown;

[0024] Figure 5 An exemplary schematic diagram of another multi-state write scheme provided in an embodiment of this application is shown;

[0025] Figure 6 An exemplary performance comparison diagram of a multi-state write circuit provided in an embodiment of this application is shown;

[0026] Figure 7 This illustration shows a schematic diagram of another read / write controller provided in an embodiment of this application;

[0027] Figure 8 This illustration shows a schematic diagram of another read / write controller provided in an embodiment of this application;

[0028] Figure 9 This illustration shows a schematic diagram of another read / write controller provided in an embodiment of this application;

[0029] Figure 10 A comparative diagram illustrating an example of a reading scheme provided in an embodiment of this application is shown.

[0030] Figure 11 An exemplary embodiment of the present application provides a read / write control timing diagram;

[0031] Figure 12 This illustration shows a schematic diagram of another read / write controller provided in an embodiment of this application;

[0032] Figure 13 This illustration shows a schematic diagram of another read / write controller provided in an embodiment of this application;

[0033] Figure 14 This paper exemplarily illustrates a structural schematic diagram of another read / write controller provided in an embodiment of this application. Detailed Implementation

[0034] The read / write controller disclosed in this application can be applied to devices with read / write functions, such as storage devices with only read / write functions, like memory, or electronic devices with read / write functions and other functions. In some embodiments of this application, the read / write controller can be a separate unit embedded in the electronic device, capable of controlling the read / write operation of the electronic device's memory. In other embodiments of this application, the read / write controller can be a unit encapsulated inside the electronic device, used to implement the read / write control function of the electronic device's memory. The electronic device can be a portable electronic device including functions such as a personal digital assistant and / or a music player, such as a mobile phone, tablet computer, wearable device with wireless communication capabilities (such as a smartwatch), or in-vehicle device. Exemplary embodiments of portable electronic devices include, but are not limited to, devices equipped with... Alternatively, it can be a portable electronic device with another operating system. The aforementioned portable electronic device can also be a laptop computer, such as one with a touch-sensitive surface (e.g., a touch panel). It should also be understood that, in some other embodiments of this application, the aforementioned electronic device can also be a desktop computer with a touch-sensitive surface (e.g., a touch panel).

[0035] By way of example, the memory may be volatile memory, or may include both volatile and non-volatile memory. Volatile memory may be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory.

[0036] Synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM), as well as newer memories such as FeRAM, PCRAM, MRAM, and ReRAM. When the memory also includes non-volatile memory, this non-volatile memory can be read-only memory.

[0037] (Read-only memory, ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. When the memory includes both volatile and non-volatile memory, the read / write controller in this application can be used to read data from non-volatile memory and / or volatile memory, and can also be used to write data to volatile memory. It should be noted that the memory described in this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that in the following description of this application, "multiple" can be understood as "at least two". Terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order. For example, the "first clock signal" and "second clock signal" mentioned below are merely used to indicate different clock signals and do not have any difference in order, priority, or importance.

[0039] Figure 1 An exemplary schematic diagram of the internal structure of a memory to which an embodiment of this application applies is shown.

[0040] It should be understood that the illustrated memory 100 is merely an example, and the memory 100 may have more or fewer components than those shown in the figure, may combine two or more components, or may have different component configurations. The various components shown in the figure may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application-specific integrated circuits.

[0041] like Figure 1 As shown, the memory 100 may include a memory array 110 and a read / write controller 120. The read / write controller 120 may include a clock generation circuit 121, a read / write drive circuit 122, a row decoding circuit 123, a word line (WL) circuit 124, a column decoding circuit 125, a sensitive amplifier 126, and an input / output drive circuit 127, etc. The various components in the read / write controller 120 refer to functional components. These components can be configured as individual devices, implemented in a single device, or arranged in any combination in at least two devices; this application does not specifically limit their configuration.

[0042] The following is combined with Figure 1 A detailed description of each component in memory 100 is provided below:

[0043] Storage array 110, used for storing data, is a matrix array composed of multiple storage cells arranged in rows and columns. Each storage cell can store one bit of binary data, such as 0 or 1. These storage cells may be located on different disks or on different tracks of the same disk. When multiple storage cells are located on different disks, this arrangement effectively combines multiple disks into one: when data needs to be stored, it is split into multiple segments and stored on multiple disks respectively; when data needs to be retrieved, multiple disks operate together to output their respective data segments in parallel. Using this arrangement in memory not only effectively improves data read / write efficiency through parallel access to multiple disks but also improves memory space utilization through the array arrangement.

[0044] Clock generation circuit 121 is used to provide operating clocks to various components in read / write controller 120. Clock generation circuit 121 may have multiple clock output terminals, each of which can be connected to one or more components in read / write controller 120 to provide an operating clock to the connected one or more components. For example... Figure 1As shown, in this example: the clock generation circuit 121 may include five clock output terminals, namely clock output terminal A1, clock output terminal A2, clock output terminal A3, clock output terminal A4, and clock output terminal A5; clock output terminal A1 is connected to the sensitive amplifier 126 and the input / output drive circuit 127 respectively, and the clock generation circuit 121 can provide the same operating clock to the sensitive amplifier 126 and the input / output drive circuit 127 through clock output terminal A1; clock output terminal A2 is connected to the read / write drive circuit 122, and the clock generation circuit 121 can provide the same operating clock to the sensitive amplifier 126 and the input / output drive circuit 127 through clock output terminal A1; Clock output terminal A2 provides a working clock to read / write drive circuit 122; clock output terminal A3 is connected to word line circuit 124, and clock generation circuit 121 can provide a working clock to word line circuit 124 through clock output terminal A3; clock output terminal A4 is connected to row decoding circuit 123, and clock generation circuit 121 can provide a working clock to row decoding circuit 123 through clock output terminal A4; clock output terminal A5 is connected to column decoding circuit 125, and clock generation circuit 121 can provide a working clock to column decoding circuit 125 through clock output terminal A5. For example, although... Figure 1 Although not shown, the memory array 110 may also have an operating clock. The operating clock of the memory array 110 may be provided by the clock generation circuit 121, by a separate clock generator packaged inside the memory array 110, or by other components in the electronic device, which are not specifically limited in this application.

[0045] The row decoding circuit 123 is used to decode the row address information to obtain the row where the target memory unit is located.

[0046] The word line circuit 124 may include multiple word lines corresponding one-to-one with multiple rows of memory cells in the memory array 110. The input of each word line is connected to the output of the row decoding circuit 123, and the output of each word line is connected to the control terminal of the corresponding row of memory cells. After decoding the row where the target memory cell is located, the row decoding circuit 123 may also send a decoding selection signal to the target word line connected to the row where the target memory cell is located in the word line circuit 124 to instruct the target word line to work, and send a decoding shutdown signal to other word lines in the word line circuit 124 to instruct other word lines to wait. When the target word line is working, it may output a first word line signal (such as a high level) to the connected row of memory cells to enable the connected row of memory cells. When other word lines are waiting, they may output a second word line signal (such as a low level) to the connected row of memory cells to disable the connected row of memory cells.

[0047] The column decoding circuit 125 is used to decode the column address information to obtain the column where the target memory unit is located.

[0048] The read / write driver circuit 122 is used to read and write data in the target storage unit. The input terminal of the read / write driver circuit 122 is connected to the output terminal of the column decoding circuit 125. Figure 1 (Not illustrated), the output of the read / write drive circuit 122 is connected to each memory cell. After decoding to obtain the column where the target memory cell is located, the column decoding circuit 125 can send an instruction to the read / write drive circuit 122 to instruct it to read / write the data in the column where the target memory cell is located. At this time, only the row where the target memory cell is located is open, so the data read / written by the read / write drive circuit 122 is the data in the target memory cell.

[0049] As described above, the read / write drive circuit 122, in conjunction with other circuits in the read / write controller 120, can perform read and write operations on data in the storage array. The following sections will detail the writing and reading of data:

[0050] The read / write driver circuit 122, in conjunction with the row decoding circuit 123, word line circuit 124, and column decoding circuit 125, can write data to the storage array 110. Assuming an external device 200 (such as a read / write device or processor) wants to write "0" to a target storage cell located in the third row and fourth column of the storage array 110, the external device 200 can first send a write request to the read / write driver circuit 122, carrying the row address information and column address information of the target storage cell in the write request. The read / write driver circuit 122 sends the row address information carried in the write request to the row decoding circuit 123. The row decoding circuit 123 decodes the row address information to determine that the row containing the target storage cell is the third row. Therefore, the row decoding circuit 123 sends a decoding selection signal to the target word line corresponding to the third row storage cell in the word line circuit 124, enabling the target word line to access the third row storage cell. Subsequently, the read / write drive circuit 122 can also send the column address information carried in the write request to the column decoding circuit 125. The column decoding circuit 125 decodes the column address information and finds that the target memory cell is located in the fourth column. Therefore, the column decoding circuit 125 returns a response to the read / write drive circuit 122 to instruct the read / write drive circuit 122 to write data to the target memory cell in the third row of the fourth column memory cells that has been opened. The read / write drive circuit 122 is equipped with a write circuit (such as a multi-state write circuit). The read / write drive circuit triggers the clock generation circuit 121 to output the level corresponding to the data to be written to the write circuit. For example, when it is necessary to write "0", the clock generation circuit 121 is triggered to output a high level to the write circuit. This high level and the local reference level of the write circuit form a first voltage difference to drive the write circuit to write "0" to the target memory cell. When it is necessary to write "1", the clock generation circuit 121 is triggered to output a low level to the write circuit. This low level and the local reference level of the write circuit form a second voltage difference to drive the write circuit to write "1" to the target memory cell. Therefore, in the scenario of writing two states consecutively, the generation time of the first voltage difference and the second voltage difference corresponding to the two states to be written determines when to start writing these two states.

[0051] The read / write driver circuit 122 can also work in conjunction with the row decoding circuit 123, word line circuit 124, column decoding circuit 125, and sensitive amplifier 126 to read data in the storage array 110. Assuming an external device 200 wants to read data stored in a target storage cell located in the third row and fourth column of the storage array 110, the external device 200 can first send a read request to the read / write driver circuit 122, carrying the row address and column address information of the target storage cell in the read request. The read / write driver circuit 122 can then, following the same logic as the write operation described above, work in conjunction with the row decoding circuit 123, word line circuit 124, and column decoding circuit 125 to open the target storage cell located in the third row and fourth column of the storage array 110. Subsequently, the read / write drive circuit 122 can be triggered by the level of the clock generation circuit 121 (e.g., outputting a low level) to charge and discharge the opened target memory cell (and reference cell; this charging and discharging operation will be described in detail later and will not be explained here). After a fixed delay or by controlling the reference cell, the sensitive amplifier is turned on, so that the sensitive amplifier 126 determines the data stored in the opened target memory cell based on the potential difference between the target memory cell and the reference cell. Therefore, in the reading scenario, the turn-on time of the sensitive amplifier determines when data reading begins.

[0052] The input / output drive circuit 127 is used to enhance the drive to enable interaction between the read / write controller 120 and the external device 200. For example, when the external device 200 requests to read data from the storage array 110, the input / output drive circuit 127 can first acquire the data read by the sensitive amplifier 126, and then increase the drive signal (such as drive current) to output the data to the external device 200. As another example, when the external device 200 requests to write data to the storage array 110, the input / output drive circuit 127 can first increase the drive signal (such as drive current) to acquire the data to be written from the external device 200, and then send the data to be written to the write circuit in the read / write drive circuit 122, so that the write circuit can write the data to be written to the storage array 110 according to the above-described write logic.

[0053] although Figure 1 As not shown in the diagram, the memory 100 may also include other components, such as the main memory data register (MDR) and the main memory address register (MAR), which will not be described in detail here.

[0054] Currently, the clock generation circuit provides a fixed-frequency operating clock to all components in the read / write controller through various clock output terminals (such as clock output terminals A1 to A5 mentioned above). This effectively couples the read / write operations of the read / write controller with other operations (such as decoding, opening rows, opening columns, and strengthening drive operations), causing the read / write controller to only execute operations according to the same operating clock, and thus unable to execute read / write operations according to its own required operating clock, resulting in poor read / write flexibility. Furthermore, the current read / write control scheme depends on the specific circuit structure. Once the circuit structure is fixed, the various time nodes involved in the read / write control process are essentially fixed, leading to poor adjustability. For example, when writing two states consecutively, currently, the second state can only be written after starting to write the first state, at a fixed time interval corresponding to the circuit structure. However, memory write times can vary depending on process variations. For example, with significant process variations, the read / write controller may take a long time to accurately write the first state to the memory array. In this case, the read / write controller actually needs a longer time interval to improve the accuracy of the written data. Conversely, with smaller process variations, the read / write controller may accurately write the first state to the memory array in a very short time. In this case, the read / write controller actually needs a shorter time interval to maximize the write speed while ensuring accurate data writing. Clearly, the fixed time interval read / write method in the prior art cannot meet the read / write performance requirements of different process scenarios, resulting in a weak ability of the read / write controller to cope with the effects of different process variations.

[0055] Based on this, this application provides a read / write controller for providing separate operating clocks for key circuits related to read / write (such as multi-state write circuits and sensitive amplifiers) in the read / write controller, so as to further improve the read / write controller's ability to cope with the effects of different process deviations while improving the read / write controller's read / write flexibility.

[0056] The following is based on Figure 1The illustrated memory is used to describe the specific structure of the read / write controller provided in this application through specific embodiments. It should be noted that "connection" in the following embodiments of this application refers to an electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components, such as the connection between A and B. Alternatively, A can be directly connected to C, and C can be directly connected to B, with A and B connected through C. It should be understood that the "1" and "0" levels in digital signals refer to "1" and "0" in logical operations, not the voltage values ​​of the digital signal's signal voltage. In most cases, a "1" level in a digital signal means that the signal voltage of the digital signal is greater than a threshold voltage, and a "0" level means that the signal voltage of the digital signal is less than a threshold voltage. For ease of description, the embodiments of this application will subsequently use "high level" to represent a "1" level in a digital signal and "low level" to represent a "0" level in a digital signal.

[0057] Example 1

[0058] Figure 2 An exemplary schematic diagram of a read / write controller provided in an embodiment of this application is shown, such as... Figure 2 As shown in this embodiment, the read / write controller 120 includes a clock generation circuit 121, a critical read / write circuit 130, and a non-critical read / write circuit 140, which are respectively connected to the storage array 110. The clock generation circuit 121 includes a first clock output terminal (B1) and a second clock output terminal (B2). The clock output terminal B1 is connected to the clock control terminal of the critical read / write circuit 130. The clock generation circuit 121 can output a first clock signal (Input) to the critical read / write circuit 130 through the clock output terminal B1, so that the critical read / write circuit 130 can perform critical read / write operations on the storage array 110 under the working clock provided by the clock signal Input. The clock output terminal B2 is connected to the clock control terminal of the non-critical read / write circuit 140. The clock generation circuit 121 can output a second clock signal (Inner) to the non-critical read / write circuit 140 through the clock output terminal B2, so that the non-critical read / write circuit 140 can perform other operations on the memory array 110 besides the aforementioned critical read / write operations under the working clock provided by the clock signal Inner, such as row decoding, word line selection, and enhanced driving. Among them, the clock frequency of the clock signal Input is higher than the clock frequency of the clock signal Inner.

[0059] In this embodiment, the key read / write circuit 130 refers to a circuit that can determine when to start reading or writing data in the target storage unit based on its own operating clock, such as the multi-state write circuit and / or described below. Figure 1The illustrated sensitive amplifier, and may also include other circuitry capable of determining when to initiate read / write operations, such as... Figure 1 The circuits in the illustrated read / write drive circuit 122 used to generate the first voltage difference and the second voltage difference, or the circuits used to determine the write timing of a state in a scenario where only one state is written, are not specifically limited. Correspondingly, the non-critical read / write circuit 140 refers to one or more other circuits besides the critical read / write circuit 130, such as those that may include... Figure 1 The diagram shows a row decoding circuit 123, a column decoding circuit 125, a read / write drive circuit 122 (or the read / write drive circuit 122 excluding the circuit used to generate the first voltage difference and the second voltage difference), or an input / output drive circuit 127, etc. Thus, by configuring different operating clocks for critical and non-critical read / write circuits, it helps to decouple critical read / write operations from other operations. By adjusting the operating clock corresponding to the critical read / write circuit, not only can the flexibility of the critical read / write circuit be effectively improved, but the normal operation of the non-critical read / write circuits will not be affected.

[0060] For ease of understanding, the following embodiments of this application use a key read / write circuit including a multi-state write circuit as an example. It should be understood that all content described below also applies to... Figure 2 The read / write controller 120 in this application will not be described in detail here.

[0061] Figure 3 An exemplary schematic diagram of another read / write controller provided in an embodiment of this application is shown, such as... Figure 3 As shown, in this example, the critical read / write circuit 130 includes a multi-state write circuit 128, and the non-critical read / write circuit 140 includes a row decoding circuit 123 and a column decoding circuit 125. In this example, when the memory is in write mode, the clock generation circuit 121 can output a first clock signal (Input) to the multi-state write circuit 128 through the clock output terminal B1. The multi-state write circuit 128 can write at least two states to the memory array 110 within one clock cycle according to the working clock provided by the clock signal Input. The clock generation circuit 121 can also output a second clock signal (Inner) to the row decoding circuit 123 and the column decoding circuit 125 through the clock output terminal B2, so that the row decoding circuit 123 and the column decoding circuit 125 can perform the row decoding and column decoding described above under the working clock provided by the clock signal Inner. For example, the row decoding circuit 123 can decode the row address information under the working clock provided by the clock signal Inner to determine the row where the target memory cell is located and send an indication to the word line circuit. The column decoding circuit 125 can decode the column address information under the working clock provided by the clock signal Inner to determine the column where the target memory cell is located and return a response to the read / write drive circuit.

[0062] In this embodiment, the clock frequency of the clock signal Input is higher than the clock frequency of the clock signal Inner. Thus, under one level state of the clock signal Inner, the clock signal Input can correspond to at least two level changes. Correspondingly, the multi-state write circuit 128 can also correspond to at least two output voltages. The at least two output voltages of the multi-state write circuit 128, compared with the voltage under the same level control of the clock signal Inner, can form at least two voltage differences. Therefore, the read / write controller 120 can complete the write control of at least two states based on these at least two voltage differences within one clock cycle of the clock signal Input. Furthermore, by having the multi-state write circuit 128 perform at least two state write operations under a fast operating clock, while other circuits perform other memory operations (such as row decoding, word line selection, and enhanced drive) under a slow operating clock, the power consumption required for other memory operations can be minimized while rapidly writing at least two states.

[0063] It should be noted that, Figure 3 The multi-state write circuit 128 shown can be corresponding to: Figure 1 The illustrated word line circuit 124, such as the multi-state write circuit 128, refers to the word line circuit 124, or the multi-state write circuit 128 is a functional component of the word line circuit 124. When the multi-state write circuit 128 is a functional component of the word line circuit 124, the other circuits in the word line circuit 124, excluding the multi-state write circuit 128, still operate based on the clock signal Inner. The above actually provides the operating clock for the row decoding circuit 123 and the column decoding circuit 125 through the clock signal Inner, but this is only one optional implementation. In other optional implementations, the clock signal Inner can also be used to provide the operating clock for the row decoding circuit 123 and the column decoding circuit 125. Figure 1 The illustrated circuit provides the operating clock for any one or more circuits other than the multi-state write circuit 128. For example, in one case, the clock output terminal B2 can also be connected to the clock control terminals of the read / write drive circuit 122, the row decoding circuit 123, the column decoding circuit 125, the input / output drive circuit 127, and the other circuits in the word line circuit 124 besides the multi-state write circuit. In this way, the clock generation circuit 121 can also provide the clock signal Inner to all other circuits in the read / write controller 120 except for the multi-state write circuit 128 through the clock output terminal B2. This implementation not only enables the read / write controller to control the write operation of the multi-state write circuit based on a separate operating clock, but also minimizes the number of clocks required to be generated by the read / write controller, which helps to reduce the cost of the read / write controller while simplifying the overall control logic of the read / write controller.

[0064] As mentioned above Figure 3The illustrated read / write controller, by configuring different operating clocks for the multi-state write circuit and other circuits in the read / write controller (such as row decoding circuits and column decoding circuits), enables the multi-state write circuit to perform multi-state write operations using a separate operating clock (for ease of explanation, this document uses "multi-state write operation" to refer to "the operation of writing at least two states within one clock cycle"). This approach helps to decouple the multi-state write operation from other operations. Thus, by adjusting the operating clock corresponding to the multi-state write circuit, not only can the flexibility of the multi-state write operation be effectively improved, but it will not affect the normal operation of other circuits.

[0065] In this embodiment, the multi-state write circuit 128 can write at least two states within one clock cycle of the clock signal Input. There are several possibilities for the multi-state write circuit 128 to achieve this function; two possible solutions are exemplarily described below.

[0066] Option 1

[0067] Figure 4 An exemplary diagram illustrates a multi-state write scheme provided in an embodiment of this application, wherein:

[0068] Figure 4 Figure (a) illustrates the circuit structure of this multi-state write scheme, as shown in Figure (a). Figure 4 As shown in Figure (a), in this scheme, the multi-state write circuit 128 may include a reverse delay chain 1281 and two identical metal oxide semiconductor (MOS) transistors, such as P-channel MOS transistors P0. 11 P-channel MOSFET 12 Or an N-channel MOSFET P 11 and N-channel MOSFET P 12 The inverse delay chain 1281 can be constructed from an odd number of inverters connected end-to-end. An inverter is a basic electronic device that receives an input signal and outputs a signal that is the inverse of the input signal. Generally, the input signal of an inverter can be a digital signal, and the input signal level can be either high or low. If the inverter receives a high-level input signal, it can output a low-level output signal; conversely, if it receives a low-level input signal, it can output a high-level output signal. The MOSFET P... 11 The source can be connected to the power supply V. 11 MOSFET P 11 The gate and the input of the reverse delay chain 1281 can be connected to the clock output B1 and the MOSFET P, respectively. 11 The drain of the MOSFET can be connected to the memory array 110. 12The source can be connected to the power supply V. 12 MOSFET P 12 The gate of the MOSFET can be connected to the output of the reverse delay chain 1281. 12 The drain of the device can be connected to the memory array 110.

[0069] Figure 4 Figure (b) illustrates the control timing when at least two states are written according to this circuit structure, where, Figure 4 The "Input" line in diagram (b) illustrates the level changes of the clock signal Input. Figure 4 The "Write Signal" line in Figure (b) illustrates the changes in the write signal. (Refer to...) Figure 4 Figure (a) and Figure 4 Figure (b) illustrates an example of writing "0" and "1" states within one clock cycle (e.g., cycle 1) of the clock signal Input. Assume the MOS transistor P... 11 and MOSFET P 12 Both are P-channel MOSFETs, and write signal delay and MOSFET P-channel latency are not considered. 11 and MOSFET P 12 To mitigate voltage drop, if there are 27 inverters in the reverse delay chain 1281, and the time required for the signal to travel from the input to the output of each inverter in the reverse delay chain 1281 is 0.1 ns (ns is a unit of time, i.e., nanosecond), then the delay duration of the reverse delay chain 1281 is 2.7 ns (i.e., 0.1 ns × 27). When the period of one cycle of the clock signal Input is greater than 2.7 ns, if the clock generation circuit 121 follows... Figure 4 As shown in Figure (b), the "Input" line outputs the clock signal Input. When the clock signal Input is low, this low-level signal is transmitted via link L11 and then directly applied to the MOS transistor P. 11 The gate of the MOSFET P 11 The source and drain of the transistor are cut off, while the signal is inverted by 27 inverters on link L12 (still a low-level signal) and applied to MOSFET P. 12 The gate of the MOSFET P 12 When the source and drain are cut off, the MOSFET P... 11 and MOSFET P 11 When all signals are cut off, the voltage at point K is 0, and the read / write controller 120 does not write data to the storage array 110. When the clock signal Input switches from low to high "1", the read / write drive circuit 122 in the read / write controller 120 is at the voltage corresponding to that level (let's assume it's V). 10 This high-level signal is transmitted via link L11 and then directly applied to MOSFET P.11 The gate of the MOSFET P 11 The source and drain of the transistor are turned on, and after being inverted by 27 inverters on link L12 (still a high-level signal), it is applied to the MOSFET P after a delay of 2.7ns. 12 The gate of the MOSFET P 12 The source and drain of the MOSFET are turned on. In this case, 2.7ns elapsed after the clock signal Input switches from low to high, the MOSFET P... 11 The MOSFET P is on. 12 At cutoff, the voltage at point K is V. 11 The voltage V in the read / write drive circuit 122 10 and the voltage V of the multi-state write circuit 128 11 A voltage difference V is formed between them 10 -V 11 Therefore, the read / write drive circuit 122 can write the voltage difference V to the storage array 110. 10 -V 11 The corresponding state (e.g., writing "0"). After 2.7ns, MOSFET P11 turns on and MOSFET P12 also turns on, and the voltage at point K changes from V... 11 Switch to V 11 +V 12 The voltage V in the read / write drive circuit 122 10 and the voltage V of the multi-state write circuit 128 11 +V 12 A voltage difference V is formed between them 10 -V 11 -V 12 Therefore, the read / write drive circuit 122 can write the voltage difference V to the storage array 110. 10 -V 11 -V 12 The corresponding state (e.g., writing "1"). Thus, according to... Figure 4 The timing control logic is shown in Figure (b). Figure 4 The multi-state write circuit 128 shown in Figure (a) can write two states to the memory array 110 within one clock cycle of the clock signal input.

[0070] In the above scheme, the time interval between the start of writing the first state and the start of writing the second state (i.e., the writing duration of one state) depends on the delay duration of the reverse delay chain 1281, which is related to the number of inverters included in the reverse delay chain 1281. Generally, the number of inverters set in the read / write controller 120 cannot be changed after the read / write controller 120 leaves the factory. In this case, the scheme can actually write each state with a fixed writing duration. However, considering that different process deviations may require different writing durations, such as writing a state only 0.3ns under some process deviations, while writing a state under other process deviations requires 1ns, if we want the multi-state write circuit 128 of this structure to also meet the requirements of different process deviations and improve the ability of the read / write controller 120 to resist the influence of different process deviations, then: a first switching component can be connected before each inverter in the reverse delay chain 1281, and another line with a second switching component can be led to the MOSFET P before the first switching component. 12 The gate of the read / write controller 120 is configured to have a required number of inverters active and other inverters inactive by controlling the on / off states of each first and second switching component, thereby changing the delay duration of the reverse delay chain 1281. Although this method requires more switching components and more inverters in the multi-state write circuit 128, which may make the circuit structure of the read / write controller 120 more complex and increase its cost, it enables the delay duration of the reverse delay chain 1281 to be adjustable, which helps the read / write controller 120 to flexibly adjust the write duration of a state when writing at least two states consecutively.

[0071] Option 2

[0072] Figure 5 An exemplary diagram illustrates another multi-state write scheme provided in an embodiment of this application, wherein:

[0073] Figure 5 Figure (a) illustrates the circuit structure of this multi-state write scheme, as shown in Figure (a). Figure 5 As shown in Figure (a), in this scheme, the multi-state write circuit 128 may include an inverter (T) and two identical metal oxide semiconductor (MOS) transistors, such as a P-channel MOS transistor P. 21 P-channel MOSFET 22 Or an N-channel MOSFET P 21 and N-channel MOSFET P 22 Among them, the input terminal of inverter T and MOSFET P 21The gates of the inverter T can be connected to the clock output terminal B1, and the output terminal of the inverter T can be connected to the MOSFET P. 22 The gate of the MOSFET P 21 The source terminal is connected to the power supply V. 21 MOSFET P 21 The drain of the memory array 110 is connected to the MOSFET P. 22 The source terminal is connected to the power supply V. 22 MOSFET P 22 The drain is connected to the memory array.

[0074] Figure 5 Figure (b) illustrates the control timing when at least two states are written according to this circuit structure, where, Figure 5 The "Inner" line in diagram (b) illustrates the level changes of the clock signal Inner. Figure 5 The "Input" line in diagram (b) illustrates the level changes of the clock signal Input. Figure 5 The "Write Signal" line in Figure (b) illustrates the changes in the write signal. (Refer to...) Figure 5 Figure (a) and Figure 5 Figure (b) illustrates an example of writing "0" and "1" states within one clock cycle (e.g., cycle 1) of the clock signal Input. Assume the MOS transistor P... 11 and MOSFET P 12 Both are P-channel MOSFETs, and write signal delay and MOSFET P-channel latency are not considered. 11 and MOSFET P 12 The voltage drop, if the clock generation circuit 121 according to Figure 5 As shown in Figure (b), the “Inner” line outputs the clock signal Inner, and the “Input” line outputs the clock signal Input. Then, in a certain level state of the clock signal Inner (such as a high level “1”), the read / write drive circuit 122 in the read / write controller 120 is at the voltage corresponding to that level state (let’s assume it’s V). 20 When the clock signal Input switches to a high level, this high-level signal is transmitted via link L21 and directly applied to MOSFET P. 21 The gate of the MOSFET P is turned on. 21 The source and drain of the transistor are inverted by the inverter T on link L22 and converted into a low-level signal, which is then applied to the MOSFET P. 22 The gate of the MOSFET P is turned off. 22 The source and drain of the MOSFET P. 21 The MOSFET P is on. 22 At cutoff, the voltage at point K is V. 21In this case, the voltage V in the read / write drive circuit 122 20 The voltage V output by the multi-state write circuit 128 21 The voltage difference between them is V 20 -V 21 Therefore, the read / write drive circuit 122 can write the voltage difference V to the storage array 110. 20 -V 21 The corresponding state (e.g., writing "0"). When the clock signal Input switches from high to low, this low-level signal is directly applied to the MOSFET P after being transmitted via link L21. 21 The gate of the MOSFET P is turned off. 21 The source and drain of the transistor are inverted by the inverter T on link L22 and converted into a high-level signal, which is then applied to the MOSFET P. 22 The gate of the MOSFET P is turned on. 22 The source and drain of the MOSFET P. 21 Cut off and MOSFET P 21 When the circuit is on, the voltage at point K is V. 22 In this case, the voltage V in the read / write drive circuit 122 20 The voltage V output by the multi-state write circuit 128 22 The voltage difference between them is V 20 -V 22 Therefore, the read / write drive circuit 122 can write the voltage difference V to the storage array 110. 20 -V 22 The corresponding state (e.g., writing "1"). Afterwards, if the clock signal Inner switches to another level state (e.g., high level "0"), the read / write drive circuit 122 controls the memory to sleep according to this level state and the level state of the multi-state write circuit 128, that is, maintaining the memory in a non-write state. Thus, according to... Figure 5 The timing control logic is shown in Figure (b). Figure 5 The multi-state circuit 128 shown in Figure (a) can write two states to the memory array 110 within one clock cycle of the clock signal Input.

[0075] In the above scheme, by controlling the clock frequency of the Input clock signal to be higher than the clock frequency of the Inner clock signal, at least two states of write operation can be implemented under one level state of the Inner clock signal: for example, when the Input clock signal is high, write operations based on the voltage difference V can be performed. 20 -V 21 Write a state to memory array 110 based on the voltage difference V when the clock signal Input switches from high to low. 20 -V 22Writing another state to the storage array 110, the above scheme actually triggers the write operation of another state when the clock signal Input undergoes a level switch. In this case, the time interval between starting to write one state and starting to write another state (i.e., the write duration of one state) depends on the level switch time of the clock signal Input (as in the example above, the trigger time of the falling edge): the later the clock signal Input triggers the level switch, the longer the write time left for one state, and the read / write drive circuit 122 will stop writing to that state and start writing to another state after a relatively long write time from the start of writing one state; the earlier the clock signal Input triggers the level switch, the shorter the write time left for one state, and the read / write drive circuit 122 can stop writing to that state and start writing to another state after a very short write time from the start of writing one state.

[0076] Based on this, in an optional implementation, considering that the level switching time of the clock signal Input is related to the cycle length of one period of the clock signal Input (the longer the cycle length, the earlier the clock signal Input will switch levels; the shorter the cycle length, the later the clock signal Input will switch levels), the read / write controller 120 can also adjust the cycle length corresponding to the clock signal Input through the clock generation circuit 121 to change the time interval when the multi-state write circuit 128 writes to different states, so as to improve the ability of the multi-state write circuit 128 to resist the influence of different process deviations. For example, when the current process deviation is large, causing the read / write controller 120 to take a long time to write a state to the storage array 110, the read / write controller 120 can configure the frequency of the clock signal Input to a smaller value through the clock generation circuit 121. In this way, the current cycle duration of the clock signal Input is relatively extended, which means that the clock signal Input will not start switching levels until a longer time has passed. Thus, the state currently being written can correspond to more writing time. This helps to ensure that the state currently being written is successfully written to the storage array 110 before starting to write another state, effectively improving the writing accuracy when writing two states consecutively. When the current process deviation is small enough that the read / write controller 120 can write a state to the memory array 110 in a very short time, the read / write controller 120 can configure the frequency of the clock signal Input to a larger value through the clock generation circuit 121. This shortens the current cycle duration of the clock signal Input, meaning that the clock signal Input will begin switching levels after a very short time. Consequently, the currently being written state corresponds to a shorter write time. This helps to quickly begin writing another state while the current state can be written to the memory array 110, thereby improving the write speed of writing two states consecutively. The current process deviation can be detected by the user in real time, or it can be preset in the memory's specification parameters by those skilled in the art; no specific limitation is made.

[0077] The following is a specific example. Figure 4 The indicated multi-state write scheme and Figure 5 The following is a comparison of write performance of the multi-state write scheme when dealing with different process variations:

[0078] Figure 6 An exemplary performance comparison diagram of a multi-state write circuit provided in an embodiment of this application is shown, such as... Figure 6 As shown, the topmost node line (i.e. Figure 6 The "Input" line shown is the level change line for the clock signal Input. The two middle lines correspond to a multi-state write circuit with an inverting delay chain (i.e., ...). Figure 4The multi-state write circuit 128 shown in Figure (a), assuming it is called multi-state write circuit 1), is shown in the figure. The solid line in these two lines (i.e. Figure 6 The line shown as "1.1 - Write a state" is the control line corresponding to the first state written by the multi-state write circuit 1. The dashed line in these two lines (i.e., Figure 6 The line shown as "1.2 - Write to another state" is the control line corresponding to the multi-state write circuit 1 writing to the second state. The two lines below correspond to the multi-state write circuit (i.e., the multi-state write circuit that achieves multi-state writing by switching level states) Figure 5 The multi-state write circuit 128 shown in Figure (a), assuming it is called multi-state write circuit 2), is shown in the figure. The solid line in these two lines (i.e. Figure 6 The line shown as "2.1 - Write a state" is the control line corresponding to the first state written by the multi-state write circuit 2. The dashed line in these two lines (i.e., Figure 6 The line “2.2 - Write another state” shown is the control line corresponding to the multi-state write circuit 2 when writing the second state.

[0079] Table 1 provides an example comparison of the write performance of these two multi-state write circuits:

[0080]

[0081] Table 1

[0082] Reference Figure 6 As shown in Table 1, in this example, the delay time of the inverting delay chain is 2.7 ns, while the memory process variation results in a minimum of 14.5 ns required to successfully write a state to the memory array. In this case:

[0083] The read / write controller employing multi-state write circuit 1 begins writing the first state to the memory array after detecting that the clock signal Input has switched to a high level (due to signal transmission delay, the time E when the clock signal Input starts to switch to a high level is...). 11 Later than the moment when the clock signal Input actually begins to switch to a high level E 10 After a delay of 2.7 ns in the reverse delay chain (i.e., at time E), 12The read / write controller using multi-state write circuit 1 stops writing to the first state and begins writing to the second state. Clearly, 2.7ns is very short compared to 14.5ns. With a process deviation of 14.5ns, such a short time is insufficient for the memory to write the first state to the memory array. Writing the second state before the first state is successfully written could lead to incorrect data being written or data loss. Therefore, the write performance of the read / write controller using multi-state write circuit 1 cannot meet the requirements of the 14.5ns process deviation, resulting in weak resistance to the effects of process deviations.

[0084] The read / write controller employing multi-state write circuit 2 begins writing the first state to the memory array after detecting that the clock signal Input has switched to a high level. (Due to signal transmission delay, the time when the clock signal Input is detected to start switching to a high level is later than the time when the clock signal Input actually starts switching to a high level; the time E when writing the first state begins is later than the time when the clock signal Input actually starts switching to a high level.) 21 Later than the time E when the clock signal Input is actually triggered 20 Subsequently, the read / write controller using multi-state write circuit 2 determines the current process deviation to be 14.5ns. Therefore, the read / write controller can maintain the clock signal Input at a high level for 14.5ns using the clock generation circuit to continuously write the first state within this 14.5ns duration. After 14.5ns, the read / write controller then controls the clock signal Input to switch from high to low level (i.e., triggering the falling edge of the clock signal Input after 14.5ns; alternatively, the arrival time of the falling edge of the clock signal Input can be changed by setting the period length corresponding to clock signal Input2 to 29ns), thus stopping the writing of the first state and starting the writing of the second state. (Due to the delay in signal transmission, the time when the clock signal Input starts to switch to low level is later than the time when the clock signal Input actually starts to switch to low level, and the time E when the writing of the second state begins is later than the time when the clock signal Input starts to switch to low level.) 23 It is also later than the moment when the clock signal Input actually triggers the falling edge E. 22 ).

[0085] As described above, in the multi-state write circuit 2, the arrival time of the falling edge of the clock signal Input is adjusted by the clock generation circuit. This allows the read / write controller using the multi-state write circuit 2 to begin writing the second state exactly 14.5ns after the process deviation. Thus, the 14.5ns duration is sufficient for the read / write controller to successfully write the first state into the memory with this process deviation. This scheme utilizes the adjustable falling edge characteristic of the clock signal to accurately track the process deviation of the memory by adjusting the arrival time of the falling edge. This helps the read / write controller resist the influence of various process deviations and improves the write performance of the read / write controller.

[0086] It should be noted that the above content only uses "writing to another state triggered by the falling edge" as an example to illustrate the specific implementation process of the multi-state write access scheme. This application does not limit whether writing to another state is triggered by the falling edge or the rising edge. For the scheme of writing to another state triggered by the rising edge, please refer to the above content for corresponding settings, which will not be elaborated on in this application.

[0087] It should be noted that the above content only uses the multi-state write circuit 128, which includes an inverter and two identical MOSFETs, as an example to illustrate the implementation process of writing to at least two states. It should be understood that as long as it can achieve "turning on the MOSFET P through different voltage levels",... 21 and MOSFET P 22 The circuit structures described herein are all within the scope of protection of this application. For example, in another alternative embodiment, the multi-state write circuit 128 may also include an inverting delay chain consisting of an odd number of inverters connected end to end and two MOS transistors of the same type, with the connection relationship still as described above. Figure 5 As shown. In this case, since the clock signal Input is directly applied to the MOSFET P... 21 On the other hand, after being inverted by an odd number of inverters and converted into an opposite clock signal, it is applied to the MOSFET P. 22 Above, therefore, the same type of MOS transistor P 21 and MOSFET P 22 At the same voltage level, one transistor is turned on and the other is turned off. Thus, in the P-channel of the MOSFET... 21 The power supply connected to the source and the MOSFET P 22 When the power supply connected to the source of a MOSFET is different, the same type of MOSFET P... 21 and MOSFET P 22The voltage applied to the memory array can also be changed when the clock signal Input level changes, thus altering the write duration of a state by adjusting the timing of the clock signal Input level switching. In another alternative embodiment, the multi-state write circuit 128 may also include two different types of MOSFETs and may not include inverters or may include an inverted delay chain consisting of an even number of inverters connected end-to-end. In this case, since the clock signal is directly applied to a certain type of MOSFET P... 21 On the other hand, after being inverted by an even number of inverters and converted into the same clock signal, it is applied to another type of MOSFET P. 22 (Or, without going through an inverter, it is directly applied to another type of MOSFET P) 22 (above), therefore, different types of MOSFETs P 21 and MOSFET P 22 At the same voltage level, one transistor is turned on and the other is turned off. Thus, in the P-channel of the MOSFET... 21 The power supply connected to the source and the MOSFET P 22 Different types of MOSFETs P are affected by different power supplies connected to their source terminals. 21 and MOSFET P 22 The voltage applied to the memory array can also be changed when the level of the clock signal Input changes. Therefore, this method can also change the write duration of a state by adjusting the timing of the clock signal Input level switching. There are many possible implementation methods, which will not be elaborated here.

[0088] The above mainly introduced the specific implementation process of the read / write controller writing at least two states. The following continues based on Example 1. Figure 5 The read / write controller 120 shown is illustrated below (for ease of understanding, the read / write drive circuit will not be described further below). The specific implementation process of the read / write controller reading data is further described in Embodiment 2. It should be noted that Embodiment 2 is only based on... Figure 5 The following description uses the illustrated read / write controller 120 as an example. The various solutions in Embodiment 2 are also applicable to any read / write controller in Embodiment 1, such as... Figure 3 or Figure 4 The read / write controller 120 shown is not described in detail in this application.

[0089] In embodiment two, the read / write controller may further include a sensitive amplifier, such as... Figure 1The illustrated sensitive amplifier 126 and the storage array may include a reference cell (such as R) and at least one storage cell, such as storage cell 1, storage cell 2, ..., storage cell M×N, where M and N are both positive integers. Storage cells 1 to M×N can be arranged in an M×N matrix. Read operations on the target storage cell can be performed in conjunction with the sensitive amplifier. Before the read operation begins, the read / write controller pre-charges the two bit lines corresponding to the reference cell R and the target storage cell to the same high level. After pre-charging, the read / write controller drives the target storage cell selected by the word line circuit to charge and discharge its corresponding bit lines according to the data stored inside (called the preparation phase). Because the target storage cell is small in size and has weak driving capability, the electrical signal on the bit line corresponding to the target storage cell changes little with charging and discharging, resulting in a small difference between the two electrical signals output from the reference cell R and the target storage cell. In this scenario, the read / write controller can also activate the sensitive amplifier. Once activated, the sensitive amplifier calculates the differential input signal based on the electrical signals output from the two bit lines, amplifies this differential input signal into a larger output signal, and uses this larger output signal to determine whether the data stored in the memory cell is "0" or "1" (this is called the decision phase). Therefore, the activation time of the sensitive amplifier serves as the dividing line between the preparation and decision phases. Once the sensitive amplifier is activated, it can read the electrical signals from the two bit lines (hereinafter referred to as the reference signal and the storage signal) and execute the subsequent decision process. The earlier the sensitive amplifier is activated, the differential input signal between the target memory cell and the reference cell R may not yet be formed, leading to potentially inaccurate data read by the sensitive amplifier. Conversely, the later the sensitive amplifier is activated, the differential input signal between the target memory cell and the reference cell R may have already been formed, resulting in less timely data reading by the sensitive amplifier. Therefore, the timing of activating the sensitive amplifier is crucial for improving the read / write controller's performance.

[0090] For ease of understanding, the following explanation uses the example of triggering the charging and discharging of the target memory cell with a high level and triggering the sensitive amplifier to turn on with a low level. It should be understood that the scheme of triggering the charging and discharging of the target memory cell with a low level or triggering the sensitive amplifier to turn on with a high level can be implemented by reference, and will not be elaborated upon here.

[0091]

Example 2

[0092] Figure 7 This illustration shows a schematic diagram of another read / write controller provided in an embodiment of this application, such as... Figure 7As shown, in this example, the read / write controller 120 may further include an inverted delay chain 129 consisting of an odd number of inverters connected end-to-end and a sensitive amplifier 126. The input of the inverted delay chain 129 is connected to the clock output B2, and the output of the inverted delay chain 129 is connected to the clock control terminal (C) of the sensitive amplifier 126. 11 ), the first input terminal (C) of the sensitive amplifier 126 12 ) connects to the reference cell R in the storage array 110, and the second input terminal (C) of the sensitive amplifier 126 13 Connect the target memory cell (such as memory cell MN) in the memory array 110, and connect the output terminal (C) of the sensitive amplifier 126. 14 Connect to the reading device 200. In a specific implementation, when the memory is in read mode, the clock generation circuit 121 can output the clock signal Inner through the clock output terminal B2. When the clock signal Inner is at a high level, the high level triggers the target memory cell MN to perform a charging and discharging operation on the corresponding bit line. On the other hand, it is reversed to a low level through the inverse delay chain 129 and then delayed and transmitted to the sensitive amplifier 126 to turn on the sensitive amplifier 126. Thus, after the target memory cell MN starts charging and discharging, the sensitive amplifier 126 starts to acquire the reference signal of the reference cell R and the storage signal of the target memory cell MN after the delay time corresponding to the inverse delay chain 129. Based on these two signals, the data stored in the target memory cell MN is calculated.

[0093] Adopting such Figure 7 In the illustrated readout scheme, the turn-on time of the sensitive amplifier 126 actually depends on the delay duration of the inverse delay chain 129, which in turn depends on the number of inverters contained in the inverse delay chain 129. Generally, the number of inverters in the inverse delay chain 129 is fixed after the read / write controller 120 leaves the factory; therefore, this scheme can only enter the decision stage after a fixed-duration preparation phase. If the turn-on time of the sensitive amplifier 126 is to be adjustable, a third switching component can be connected before each inverter in the inverse delay chain 129, and another line with a fourth switching component can be connected before the third switching component to the clock control terminal C of the sensitive amplifier 126. 11 The required number of inverters are enabled and the others are disabled by controlling the on / off states of each third and fourth switching component, thereby changing the delay duration of the inverse delay chain 129. Although this method requires more additional switching components and inverters, it makes the delay duration of the inverse delay chain 129 adjustable, which helps the read / write controller 120 flexibly adjust the turn-on time of the sensitive amplifier 126.

[0094] Figure 8This illustration shows a schematic diagram of another read / write controller provided in an embodiment of this application, such as... Figure 8 As shown, in this example, the read / write controller 120 may further include a sensitive amplifier 126, and the clock control terminal (C) of the sensitive amplifier 126... 21 ) and the first input terminal (C 22 ) are respectively connected to the reference cell R in the storage array 110, and the second input terminal (C) of the sensitive amplifier 126. 23 Connect the target memory cell (such as memory cell MN) in the memory array 110, and connect the output terminal (C) of the sensitive amplifier 126. 24 Connect to reading device 200. In specific implementation, the reference unit R has a locally preset potential difference threshold. When the memory is in read mode, the clock generation circuit 121 can output a clock signal Inner through the clock output terminal B2. When the clock signal Inner is at a high level, this high level triggers the target memory cell MN to perform a charging and discharging operation on the corresponding bit line. During the charging and discharging process, the reference unit R can also detect the electrical signal on the bit line corresponding to the target memory cell MN. When it is determined that the potential difference between the electrical signal on the bit line corresponding to the target memory cell MN and the electrical signal on the bit line corresponding to the reference unit R reaches the locally preset potential difference threshold, the reference unit R can send a sense amplifier enable (SAE) signal to the clock control terminal of the sense amplifier 126 to turn on the sense amplifier 126. In this way, the sense amplifier 126 can start to acquire the reference signal of the reference unit R and the storage signal of the target memory cell MN when the electrical signal on the bit line corresponding to the target memory cell MN reaches a certain change, and calculate the data stored in the target memory cell MN based on these two signals. The SAE signal can be an electrical signal with an enable function, such as a voltage signal or a current signal. The locally preset potential difference threshold stored in the reference unit R can be set by those skilled in the art based on experience, or it can be determined experimentally; no specific limitation is imposed.

[0095] Adopting such Figure 8In the illustrated readout scheme, the activation timing of the sensitive amplifier 126 is actually determined by a locally preset potential difference threshold stored in the reference cell R. The reference cell R sends an SAE signal when the electrical signal on the bit line of the target memory cell reaches the locally preset potential difference threshold. However, the locally preset potential difference threshold is essentially a preset value that cannot be changed after the memory leaves the factory, resulting in poor adjustability of the activation timing of the sensitive amplifier 126. Under different process deviation scenarios, the sensitive amplifier 126 may need to correspond to different activation times. For example, in scenarios with small process deviations, although the target memory cell has not yet been charged or discharged to the point where the potential difference reaches the locally preset potential difference threshold, the potential difference between the two bit lines of the target memory cell and the reference cell R is sufficient for decision-making. In this case, even if charging and discharging are stopped and the decision-making stage is entered directly, relatively accurate data can be obtained. Obviously, the scheme of using the reference cell R to control the activation of the sensitive amplifier 126 is not suitable for this type of working scenario.

[0096] Figure 9 This illustration shows a schematic diagram of another read / write controller provided in an embodiment of this application, such as... Figure 9 As shown, in this example, the read / write controller 120 may further include a sensitive amplifier 126, and the clock control terminal (C) of the sensitive amplifier 126... 31 Connect the clock output terminal B1 to the first input terminal (C) of the sensitive amplifier 126. 32 ) connects to the reference cell R in the storage array 110, and the second input terminal (C) of the sensitive amplifier 126 33 Connect the target memory cell (such as memory cell MN) in the memory array 110, and connect the output terminal (C) of the sensitive amplifier 126. 34 The read / write controller 120 connects to the reading device 200. In a specific implementation, when the memory is in read mode, the clock generation circuit 121 outputs a clock signal Input to the sensitive amplifier 126 via clock output terminal B1 and a clock signal Inner via clock output terminal B2. When the clock signal Inner is high, this high-level signal can trigger the target memory cell MN to perform a charging / discharging operation on the corresponding bit line. The read / write controller 120 can also activate the sensitive amplifier 126 as needed. For example, when it is necessary to activate the sensitive amplifier 126, the clock generation circuit 121 switches the clock signal Input to a low level. This low-level signal can then be directly applied to the clock control terminal of the sensitive amplifier 126 (triggering the SAE signal) to activate the sensitive amplifier 126. The sensitive amplifier 126 then calculates the data stored in the target memory cell MN based on the acquired reference signal and the stored signal.

[0097] Adopting such Figure 9The illustrated read scheme uses an independent clock signal to provide the operating clock for the sensitive amplifier 126. The turn-on time of the sensitive amplifier 126 can be flexibly adjusted by changing the level switching timing of this independent clock signal. This not only allows the read / write controller 120 to adapt to different read scenarios but also eliminates the need for additional components such as inverters, thereby helping to reduce the cost and circuit complexity of the read / write controller 120. Furthermore, considering that read and write operations of the read / write controller 120 generally do not occur simultaneously, this scheme uses the same operating clock for the sensitive amplifier 126 and the multi-state write circuit 128, instead of allocating separate operating clocks. This approach further reduces the complexity of the circuit structure and lowers circuit costs while independently controlling read and write operations.

[0098] In an alternative implementation, considering that the scheme of using the clock signal Input to pre-activate the sensitive amplifier 126 has a faster read speed, while the scheme of using the reference unit R to activate the sensitive amplifier 126 has better read accuracy, therefore, to balance read speed and read accuracy, the read / write controller 120 can also combine the reference unit R and the clock signal Input to comprehensively activate the sensitive amplifier 126. In this case, the clock control terminal C of the sensitive amplifier 126... 31 Alternatively, a switch can be used to connect the clock output B1 and the reference unit R respectively, with the control terminal of the switch connected to the read / write driver circuit 122. In scenarios where the current circuit environment has good process variation consistency, or where the requirements for reading accuracy are not high, or where the requirements for reading speed are high, the read / write driver circuit 122 can control the switch to connect to the clock control terminal C of the sensitive amplifier 126. 31 Disconnect the clock control terminal C of the sensitive amplifier 126 from the clock output terminal B1. 31 And the reference cell R. Thus, even if the target memory cell has not yet been charged or discharged to the locally preset potential difference threshold stored in the reference cell R, as long as the potential difference between the two bit lines of the target memory cell and the reference cell R is sufficient for decision-making, the sensitive amplifier 126 can be turned on in advance under the control of the clock signal Input to execute the decision in advance, helping the read / write controller 120 to read data as quickly as possible. In scenarios where the current circuit environment has large process deviations, or where high read accuracy or low read speed requirements are present, the read / write drive circuit 122 can control the switch to connect the clock control terminal C of the sensitive amplifier 126. 31 And the reference unit R, disconnect the clock control terminal C of the sensitive amplifier 126. 31And clock output terminal B1. Thus, when the target memory cell is charging and discharging, the reference cell R can acquire the electrical signal on the bit line corresponding to the target memory cell in real time, and calculate the potential difference between the electrical signal and the electrical signal on the bit line corresponding to the reference cell R. When the potential difference between the electrical signals on the two bit lines is greater than the locally preset potential difference threshold stored in the reference cell R, the reference cell R can turn on the sensitive amplifier 126. In this way, the sensitive amplifier 126 can start the decision only when the potential difference between the target memory cell and the reference cell R is large enough, which helps to improve the reading accuracy of the read / write controller 120.

[0099] The following is a specific example. Figure 7 The intended reading scheme and Figure 9 The example demonstrates a comparison of read performance between different read schemes. This example was performed at an ambient temperature of 25°C (°C is a unit of temperature, i.e., degrees Celsius) and a TT process angle.

[0100] Figure 10 An exemplary comparison diagram of a reading scheme provided in an embodiment of this application is shown, such as... Figure 10 As shown, the three lines above correspond to... Figure 7 The illustration shows the readout mode (referred to as readout mode 1) using the reference unit to enable the sensitive amplifier, where the node line (i.e., ...) of these three lines... Figure 10 The “Innner” line shown is the level change line of the clock signal Innner corresponding to reading mode 1. The solid line among these three lines (i.e., Figure 10 The "SAE1" line shown is the SAE signal change line received by the sensitive amplifier in readout mode 1. The dashed line among these three lines (i.e., Figure 10 The "Q1" line shown is the readout data signal change line of the sensitive amplifier in readout mode 1. The three lines below correspond to... Figure 9 The illustration shows the reading mode (referred to as reading mode 2) of the sensitive amplifier by switching the level state, where the node line (i.e., ...) of these three lines... Figure 10 The "Input" line shown is the level change line of the clock signal Input corresponding to reading mode 2. The solid line among these three lines (i.e., Figure 10 The "SAE2" line shown is the line representing the change in the SAE signal received by the sensitive amplifier in readout mode 2. The dashed line among these three lines (i.e.,...) Figure 10 The “Q2” line shown is the readout data signal change line of the sensitive amplifier in readout mode 2.

[0101] Table 2 provides an example of a performance comparison between the two reading schemes described above:

[0102]

[0103]

[0104] Table 2

[0105] Reference Figure 10 As shown in Table 2, in this example, the target memory cell requires at least 92.34 ns to complete charging and discharging. In this case:

[0106] When the reference cell is used to turn on the sensitive amplifier, the target memory cell is as follows: Figure 10 The time Y shown 11 The clock signal Inner was detected to switch to a high level, therefore the target memory cell is as follows: Figure 10 The time Y shown 11 The charging and discharging process begins on the corresponding bit line and ends after 92.34 ns. The reference cell, as shown... Figure 10 The time Y shown 12 Upon detecting that the charge / discharge has reached a threshold voltage difference preset locally by the reference cell, the reference cell can, as... Figure 10 The time Y shown 12 The SAE signal triggers the sensitive amplifier to turn it on. At this point, the preparation phase ends, and the sensitive amplifier enters the decision phase. In this case, because the sensitive amplifier turns on relatively late, the potential difference between the output signals on the two bit lines is large. The sensitive amplifier only needs a short time (e.g., 1.66 ns) to complete the decision. Therefore, the sensitive amplifier can... Figure 10 The time Y shown 13 Reading the data. Based on this, the reading method using the reference unit to turn on the sensitive amplifier requires a total of 94ns to read the data.

[0107] When the sensitive amplifier is activated by switching the level state, the target memory cell is in such a state as Figure 10 The time Y shown 21 The clock signal Inner was detected to switch to a high level, therefore the target memory cell is as follows: Figure 10 The time Y shown 21 The system begins charging and discharging the corresponding bit line, ending after 92.34 ns. When the read / write controller determines that the current circuit environment's process deviations allow a potential difference to be formed within a 39.9 ns charging / discharging time interval, it can... Figure 10 The time Y shown 22The clock signal Input is switched low by a clock generation circuit to trigger the sensitive amplifier to turn on in advance. At this point, the preparation phase ends, and the sensitive amplifier enters the decision phase. In this case, because the sensitive amplifier turns on early, the potential difference between the output signals on the two bit lines is small, so the sensitive amplifier may need a longer time (e.g., 9.1 ns) to determine the reading. Therefore, the sensitive amplifier can... Figure 10 The time Y shown 33 Data can be read out. Based on this, the data reading method, which activates the sensitive amplifier by switching the level state, can be completed in just 49ns.

[0108] As described above, the reading method of activating the sensitive amplifier by switching the level state allows for earlier activation of the sensitive amplifier. Although this method increases the decision time of the sensitive amplifier, it optimizes the overall readout time by 47.8% compared to the reading method using the reference unit with the sensitive amplifier activated, and optimizes the preparation phase by 56.8%. The specific time for activating the sensitive amplifier earlier can be set by those skilled in the art based on experience, or it can be calculated experimentally. For example, by determining a time with a high probability of no error through multiple experiments, this time can be used as the accurate duration of the sensitive amplifier's activation phase. This can reduce the probability of reading errors caused by rapid readings in certain extreme cases.

[0109] The following is combined with Figure 9 The illustrated read / write controller is used to illustrate the specific implementation process of the read / write scheme in this application through a concrete timing control flow:

[0110] Figure 11 An exemplary embodiment of this application provides a read / write control timing diagram, such as... Figure 11As shown, the read / write control timing involves the following control signals: Input clock signal Input, Input clock signal Inner, Write enable signal WEN, Read enable signal REN, Input / output signal DATA, Word line signal WL, Sensitive amplifier enable signal SAE, and Read data signal Q. The Input / output signal DATA refers to the signals received by the read / write controller from external devices, such as write request signals and read request signals sent by external devices to the read / write controller. The Write enable signal WEN and the Read enable signal REN enable the read / write controller in write mode and read mode, respectively. When the Write enable signal WEN is triggered (e.g., low-level trigger), the read / write controller switches to write mode; when the Read enable signal REN is triggered (e.g., low-level trigger), the read / write controller switches to read mode. The Read data signal Q is the signal sent by the read / write controller to the external device to read data. The word line signal WL runs throughout the entire read / write logic of the read / write controller. It not only opens the target memory cell according to the row decoder circuit, allowing the read / write drive circuit to perform read / write operations on the target memory cell according to the column decoder circuit, but also writes the data to be written to the target memory cell during write operations and triggers the charging and discharging of the target memory cell according to the data stored in the target memory cell during read operations. The sensitive amplifier enable signal SAE is used to turn on the sensitive amplifier. When the sensitive amplifier enable signal SAE is triggered (e.g., high-level trigger), the sensitive amplifier acquires the electrical signals output from the two bit lines and initiates a decision. Among these control signals, the write enable signal WEN, the read state of the word line signal WL, the read enable signal REN, the input / output signal DATA, and the read data signal Q can be triggered by the input clock signal Inner, while the write state of the word line signal WL and the sensitive amplifier enable signal SAE can be triggered by the input clock signal Input.

[0111] In the specific implementation of the write operation, the input clock signal Input, the input clock signal Inner, the write enable signal WEN, the input / output signal DATA, and the word line signal WL can work together to complete the write operation. For details, please refer to... Figure 11 As shown, when an external device needs to write two data items to the memory consecutively, the external device can send a write request to the read / write controller at time h1. This write request is a type of input / output signal DATA. This write request triggers the write enable signal WEN at time h2 (if signal transmission delay is ignored, then h2 is the same as h1; if signal transmission delay is considered, then h2 is later than h1), causing the read / write controller to switch to write mode. When in write mode, at a certain level of the clock signal Inner (e.g., ... Figure 11 As shown in the diagram, from time x1 to x2, the read / write drive circuit has a fixed level. The word line circuit triggers the word line signal WL to different levels based on the level changes of the input clock signal Input. For example, when the input clock signal Input switches to a high level at time h3, the word line circuit will trigger the word line signal WL to a high level at time h4 (if signal transmission delay is not considered, then time h4 is the same as time h3; if signal transmission delay is considered, then time h4 is later than time h3) based on this high level. In this way, the read / write drive circuit gradually writes the first state (such as "0") into the memory array based on the voltage difference between the level of the read / write drive circuit and the high level of the word line signal WL, until the input clock signal Input switches to a low level. When the input clock signal Input switches to a low level at time h5, the word line circuit, based on this low level, will trigger the word line signal WL to a low level at time h6 (if signal transmission delay is not considered, then time h6 is the same as time h5; if signal transmission delay is considered, then time h6 is later than time h5). Thus, the read / write drive circuit, based on the voltage difference between the level of the read / write drive circuit and the low level of the word line signal WL, ends the writing of the first state and starts writing of the second state (such as "1"). During the writing process, the read / write controller can also adjust time h5 within time period t1 through the clock generation circuit to change the arrival time of time h6. For example, if a large process bias causes the memory to require a long time to write the first state, the read / write controller can adjust time h5 to a later time value within time period t1 through the clock generation circuit. In this way, time h6 will also arrive later, allowing the word line signal WL to switch to a low level a considerable time after switching to a high level, thus reserving more time for the memory to write the first state. For example, when the process bias is low, allowing the memory to write to the first state in a very short time, the read / write controller can adjust time h5 to an earlier value in time period t1 via the clock generation circuit. This ensures that time h6 also arrives earlier, allowing the word line signal WL to switch low very quickly after reaching a high level, enabling the memory to rapidly begin writing to the second state. After the second state is written, the word line signal WL can return to its sleep level at time h7, ending the write operation. Correspondingly, the write enable signal WEN switches low at time h8, causing the read / write controller to exit write mode. At this point, the read / write controller has completed the write operation.

[0112] In the specific implementation of the read operation, the input clock signal Input, the input clock signal Inner, the read enable signal REN, the input / output signal DATA, the word line signal WL, the sensitive amplifier enable signal SAE, and the read data signal Q can work together to complete the read operation. Specifically, refer to... Figure 11 As shown, when an external device needs to read data from the memory, it can send a read request to the read / write controller at time m1. This read request is a type of input / output signal DATA. At time m2 (if signal transmission delay is not considered, then time m2 is the same as time m1; if signal transmission delay is considered, then time m2 is later than time m1), the read enable signal REN is triggered, causing the read / write controller to switch to read mode. In read mode, the read / write controller initiates a discharge operation based on the level changes of the input clock signal Inner. For example, when the input clock signal Inner switches to a high level at time y1, the word line circuit, based on this high level, will trigger the word line signal WL to switch to a low level at time m4 (if signal transmission delay is not considered, then time m4 is the same as time y1; if signal transmission delay is considered, then time m4 is later than time y1). This low level can be the same as or different from the low level in write mode, without limitation, to charge and discharge the bit line corresponding to the target memory cell. This continues until the input clock signal Inner switches to a low level at time y2, triggering the word line signal WL to switch to a sleep level, or until the target memory cell's charging and discharging is complete. During the charging and discharging process, because the input clock signal Input is at a high level between times m3 and m5, the sensitive amplifier is not triggered to turn on. Until the input clock signal Input switches to a low level at time m5, this low level will trigger the sensitive amplifier enable signal SAE to switch to a high level at time m6 (if signal transmission delay is not considered, then time m6 is the same as time m5; if signal transmission delay is considered, then time m6 is later than time m5) to turn on the sensitive amplifier. At this time, the sensitive amplifier reads the electrical signal output on the bit line corresponding to the target memory cell and the electrical signal output on the bit line corresponding to the reference cell, and determines the data stored in the target memory cell based on these two electrical signals. During the discharge process, the read / write controller can also adjust time m5 within time period t2 through the clock generation circuit to change the arrival time of time m6. For example, if it is determined that the current circuit environment is good and the current turn-on time is late, the read / write controller can trigger the falling edge of the input clock signal Input in advance through the clock generation circuit, that is, control the arrival of time m5 in advance. In this way, time m6 can also arrive in advance, so that the sensitive amplifier can turn on earlier and enter the decision stage earlier, thereby shortening the readout time. After the decision is made, the read / write controller can send the read data to the external device at time m7 via the read data signal Q. At this point, the read / write controller has completed the read operation.

[0113] As described above, by setting separate operating clocks for the multi-state write circuit and the sensitive amplifier, the read / write controller can advance or delay the writing of another state or the read decision by switching the level of this separate operating clock. This allows for a wide adjustable range of write and read times. Even under severe process variations, this type of read / write controller can adjust the write and read times to meet the requirements of these variations, balancing read / write accuracy and efficiency, and effectively improving the read / write performance of the controller.

[0114] The following continues based on Example 2. Figure 9 The schematic read / write controller 120 is illustrated, and the possible structure of the clock generation circuit 121 is further described in Embodiment 3. It should be noted that Embodiment 3 is only based on... Figure 9 The following description uses the illustrated read / write controller 120 as an example. The various solutions in Embodiment 3 are also applicable to any read / write controller in Embodiment 1 or Embodiment 2, such as... Figure 3 , Figure 4 , Figure 7 or Figure 7 The read / write controller 120 shown is not described in detail in this application.

[0115]

Example 3

[0116] In this embodiment, the clock generation circuit 121 capable of generating clock signals Input and Inner can have several possibilities. Three possible implementations are illustrated below:

[0117] Implementation Method 1

[0118] Figure 12 This illustration shows a schematic diagram of another read / write controller provided in an embodiment of this application, such as... Figure 12 As shown, in this example, the clock generation circuit 121 may further include a first clock generator 1211 and a frequency divider 1212. The output of the first clock generator 1211 is connected to the clock output terminal B1 and the input of the frequency divider 1212, respectively. The output of the frequency divider 1212 is connected to the clock output terminal B2. In this case, the first clock generator 1211 can generate a clock signal Input and provide it to the clock output terminal B1 and the frequency divider 1212, respectively. Thus, the clock signal Input can be output to the multi-state write circuit 128 and the sensitive amplifier 126 through the clock output terminal B1, and can also be divided into a lower frequency clock signal Inner by the frequency divider 1212 and provided to the clock output terminal B2, so that the lower frequency clock signal Inner can be output to one or more other circuits besides the multi-state write circuit 128 and the sensitive amplifier 126 through the clock output terminal B2. Figure 12 The clock generation circuit 121 and read / write drive circuit 122, as illustrated, can send a first indication message to the first clock generator 1211 when they need to switch the level of the clock signal Input in advance. Upon receiving the first indication message, the first clock generator 1211 can switch the level in advance according to the indication message. The first indication message may also specify how much in advance the switch should be. Alternatively, when the read / write drive circuit 122 needs to delay the switch of the clock signal Input, it can send a second indication message to the first clock generator 1211. Upon receiving the second indication message, the first clock generator 1211 can delay the switch according to the indication message. The second indication message may also specify how much the switch should be delayed.

[0119] In this embodiment, the frequency divider 1212 can be any device capable of frequency reduction, such as... Figure 12 The diagram shows a D flip-flop. In this case, assuming that writing a state takes 20ns under certain process variations, and the delay of an inverter is 100-200ps, then according to... Figure 4 The illustrated scheme of implementing multi-state writing via an inverting delay chain 1281 requires at least 100-200 inverters to achieve a 20ns delay. According to... Figure 12 The illustrated scheme for multi-state writing via switching level states demonstrates that when the frequency divider is a D flip-flop, only 4-7 inverters and 2-4 transmission gates are needed internally to achieve frequency division. Clearly, Figure 12 The intended read / write controller can have fewer circuit components, which helps save space in the read / write controller.

[0120] For example, the frequency divider 1212 can also divide the clock signal Input into multiple clock signals of different frequencies, and provide them to various circuits other than the multi-state write circuit 128 and the sensitive amplifier 126. In this way, each of the other circuits can correspond to a different operating clock, which helps to individually adjust other operations in the memory and further improves the flexibility of the read / write controller.

[0121] Implementation Method 2

[0122] Figure 13 This illustration shows a schematic diagram of another read / write controller provided in an embodiment of this application, such as... Figure 13As shown, in this example, the clock generation circuit 121 may further include a second clock generator 1213 and a frequency multiplier 1214. The output of the second clock generator 1213 is connected to the clock output terminal B2 and the input of the frequency multiplier 1214, respectively. The output of the frequency multiplier 1214 is connected to the clock output terminal B1. In this case, the second clock generator 1213 can generate a clock signal Inner and provide it to the clock output terminal B2 and the frequency multiplier 1214, respectively. This clock signal Inner can be output through the clock output terminal B2 to one or more other circuits besides the multi-state write circuit 128 and the sensitive amplifier 126. Alternatively, it can be multiplied by the frequency multiplier 1214 to a higher frequency clock signal Input and then provided to the clock output terminal B1, so that the higher frequency clock signal Input can be output to the multi-state write circuit 128 and the sensitive amplifier 126 through the clock output terminal B1. The frequency multiplier 1214 can be any device capable of frequency upscaling, such as a phase-locked loop. Figure 13 The clock generation circuit 121 and read / write drive circuit 122, as shown in the diagram, can send a third indication message to the frequency multiplier 1214 when the clock signal Input needs to be switched ahead of time. Upon receiving the third indication message, the frequency multiplier 1214 can switch the level ahead of time according to the instruction in the third indication message. The third indication message can also specify how far in advance the switch should be made. Alternatively, when the read / write drive circuit 122 needs to delay the switch of the clock signal Input, it can send a fourth indication message to the frequency multiplier 1214. Upon receiving the fourth indication message, the frequency multiplier 1214 can delay the switch of the level according to the instruction in the fourth indication message. The fourth indication message can also specify how far in advance the switch should be made.

[0123] For example, the frequency multiplier 1214 can also divide the clock signal Inner into two clock signals of different frequencies, and provide them to the multi-state write circuit 128 and the sensitive amplifier 126 respectively. In this way, the multi-state write circuit 128 and the sensitive amplifier 126 can also correspond to different operating clocks, which helps to adjust the read and write operations in the memory individually and further improves the flexibility of the read and write controller 120.

[0124] Implementation Method 3

[0125] Figure 14 This illustration shows a schematic diagram of another read / write controller provided in an embodiment of this application, such as... Figure 14As shown, in this example, the clock generation circuit 121 may further include a third clock generator 1215 and a fourth clock generator 1216. The output of the third clock generator 1215 is connected to the clock output terminal B1, and the output of the fourth clock generator 1216 is connected to the clock output terminal B2. In this case, the third clock generator 1215 can generate a clock signal Input and provide it to the clock output terminal B1, so that the clock signal Input can be output to the multi-state write circuit 128 and the sensitive amplifier 126 through the clock output terminal B1. The fourth clock generator 1216 can generate a clock signal Inner and provide it to the clock output terminal B2, so that the clock signal Inner can be output to one or more other circuits besides the multi-state write circuit 128 and the sensitive amplifier 126 through the clock output terminal B2. Figure 14 The clock generation circuit 121 and read / write drive circuit 122, as shown in the diagram, can send a fifth indication message to the third clock generator 1215 when they need to switch the level of the clock signal Input in advance. Upon receiving the fifth indication message, the third clock generator 1215 can switch the level in advance according to the instruction in the fifth indication message. The fifth indication message can also specify how much in advance the switch should be. Alternatively, when the read / write drive circuit 122 needs to delay the switch of the clock signal Input level, it can send a sixth indication message to the third clock generator 1215. Upon receiving the sixth indication message, the third clock generator 1215 can delay the switch according to the instruction in the sixth indication message. The sixth indication message can also specify how much the switch should be delayed.

[0126] It should be noted that the above embodiment three is merely an exemplary illustration of three possible structures for a clock generation circuit. It should be understood that this application does not limit the clock generation circuit to only these few structures; any clock generation circuit capable of generating two clock signals with different frequencies falls within the scope of protection of this application, and will not be elaborated upon further in this application.

[0127] It should be understood that the above embodiments of this application can be combined with each other to obtain new embodiments, which will not be described in detail here.

[0128] It should be understood that each component in the above embodiments of this application refers to a functional device, and this application does not limit the specific implementation of these functional components. For example, the MOS transistor described above can also be replaced with other devices that can be controlled to switch on and off via level switching, such as a transistor.

[0129] Based on the above embodiments, this application also provides a memory, including any of the above-described read / write controllers and a storage array. The read / write controller can be connected to the storage array and used to read and write data in the storage array according to the scheme described in the above embodiments.

[0130] Based on the above embodiments, this application also provides an electronic device, which includes the above-described memory and a PCB, with the memory disposed on the surface of the PCB.

[0131] For example, the electronic device includes, but is not limited to: smartphones, smartwatches, tablets, VR devices, AR devices, in-vehicle devices, desktop computers, personal computers, handheld computers, or personal digital assistants.

[0132] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0133] The terms “component,” “module,” “system,” etc., used in this specification are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0134] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0135] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0136] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0137] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0138] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0139] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0140] Although some possible embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the embodiments of this application as well as all changes and modifications falling within the scope of this application.

[0141] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A read / write controller, characterized in that, It includes a clock generation circuit, a multi-state write circuit, a row decoding circuit, and a column decoding circuit; the clock generation circuit includes a first clock output terminal and a second clock output terminal, wherein the clock frequency of the first clock signal output by the first clock output terminal is higher than the clock frequency of the second clock signal output by the second clock output terminal. The first clock output terminal is connected to the input terminal of the multi-state write circuit, and the output terminal of the multi-state write circuit is connected to the memory array; The multi-state write circuit is used to write at least two states to the memory array within one clock cycle according to the first clock signal; The second clock output terminal is connected to the input terminal of the row decoding circuit and the input terminal of the column decoding circuit, respectively, and the output terminal of the row decoding circuit and the output terminal of the column decoding circuit are connected to the memory array, respectively. The second clock signal is used to provide a working clock for the row decoding circuit and the column decoding circuit.

2. The read / write controller as described in claim 1, characterized in that, The read / write controller further includes a sensitive amplifier, the clock control terminal of which is connected to the first clock output terminal, the first input terminal of which is connected to a reference cell in the storage array, the second input terminal of which is connected to at least one storage cell in the storage array, and the output terminal of which is connected to a read device.

3. The read / write controller as described in claim 2, characterized in that, When the storage array is in read mode, within one cycle of the first clock signal: If the first clock signal switches from the second level to the first level, the sensitive amplifier acquires the reference signal in the reference unit and the stored signal in the at least one storage unit.

4. The read / write controller as described in any one of claims 1 to 3, characterized in that, The clock generation circuit further includes a first clock generator and a frequency divider; the output terminal of the first clock generator is connected to the first clock output terminal and the input terminal of the frequency divider, respectively, and the output terminal of the frequency divider is connected to the second clock output terminal.

5. The read / write controller as described in any one of claims 1 to 3, characterized in that, The clock generation circuit further includes a second clock generator and a frequency multiplier; the output terminal of the second clock generator is connected to the second clock output terminal and the input terminal of the frequency multiplier, respectively, and the output terminal of the frequency multiplier is connected to the first clock output terminal.

6. The read / write controller as described in any one of claims 1 to 3, characterized in that, The clock generation circuit further includes a third clock generator and a fourth clock generator. The output of the third clock generator is connected to the first clock output, and the output of the fourth clock generator is connected to the second clock output.

7. The read / write controller as described in any one of claims 1 to 3, characterized in that, The multi-state write circuit includes an inverter, a first MOS transistor, and a second MOS transistor. The input terminal of the inverter and the gate of the second MOS transistor are respectively connected to the input terminal of the multi-state write circuit. The output terminal of the inverter is connected to the gate of the first MOS transistor. The source of the first MOS transistor is connected to a first power supply, the source of the second MOS transistor is connected to a second power supply, and the drains of the first MOS transistor and the drains of the second MOS transistor are connected to the memory array.

8. The read / write controller as described in claim 7, characterized in that, When the storage array is in write mode, within one cycle of the first clock signal: When the first clock signal switches from the first level to the second level, the multi-state write circuit writes the first state to the memory array; When the first clock signal switches from the second level to the first level, the multi-state write circuit writes the second state to the memory array.

9. A memory, characterized in that, Includes a storage array and a read / write controller as described in any one of claims 1 to 8, wherein the read / write controller is connected to the storage array; The storage array is used to store data; The read / write controller is used to write data to the storage array or read data from the storage array.

10. An electronic device, characterized in that, It includes a printed circuit board (PCB) and the memory as described in claim 9, wherein the memory is disposed on the surface of the PCB.

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