Information representation method based on chip thermal distribution expansion and contraction rate

Abstract

The application discloses a kind of information representation methods based on chip thermal distribution expansion shrinkage rate, information representation method based on hot spot change rate is by dividing FPGA chip space area, and then the position of coding "hot spot" and change rate are realized information representation, to express specific information.The information representation method of thermal distribution expansion / shrinkage rate proposed in the application defines the "acceleration" of thermal image expansion shrinkage, i.e., thermal distribution change, and realizes a more covert information representation.The application uses FPGA as the carrier of the mounted circuit, and based on the circuit structure of the hot spot change information representation, designs the supporting circuit to realize the information representation method of thermal distribution expansion / shrinkage rate proposed in the application, so the information representation method based on the method proposed in the application is more secure for information expression.

Description

Technical Field

[0001] This invention relates to a chip thermal distribution change monitoring technology, and more particularly to a method for representing information based on the chip thermal distribution expansion and contraction rate. Background Technology

[0002] Research on representing temperature information generated by circuit thermal effects originates from information transmission using circuit thermal effects.

[0003] Existing technology constructs a BitWhisper air gap covert channel between two spatially adjacent but network-isolated computers using thermal signals. It utilizes the heat emissions of the machines to control the temperature of the surrounding environment, thereby representing different covert information based on temperature differences, providing theoretical guidance for the representation of thermal effect information.

[0004] Information representation methods based on FPGA single hotspot and multi-hotspot distribution are achieved by dividing the FPGA chip space into regions and constraining the circuit layout to create temperature differences between different parts of the circuit during operation, thereby utilizing the location of "hotspots" to represent information.

[0005] The information representation method based on FPGA hotspot changes represents information by combining multiple FPGA-based hotspot distributions, but it still focuses on the changes in hotspot distributions without considering the rate of change. Summary of the Invention

[0006] The purpose of this invention is to provide a method for representing information based on the thermal distribution expansion and contraction rate of a chip.

[0007] To achieve the above objectives, the present invention is implemented according to the following technical solution:

[0008] This invention includes the following steps:

[0009] S1: Divide the chip into 3*3 regions according to its physical location;

[0010] S2: Based on the divided areas, a thermal circuit capable of high-frequency switching is arranged in each target physical area, and the thermal circuit is controlled by an enable signal.

[0011] S3: Based on the changes in the thermal circuit, the chip state is encoded and recorded at time intervals of expansion and contraction.

[0012] S4: Observe the changes in heat distribution using a thermal imager, record the time interval between the expansion and contraction of the heat distribution using an additional timer, and subtract the time interval from the previous expansion and contraction to represent the information of the heat distribution expansion / contraction rate.

[0013] S5: Based on the mapping relationship of the custom encoding and decoding, the thermal distribution expansion / contraction rate information is read out as the corresponding expression information.

[0014] Specifically, step S3 involves taking the thermal distribution "expansion and contraction" action as a benchmark, obtaining the encoding relationship between the time interval of thermal distribution "expansion and contraction" and the hot spot change rate as reciprocals, and using the difference between two adjacent "expansion and contraction" time intervals as the final information mapping, namely the thermal distribution expansion / contraction rate.

[0015] The thermal distribution expansion / contraction rate is specifically defined as follows: the expansion begins when only the central "hot spot" is lit up and the contraction ends when all nine points are lit up, and the expansion ends when all nine points are lit up and the contraction begins. The expansion and contraction cycle is defined as the cycle from the center point to the nine points and back to the center point.

[0016] By custom-encoding the expansion / contraction rate of the circuit's thermal distribution, different information is represented by the difference in the rate of change of the thermal distribution, thus representing the information of the thermal expansion / contraction rate. Based on this, the circuit structure that represents the thermal distribution information serves as the basic heating unit, and a corresponding thermal control unit is designed so that the hot spots of the circuit can change according to a preset rate. The expansion / contraction rate of the thermal image is then observed through a thermal imager, and the corresponding information is decoded.

[0017] The beneficial effects of this invention are:

[0018] This invention is an information representation method based on the thermal expansion and contraction rate of a chip. Compared with the prior art, this invention focuses on the location of the thermal distribution in information representation. The information representation method based on the thermal expansion / contraction rate of FPGA performs deep encoding and combination of the time of thermal distribution changes when representing information, which is more difficult to crack. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the hotspot distribution layout of the present invention;

[0020] Figure 2 This is a circuit architecture diagram of the information representation of the present invention;

[0021] Figure 3 This is a schematic diagram of the control logic state transition principle of the present invention. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. The illustrative embodiments and descriptions herein are used to explain the present invention, but are not intended to limit the present invention.

[0023] This invention is based on a 3×3 layout for representing 8-bit information. To represent changes in thermal distribution, the FPGA device is first divided into regions according to its physical location, as shown in the spatial layout diagram above. Figure 1 As shown.

[0024] Taking FPGA chips as an example, according to the divided areas, thermal circuits capable of high-frequency switching are arranged in each target physical area. For example, the DSP resources of the FPGA implement multiplication and addition operations and continuously input data to generate heat for circuit calculation. The thermal circuit is controlled by an enable signal, that is, under the action of the enable control signal, the enabled area generates a temperature difference with other areas when working.

[0025] Based on this, the present invention proposes an encoding and decoding scheme for the thermal distribution expansion / contraction rate. Taking the thermal distribution's "expansion and contraction" action as a benchmark, it obtains an encoding relationship where the time interval of the thermal distribution's "expansion and contraction" is the reciprocal of the hotspot change rate. The difference between two adjacent "expansion and contraction" time intervals is used as the final information mapping, i.e., the thermal distribution expansion / contraction rate. This invention uses the "expansion and contraction" time interval for encoding and recording.

[0026] Based on the above coding scheme for thermal expansion / contraction rate, the start of expansion and the end of contraction are defined as only the central "hot spot" being lit, and the end of expansion and the start of contraction are defined as all nine points being lit. A single "expansion and contraction" occurs between the center point and the nine points and back to the center point. To implement this coding, the following was designed: Figure 2 The circuit architecture shown allows the control unit to control the effective time and sequence of enabling each "hot spot" circuit, and the control logic of the control unit is designed so that the thermal distribution of the FPGA can "expand and contract" according to the expressed information.

[0027] The thermal imager is used to observe changes in heat distribution. An additional timer records the time interval between the expansion and contraction of the heat distribution and calculates the difference between the time interval and the previous time interval. This difference is used to represent the information on the expansion / contraction rate of the heat distribution.

[0028] Finally, based on the mapping relationship of the custom encoding and decoding, the thermal distribution expansion / contraction rate information is read out as the corresponding expression information.

[0029] Example

[0030] This invention is based on a Xilinx XC7A100T FPGA and uses a DSP to implement multiply-accumulate operations as a "hotspot" unit to illustrate the specific implementation process of this method.

[0031] exist Figure 1Based on the physical layout, to ensure sufficient power consumption of the DSP circuit and good resolution of the generated thermal distribution map, each hot cell undergoes a 16-bit input one-dimensional discrete convolution operation with four input polynomial terms, resulting in seven 32-bit outputs. After assigning and encoding the hot cells, the control unit reads the mapping information (expressed information) stored in RAM according to the address sequence, and converts this information into corresponding spatial distribution and time interval information through a decoding unit. The control unit then uses a timer to control the lighting of the hot cells and the lighting time.

[0032] The circuit information is converted into a bit stream file using a synthesis tool, configured into the FPGA, and then the temperature of the FPGA chip is detected by a thermal imager. The thermal distribution map is observed, and the content of the information is determined based on the thermal expansion / contraction rate.

[0033] For example, if the data in RAM is sequentially 1, 2, 3, the control unit first reads the data "1", decodes it, and controls the lighting sequence of the various hot spots. This ensures that the time interval between the center lighting up and the nine o'clock position lighting up is 0.5 seconds, and the time interval between the nine o'clock position lighting up and the center lighting up is also 0.5 seconds. The total duration for the first expansion and contraction is 1 second. Similarly, the total duration for the second expansion and contraction is 3 seconds, and the total duration for the third expansion and contraction is 6 seconds. The difference between the durations of each expansion and contraction is used to obtain the final multi-bit data representation (the control logic state transition principle is as follows). Figure 3 (As shown).

[0034] The technical solutions of the present invention are not limited to the specific embodiments described above. Any technical modifications made in accordance with the technical solutions of the present invention fall within the protection scope of the present invention.

Claims

1. A method for representing information based on the thermal expansion and contraction rate of a chip, characterized in that, Includes the following steps: S1: Divide the chip into 3*3 regions according to its physical location; S2: Based on the divided areas, a thermal circuit capable of high-frequency switching is arranged in each target physical area, and the thermal circuit is controlled by an enable signal. S3: Based on the changes in the thermal circuit, the chip state is encoded and recorded at time intervals of expansion and contraction. S4: Observe the changes in heat distribution using a thermal imager, record the time interval between the expansion and contraction of the heat distribution using an additional timer, and calculate the difference between the time interval and the previous expansion and contraction time interval to represent the information of the heat distribution expansion and contraction rate. S5: Based on the mapping relationship of the custom encoding and decoding, the thermal distribution expansion and contraction rate information is read out as the corresponding expression information; Specifically, step S3 involves taking the thermal distribution "expansion and contraction" action as a benchmark, obtaining the encoding relationship between the time interval of thermal distribution "expansion and contraction" and the hot spot change rate as reciprocals, and using the difference between two adjacent "expansion and contraction" time intervals as the final information mapping, namely the thermal distribution expansion and contraction rate.

2. The method for representing information based on the thermal expansion and contraction rate of a chip according to claim 1, characterized in that: The thermal distribution expansion and contraction rate is specifically defined as follows: the expansion begins when only the central "hot spot" is lit and the contraction ends when all nine points are lit, and the expansion ends when all nine points are lit and the contraction begins. The expansion and contraction cycle is defined as the cycle from the center point to the nine points and back to the center point.

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