Wafer notch positioning methods, devices, electronic equipment and storage media

Abstract

This application discloses a wafer notch location method, apparatus, electronic device, and storage medium, belonging to the field of wafer inspection technology. The wafer notch location method includes: acquiring a linear array image of the wafer's edge; determining the notch edge points in the linear array image; and determining the notch position based on the notch edge points. This method determines the wafer notch position by searching the linear array image, replacing the method of using linear sensors to locate the notch. Furthermore, it can use the linear array image to determine the relative position of the notch on the wafer, thus integrating the notch location step with the wafer ID recognition step, reducing the testing process and significantly improving testing efficiency.

Description

Technical Field

[0001] This application belongs to the field of wafer inspection technology, specifically relating to a wafer notch positioning method, apparatus, electronic device, and storage medium. Background Technology

[0002] One step in the wafer fabrication process involves cutting a notch in the silicon wafer ingot. If it's a flat notch, it's called a flat notch. To reduce wafer waste, usually only a small circular notch is cut, called a notch. In subsequent wafer fabrication processes, the notch is used to determine the wafer's placement, facilitating subsequent dicing and testing.

[0003] In wafer testing, there is a pre-alignment step before wafer loading. This step corrects the wafer position and identifies the wafer ID. Therefore, this step requires locating and identifying the wafer notch. The conventional notch location method uses a linear sensor, which has the advantage of relatively high accuracy. However, linear sensors cannot be used for wafer ID identification. Summary of the Invention

[0004] The purpose of this application is to provide a wafer notch location method, apparatus, electronic device, and storage medium to identify the wafer ID while locating the notch position.

[0005] According to a first aspect of the embodiments of this application, a wafer notch positioning method is provided, the method comprising:

[0006] Acquire linear array images of the wafer edges;

[0007] Identify the notch edge points of the wafer in the edge linear array image;

[0008] The location of the notch on the wafer is determined by the edge of the notch.

[0009] In some optional embodiments of this application, determining the notch edge points of the wafer in the edge linear array image may include:

[0010] Search for the edge points of the wafer by moving row by row along the first direction and getting closer to the wafer;

[0011] Determine the edge points of the gap based on the edge points.

[0012] In some optional embodiments of this application, searching for the edge points of the wafer row by row and closer to the wafer along the first direction may include:

[0013] In the edge linear array image, pixels are retrieved row by row along the first direction and moved closer to the wafer, and pixels with pixel values ​​less than the target threshold are identified as edge points.

[0014] In some optional embodiments of this application, determining the notch edge point based on the edge point may include:

[0015] Starting from the edge point, retrieve pixels along the second direction and update pixels with pixel values ​​less than the target threshold as edge points;

[0016] The search continues until no pixel with a value less than the target threshold is found within a first preset distance from the edge point along the second direction;

[0017] The edge point is defined as the first gap edge point, wherein the first direction is perpendicular to the second direction.

[0018] In some optional embodiments of this application, determining the notch edge point based on the edge point may further include:

[0019] Starting from the first gap edge point, the first pixel point whose pixel value is less than the target threshold is determined as the second gap edge point along the second direction;

[0020] Starting from the midpoint between the first and second gap edge points, the first pixel point whose pixel value is less than the target threshold is determined as the third gap edge point.

[0021] In some optional embodiments of this application, determining the notch location of the wafer based on the notch edge point may include:

[0022] Calculate the distance between the edge point of the third gap and the edge point of the first gap in the first direction;

[0023] The coordinates of the third edge point, which is at a distance greater than the second preset distance, are determined as the suspected notch location on the wafer;

[0024] The notch location on the wafer is determined based on the suspected notch location.

[0025] In some optional embodiments of this application, determining the notch location of the wafer based on the suspected notch location may further include:

[0026] In the edge linear array image, a preset range of suspected gap images is cropped with the suspected gap location as the center;

[0027] Determine whether the edge curve of the suspected gap in the suspected gap image satisfies continuity;

[0028] Suspected gaps that satisfy the continuity of edge curves are identified as target gaps on the wafer.

[0029] In some optional embodiments of this application, after cropping a pre-defined range of the suspected notch image centered on the suspected notch location in the edge linear array image, the wafer notch localization method may further include:

[0030] The suspected gap image is denoised, binarized, and the gap is eliminated.

[0031] In some optional embodiments of this application, determining whether the edge curve of the suspected gap in the suspected gap image satisfies continuity may include:

[0032] Determine whether the distance between two adjacent pixels of the edge curve in the first or second direction is less than a third preset distance;

[0033] If so, then the edge curve is determined to be continuous.

[0034] In some optional embodiments of this application, after identifying a suspected notch whose edge curve satisfies continuity as the target notch of the wafer, the wafer notch location method may further include:

[0035] The coordinates of the target notch closest to the center of the edge linear array image are determined as the notch location on the wafer.

[0036] In some optional embodiments of this application, acquiring a linear array image of the wafer's edge includes:

[0037] A pre-aligned wafer edge image is acquired using a linear array camera;

[0038] The edge image of the pre-aligned wafer is denoised to obtain an edge linear array image.

[0039] According to a second aspect of the embodiments of this application, a wafer notch positioning device is provided, the device comprising:

[0040] Linear scan camera, used to acquire linear scan images of the wafer's edge;

[0041] Edge point determination module, used to determine the notch edge points of the wafer in the edge linear array image;

[0042] The first notch location determination module is used to determine the notch location of the wafer based on the notch edge points.

[0043] In some optional embodiments of this application, the edge point determination module may include:

[0044] The first direction edge point determination unit is used to find the edge points of the wafer row by row and move closer to the wafer along the first direction;

[0045] The first edge point determination unit is used to determine the edge point of the gap based on the edge point.

[0046] In some optional embodiments of this application, the first direction edge point determination unit is specifically used to retrieve pixel points in the edge linear array image row by row along the first direction and closer to the wafer, and determine the pixel points with pixel values ​​less than the target threshold as edge points.

[0047] In some optional embodiments of this application, the first edge point determination unit may include:

[0048] The edge point update subunit is used to retrieve pixel points along the second direction starting from the edge point and update the pixel points with pixel values ​​less than the target threshold as edge points.

[0049] The stop judgment subunit is used to stop the search until there are no pixels with a value less than the target threshold within a range of a first preset distance from the edge point along the second direction;

[0050] The first gap edge point determination sub-unit is used to determine the edge point as the first gap edge point, wherein the first direction is perpendicular to the second direction.

[0051] In some optional embodiments of this application, the first edge point determination unit may further include:

[0052] The second gap edge point determination subunit is used to determine the first pixel point whose pixel value is less than the target threshold and retrieved along the second direction as the second gap edge point, starting from the first gap edge point.

[0053] The third gap edge point determination subunit is used to determine the first pixel point whose pixel value is less than the target threshold, which is retrieved along the first direction, as the third gap edge point, starting from the midpoint between the first gap edge point and the second gap edge point.

[0054] In some optional embodiments of this application, the notch location determination module may include:

[0055] The distance calculation unit is used to calculate the distance between the edge point of the third gap and the edge point of the first gap in the first direction;

[0056] The suspected notch location determination unit is used to determine the coordinates of a third edge point that is at a distance greater than a second preset distance as the suspected notch location of the wafer;

[0057] The notch location determination unit is used to determine the notch location of the wafer based on the suspected notch location.

[0058] In some optional embodiments of this application, the notch location determination unit may further include:

[0059] The suspected gap image cropping subunit is used to crop a suspected gap image within a preset range centered on the suspected gap location in the edge linear array image;

[0060] The continuity judgment subunit is used to determine whether the edge curve of the suspected gap in the suspected gap image satisfies the continuity requirement;

[0061] The target gap determination sub-unit is used to identify potential gaps that satisfy the continuity requirement of the edge curve as target gaps on the wafer.

[0062] In some optional embodiments of this application, the wafer notch positioning device may further include:

[0063] The suspected gap processing module is used to denoise, binarize, and eliminate gaps in images with suspected gaps.

[0064] In some optional embodiments of this application, the continuity determination subunit may include:

[0065] The edge curve judgment subunit is used to determine whether the distance between two adjacent pixels in the first or second direction of the edge curve is less than a third preset distance.

[0066] The continuity determination sub-unit is used to determine whether the edge curves satisfy the continuity requirement.

[0067] In some optional embodiments of this application, the wafer notch positioning device may further include:

[0068] The second notch location determination module is used to determine the coordinates of the target notch closest to the center of the edge linear array image as the notch location of the wafer.

[0069] In some optional embodiments of this application, a line scan camera is specifically used to acquire pre-aligned wafer edge images;

[0070] The wafer notch positioning device may also include:

[0071] The noise reduction module is used to denoise the pre-aligned wafer edge image to obtain an edge linear array image.

[0072] According to a third aspect of the embodiments of this application, an electronic device is provided, which may include:

[0073] processor;

[0074] Memory used to store processor-executable instructions;

[0075] The processor is configured to execute instructions to implement the wafer notch positioning method as shown in any embodiment of the first aspect.

[0076] According to a fourth aspect of the embodiments of this application, a storage medium is provided, which, when the instructions in the storage medium are executed by a processor of an information processing device or a server, causes the information processing device or server to implement the wafer notch positioning method as shown in any embodiment of the first aspect.

[0077] The above-mentioned technical solution of this application has the following beneficial technical effects:

[0078] The method in this application determines the wafer notch location by searching the edge linear array image, instead of using a linear sensor to locate the notch. This allows the edge linear array image to be used to determine the relative position of the notch on the wafer, thus integrating the notch search step with the wafer ID recognition step, reducing the testing process and greatly improving testing efficiency. Attached Figure Description

[0079] Figure 1 This is a flowchart of a wafer notch positioning method in an exemplary embodiment of this application;

[0080] Figure 2 This is a flowchart illustrating the determination of notch edge points on a wafer in an exemplary embodiment of this application;

[0081] Figure 3 This is a notched linear array image in an exemplary embodiment of this application;

[0082] Figure 4 This is a flowchart illustrating the process of locating edge points of a wafer in an exemplary embodiment of this application;

[0083] Figure 5 This is a flowchart illustrating the determination of notch edge points based on edge points in an exemplary embodiment of this application;

[0084] Figure 6 This is a flowchart illustrating the determination of notch edge points based on edge points in another exemplary embodiment of this application;

[0085] Figure 7 This is an image of an edge-recessed region in an exemplary embodiment of this application;

[0086] Figure 8 This is a flowchart illustrating the determination of the notch position on a wafer based on notch edge points in an exemplary embodiment of this application;

[0087] Figure 9 This is a flowchart illustrating the determination of the notch location of a wafer based on a suspected notch location in an exemplary embodiment of this application;

[0088] Figure 10 This is an image of a suspicious gap in an exemplary embodiment of this application;

[0089] Figure 11 This is a flowchart of a wafer notch positioning method in another exemplary embodiment of this application;

[0090] Figure 12 This is a denoised image of a suspected gap in an exemplary embodiment of this application;

[0091] Figure 13 This is a binarized image of a suspected gap in an exemplary embodiment of this application;

[0092] Figure 14 This is an image of a suspected gap after the gap has been eliminated in an exemplary embodiment of this application;

[0093] Figure 15 This is a flowchart illustrating the determination of whether the edge curve satisfies continuity in an exemplary embodiment of this application;

[0094] Figure 16 This is an image of the notch edge in an exemplary embodiment of this application;

[0095] Figure 17 This is a flowchart of a wafer notch positioning method in yet another exemplary embodiment of this application;

[0096] Figure 18 This is a flowchart of obtaining an edge linear array image of a wafer in another exemplary embodiment of this application;

[0097] Figure 19 This is a schematic diagram of the wafer notch positioning device structure in an exemplary embodiment of this application;

[0098] Figure 20 This is a schematic diagram of the electronic device structure in an exemplary embodiment of this application;

[0099] Figure 21 This is a schematic diagram of the hardware structure of an electronic device in an exemplary embodiment of this application. Detailed Implementation

[0100] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to specific embodiments and accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0101] The accompanying drawings illustrate layer structure diagrams according to embodiments of this application. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0102] Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0103] In the description of this application, it should be noted that the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0104] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0105] The wafer notch positioning method, apparatus, electronic device, and storage medium provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0106] like Figure 1 As shown, in a first aspect of this application, a wafer notch positioning method is provided, which may include:

[0107] Step S110: Obtain the edge linear array image of the wafer;

[0108] Step S120: Determine the notch edge points of the wafer in the edge linear array image;

[0109] Step S130: Determine the notch location of the wafer based on the notch edge points.

[0110] This embodiment of the method determines the wafer notch location by searching the edge linear array image, instead of using a linear sensor to locate the notch. This allows the edge linear array image to be used to determine the relative position of the notch on the wafer, thus integrating the notch search step with the wafer ID recognition step, reducing the testing process and greatly improving testing efficiency.

[0111] To illustrate this more clearly, the steps described above will be explained in detail below:

[0112] The first step is S110: acquiring the edge linear array image of the wafer.

[0113] The reason for using edge linear array images in this step is that they contain not only wafer notch location information but also wafer ID information. This allows the wafer notch location step to be integrated with the wafer ID identification step, reducing the testing process and greatly improving testing efficiency.

[0114] Then comes step S120: determining the notch edge points of the wafer in the edge linear array image.

[0115] Since there are certain differences between wafer edge points and notch edge points during image recognition, this step identifies the notch by finding the notch edge points on the wafer, thereby determining the location of the notch.

[0116] Finally, step S130: determine the notch location of the wafer based on the notch edge points.

[0117] This step determines the location of the gap by utilizing the positional information of the edge points of the gap. After determining the location of the gap, the ID is located by the relative position of the gap, and the ID image is extracted for recognition.

[0118] like Figure 2 As shown, in some embodiments, step S120: determining the notch edge points of the wafer in the edge linear array image may include:

[0119] Step S121: Proceed row by row along the first direction and move closer to the wafer to find the edge point of the wafer;

[0120] Step S122: Determine the edge points of the gap based on the edge points.

[0121] This embodiment searches the edge linear array image line by line. For example, such as... Figure 3 As shown, the black area represents the edge of the wafer. Due to the wafer's position in the image, this exemplary embodiment searches for the wafer's edge points by moving horizontally towards the wafer side, row by row. In the actual search process, the first direction can be specifically determined based on the wafer's relative position in the image.

[0122] like Figure 4 As shown, in some embodiments, step S121: searching for the edge point of the wafer row by row and moving closer to the wafer along the first direction may include:

[0123] Step S1211: Search for pixels row by row along the first direction and move closer to the wafer in the edge linear array image, and determine the pixels with pixel values ​​less than the target threshold as edge points.

[0124] In this embodiment, the target threshold can be set according to the actual situation. For example, the target threshold can be set to 200. The coordinates of the edge points determined in this embodiment can be used as the starting position for gap retrieval.

[0125] like Figure 5 As shown, in some embodiments, step S122: determining the notch edge point based on the edge point may include:

[0126] Step S1221: Starting from the edge point, retrieve pixel points along the second direction, and update the pixel points with pixel values ​​less than the target threshold as edge points;

[0127] Step S1222: Stop searching until there are no pixels with a value less than the target threshold within a first preset distance from the edge point along the second direction;

[0128] Step S1223: Determine the edge point as the first notch edge point, wherein the first direction is perpendicular to the second direction.

[0129] In this embodiment, after determining the starting position of the edge point retrieval, a retrieval and judgment are performed along a second direction perpendicular to the first direction. The first preset distance can be the diameter of the notch, or slightly smaller than the notch diameter; the specific length can be set according to actual conditions. This embodiment determines whether an edge point exists within the notch diameter range in the second direction. If it exists, the coordinates of the newly discovered edge point are used as the coordinates of the edge point; if it does not exist, it indicates that the location is a region recessed towards the inside of the wafer.

[0130] like Figure 6 As shown, in some embodiments, step S122: determining the notch edge point based on the edge point may further include:

[0131] Step S1224: Starting from the first notch edge point, determine the first pixel point whose pixel value is less than the target threshold retrieved along the second direction as the second notch edge point;

[0132] Step S1225: Taking the midpoint between the first gap edge point and the second gap edge point as the starting point, determine the first pixel point whose pixel value is less than the target threshold retrieved along the first direction as the third gap edge point.

[0133] This embodiment is for determining the overall location of the gap, such as Figure 7 As shown, starting from the first notch edge point P1, the first pixel point whose pixel value is less than the target threshold is determined as the second notch edge point P2 along the second direction. Then, the midpoint P3 between P1 and P2 is calculated, and the third notch edge point P4 is found by traversing horizontally from point P3 to the wafer side.

[0134] like Figure 8 As shown, in some embodiments, step S130: determining the notch location of the wafer based on the notch edge points may include:

[0135] Step S131: Calculate the distance between the edge point of the third gap and the edge point of the first gap in the first direction;

[0136] Step S132: Determine the coordinates of the third edge point with a distance greater than the second preset distance as the suspected notch location of the wafer;

[0137] Step S133: Determine the notch location of the wafer based on the suspected notch location.

[0138] This embodiment aims to further confirm the location of the gap and to make further judgments on the edge points that have already been obtained, similar to... Figure 7As shown, the depth d of the recessed area is obtained by subtracting the x-coordinate of the middle point P3 from the x-coordinate of the third notch edge point P4. If the depth d of the recessed area is greater than the set notch depth, then the third notch edge point P4 is determined as the suspected notch position of the wafer.

[0139] The above embodiments employ a line array image that traverses the wafer edge row by row to calculate the position of the wafer edge within the line array image, and determine whether there is a depression within the notch diameter range below the edge position to locate the notch. Compared to the sensor-based notch-finding method, the method of this application can achieve compatibility with both line array images and ID recognition. Furthermore, by traversing the entire image, it can effectively ensure the stability of small notch identification.

[0140] like Figure 9 As shown, in some embodiments, step S133: determining the notch location of the wafer based on the suspected notch location may further include:

[0141] Step S1331: Extract a pre-defined range of the suspected gap image from the edge linear array image, centered on the suspected gap location;

[0142] Step S1332: Determine whether the edge curve of the suspected gap in the suspected gap image satisfies continuity;

[0143] Step S1333: Identify suspected gaps that satisfy the continuity of edge curves as target gaps on the wafer.

[0144] This embodiment extracts the suspected gap from the edge linear array image to obtain the suspected gap image, such as... Figure 10 As shown, the suspected gap is then further assessed to ensure its accuracy. This embodiment determines the accuracy by judging whether the edge curve of the suspected gap satisfies continuity. If continuity is satisfied, it indicates that the suspected gap is the target gap being sought.

[0145] like Figure 11 As shown, in some embodiments, after step S1331: cropping a preset range of the suspected notch image centered on the suspected notch location in the edge linear array image, the wafer notch localization method may further include:

[0146] Step S1334: Denoise, binarize, and eliminate gaps in the suspected gap image.

[0147] In this embodiment, to eliminate noise and gap interference, the suspected gap image underwent denoising, binarization, and gap elimination processing, such as... Figure 12-14As shown. For example, noise reduction can be achieved using median filtering to eliminate minor noise interference. Median filtering is a non-linear smoothing technique that sets the gray value of each pixel to the median of the gray values ​​of all pixels within a neighborhood window of that pixel. Binarization can be achieved using thresholding methods. Thresholding methods include, but are not limited to: fixed thresholding, local adaptive thresholding, maximum entropy thresholding, Otsu's method, iterative thresholding, etc. Binary images have only 0 and 255 pixel values; black areas have a pixel value of 0, and white areas have a pixel value of 255. Gap elimination can be achieved using closing operations to eliminate any small gaps that may exist. Closing operations involve first dilating the image and then eroding it, used to fill small holes within objects, connect neighboring objects, and smooth the boundaries of larger objects without significantly changing their area.

[0148] like Figure 15 In some embodiments, step S1332: determining whether the edge curve of the suspected gap in the suspected gap image satisfies continuity may include:

[0149] Step S13321: Determine whether the distance between two adjacent pixels of the edge curve in the first or second direction is less than a third preset distance;

[0150] Step S13322: If so, determine that the edge curve satisfies continuity.

[0151] This embodiment determines the continuity of the edge curve. For example, as shown below... Figure 16 As shown, edge detection is performed on a suspected gap image to obtain the edge image. Edge detection operators include, but are not limited to, Canny, Sobel, Rrewitt, and Roberts. The Canny operator can be chosen to find the optimal edge detection algorithm. In determining the continuity of the edge curve, the suspected gap image is traversed. If the distance between horizontally adjacent points is greater than a set value, or the distance between vertically adjacent points is greater than a set value, the edge curve is considered discontinuous, and the suspected gap image is determined not to be a gap. The traversal of suspected gaps continues until all gaps are traversed. Otherwise, the suspected gap image is determined to be a gap image.

[0152] The above embodiments determine whether a wafer edge recess is a notch based on the depth and continuity of the recess, which can effectively improve the accuracy of notch identification and ensure that notches are not incorrectly identified.

[0153] like Figure 17 As shown, in some embodiments, after determining the suspected notch that satisfies the continuity of the edge curve as the target notch of the wafer in step S1333, the wafer notch location method may further include:

[0154] Step S13335: Determine the coordinates of the target notch closest to the center of the edge linear array image as the notch location of the wafer.

[0155] In this embodiment, the obtained notch positions are filtered, and the notch position closest to the center of the image is output. The reason for outputting the notch closest to the center of the image is that the wafer may have rotated more than one revolution. At this time, the notch may have been scanned two or more times, but there is actually only one notch. Therefore, only the notch position closest to the center of the image should be selected as the actual notch position.

[0156] like Figure 18 As shown, in some embodiments, step S110: acquiring the edge linear array image of the wafer includes:

[0157] Step S111: Use a line scan camera to acquire a pre-aligned wafer edge image;

[0158] Step S112: Denoise the pre-aligned wafer edge image to obtain an edge linear array image.

[0159] Since the images acquired by the line scan camera contain minor noise interference, this embodiment performs median filtering on the line scan image to eliminate minor noise interference and improve the accuracy and stability of notch positioning.

[0160] It should be noted that the wafer notch positioning method provided in this application can be executed by a wafer notch positioning device or a control module within that device for performing the wafer notch positioning method. This application uses the wafer notch positioning device performing the wafer notch positioning method as an example to illustrate the wafer notch positioning device provided in this application.

[0161] like Figure 19 As shown, in a second aspect of the embodiments of this application, a wafer notch positioning device is provided, the device may include:

[0162] Linear scan camera 1910 is used to acquire linear scan images of the edges of wafers;

[0163] Edge point determination module 1920 is used to determine the notch edge points of the wafer in the edge linear array image;

[0164] The first notch location determination module 1930 is used to determine the notch location of the wafer based on the notch edge points.

[0165] In some embodiments, the edge point determination module 1920 may include:

[0166] The first direction edge point determination unit is used to find the edge points of the wafer row by row and move closer to the wafer along the first direction;

[0167] The first edge point determination unit is used to determine the edge point of the gap based on the edge point.

[0168] In some embodiments, the first direction edge point determination unit is specifically used to retrieve pixel points row by row and closer to the wafer in the edge linear array image, and determine pixel points with pixel values ​​less than a target threshold as edge points.

[0169] In some embodiments, the first edge point determination unit may include:

[0170] The edge point update subunit is used to retrieve pixel points along the second direction starting from the edge point and update the pixel points with pixel values ​​less than the target threshold as edge points.

[0171] The stop judgment subunit is used to stop the search until there are no pixels with a value less than the target threshold within a range of a first preset distance from the edge point along the second direction;

[0172] The first gap edge point determination sub-unit is used to determine the edge point as the first gap edge point, wherein the first direction is perpendicular to the second direction.

[0173] In some embodiments, the first edge point determination unit may further include:

[0174] The second gap edge point determination subunit is used to determine the first pixel point whose pixel value is less than the target threshold and retrieved along the second direction as the second gap edge point, starting from the first gap edge point.

[0175] The third gap edge point determination subunit is used to determine the first pixel point whose pixel value is less than the target threshold, which is retrieved along the first direction, as the third gap edge point, starting from the midpoint between the first gap edge point and the second gap edge point.

[0176] In some embodiments, the first notch location determination module 1930 may include:

[0177] The distance calculation unit is used to calculate the distance between the edge point of the third gap and the edge point of the first gap in the first direction;

[0178] The suspected notch location determination unit is used to determine the coordinates of a third edge point that is at a distance greater than a second preset distance as the suspected notch location of the wafer;

[0179] The notch location determination unit is used to determine the notch location of the wafer based on the suspected notch location.

[0180] In some embodiments, the notch location determining unit may further include:

[0181] The suspected gap image cropping subunit is used to crop a suspected gap image within a preset range centered on the suspected gap location in the edge linear array image;

[0182] The continuity judgment subunit is used to determine whether the edge curve of the suspected gap in the suspected gap image satisfies the continuity requirement;

[0183] The target gap determination sub-unit is used to identify potential gaps that satisfy the continuity requirement of the edge curve as target gaps on the wafer.

[0184] In some embodiments, the wafer notch positioning device may further include:

[0185] The suspected gap processing module is used to denoise, binarize, and eliminate gaps in images with suspected gaps.

[0186] In some embodiments, the continuity determination subunit may include:

[0187] The edge curve judgment subunit is used to determine whether the distance between two adjacent pixels in the first or second direction of the edge curve is less than a third preset distance.

[0188] The continuity determination sub-unit is used to determine whether the edge curves satisfy the continuity requirement.

[0189] In some embodiments, the wafer notch positioning device may further include:

[0190] The second notch location determination module is used to determine the coordinates of the target notch closest to the center of the edge linear array image as the notch location of the wafer.

[0191] In some embodiments, the line scan camera 1910 is specifically used to acquire a pre-aligned wafer edge image;

[0192] The wafer notch positioning device may also include:

[0193] The noise reduction module is used to denoise the pre-aligned wafer edge image to obtain an edge linear array image.

[0194] The wafer notch positioning device in this application embodiment can be a device, or a component, integrated circuit, or chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. For example, mobile electronic devices can be mobile phones, tablets, laptops, PDAs, in-vehicle electronic devices, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc., while non-mobile electronic devices can be servers, network attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. This application embodiment does not impose specific limitations.

[0195] The wafer notch positioning device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0196] The wafer notch positioning device provided in this application embodiment can achieve... Figure 1 The various processes implemented in the method implementation examples will not be described again here to avoid repetition.

[0197] Optionally, such as Figure 20 As shown, this application embodiment also provides an electronic device 2000, including a processor 2001, a memory 2002, and a program or instructions stored in the memory 2002 and executable on the processor 2001. When the program or instructions are executed by the processor 2001, they implement the various processes of the above-described wafer notch positioning method embodiment and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0198] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0199] Figure 21 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0200] The electronic device 2100 includes, but is not limited to, components such as: radio frequency unit 2101, network module 2102, audio output unit 2103, input unit 2104, sensor 2105, display unit 2106, user input unit 2107, interface unit 2108, memory 2109, and processor 2110.

[0201] Those skilled in the art will understand that the electronic device 2100 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 2110 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 21 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0202] It should be understood that, in this embodiment, the input unit 2104 may include a graphics processing unit (GPU) 21041 and a microphone 21042. The GPU 21041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 2106 may include a display panel 21061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, etc. The user input unit 2107 includes a touch panel 21071 and other input devices 21072. The touch panel 21071 is also called a touch screen. The touch panel 21071 may include a touch detection device and a touch controller. Other input devices 21072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, joysticks, etc., which will not be described in detail here. The memory 2109 can be used to store software programs and various data, including but not limited to applications and operating systems. Processor 2110 may integrate an application processor and a modem processor. The application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may also not be integrated into processor 2110.

[0203] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described wafer notch positioning method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0204] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0205] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0206] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0207] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A wafer notch positioning method, characterized in that, The method comprises the following steps: acquiring an edge line array image of a wafer; determining a notch edge point of the wafer in the edge line array image; determining a notch position of the wafer according to the notch edge point; the step of determining the notch edge point of the wafer in the edge line array image comprises the following steps: finding an edge point of the wafer row by row along a first direction and approaching the wafer; determining the notch edge point according to the edge point; the step of finding the edge point of the wafer row by row along the first direction and approaching the wafer comprises the following steps: retrieving pixel points in the edge line array image row by row along the first direction and approaching the wafer, and determining a pixel point with a pixel value less than a target threshold as the edge point; the step of determining the notch edge point according to the edge point comprises the following steps: starting from the edge point, retrieving pixel points along a second direction, and updating a pixel point with a pixel value less than the target threshold as the edge point; stopping the retrieval until there is no pixel point with a pixel value less than the target threshold within a range of a first preset distance from the edge point along the second direction; determining the edge point as a first notch edge point, wherein the first direction is perpendicular to the second direction; the step of determining the notch edge point according to the edge point further comprises the following steps: starting from the first notch edge point, determining a first pixel point with a pixel value less than the target threshold retrieved along the second direction as a second notch edge point; starting from a midpoint of the first notch edge point and the second notch edge point, determining a first pixel point with a pixel value less than the target threshold retrieved along the first direction as a third notch edge point; the step of determining the notch position of the wafer according to the notch edge point comprises the following steps:

2. The wafer gap positioning method of claim 1, wherein calculating a distance between the third notch edge point and the first notch edge point in the first direction; determining a coordinate of the third notch edge point with a distance greater than a second preset distance as a suspected notch position of the wafer; determining a notch position of the wafer based on the suspected notch position. the step of determining the notch position of the wafer based on the suspected notch position further comprises the following steps:

3. The wafer gap positioning method of claim 2, wherein cutting a suspected notch image of a preset range from the suspected notch position in the edge line array image; judging whether an edge curve of a suspected notch in the suspected notch image satisfies continuity; 4. The wafer notch positioning method of claim 2, wherein, determining the suspected notch with the edge curve satisfying continuity as a target notch of the wafer. after the step of cutting the suspected notch image of the preset range from the suspected notch position in the edge line array image, the wafer notch positioning method further comprises the following steps: performing denoising, binarization and gap elimination on the suspected notch image.

5. The wafer gap positioning method of claim 2, wherein, the step of judging whether the edge curve of the suspected notch in the suspected notch image satisfies continuity comprises the following steps: judging whether a distance between two adjacent pixel points of the edge curve in the first direction or the second direction is less than a third preset distance; if yes, judging that the edge curve satisfies continuity. after the step of determining the suspected notch with the edge curve satisfying continuity as the target notch of the wafer, the wafer notch positioning method further comprises the following steps: Determine the coordinates of the target notch closest to the center of the edge linear array image as the notch position of the wafer.

6. The wafer break location method of any of claims 1-5, wherein, The edge linear array image of the wafer is acquired, comprising: A linear array camera is used to acquire a pre-alignment wafer edge image of the wafer. The pre-alignment wafer edge image is denoised to obtain the edge linear array image.

7. A wafer gap positioning device, comprising: Comprise: A linear array camera is used to acquire an edge linear array image of a wafer. An edge point determination module is used to determine a notch edge point of the wafer in the edge linear array image, and the edge point determination module is specifically configured to retrieve pixel points in the edge linear array image along a first direction row by row and towards the wafer, determine pixel points with pixel values less than a target threshold as the edge points, take the edge points as a starting point, retrieve pixel points along a second direction, and update pixel points with pixel values less than the target threshold as the edge points; stop retrieving until there is no pixel point with a pixel value less than the target threshold within a range of a first preset distance from the edge point along the second direction; determine the edge point as a first notch edge point, wherein the first direction is perpendicular to the second direction; take the first notch edge point as a starting point, and determine the first pixel point with a pixel value less than the target threshold retrieved along the second direction as a second notch edge point; take the midpoint of the first notch edge point and the second notch edge point as a starting point, and determine the first pixel point with a pixel value less than the target threshold retrieved along the first direction as a third notch edge point. A notch position determination module is used to determine a notch position of the wafer according to the notch edge point, and the notch position determination module is specifically configured to calculate the distance of the third notch edge point and the first notch edge point in the first direction; determine the coordinates of the third notch edge point with a distance greater than a second preset distance as a suspected notch position of the wafer; and determine the notch position of the wafer based on the suspected notch position.

8. An electronic device, comprising: Comprise: A processor, a memory, and a program or instructions stored on the memory and executable on the processor, wherein the program or instructions are executed by the processor to implement the steps of the wafer notch positioning method according to any one of claims 1-6.

9. A readable storage medium, characterized by, A readable storage medium stores a program or instructions, wherein the program or instructions are executed by a processor to implement the steps of the wafer notch positioning method according to any one of claims 1-6.

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