A topcon cell and a preparation method thereof

Abstract

The application provides a TOPCon cell, which comprises a doped polysilicon layer; the doped polysilicon layer comprises a first doped polysilicon region and a second doped polysilicon alloy region; the first doped polysilicon region is selected from phosphorus-doped polysilicon; the second doped polysilicon alloy region is selected from phosphorus-doped polysilicon alloyed with at least one element selected from oxygen, carbon and nitrogen; the doping concentration of the first doped polysilicon region is not less than 1E20 cm ‑3 -3; the band gap of the second doped polysilicon alloy region is greater than that of the first doped polysilicon region, and the doping concentration of the second doped polysilicon alloy region is less than that of the first doped polysilicon region. The TOPCon cell structure provided by the application can ensure the thickness of the doped polysilicon in the metal contact region, avoid the destruction of the tunneling oxide layer in the slurry sintering process, reduce the recombination current and the contact resistance, and reduce the light parasitic absorption in the non-metal region, especially the free carrier absorption.

Description

Technical Field

[0001] This invention belongs to the field of battery technology, and in particular relates to a TOPCon battery and its preparation method. Background Technology

[0002] On the back of TOPCon cells, an Ag paste is typically used to burn through the SiNx dielectric film to form an ohmic contact with doped polycrystalline silicon. During the paste sintering process, metallic Ag grains can potentially penetrate the doped polycrystalline silicon film, compromising the passivation effect of the interface oxide layer. To reduce the recombination current density in the metal contact area, a sufficient thickness of doped polycrystalline silicon is required, typically 100–150 nm. To ensure good field passivation and low ohmic contact, the doped polycrystalline silicon needs a sufficient doping concentration, typically >1e20 cm⁻¹. -3 However, excessively thick or concentrated doped polycrystalline silicon films can lead to losses in short-circuit current in TOPCon cells due to free carrier absorption (FCA) of long-wavelength light. Simultaneously, parasitic absorption of back-incident light by doped polycrystalline silicon reduces the cell's bifaciality. Achieving a balance between recombination, resistive losses, and optical losses in terms of film thickness and doping concentration is extremely difficult. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a TOPCon battery and a method for preparing the same. The TOPCon battery provided by the present invention can reduce the recombination current and contact resistance while reducing the photoparasitic absorption in the non-metallic region, especially the absorption of free carriers.

[0004] This invention provides a TOPCon battery, comprising:

[0005] Doped polycrystalline silicon layer;

[0006] The doped polycrystalline silicon layer includes: a first doped polycrystalline silicon region and a second doped polycrystalline alloy silicon region;

[0007] The first doped polysilicon region is selected from phosphorus-doped polysilicon;

[0008] The second doped polycrystalline silicon region is selected from phosphorus-doped polycrystalline silicon alloyed with at least one element selected from oxygen, carbon, and nitrogen;

[0009] The thickness of the first doped polycrystalline silicon region is selected from 100 to 200 nm.

[0010] In the embodiments of the present invention, other layer structures of the TOPCon cell can be set according to the structure of the TOPCon cell known to those skilled in the art. For example, a diffusion layer, a passivation layer, a front anti-reflection layer and a front metal electrode can be sequentially set on the front side of the monocrystalline silicon wafer; a tunneling layer, a doped polycrystalline silicon layer, a back anti-reflection layer and a back metal electrode can be sequentially set on the back side of the monocrystalline silicon wafer.

[0011] In embodiments of the present invention, the single-crystal silicon wafer can be a phosphorus-doped N-type single-crystal silicon wafer with a resistivity of 0.1 to 10 Ωcm, such as 0.5 Ωcm, 1 Ωcm, 2 Ωcm, 4 Ωcm, 6 Ωcm, or 8 Ωcm; and a thickness of 100 to 200 micrometers, such as 120 micrometers, 140 micrometers, 160 micrometers, or 180 micrometers.

[0012] In an embodiment of the invention, the diffusion layer can be a P-type doped layer formed by boron doping, and the sheet resistance can be selected from 100 to 300 Ω, such as 150 Ω, 200 Ω, or 250 Ω.

[0013] In embodiments of the present invention, the passivation layer may be selected from an aluminum oxide layer; the thickness of the passivation layer may be selected from 2 to 6 nm, such as 3 nm, 4 nm, or 5 nm.

[0014] In embodiments of the present invention, the front antireflective layer may be a composite film formed from one or more of silicon nitride, silicon oxynitride, and silicon oxide layers; the (total) thickness of the front antireflective layer may be selected from 70–120 nm, such as 80 nm, 90 nm, 100 nm, or 110 nm; the (overall) refractive index of the front antireflective layer may be selected from 1.9–2.1, such as 2.0. In embodiments of the present invention, the refractive index of the front antireflective layer may decrease sequentially in the direction away from the single-crystal silicon wafer.

[0015] In embodiments of the present invention, the front metal electrode may be selected from AgAl gate electrode.

[0016] In embodiments of the present invention, the tunneling layer may be a silicon oxide layer; the thickness of the tunneling layer may be 1 to 3 nm, such as 2 nm.

[0017] In an embodiment of the present invention, a first doped polycrystalline silicon region (which may be referred to as a first doped polycrystalline silicon layer) is disposed at the position corresponding to the metal electrode in the TOPCon cell. The first doped polycrystalline silicon region may be disposed at the position corresponding to the tunneling layer of the back metal electrode of the monocrystalline silicon wafer. A second doped polycrystalline alloy silicon region (which may be referred to as a second doped polycrystalline alloy silicon layer) is disposed at the position corresponding to the tunneling layer of the non-back metal electrode. The first doped polycrystalline silicon region and the second doped polycrystalline alloy silicon region together form a doped polycrystalline silicon layer.

[0018] In an embodiment of the present invention, the first doped polysilicon region is phosphorus-doped polysilicon with a doping concentration of not less than 1E20cm⁻¹. -3 (i.e., 1×10) 20 cm -3 ), such as 1~3E20cm -3 (i.e. (1~3)×10) 20 cm -3 ), such as 2E20cm -3 The thickness of the first doped polysilicon region can be selected from 100 to 200 nm, such as 120 nm, 140 nm, 160 nm, and 180 nm.

[0019] In embodiments of the present invention, the second doped polycrystalline silicon alloy region is selected from doped polycrystalline silicon alloyed with at least one element selected from oxygen, carbon, and nitrogen, such as doped polycrystalline silicon oxide, doped polycrystalline silicon carbide, and doped polycrystalline silicon nitride. The band gap of the second doped polycrystalline silicon alloy region is greater than that of the first doped polycrystalline silicon region. The band gap of the second doped polycrystalline silicon alloy region can be selected from 1.9 to 2.2 eV, such as 2.1 eV. The doping concentration of the second doped polycrystalline silicon alloy region is less than that of the first doped polycrystalline silicon region. The second doped polycrystalline silicon alloy region can be phosphorus-doped polycrystalline silicon, and the doping concentration can be selected from 1 to 5E19 cm⁻¹. -3 (i.e. (1~5)×10) 19 cm -3 ), such as 2E20cm -3 3E20cm -3 4E20cm -3 The thickness of the second doped polycrystalline silicon region can be selected from 100 to 200 nm, such as 120 nm, 140 nm, 160 nm, or 180 nm. In embodiments of the present invention, the thicknesses of the doped polycrystalline silicon layer, the first doped polycrystalline silicon region, and the second doped polycrystalline silicon region are the same.

[0020] In embodiments of the present invention, the back antireflection layer may be a composite film formed from one or more of silicon nitride, silicon oxynitride, and silicon oxide layers; the (total) thickness of the back antireflection layer may be selected from 70 to 120 nm, such as 80 nm, 90 nm, 100 nm, or 110 nm; the (overall) refractive index of the back antireflection layer may be selected from 1.9 to 2.1, such as 2.0. In embodiments of the present invention, the refractive index of the back antireflection layer decreases sequentially in the direction away from the single-crystal silicon wafer.

[0021] In embodiments of the present invention, the back metal electrode may be selected from Ag gate electrode.

[0022] In embodiments of the present invention, the structure of the TOPCon battery can be as follows: Figure 1As shown, it includes: an N-type monocrystalline silicon wafer 1; a diffusion layer 2; a passivation layer 3; a front antireflection layer 4; a front metal electrode 5; a tunneling layer 6; a doped polycrystalline silicon layer 7; a first doped polycrystalline silicon region 7-1; a second doped polycrystalline alloy silicon region 7-2; a back antireflection layer 8; and a back metal electrode 9. The diffusion layer, passivation layer, front antireflection layer, and front metal electrode are sequentially disposed on the upper surface of the N-type monocrystalline silicon wafer. The tunneling layer, doped polycrystalline silicon layer, back antireflection layer, and back metal electrode are sequentially disposed on the lower surface of the N-type monocrystalline silicon wafer. The first doped polycrystalline silicon region is disposed in a portion of the lower surface of the tunneling layer, and the second doped polycrystalline alloy silicon region is disposed in the remaining areas. The first doped polycrystalline silicon region and the second doped polycrystalline alloy silicon region form an integral doped polycrystalline silicon layer. The position of the first doped polycrystalline silicon region corresponds to the position of the back metal electrode, that is, the first doped polycrystalline silicon region is disposed at the position of the back metal electrode corresponding to the position of the tunneling layer.

[0023] This invention provides a method for preparing a TOPCon battery, comprising:

[0024] A tunneling layer and an intrinsic amorphous silicon layer are sequentially prepared on the lower surface of a single-crystal silicon wafer;

[0025] By using a mask to block the intrinsic amorphous silicon layer, an ion implantation method is used to convert the intrinsic amorphous silicon layer into an amorphous alloy silicon layer.

[0026] Phosphorus diffusion doping is performed on the intrinsic amorphous silicon layer (the intrinsic amorphous silicon layer region that is blocked by the mask during ion implantation, and the mask is removed during phosphorus diffusion doping) and the amorphous alloy silicon layer to transform them from an amorphous state to a crystalline state; thus forming the first doped polycrystalline silicon region and the second doped polycrystalline alloy silicon region.

[0027] In embodiments of the present invention, the method for preparing a TOPCon battery may further include:

[0028] A diffusion layer, a passivation layer, a front antireflection layer, and a front metal electrode are sequentially fabricated on the upper surface (front) of a single-crystal silicon wafer.

[0029] A tunneling layer, a doped polycrystalline silicon layer, a back antireflection layer, and a back metal electrode are sequentially fabricated on the lower surface (back side) of a single-crystal silicon wafer.

[0030] In embodiments of the present invention, the method for preparing a single-crystal silicon wafer may include:

[0031] Chemicals are used to remove contaminants from the surface of monocrystalline silicon wafers and to form surface textures on the surface of monocrystalline silicon wafers.

[0032] In embodiments of the present invention, the chemical reagent can be an acid or alkali; the contaminant can be an organic stain or a metallic impurity; forming a texture on the surface of a single-crystal silicon wafer can increase the absorption of sunlight and reduce reflection.

[0033] In the embodiments of the present invention, the diffusion layer can be prepared by high-temperature diffusion, such as by high-temperature diffusion of boride to form a diffusion layer, i.e., boron diffusion to form a front PN junction; the boride can be selected from BCl3 or BBr3; the diffusion temperature can be selected from 950 to 1050°C, such as 1000°C; there are no special restrictions on the specific preparation method of the diffusion layer, and the diffusion layer can be prepared by following the high-temperature diffusion method well known in the art.

[0034] In embodiments of the present invention, after obtaining the diffusion layer, the method may further include:

[0035] HF etching is performed on one side of a single-crystal silicon wafer to remove the BSG (borosilicate glass) on the back side;

[0036] Backside etching removes the PN junction formed by parasitic diffusion on the backside, preventing edge leakage.

[0037] In embodiments of the present invention, the passivation layer can be prepared by using ALD (atomic deposition) to prepare an alumina film on the surface of the diffusion layer; there are no special restrictions on the specific preparation method of the passivation layer, and it can be prepared by using the ALD method for preparing alumina (AlOx) films well known in the art.

[0038] In embodiments of the present invention, the front antireflection layer can be prepared by depositing one or more stacked films of silicon oxide film, silicon nitride film, and silicon oxynitride film on the surface of the passivation layer using PECVD (plasma-enhanced chemical vapor deposition). There are no special restrictions on the specific preparation method of the front antireflection layer, and it can be prepared by using the PECVD method well known in the art to prepare silicon oxide film, silicon nitride film, or silicon oxynitride film.

[0039] In the embodiments of the present invention, the front metal electrode can be prepared by coating with Ag / Al paste; there are no special restrictions on the specific preparation method, and it can be prepared by the printing electrode method well known in the art.

[0040] In embodiments of the present invention, the tunneling layer can be prepared by thermal oxidation, wet chemical oxidation, ozone oxidation, or plasma oxidation to form silicon oxide. In embodiments of the present invention, the tunneling oxide layer can be generated by in-situ oxidation using LPCVD (low-pressure chemical vapor deposition), with the temperature controlled between 550 and 650°C, such as 580°C, 600°C, or 620°C.

[0041] In the embodiments of the present invention, the method for preparing the doped polycrystalline silicon layer is the process described in the above technical solution for obtaining the first doped polycrystalline silicon region and the second doped polycrystalline alloy silicon region. The thickness of the intrinsic amorphous layer in the above technical solution can be selected from 120-150 nm, such as 130 nm or 140 nm. The back metal electrode of the single crystal silicon wafer is blocked by a mask in the region corresponding to the intrinsic amorphous silicon layer. Alloy ions, such as at least one of oxygen, carbon, and nitrogen, are implanted by ion implantation to form an amorphous alloy silicon layer at the corresponding position of the non-metallic electrode region. Oxygen ion implantation can be used, and the ion energy can be selected from 20-30 keV, such as 25 keV. The ion implantation rate can be selected from 1-5E1017 ions / cm. 2 (i.e. (1~5)×10) 17 ions / cm 2 ), such as 2E1017 ions / cm 2 3E1017ions / cm 2 4E1017ions / cm 2 Then the mask is removed, and phosphorus diffusion doping is performed on the intrinsic amorphous silicon layer region that has not undergone ion implantation and the amorphous alloy silicon layer obtained above, and the amorphous silicon layer is transformed into a crystalline silicon layer. During the phosphorus diffusion doping process, POCl3 is used as the diffusion source, and the diffusion temperature can be selected from 800 to 900℃, such as 820℃, 840℃, 860℃, and 880℃.

[0042] A first phosphorus-doped polycrystalline silicon region is obtained at the location of the masked position, i.e., the position corresponding to the intrinsic amorphous silicon layer of the back metal electrode; the remaining amorphous alloy silicon layer forms a second doped polycrystalline alloy silicon region, which is phosphorus-doped polycrystalline silicon alloyed with at least one of oxygen, carbon, and nitrogen.

[0043] In embodiments of the present invention, the back antireflection layer can be prepared by depositing one or more stacked films of silicon oxide, silicon nitride, and silicon oxynitride on the lower surface of a polycrystalline silicon doped layer using PECVD. There are no special restrictions on the specific preparation method of the back antireflection layer, and it can be prepared by using the PECVD method well known in the art to prepare silicon oxide, silicon nitride, or silicon oxynitride films.

[0044] In an embodiment of the present invention, the back metal electrode can be printed with Ag paste by means of screen printing, laser transfer, etc., and ohmic contact is formed with the back antireflection layer and the doped polycrystalline silicon layer by sintering.

[0045] In an embodiment of the present invention, after obtaining the front metal electrode and the back metal electrode, the method further includes:

[0046] Photoinjection repairs defects in the cell body and on its surface.

[0047] In embodiments of the present invention, the method for preparing a TOPCon battery may include the following steps, such as... Figure 2 As shown:

[0048] 1) Texturing: Using acid and alkali chemicals, organic contaminants and metallic impurities on the surface of silicon wafers are removed, and a surface texture is formed on the surface of silicon wafers to increase the absorption of sunlight and reduce reflection;

[0049] 2) Boron diffusion: forms a front-side PN junction, creating a diffusion layer;

[0050] 3) BSG: Single-sided HF etching to remove BSG on the back side;

[0051] 4) Backside etching: Removes the PN junction formed by parasitic diffusion on the backside to prevent edge leakage;

[0052] 5) LPCVD: In-situ oxidation to generate a tunneling oxide layer and deposit an intrinsic amorphous silicon layer;

[0053] 6) Local alloy ion implantation: By using a mask to block the view, at least one element among oxygen, carbon, and nitrogen is implanted into the intrinsic amorphous silicon layer at the corresponding position of the non-metallic contact area, thereby converting the intrinsic amorphous silicon layer into an amorphous alloy silicon layer.

[0054] 7) Phosphorus diffusion: Phosphorus diffusion doping is performed on the back side of the monocrystalline silicon wafer to transform it from an amorphous state to a crystalline state, forming a doped polycrystalline silicon layer.

[0055] 8) PSG: Single-sided HF etching to remove PSG from the front side of the polysilicon surface after diffusion;

[0056] 9) Front etching: The polysilicon layer is removed by etching with an alkaline solution, and the BSG on the front and the PSG on the back are removed by cleaning with hydrofluoric acid.

[0057] 10) ALD: A dense AlOx film is deposited on the front side of the substrate (diffusion layer) using ALD atomic layer deposition.

[0058] 11) Front-side PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the front side of a substrate (alumina film) using PECVD;

[0059] 12) Backside PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the backside of a substrate (doped polycrystalline silicon layer) using PECVD;

[0060] 13) Printing / Sintering / Photoinjection: The negative electrode Ag / Al paste is printed on the front side, and the electrode Ag paste is printed on the back side; co-sintering is performed to form a good ohmic contact; photoinjection is used to repair defects in the cell body and on the surface.

[0061] This invention involves forming a first doped polycrystalline silicon region at a corresponding position on the back side of an N-type single-crystal silicon wafer, and a second doped polycrystalline alloy silicon region at a corresponding position on the back side of the non-metallic region. The first doped polycrystalline silicon region is phosphorus-doped polycrystalline silicon with a thickness of 100–200 nm and a doping concentration of not less than 1E20cm⁻¹. -3 The first doped polycrystalline silicon region has sufficient thickness to effectively shield the penetration of slurry during sintering, preventing damage to the interface tunneling oxide layer and thus ensuring a low recombination current in the metal contact area. Furthermore, the first doped polycrystalline silicon region has sufficient concentration to ensure a low contact resistance in the metal contact area. The second doped polycrystalline alloy silicon region is a doped polycrystalline silicon compound alloyed with at least one element from oxygen, carbon, and nitrogen. Its band gap is larger than that of the first doped polycrystalline silicon region, which can reduce photoparasitic absorption in the non-metallic region and improve the bifaciality of the battery. On the other hand, due to the influence of the alloying compounds, its doping concentration is lower than that of the first doped polycrystalline silicon region, resulting in a corresponding reduction in long-wavelength free carrier absorption and thus an increase in the front-side short-circuit current of the battery.

[0062] This invention improves the optical bandgap by locally implanting ions into the intrinsic amorphous silicon layer at the corresponding position in the non-metallic region to convert it into an amorphous silicon compound layer. Then, phosphorus diffusion is used to dope and crystallize the amorphous silicon at the corresponding position in the metallic region (back metal electrode) and the amorphous silicon compound layer at the corresponding position in the non-metallic region. The alloying elements oxygen, carbon, and nitrogen in the amorphous silicon compound are used to reduce the doping concentration of the second doped polycrystalline alloy silicon region. The method provided by this invention is simple and easy to implement. Attached Figure Description

[0063] Figure 1 This is a schematic diagram of the TOPCon battery structure in an embodiment of the present invention;

[0064] Figure 2 This is a flowchart illustrating the fabrication process of the TOPCon battery structure in an embodiment of the present invention.

[0065] Figure 3 This is a schematic diagram of the TOPCon battery structure in Comparative Example 1 of the present invention. Detailed Implementation

[0066] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0067] Example 1

[0068] according to Figure 2 The flowchart shown illustrates the fabrication of a TOPCon battery, including the following specific steps:

[0069] S1 texturing: Select phosphorus-doped N-type single crystal silicon wafers with resistivity of 0.5-1.0 Ωcm and thickness of 130-160 micrometers; use acid and alkali chemicals to remove organic contaminants and metallic impurities from the silicon wafer surface, forming a surface texture on the silicon wafer surface to increase the absorption of sunlight and reduce reflection;

[0070] S2 boron diffusion: BCl3 low-pressure diffusion is used to form a front PN junction with a diffusion temperature of 950-1050℃ and a sheet resistance of 150-250Ω to form a boron diffusion layer.

[0071] S3 BSG: Single-sided HF etching to remove backside BSG;

[0072] S4 Backside Etching: Alkaline solution etching is used to remove the PN junction formed by parasitic diffusion on the backside and prevent edge leakage.

[0073] S5 LPCVD: In-situ oxidation using LPCVD is employed to generate a tunneling oxide layer at a temperature of 550–650℃ and a thickness of 1–3 nm, and an intrinsic amorphous silicon layer with a thickness of 120–150 nm is deposited.

[0074] S6 Localized Oxygen Ion Implantation: The back metal area (back metal electrode area) is masked using a mask. Oxygen ions are implanted at the corresponding location in the non-metallic contact area, with an ion energy of 20–30 keV and an ion flux of 1–5 E10¹⁷ ions / cm². 2 (i.e. (1~5)×10) 17 ions / cm 2 This transforms the intrinsic amorphous silicon layer at the corresponding position in the non-metallic region into an amorphous silicon oxide layer.

[0075] S7 phosphorus diffusion: Using POCl3 as the diffusion source, phosphorus diffusion doping is performed on amorphous silicon and amorphous silicon oxide at a diffusion temperature of 800-900℃, and the amorphous state is transformed into the crystalline state to form a doped polycrystalline silicon layer.

[0076] S8 PSG: Single-sided HF etching to remove the PSG on the front side of the polysilicon surface after diffusion;

[0077] S9 front etching: Alkaline solution etching is used to remove the polysilicon layer, and hydrofluoric acid cleaning is used to remove the BSG on the front and the PSG on the back.

[0078] S10 ALD: A dense AlOx film with a thickness of 3-5 nm is deposited on the front side of the substrate (boron diffusion layer) using ALD atomic layer deposition.

[0079] S11 Front-side PECVD: One or more stacked films of silicon nitride and silicon oxynitride are deposited on the front side of the alumina film by PECVD, with a total thickness of 70-120nm and a comprehensive refractive index of 1.9-2.1.

[0080] S12 Backside PECVD: One or more stacked films of silicon nitride and silicon oxynitride are deposited on the backside of the doped polycrystalline silicon layer by PECVD, with a total thickness of 70-120 nm and a comprehensive refractive index of 1.9-2.1.

[0081] S13 Printing / Sintering / Photoinjection: Front side is printed with negative electrode Ag / Al paste, and back side is printed with electrode Ag paste; co-sintering forms good ohmic contact; photoinjection repairs defects in the cell body and surface.

[0082] A schematic diagram of the TOPCon battery structure prepared in Example 1 of this invention is shown below. Figure 1 As shown, the device includes a monocrystalline silicon wafer, with a diffusion layer, a passivation layer, a front antireflection layer, and a front metal electrode sequentially disposed on the front side of the monocrystalline silicon wafer, and a tunneling layer, a doped polycrystalline silicon layer, a back antireflection layer, and a back metal electrode sequentially disposed on the back side of the monocrystalline silicon wafer. The doped polycrystalline silicon layer includes a first doped polycrystalline silicon region located at a corresponding position in the back metal region (back metal electrode) and a second doped polycrystalline alloy silicon region located at a corresponding position in the back non-metal region. The first doped polycrystalline silicon layer is phosphorus-doped polycrystalline silicon with a thickness of 120–150 nm and a doping concentration of 1–3E20 cm⁻¹. -3 The second doped polycrystalline silicon alloy region is phosphorus-doped polycrystalline silicon oxide, with a band gap of 1.9–2.2 eV and a doping concentration of 1–5 E19 cm⁻¹. -3 .

[0083] Example 2

[0084] The TOPCon battery was prepared according to the method of Example 1, except that S6 was a local nitrogen ion implantation:

[0085] By masking the back metal area (back metal electrode area) with a mask, nitrogen ion implantation is performed at the corresponding position of the non-metallic contact area. The ion energy is 25–30 keV and the ion flux is (1–2) × 10⁻⁶. 17 ions / cm 2 The intrinsic amorphous silicon layer at the corresponding position of the non-metallic region is converted into an amorphous silicon nitride layer;

[0086] S7 phosphorus diffusion: Using POCl3 as the diffusion source, phosphorus diffusion doping is performed on amorphous silicon and amorphous silicon nitride at a diffusion temperature of 800-900℃, transforming them from an amorphous state to a crystalline state to form a doped polycrystalline silicon layer.

[0087] Example 3

[0088] The TOPCon battery was prepared according to the method of Example 1, except that S6 was a local carbon ion implantation:

[0089] By masking the back metal area (back metal electrode area) with a mask, carbon ion implantation is performed at the corresponding position of the non-metallic contact area. The ion energy is 20–25 keV and the ion flux is (3–5) × 10⁻⁶. 17 ions / cm 2 The intrinsic amorphous silicon layer at the corresponding position of the non-metallic region is converted into an amorphous silicon carbide layer;

[0090] S7 phosphorus diffusion: Using POCl3 as the diffusion source, phosphorus diffusion doping is performed on amorphous silicon and amorphous silicon carbide at a diffusion temperature of 800-900℃, transforming them from an amorphous state to a crystalline state to form a doped polycrystalline silicon layer.

[0091] Comparative Example 1

[0092] The TOPCon battery was prepared according to the method of Example 1, except that the doped polycrystalline silicon layer is a single doped polycrystalline silicon layer; its structural schematic diagram is shown below. Figure 3 As shown, compared with Example 1, the thickness of the single-concentration doped polycrystalline silicon layer is 120-130 nm, and the doping concentration is 2-3E20 cm⁻¹. -3 ; Figure 3 1 is an N-type single-crystal silicon wafer; 2 is a diffusion layer; 3 is a passivation layer; 4 is a front anti-reflection layer; 5 is a front metal electrode; 6 is a tunneling layer; 7 is a doped polycrystalline silicon layer; 8 is an anti-reflection layer; and 9 is a back metal electrode.

[0093] Performance testing

[0094] IV performance tests were performed on the TOPCon batteries prepared in the embodiments and comparative examples of this invention. The test results are as follows:

[0095]

[0096] Comparing the TOPCon cells prepared in the examples and the comparative examples, it can be seen that in the examples, by setting a first doped polycrystalline silicon region at the corresponding position of the back metal region and a second doped polycrystalline alloy silicon region at the corresponding position of the back non-metal region on the back side of the N-type monocrystalline silicon wafer, the first doped polycrystalline silicon region is phosphorus-doped polycrystalline silicon with a large thickness, which can effectively shield the penetration of slurry during sintering and avoid damage to the interface tunneling oxide layer, thereby ensuring that the metal contact area has a low recombination current. On the other hand, the first doped polycrystalline silicon region has a sufficient concentration, which can ensure that the metal contact area has a low contact resistance. The second doped polycrystalline alloy silicon region is doped polycrystalline silicon oxide with a larger band gap than the first doped polycrystalline silicon region, which can reduce photoparasitic absorption in the non-metal region and improve the bifaciality of the cell. On the other hand, due to the influence of oxygen in the doped polycrystalline silicon, its doping concentration is lower than that of the first doped polycrystalline silicon region, and the corresponding long-wavelength free carrier absorption is also reduced, thus increasing the front short-circuit current of the cell.

[0097] In addition, the embodiment improves the optical bandgap by converting the intrinsic amorphous silicon layer at the corresponding position in the non-metal region into an amorphous silicon oxide layer by local oxygen ion implantation at the corresponding position in the non-metal region; and uses phosphorus diffusion method to dope and crystallize the amorphous silicon at the corresponding position in the metal region and the amorphous silicon oxide at the corresponding position in the non-metal region, and uses oxygen in the amorphous silicon oxide to reduce the doping concentration of the second doped polycrystalline alloy silicon region. The process is simple and easy to implement.

[0098] While the invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not intended to limit the invention. It will be readily understood by those skilled in the art that various changes may be made to suit particular circumstances, materials, compositions, substances, methods, or processes to the objectives, spirit, and scope of this application without departing from the true spirit and scope of the invention as defined by the appended claims. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this application.

Claims

1. A method for preparing a TOPCon battery, characterized in that, include: A tunneling layer and an intrinsic amorphous silicon layer are sequentially prepared on the lower surface of a single-crystal silicon wafer; By using a photomask to block the view, ion elements are implanted into the non-metallic contact area on the back of the TOPCon battery at the location corresponding to the intrinsic amorphous silicon layer, thereby converting the intrinsic amorphous silicon layer into an amorphous alloy silicon layer; the ion element is selected from at least one of oxygen, carbon, and nitrogen. Phosphorus diffusion doping is performed on the intrinsic amorphous silicon layer and the amorphous alloy silicon layer to transform them from an amorphous state to a crystalline state; a first doped polycrystalline silicon region and a second doped polycrystalline alloy silicon region are formed, the first doped polycrystalline silicon region corresponds to the back metal contact region, and the second doped polycrystalline alloy silicon region corresponds to the back non-metal contact region. The thickness of the first doped polycrystalline silicon region and the second doped polycrystalline alloy silicon region are the same, and the doping concentration of the second doped polycrystalline alloy silicon region is less than that of the first doped polycrystalline silicon region.

2. The preparation method according to claim 1, characterized in that, The ion energy of the ion implantation is selected from 20~30 keV; the ion flux is selected from 1 E17 ions / cm. 2 ~5 E17ions / cm 2 .

3. A TOPCon battery prepared by the preparation method as described in claim 1 or 2, characterized in that, include: Doped polycrystalline silicon layer; The doped polycrystalline silicon layer includes: a first doped polycrystalline silicon region and a second doped polycrystalline alloy silicon region; The first doped polysilicon region is selected from phosphorus-doped polysilicon; The second doped polycrystalline silicon region is selected from phosphorus-doped polycrystalline silicon alloyed with at least one element selected from oxygen, carbon, and nitrogen; The thickness of the first doped polysilicon region is selected from 100~200 nm; The band gap of the second doped polycrystalline silicon region is greater than the band gap of the first doped polycrystalline silicon region.

4. The TOPCon battery according to claim 3, characterized in that, The doping concentration of the first doped polysilicon region is not less than 1E20cm. -3 .

5. The TOPCon battery according to claim 4, characterized in that, The doping concentration of the first doped polysilicon region is selected from 1 E20cm. -3 ~3E20cm -3 .

6. The TOPCon battery according to claim 4, characterized in that, The doping concentration of the second doped polycrystalline silicon region is selected from 1 E19cm. -3 ~5E19cm -3 .

7. The TOPCon battery according to claim 3, characterized in that, The bandgap of the second doped polycrystalline silicon alloy region is selected from 1.9~2.2eV.

8. The TOPCon battery according to claim 3, characterized in that, The first doped polycrystalline silicon region is disposed at the position of the metal electrode on the back side of the single-crystal silicon wafer corresponding to the tunneling layer.

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