A t-type three-level inverter and control method

Abstract

The application discloses a T-type three-level inverter and a control method. The inverter comprises an inverter circuit, the inverter circuit has a positive input terminal and a negative input terminal for connecting a direct current, an output terminal, at least one vertical bridge and at least one horizontal bridge, the vertical bridge and the horizontal bridge comprise at least two switch modules connected in series; the inverter further comprises an inverter protection device, which comprises a first shutdown driving module, a second shutdown driving module, a controller and a driving delay module. The T-type three-level inverter in the application realizes maximized promotion of the vertical pipe switch speed and reduction of the vertical pipe switch loss under the premise of meeting the device voltage stress range through the first shutdown driving module, the second shutdown driving module and the inverter protection device, and the device use cost is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of photovoltaic inverters, and particularly relates to a T-type three-level inverter and a control method. BACKGROUND

[0002] The T-type three-level inverter is widely used in photovoltaic systems due to its simple topology structure, small number of switching tubes, no strict driving timing sequence requirement for the switching tubes and reliable application. However, the vertical tube needs to bear the total bus voltage, and the working voltage of the vertical tube generally needs to be about twice that of the horizontal tube. For example, the switching tube with a voltage of 1200V is generally used in the vertical tube in a direct current 1100V photovoltaic system. The higher the voltage of the switching tube, the worse the switching loss characteristic compared with the switching tube with the same current specification but lower voltage. In the T-type three-level topology, in order to meet the voltage stress requirement, the driving resistance is generally adjusted to reduce the turn-off speed, but this brings the disadvantage of large turn-off loss. In the photovoltaic system, the working conduction duty cycle of the vertical tube is large, and the switching current is large when the switching tube is switched, so the overall loss is large. The horizontal tube is basically only diode conduction, and the insulated gate bipolar transistor (IGBT) basically does not bear the switching loss when the power factor (PF) is 1, and only the diode has switching loss, so the slow turn-off speed has little effect on the overall loss. The existing part of the T-type three-level inverter does not fully utilize the switching performance of the IGBT of the horizontal tube. Therefore, under the premise of meeting the voltage stress range of the device, maximizing the switching speed of the vertical tube and reducing the switching loss of the vertical tube are the goals pursued by people in the field. SUMMARY

[0003] In view of the above technical problems, the purpose of the present application is to provide an improved T-type three-level inverter and control method.

[0004] To achieve the above-mentioned purpose, the technical scheme adopted by the present application is:

[0005] A T-type three-level inverter, comprising an inverter circuit, the inverter circuit having a positive input terminal and a negative input terminal for connecting a direct current and an output terminal, the inverter circuit comprising:

[0006] at least one vertical bridge and at least one horizontal bridge, one end of the vertical bridge being connected to the positive input terminal, the other end of the vertical bridge being connected to the negative input terminal; one end of the horizontal bridge being connected to the neutral point between the positive input terminal and the negative input terminal, the other end of the horizontal bridge being connected to the output terminal; the connection point of the vertical bridge and the horizontal bridge being connected to the output terminal;

[0007] The vertical bridge comprises at least two switch modules connected in series, and the horizontal bridge comprises at least two switch modules connected in series, each of the switch modules comprising a diode and a power switch connected in parallel with each other;

[0008] The T-type three-level inverter further comprises an inverter protection device, the inverter protection device comprising:

[0009] a first turn-off driving module electrically connected to the control end of the power switch of each of the switch modules on the vertical bridge;

[0010] a second turn-off driving module electrically connected to the control end of the power switch of each of the switch modules on the horizontal bridge;

[0011] The turn-off speed of the first turn-off driving module is configured to be greater than the turn-off speed of the second turn-off driving module.

[0012] a driving delay module for prolonging the turn-off time of each of the switch modules on the horizontal bridge, the driving delay module being connected in series with the second turn-off driving module;

[0013] a controller electrically connected to the driving delay module and the first turn-off driving module, respectively.

[0014] Preferably, the driving delay module comprises an RC filter circuit or an FPGA device.

[0015] Preferably, the first turn-off driving module comprises a first turn-off driving resistor, and the second turn-off driving module comprises a second turn-off driving resistor, the resistance value of the first turn-off driving resistor being smaller than the resistance value of the second turn-off driving resistor.

[0016] Preferably, the power switch is an insulated gate bipolar transistor or a MOS tube.

[0017] Preferably, the vertical bridge comprises a first switch module and a second switch module, and the horizontal bridge comprises a third switch module and a fourth switch module.

[0018] One end of the first switch module is connected to the positive input terminal, and the other end of the first switch module is connected to the output terminal.

[0019] One end of the second switch module is connected to the negative input terminal, and the other end of the second switch module is connected to the output terminal.

[0020] One end of the third switch module is connected to the neutral point, the other end of the third switch module is electrically connected to the fourth switch module, and the other end of the fourth switch module is connected to the output terminal.

[0021] Further, the first switch module comprises a first power switch and a first diode; the second switch module comprises a second power switch and a second diode;

[0022] The control end of the first power switch and the control end of the second power switch are electrically connected with the first off-driving module;

[0023] The cathode of the first diode is connected to the positive input terminal, and the anode of the second diode is connected to the negative input terminal;

[0024] The third switch module comprises a third power switch and a third diode; the fourth switch module comprises a fourth power switch and a fourth diode;

[0025] The control end of the third power switch and the control end of the fourth power switch are electrically connected with the second off-driving module;

[0026] The cathode of the third diode is connected to the neutral point, and the cathode of the fourth diode is connected to the output terminal.

[0027] Further, the gate of the first power switch and the gate of the second power switch are electrically connected with the first off-driving module; the collector of the first power switch is connected to the positive input terminal, and the emitter of the first power switch is connected to the output terminal; the collector of the second power switch is connected to the output terminal, and the emitter of the second power switch is connected to the negative input terminal; the gate of the third power switch and the gate of the fourth power switch are electrically connected with the second off-driving module; the collector of the third power switch is connected to the neutral point, and the emitter of the third power switch is connected to the fourth switch module; the collector of the fourth power switch is connected to the output terminal, and the emitter of the fourth power switch is connected to the third switch module.

[0028] Further, the first switch module and a first stray inductance are connected in series, one end of the first stray inductance is connected to the positive input terminal, and the other end of the first stray inductance is connected to the connection point of the first power switch and the first diode;

[0029] The second switch module and a second stray inductance are connected in series, one end of the second stray inductance is connected to the output terminal, and the other end of the second stray inductance is connected to the connection point of the second power switch and the second diode;

[0030] The third switch module and a third stray inductance are connected in series, one end of the third stray inductance is connected to the neutral point, and the other end of the third stray inductance is connected to the connection point of the third power switch and the third diode;

[0031] The fourth switch module and the fourth stray inductance are connected in series, one end of the fourth stray inductance is connected to the output terminal, and the other end of the fourth stray inductance is connected to the connection point of the fourth power switch and the fourth diode.

[0032] The inductance values of the first stray inductance, the second stray inductance, the third stray inductance and the fourth stray inductance are different.

[0033] Preferably, the inverter circuit further comprises a first voltage division capacitor and a second voltage division capacitor, one end of the first voltage division capacitor is connected to the positive input terminal, and the other end of the first voltage division capacitor is connected to the neutral point; one end of the second voltage division capacitor is connected to the negative input terminal, and the other end of the second voltage division capacitor is connected to the neutral point.

[0034] A control method of a T-type three-level inverter as described above, the inverter having a first working mode and a second working mode, the inverter being in the first working mode when the inverter is in a shutdown or abnormal fault state, the control method comprising:

[0035] S1, the controller determines whether the inverter is in the first working mode or the second working mode, if the inverter is in the first working mode, jump to step S2; if the inverter is in the second working mode, jump to step S17;

[0036] S2, the controller determines whether the modulation wave in the inverter circuit is in a positive half cycle, if yes, jump to step S3; if no, jump to step S10;

[0037] S3, the controller determines the current flow direction in the inverter circuit, if the current flows from the output terminal to the load, jump to step S4; if the current flows from the load to the output terminal, jump to step S7;

[0038] S4, the controller determines the opening and closing state of the power switch before the envelope time, if the first power switch and the second power switch are open, the third power switch and the fourth power switch are closed, jump to step S5; if the second power switch and the fourth power switch are open, the first power switch and the third power switch are closed, jump to step S6;

[0039] S5, the controller controls the third power switch and the fourth power switch to be open;

[0040] S6, the controller controls the first power switch to be open, after the delay module is driven to run, the controller controls the third power switch to be open;

[0041] S7, the controller determines the open and close state of the power switch before the sealing wave moment, if the first power switch and the second power switch are opened, the third power switch and the fourth power switch are closed, then jump to step S8; if the second power switch and the fourth power switch are opened, the first power switch and the third power switch are closed, then jump to step S9;

[0042] S8, the controller controls the third power switch and the fourth power switch to be opened;

[0043] S9, the controller controls the first power switch to be opened, and after the driving delay module is running, the controller controls the third power switch to be opened;

[0044] S10, the controller determines the current flow direction in the inverter circuit, if the current flows from the output terminal to the load, then jump to step S11; if the current flows from the load to the output terminal, then jump to step S14;

[0045] S11, the controller determines the open and close state of the power switch before the sealing wave moment, if the first power switch and the second power switch are opened, the third power switch and the fourth power switch are closed, then jump to step S12; if the first power switch and the third power switch are opened, the second power switch and the fourth power switch are closed, then jump to step S13;

[0046] S12, the controller controls the third power switch and the fourth power switch to be opened;

[0047] S13, the controller controls the second power switch to be opened, and after the driving delay module is running, the controller controls the fourth power switch to be opened;

[0048] S14, the controller determines the open and close state of the power switch before the sealing wave moment, if the first power switch and the second power switch are opened, the third power switch and the fourth power switch are closed, then jump to step S15; if the first power switch and the third power switch are opened, the second power switch and the fourth power switch are closed, then jump to step S16;

[0049] S15, the controller controls the third power switch and the fourth power switch to be opened;

[0050] S16, the controller controls the second power switch to be opened, and after the driving delay module is running, the controller controls the fourth power switch to be opened;

[0051] S17, the control strategy in the second working mode is executed.

[0052] Preferably, the control strategy in the second working mode comprises:

[0053] S171, the controller judges whether the modulation wave in the inverter circuit is in a positive half cycle, if yes, jump to step S172, if not, jump to step S173;

[0054] S172, the controller controls the third power switch to be closed, one of the first power switch and the fourth power switch to be opened, and the other to be closed;

[0055] S173, the controller controls the fourth power switch to be closed, one of the second power switch or the third power switch to be opened, and the other to be closed.

[0056] Due to the above technical scheme, the present application has the following advantages compared with the prior art:

[0057] In the T-type three-level inverter in the present application, the inverter protection device is arranged, the first turn-off driving module adjusts the turn-off of each switch module on the vertical bridge, the second turn-off driving module adjusts the turn-off of each switch module on the horizontal bridge, and the turn-off speed of the first turn-off driving module is greater than that of the second turn-off driving module. Whether the inverter is in the first working mode (the inverter is in the shutdown or abnormal fault state) or the second working mode (the inverter is in the normal working state without abnormal fault), the vertical pipe is configured to have a faster turn-off speed, which reduces the turn-off loss of the vertical pipe. Moreover, each switch module on the horizontal pipe is connected with the second turn-off driving module and a driving delay module in series, the instantaneous current on the horizontal pipe is small, the voltage stress generated by the commutation of the horizontal pipe on the vertical pipe is small when the horizontal pipe is turned off, the vertical pipe switching speed is maximized and the switching loss of the vertical pipe is reduced under the premise of meeting the voltage stress range of the device, and the use cost of the device is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0059] Figure 1 It is a topological graph of the inverter circuit of the T-type three-level inverter in the embodiment of the present application.

[0060] Figure 2 It is a control method flow chart of the T-type three-level inverter in the first working mode in the embodiment of the present application.

[0061] Figure 3A control method flow chart for the T-type three-level inverter in the second working mode in the embodiment of the present application;

[0062] Wherein, 01, inverter protection device; 02, inverter circuit; 11, positive input terminal; 12, negative input terminal; 21, output terminal; 22, bridge arm output inductor; 31, first voltage dividing capacitor; 32, second voltage dividing capacitor; 4, vertical bridge; 41, first switch module; 411, first power switch; 412, first diode; 413, first leakage inductor; 42, second switch module; 421, second power switch; 422, second diode; 423, second leakage inductor; 5, horizontal bridge; 51, third switch module; 511, third power switch; 512, third diode; 513, third leakage inductor; 52, fourth switch module; 521, fourth power switch; 522, fourth diode; 523, fourth leakage inductor; 6, neutral point; 7, first turn-off drive module; 8, second turn-off drive module; 9, controller; 10, drive delay module. DETAILED DESCRIPTION

[0063] The preferred embodiments of the present application will be described in detail with reference to the drawings, so that the advantages and features of the present application can be more easily understood by those skilled in the art. It should be noted that the description of the embodiments is used to help understand the present application, but does not constitute a limitation of the present application. In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0064] As Figure 1 described above, the T-type three-level inverter in the embodiment includes an inverter circuit 02, which has a positive input terminal 11, a negative input terminal 12, an output terminal 21, a vertical bridge 4 and a horizontal bridge 5 for connecting to a direct current. One end of the vertical bridge 4 is connected to the positive input terminal 11, and the other end of the vertical bridge 4 is connected to the negative input terminal 12. One end of the horizontal bridge 5 is connected to the neutral point 6 between the positive input terminal 11 and the negative input terminal 12, and the other end of the horizontal bridge 5 is connected to the output terminal 21. In the embodiment, the connection points of the vertical bridge 4 and the horizontal bridge 5 are connected to the output terminal 21 through a power output line. The positive input terminal 11 and the negative input terminal 12 are respectively connected to the front-end photovoltaic panel or Boost circuit, and the output terminal 21 is connected to the rear-end load.

[0065] The vertical bridge 4 in the embodiment includes two switch modules connected in series, and the horizontal bridge includes two switch modules connected in series, and each switch module includes a diode and a power switch connected in parallel with each other. The power switch is an insulated gate bipolar transistor (IGBT) or a MOS tube.

[0066] The T-type three-level inverter further comprises an inverter protection device 01, which comprises a first turn-off driving module 7, a second turn-off driving module 8, a controller 9 and a driving delay module 10. The first turn-off driving module 7 is electrically connected to the control end of the power switch of each switch module on the vertical bridge 4, and the second turn-off driving module 8 is electrically connected to the control end of the power switch of each switch module on the horizontal bridge 5. The turn-off speed of the first turn-off driving module 7 is configured to be greater than the turn-off speed of the second turn-off driving module 8. Specifically, the first turn-off driving module 7 comprises a first turn-off driving resistor, and the second turn-off driving module 8 comprises a second turn-off driving resistor, and the resistance value of the first turn-off driving resistor is less than the resistance value of the second turn-off driving resistor. In other embodiments, the first turn-off driving module 7 and the second turn-off driving module 8 can also comprise a gate-level parallel capacitor, which is not limited here.

[0067] The controller 9 is electrically connected to the driving delay module 10 and the first turn-off driving module 7, respectively. The controller 9 in the embodiment is a pulse width modulation (PWM) controller, and in other embodiments, it can also be a microcontroller unit (MCU) controller, which is not limited here.

[0068] The driving delay module 10 is arranged between the controller 9 and the first turn-off driving module 7, and is used to prolong the turn-off time of each switch module on the horizontal bridge 5. The driving delay module 10 in the embodiment is preferably an RC filter circuit, and can also be a field programmable gate array (FPGA). The delay time of the driving delay module 10 needs to be much lower than the dead time to avoid a large impact on the dead time, which leads to insufficient dead time. The delay time is set to meet the voltage stress target requirement, which is generally around hundreds of nanoseconds. It should be noted that if the driving delay module 10 is an RC filter circuit, the driving delay module 10 is always in working state whether the inverter is in normal working mode or shutdown or abnormal fault state. If the driving delay module 10 is implemented by an FPGA, the driving delay module 10 is in working state only when the inverter is in shutdown or abnormal fault state.

[0069] The vertical bridge 4 includes a first switch module 41 and a second switch module 42. One end of the first switch module 41 is connected to the positive input terminal 11, and the other end of the first switch module 41 is connected to the output terminal 21. One end of the second switch module 42 is connected to the negative input terminal 12, and the other end of the second switch module 42 is connected to the output terminal 21. The horizontal bridge 5 includes a third switch module 51 and a fourth switch module 52. One end of the third switch module 51 is connected to the neutral point 6, and the other end of the third switch module 51 and the fourth switch module 52 are electrically connected, and the other end of the fourth switch module 52 is connected to the output terminal 21.

[0070] The first switch module 41 includes a first power switch 411 and a first diode 412. The second switch module 42 includes a second power switch 421 and a second diode 422. The control end (gate) of the first power switch 411 and the control end of the second power switch 421 are electrically connected with the first shutdown drive module 7. The cathode of the first diode 412 is connected to the positive input terminal 11, and the anode of the first diode 412 is connected to the neutral point 6. The collector of the first power switch 411 is connected to the positive input terminal 11, and the emitter of the first power switch 411 is connected to the output terminal 21. The anode of the second diode 422 is connected to the negative input terminal 12, and the cathode of the second diode 422 is connected to the neutral point 6. The emitter of the second power switch 421 is connected to the negative input terminal 12, and the collector of the second power switch 421 is connected to the output terminal 21.

[0071] The third switch module 51 includes a third power switch 511 and a third diode 512. The fourth switch module 52 includes a fourth power switch 521 and a fourth diode 522. The control end of the third power switch 511 and the control end of the fourth power switch 521 are electrically connected with the second shutdown drive module 8. The cathode of the third diode 512 is connected to the neutral point 6, and the anode of the third diode 512 is connected to the fourth switch module 52. The collector of the third power switch 511 is connected to the neutral point 6, and the emitter of the third power switch is connected to the fourth switch module 52. The cathode of the fourth diode 522 is connected to the output terminal 21, and the anode of the fourth diode 522 is connected to the third switch module 51. The collector of the fourth power switch 512 is connected to the output terminal 21, and the emitter of the fourth power switch 512 is connected to the third switch module 51.

[0072] The first switch module 41 is further connected in series with a first stray inductance 413, one end of the first stray inductance 413 being connected to the positive input terminal 11, and the other end of the first stray inductance 413 being connected to a connection point of the first power switch 411 and the first diode 412. The second switch module 42 is further connected in series with a second stray inductance 423, one end of the second stray inductance 423 being connected to the output terminal 21, and the other end of the second stray inductance 423 being connected to a connection point of the second power switch 421 and the second diode 422. The third switch module 51 is further connected in series with a third stray inductance 513, one end of the third stray inductance 513 being connected to the neutral point 6, and the other end of the third stray inductance 513 being connected to a connection point of the third power switch 511 and the third diode 512. The fourth switch module 52 is further connected in series with a fourth stray inductance 523, one end of the fourth stray inductance 523 being connected to the output terminal 21, and the other end of the fourth stray inductance 523 being connected to a connection point of the fourth power switch 521 and the fourth diode 522. The inductance values of the first stray inductance 413, the second stray inductance 423, the third stray inductance 513 and the fourth stray inductance 523 are different. A bridge arm output inductance 22 is further provided on the power output line. It should be noted that the first stray inductance 413, the second stray inductance 423, the third stray inductance 513 and the fourth stray inductance 523 are parasitic inductances attached to conductors, and in actual applications, each stray inductance is integrated on each switch module.

[0073] The inverter circuit 02 of the T-type three-level inverter in the embodiment further comprises a first voltage dividing capacitor 31 and a second voltage dividing capacitor 32. One end of the first voltage dividing capacitor 31 is connected to the positive input terminal 11, and the other end of the first voltage dividing capacitor 31 is connected to the neutral point 6. One end of the second voltage dividing capacitor 32 is connected to the negative input terminal 12, and the other end of the second voltage dividing capacitor 32 is connected to the neutral point 6.

[0074] The embodiment also discloses a control method of the T-type three-level inverter. The inverter has a first working mode (the inverter is in a shutdown or abnormal fault state) and a second working mode (the inverter is in a normal working state without abnormal fault). If the inverter is in the first working mode and all the switch modules are clamped (the moment of switching from the second working mode to the first working mode), when the modulation wave is a positive half cycle (the third power switch 511 is closed and the second power switch 421 is opened), and the current is a positive current (flows from the output terminal 21 to the load), if the fourth power switch 521 is closed and the first power switch 411 is opened before the clamping moment (in the second working mode), then the third power switch 511 and the fourth power switch 521 are opened after the clamping moment (in the first working mode), the current commutation path is to the second diode 422 on the second switch module 42, and the first switch module 41 bears the total bus voltage and (dI / dt)*Lp on the second switch module 42, wherein dI / dt is the instantaneous current and Lp is the inductance value of the stray inductance. Because the turn-off speed of the third switch module 51 and the fourth switch module 52 is configured as slow turn-off, the instantaneous current dI / dt is reduced, (dI / dt)*Lp is small, and the total voltage stress on the first switch module 41 is small. If the fourth power switch 521 is opened and the first power switch 411 is closed before the clamping moment, because the third switch module 51 is connected to the drive delay module 10, the first power switch 411 is opened first, the current is commutated through the third power switch 511 and the fourth diode 522 first, and the total voltage stress under the commutation of the half bus voltage is small. When the delay of the drive delay module 10 ends (usually about a few hundred nanoseconds), the third power switch 511 is opened. Because of the slow turn-off, the instantaneous current is small, and the total voltage stress is small.

[0075] When the modulation wave is a positive half cycle (the third power switch 511 is closed and the second power switch 421 is opened), and the current is a negative current (flows from the load to the output terminal 21), if the fourth power switch 521 is closed and the first power switch 411 is opened before the clamping moment, then the third power switch 511 and the fourth power switch 521 are opened after the clamping moment, the current commutation path is to the first diode 412 of the first switch module 41, and the second switch module 42 bears the total bus voltage and (dI / dt)*Lp on the first switch module 41. Because the turn-off speed of the third switch module 51 and the fourth switch module 52 is configured as slow turn-off, the instantaneous current dI / dt is reduced, (dI / dt)*Lp is small, and the total voltage stress on the second switch module 42 is small. If the fourth power switch 521 is opened and the first power switch 411 is closed before the clamping moment, the first power switch 411 is opened after the clamping moment, and the delayed turn-off of the third power switch 511 does not produce commutation action, and no additional voltage stress is produced.

[0076] When the modulation wave is the negative half cycle (the fourth power switch 521 is closed and the first power switch 411 is opened), the current is the positive current (flows from the output terminal 21 to the load), if the third power switch 511 is closed and the second power switch 421 is opened before the clamping time, then the third power switch 511 and the fourth power switch 521 are opened after the clamping time, the current commutation path is to the second diode 422 of the second switch module 42, and the first switch module 41 bears the total bus voltage and (dI / dt)*Lp on the second switch module 42. Because the turn-off speed of the third switch module 51 and the fourth switch module 52 is configured to be slow turn-off, the instantaneous current dI / dt is reduced, (dI / dt)*Lp is small, and the total voltage stress on the first switch module 41 is small. If the third power switch 511 is opened and the second power switch 421 is closed before the clamping time, the second power switch 421 is opened after the clamping time, and the delayed opening of the fourth power switch 521 does not produce commutation action, and no additional voltage stress AVce (i.e. (dI / dt)*Lp) is generated.

[0077] When the modulation wave is the negative half cycle (the fourth power switch 521 is closed and the first power switch 411 is opened), the current is the positive current (flows from the output terminal 21 to the load), if the third power switch 511 is closed and the second power switch 421 is opened before the clamping time, then the third power switch 511 and the fourth power switch 521 are opened after the clamping time, the current commutation path is to the second diode 422 of the second switch module 42, and the first switch module 41 bears the total bus voltage and (dI / dt)*Lp on the second switch module 42. Because the turn-off speed of the third switch module 51 and the fourth switch module 52 is configured to be slow turn-off, the instantaneous current dI / dt is reduced, (dI / dt)*Lp is small, and the total voltage stress on the first switch module 41 is small. If the third power switch 511 is opened and the second power switch 421 is closed before the clamping time, the second power switch 421 is opened after the clamping time, and the delayed opening of the fourth power switch 521 does not produce commutation action, and no additional voltage stress AVce (i.e. (dI / dt)*Lp) is generated.

[0078] If the inverter is in the second working mode, when the modulation wave is in the positive half cycle, the first power switch 411 and the fourth power switch 521 are driven complementarily (that is, any one of the two is closed and the other is opened), and the third power switch 511 is always closed. When the external inductance current is positive current, the first power switch 411 is quickly turned off to generate a larger commutation dI / dt, but since the third power switch 511 is always closed, the commutation passes through the neutral point 6, and the total voltage stress of the first switch module 41 is half bus voltage plus (dI / dt)*Lp on the second switch module 42. Although △Vce is large, the total voltage stress is far below the specifications of each device on the first switch module 41. When the external inductance current is negative current, the first power switch 411 is opened and no commutation action is generated, and no excess voltage stress △Vce is generated.

[0079] When the modulation wave is in the negative half cycle, the third power switch 511 and the second power switch 421 are driven complementarily, and the fourth power switch 521 is always closed. When the external inductance current is negative current, the second power switch 421 is quickly turned off to generate a larger commutation dI / dt, that is, △Vce is large, but since the fourth power switch 521 is always closed, the commutation passes through the neutral point 6, and the total voltage stress of the second switch module 42 is half bus voltage plus (dI / dt)*Lp on the first switch module 41. Although △Vce is large, the total voltage stress is far below the specifications of each device on the second switch module 42. When the external inductance current is positive current, the second power switch 421 is opened and no commutation action is generated, and no excess voltage stress △Vce is generated.

[0080] It should be noted that the inductance values of the first stray inductance 413, the second stray inductance 423, the third stray inductance 513 and the fourth stray inductance 523 in the embodiment are not completely the same, and are represented by Lp for simplification.

[0081] In summary, in the T-type three-level inverter in the application, the inverter protection device is arranged, the first turn-off driving module adjusts the turn-off of each switch module on the vertical bridge, the second turn-off driving module adjusts the turn-off of each switch module on the horizontal bridge, and the turn-off speed of the first turn-off driving module is greater than that of the second turn-off driving module. Whether the inverter is in the first working mode (the inverter is in the shutdown or abnormal fault state) or the second working mode (the inverter is in the normal working state without abnormal fault), the vertical pipe is configured to have a faster turn-off speed, the turn-off loss is reduced, each switch module on the horizontal pipe is connected to the second turn-off driving module and is connected in series with the driving delay module, the instantaneous current on the horizontal pipe is small, the voltage stress generated by the commutation of the horizontal pipe on the vertical pipe is small, the switch speed of the vertical pipe is maximized and the switch loss of the vertical pipe is reduced under the premise of meeting the voltage stress range of the device, and the use cost of the device is reduced.

[0082] As shown in the specification and claims, the terms "comprise" and "include" only indicate the inclusion of the steps and elements explicitly identified, and these steps and elements do not constitute an exclusive list, and the method or device can also include other steps or elements. The term "and / or" used herein includes any combination of one or more related listed items.

[0083] It should be noted that, unless otherwise specified, when a certain feature is referred to as being "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. In addition, the up, down, left, right and other descriptions used in the present application are only relative to the mutual positional relationship of the components of the present application in the drawings.

[0084] The above embodiments are only to illustrate the technical concepts and characteristics of the present application, and are a preferred embodiment, the purpose of which is to enable those skilled in the art to understand the content of the present application and implement it, and cannot limit the protection scope of the present application. Any equivalent transformation or modification made according to the principle of the present application should be covered within the protection scope of the present application.

Claims

1. A T-type three-level inverter, comprising an inverter circuit, wherein the inverter circuit has a positive input terminal and a negative input terminal for receiving direct current power, and an output terminal, and further comprising: At least one vertical bridge and at least one horizontal bridge, one end of the vertical bridge is connected to the positive input terminal, and the other end of the vertical bridge is connected to the negative input terminal; one end of the horizontal bridge is connected to the neutral point between the positive input terminal and the negative input terminal, and the other end of the horizontal bridge is connected to the output terminal; the connection point between the vertical bridge and the horizontal bridge is connected to the output terminal; The vertical bridge includes at least two switch modules connected in series, and the horizontal bridge includes at least two switch modules connected in series, each of the switch modules includes a diode and a power switch connected in parallel; It is characterized in that the T-type three-level inverter further includes an inverter protection device, and the inverter protection device includes: a first shutoff drive module electrically connected to a control terminal of a power switch of each of the switch modules on the vertical bridge; a second shutdown driving module electrically connected to a control terminal of a power switch of each of the switch modules on the cross bridge; The shutoff speed of the first shutoff driving module is configured to be greater than the shutoff speed of the second shutoff driving module; a driving delay module, configured to extend the turn-off time of each of the switch modules on the cross bridge, wherein the driving delay module and the second turn-off driving module are connected in series; A controller is electrically connected to the driving delay module and the first shutoff driving module respectively.

2. The T-type three-level inverter according to claim 1, characterized in that: The driving delay module includes an RC filter circuit or an FPGA device.

3. The T-type three-level inverter according to claim 1, characterized in that: The first off-driving module includes a first off-driving resistor, the second off-driving module includes a second off-driving resistor, and the resistance of the first off-driving resistor is smaller than the resistance of the second off-driving resistor.

4. The T-type three-level inverter according to claim 1, characterized in that: The power switch is an insulated gate bipolar transistor or a MOS tube; the vertical bridge includes a first switch module and a second switch module; the horizontal bridge includes a third switch module and a fourth switch module; One end of the first switch module is connected to the positive input terminal, and the other end of the first switch module is connected to the output terminal; One end of the second switch module is connected to the negative input terminal, and the other end of the second switch module is connected to the output terminal; One end of the third switch module is connected to the neutral point, the other end of the third switch module is electrically connected to the fourth switch module, and the other end of the fourth switch module is connected to the output terminal.

5. The T-type three-level inverter according to claim 4, characterized in that: The first switch module includes a first power switch and a first diode; the second switch module includes a second power switch and a second diode; The control end of the first power switch and the control end of the second power switch are electrically connected to the first shutdown driving module; The cathode of the first diode is connected to the positive input terminal, and the anode of the second diode is connected to the negative input terminal; The third switch module includes a third power switch and a third diode; the fourth switch module includes a fourth power switch and a fourth diode; The control end of the third power switch and the control end of the fourth power switch are electrically connected to the second shutdown driving module; A cathode of the third diode is connected to the neutral point, and a cathode of the fourth diode is connected to the output terminal.

6. The T-type three-level inverter according to claim 5, characterized in that: The gate of the first power switch and the gate of the second power switch are electrically connected to the first shutdown driving module; the collector of the first power switch is connected to the positive input terminal, and the emitter of the first power switch is connected to the output terminal; the collector of the second power switch is connected to the output terminal, and the emitter of the second power switch is connected to the negative input terminal; the gate of the third power switch and the gate of the fourth power switch are electrically connected to the second shutdown driving module; the collector of the third power switch is connected to the neutral point, and the emitter of the third power switch is connected to the fourth switch module; the collector of the fourth power switch is connected to the output terminal, and the emitter of the fourth power switch is connected to the third switch module.

7. The T-type three-level inverter according to claim 5, characterized in that: The first switch module and the first stray inductor are connected in series, one end of the first stray inductor is connected to the positive input terminal, and the other end of the first stray inductor is connected to the connection point of the first power switch and the first diode; The second switch module and the second stray inductor are connected in series, one end of the second stray inductor is connected to the output terminal, and the other end of the second stray inductor is connected to the connection point of the second power switch and the second diode; The third switch module and the third stray inductor are connected in series, one end of the third stray inductor is connected to the neutral point, and the other end of the third stray inductor is connected to the connection point between the third power switch and the third diode; The fourth switch module and the fourth stray inductor are connected in series, one end of the fourth stray inductor is connected to the output terminal, and the other end of the fourth stray inductor is connected to the connection point of the fourth power switch and the fourth diode; The inductance values ​​of the first stray inductance, the second stray inductance, the third stray inductance, and the fourth stray inductance are different.

8. The T-type three-level inverter according to claim 1, characterized in that: The inverter circuit also includes a first voltage-dividing capacitor and a second voltage-dividing capacitor, one end of the first voltage-dividing capacitor is connected to the positive input terminal, and the other end of the first voltage-dividing capacitor is connected to the neutral point; one end of the second voltage-dividing capacitor is connected to the negative input terminal, and the other end of the second voltage-dividing capacitor is connected to the neutral point.

9. A control method for a T-type three-level inverter according to any one of claims 1 to 8, characterized in that: The inverter has a first operating mode and a second operating mode. When the inverter is in the first operating mode, the inverter is in a shutdown or abnormal fault state. The control method includes: S1. The controller determines whether the inverter is in the first working mode or the second working mode. If the inverter is in the first working mode, the controller jumps to step S2; if the inverter is in the second working mode, the controller jumps to step S17; S2, the controller determines whether the modulation wave in the inverter circuit is in the positive half cycle, if so, jumps to step S3; if not, jumps to step S10; S3, the controller determines the direction of current flow in the inverter circuit. If the current flows from the output terminal to the load, the process jumps to step S4; if the current flows from the load to the output terminal, the process jumps to step S7; S4. The controller determines the on / off status of the power switches before the wave blocking moment. If the first power switch and the second power switch are off and the third power switch and the fourth power switch are on, the controller jumps to step S5. If the second power switch and the fourth power switch are off and the first power switch and the third power switch are on, the controller jumps to step S6. S5, the controller controls the third power switch and the fourth power switch to be disconnected; S6. The controller controls the first power switch to be turned off. After the driving delay module finishes running, the controller controls the third power switch to be turned off. S7, the controller determines the on / off status of the power switches before the wave blocking moment. If the first power switch and the second power switch are off, and the third power switch and the fourth power switch are on, the controller jumps to step S8; if the second power switch and the fourth power switch are off, and the first power switch and the third power switch are on, the controller jumps to step S9. S8, the controller controls the third power switch and the fourth power switch to be disconnected; S9, the controller controls the first power switch to be turned off. After the driving delay module finishes running, the controller controls the third power switch to be turned off. S10, the controller determines the direction of current flow in the inverter circuit. If the current flows from the output terminal to the load, the controller jumps to step S11; if the current flows from the load to the output terminal, the controller jumps to step S14; S11, the controller determines the on / off status of the power switches before the wave blocking moment. If the first power switch and the second power switch are off, and the third power switch and the fourth power switch are on, the controller jumps to step S12; if the first power switch and the third power switch are off, and the second power switch and the fourth power switch are on, the controller jumps to step S13. S12, the controller controls the third power switch and the fourth power switch to be disconnected; S13, the controller controls the second power switch to be turned off. After the driving delay module finishes running, the controller controls the fourth power switch to be turned off. S14, the controller determines the on / off status of the power switches before the wave blocking moment. If the first power switch and the second power switch are off, and the third power switch and the fourth power switch are on, the controller jumps to step S15; if the first power switch and the third power switch are off, and the second power switch and the fourth power switch are on, the controller jumps to step S16. S15, the controller controls the third power switch and the fourth power switch to be disconnected; S16, the controller controls the second power switch to be turned off. After the driving delay module finishes running, the controller controls the fourth power switch to be turned off. S17: Execute the control strategy in the second working mode.

10. The control method of a T-type three-level inverter according to claim 9, characterized in that: The control strategy in the second working mode includes: S171, the controller determines whether the modulation wave in the inverter circuit is in the positive half cycle, if so, jumps to step S172; if not, jumps to step S173; S172: The controller controls the third power switch to be closed, so that one of the first power switch and the fourth power switch is opened and the other is closed; S173. The controller controls the fourth power switch to be closed, and one of the second power switch or the third power switch to be opened, and the other to be closed.

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