A low mismatch Class-AB output stage bias circuit

Abstract

This invention belongs to the field of analog integrated circuit technology, specifically to a Class-AB output stage bias circuit with low mismatch and stable output current, suitable for fully differential circuits. This invention provides a bias circuit for the Class-AB output stage with extremely low current mirror mismatch, overcoming the mismatch caused by channel length modulation. Furthermore, when the output common mode changes, the bias circuit can adapt accordingly, providing a new bias, thereby minimizing the impact of common-mode voltage changes on the output stage's quiescent current.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, and in particular relates to a Class-AB output stage bias circuit with low mismatch and stable output current suitable for fully differential circuits. Background Art

[0002] As the feature size of integrated circuits continues to decrease, the power supply voltage of the circuit is also gradually decreasing. For an operational amplifier, its output stage requires both a sufficiently large dynamic range and strong driving capability. Common output stage circuits include Class-A, Class-B, and Class-AB (also known as push-pull output stages). The IV characteristics of their outputs during operation are as follows: Figure 1 As shown in the figure, the quiescent current of a Class A amplifier is greater than its peak current during operation, allowing it to output a signal with extremely low distortion at any moment. However, its quiescent power consumption is excessive, resulting in low conversion efficiency, and therefore it is rarely used. A Class B amplifier has zero quiescent current, and the output transistors are biased at the edge of their cutoff state, resulting in extremely low quiescent power consumption. However, because the output current flows through each transistor only during half of the input cycle, the output waveform is not an exact replica of the input waveform, resulting in distortion. This distortion occurs at each zero-crossing of the input signal as the two transistors switch "ON" between them, resulting in a phenomenon commonly known as "crossover distortion." A Class AB amplifier offers the best compromise between current consumption and distortion. Its quiescent current is smaller than its peak current swing during operation, and when no input signal is present, both transistors are biased slightly on. This small bias setting ensures that both transistors conduct simultaneously during a small portion of the input waveform, exceeding 50% of the input cycle. This smooths the connection between the two half-waveforms and minimizes crossover distortion, making Class-AB output stages more common.

[0003] Figure 2 : This is a schematic diagram of the operational amplifier circuit module used in the present invention. The circuit is a three-stage fully differential operational amplifier. The first stage is a sleeve-type cascode structure that provides high gain and outputs ON1 and OP1 to the second stage. Since the common mode of the first-stage output is determined by an independent common-mode feedback circuit in this module, it does not affect the subsequent analysis and description and is therefore not shown here. Figure 3This is a schematic diagram of the second-stage and output-stage circuits of the fully differential operational amplifier used in the present invention. This circuit utilizes a push-pull output structure. Op amps designed with a Class-AB output stage can achieve a wide output range at a low quiescent current. This push-pull output structure allows the current during large-signal buildup to be unconstrained by the quiescent current, resulting in a better slew rate. However, since both the PMOS and NMOS outputs of the Class-AB design are controlled by the preceding stage's signal, compared to traditional structures where only the PMOS or NMOS output stage is controlled by the preceding stage's input signal, more complex biasing is required. A more classic approach is to have the output transistor gate voltage jointly biased by a pair of PMOS and NMOS transistors embedded in the preceding stage. This structure, also known as a "floating current source," acts approximately as a short circuit under small signals.

[0004] The gate bias of the conventional floating current source PMOS and NMOS can be provided by a transistor bias circuit connected in series with two diodes, such as Figure 4 As shown, a bias current of Ib (40uA in this example) flowing through two diode-connected transistors can generate a certain Vgs voltage drop. Using the two transistors in the bias circuit as unit transistors, Ib can be replicated with a certain mirror ratio to obtain the output stage quiescent current. However, this biasing method still has problems: because the output Vout is limited to VCM (usually 1 / 2VDD) by the common-mode feedback circuit CMFB, there is a large deviation between the source-drain voltage of the output transistor and the source-drain voltage of the mirror transistor (which is also its gate-source voltage). The channel length modulation effect of the transistor will cause a mismatch in the current replication, especially when the mirror ratio is large, where the mismatch is further amplified. At the same time, when Ib is independent and fixed, the traditional biasing method provides a fixed bias voltage that does not change with the common-mode voltage of the circuit. This also means that if the common-mode voltage changes, the mismatch caused by the channel length modulation effect will also change, which will bring greater uncertainty. Summary of the Invention

[0005] To address the shortcomings of the above-mentioned traditional Class-AB output stage bias circuit, the present invention proposes a low-mismatch bias circuit that can achieve near-complete replication of the output stage transistors and the bias circuit mirror transistors during operation, overcoming the current mismatch caused by the channel length modulation effect. At the same time, when the common-mode voltage changes, the bias circuit can be adjusted accordingly, making the output stage current less affected by the common-mode voltage change.

[0006] The technical solution of the present invention is:

[0007] A low mismatch Class-AB output stage bias circuit, Figure 5 A Class-AB output stage bias voltage generating circuit is presented, which is characterized by comprising a first bias voltage generating circuit and a second bias voltage generating circuit;

[0008] The first bias voltage generating circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first resistor, a second resistor and a third resistor; wherein, the source of the first PMOS transistor is connected to a power supply, and the gate and drain thereof are interconnected; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, and the gate of the first NMOS transistor is connected to a common mode voltage; the source of the second PMOS transistor is connected to a power supply, and the gate and drain thereof are interconnected; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the second NMOS transistor is connected to the drain of the fifth PMOS transistor; the drain of the third NMOS transistor is connected to the source of the first NMOS transistor and the source of the second NMOS transistor, and the gate of the third NMOS transistor is connected to a first external bias voltage; the drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor, and the gate of the fourth NMOS transistor is connected to the first external bias voltage The source of the fourth NMOS transistor is connected to ground after passing through the first resistor; the source of the third PMOS transistor is connected to the power supply, and the gate of the third PMOS transistor is connected to the drain of the second PMOS transistor; the source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, and the gate and drain of the fourth PMOS transistor are interconnected; the drain of the fifth NMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the fifth NMOS transistor is connected to the first external bias voltage; the drain of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor, and the gate of the sixth NMOS transistor is connected to the first external bias voltage, and the source of the sixth NMOS transistor is connected to ground after passing through the second resistor; the source of the fifth PMOS transistor is connected to the power supply, and the gate of the fifth PMOS transistor is connected to the drain of the third PMOS transistor; the drain of the seventh NMOS transistor is connected to the drain of the fifth PMOS transistor, and the gate of the seventh NMOS transistor is connected to the first external bias voltage; the drain of the eighth NMOS transistor is connected to the source of the seventh NMOS transistor, and the gate of the eighth NMOS transistor is connected to the first external bias voltage, and the source of the eighth NMOS transistor is connected to ground after passing through the third resistor; the drain of the fourth PMOS transistor is the output end of the first bias voltage generating circuit;

[0009] The second bias voltage generating circuit includes an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, and a thirteenth PMOS transistor; wherein the source of the eighth NMOS transistor is grounded, and its gate and drain are interconnected; the drain of the sixth PMOS transistor is connected to the drain of the eighth NMOS transistor, and the gate of the sixth PMOS transistor is connected to a common mode voltage; the source of the ninth NMOS transistor is grounded, and its gate and drain are interconnected; the drain of the seventh PMOS transistor is connected to the drain of the ninth NMOS transistor, and the gate of the eighth PMOS transistor is connected to the drain of the twelfth NMOS transistor; the drain of the eighth PMOS transistor is connected to the source of the sixth PMOS transistor and the source of the seventh PMOS transistor, and the gate of the eighth PMOS transistor is connected to the second external bias voltage; the drain of the ninth PMOS transistor is connected to the source of the eighth PMOS transistor, and the gate of the ninth PMOS transistor is connected to the third external bias voltage. The source of the ninth PMOS transistor is connected to a power supply; the source of the tenth NMOS transistor is grounded, and the gate of the tenth NMOS transistor is connected to the drain of the ninth NMOS transistor; the source of the eleventh NMOS transistor is connected to the drain of the tenth NMOS transistor, and the gate and drain of the eleventh NMOS transistor are interconnected; the drain of the tenth PMOS transistor is connected to the drain of the eleventh NMOS transistor, and the gate of the tenth PMOS transistor is connected to the second external bias voltage; the drain of the eleventh PMOS transistor is connected to the source of the tenth PMOS transistor, and the gate of the eleventh PMOS transistor is connected to the third external bias voltage, and the source of the eleventh PMOS transistor is connected to the power supply; the source of the twelfth NMOS transistor is grounded, and the gate of the twelfth NMOS transistor is connected to the drain of the tenth NMOS transistor; the drain of the twelfth PMOS transistor is connected to the drain of the twelfth NMOS transistor, and the gate of the twelfth PMOS transistor is connected to the second external bias voltage; the drain of the thirteenth PMOS transistor is connected to the source of the twelfth PMOS transistor, and the gate of the twelfth PMOS transistor is connected to the third external bias voltage, and the source of the twelfth PMOS transistor is connected to the power supply; the drain of the eleventh NMOS transistor is the output end of the second bias voltage generating circuit.

[0010] Beneficial effects of the present invention: The present invention provides a bias circuit with extremely low current mirror mismatch for a Class-AB output stage, overcoming the mismatch caused by the channel length modulation effect. At the same time, when the output common mode changes, the bias circuit can be adjusted accordingly to provide a new bias, so that the quiescent current of the output stage is less affected by the change of the common mode voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Schematic diagrams of IV waveforms of three common output stage circuits.

[0012] Figure 2 This is a schematic diagram of the operational amplifier circuit module used in the present invention.

[0013] Figure 3 This is a schematic diagram of the second stage and output stage circuits of the fully differential operational amplifier used in the present invention.

[0014] Figure 4 This is a schematic diagram of the traditional Class-AB output stage bias circuit.

[0015] Figure 5 This is a schematic diagram of a novel Class-AB output stage bias voltage generating circuit adopted by the present invention.

[0016] Figure 6 This is the simulation result of the output stage quiescent current change when the common-mode voltage changes under traditional bias.

[0017] Figure 7 This is the simulation result of the output stage static current change when the common mode voltage of the novel bias circuit adopted by the present invention changes.

[0018] Figure 8 The figure compares the output stage static current changes of the conventional bias circuit and the bias circuit of the present invention when the common mode voltage changes. DETAILED DESCRIPTION

[0019] The present invention is described in detail below with reference to the accompanying drawings.

[0020] because Figure 3 The mid-output stage is a fully differential and completely symmetrical structure, so only one side of the branch is used for illustration.

[0021] First, combine Figure 3 and Figure 4 Let's explain the principle of determining current in a traditional Class-AB output stage. The static gate voltages of the output-stage PMOS transistors Mp8 and Mn8 are controlled by a "floating current source" consisting of the NMOS transistors Mn6 and Mp2. Under static conditions, Mn6 and Mp2 are assumed to flow with the same current. When the secondary effects of the transistors are ignored, the currents of Mn6 and Mp2 in the saturated state are:

[0022]

[0023]

[0024] The gain factor μ is the carrier mobility of the MOS tube (electron mobility for NMOS tube and hole mobility for PMOS tube), C ox is the capacitance per unit area of ​​the gate oxide layer of the MOS tube (determined by the process), W / L is the width-to-length ratio of the MOS tube, so β ​​is determined by the process and the width-to-length ratio. Assuming that the threshold voltage remains unchanged, when the current flowing through the transistor is determined by the tail current source, the gate-source voltage Vgs can be determined.

[0025] The gate voltage of the PMOS tube Mp2 (i.e., the first bias voltage) is determined by Figure 4 The gate voltage of the PMOS tube Mp9 is given by the gate voltage of Mp2 minus the gate-source voltage Vgs. ，P The gate voltage of the NMOS transistor Mn6 (i.e., the second bias voltage) is given by Figure 4 The gate voltage of the NMOS tube Mn9 is given by the gate voltage of Mn6 minus the gate-source voltage Vgs. ，N That is its source voltage, that is, the gate voltage of the output stage NMOS tube Mn8.

[0026] if Figure 3 The PMOS tube Mp2 and Figure 4 The PMOS tubes Mp9 in the circuit are current mirrors of each other, that is, they use the same unit MOS tubes, and the ratio of the number of parallel connections is equal to the ratio of their static currents (1:1 in this example). Then the gate-source voltages they generate are the same. Since the gate terminals are connected together, the sum of the source voltages of the two is the same, that is, Figure 3 The output stage PMOS tube Mp8 and Figure 4 The gate voltage of the NMOS transistor Mp10 in the circuit is the same. At the same time, since the source terminals of both are connected to the power supply, the gate-source voltage Vgs of the two are also the same. If the same unit MOS transistor is used for both, according to the saturation region MOS transistor current formula, the ratio of the currents of the two is equal to the ratio of the number of parallel MOS transistors (here it is 12:1). Therefore, the static operating current of the output PMOS transistor Mp8 can be determined. Figure 3 The principle for determining the static operating current of the output stage NMOS tube Mn8 is the same as above. Therefore, Figure 3 Mp8 and Figure 4 Mp10 in, Figure 3 Mn8 and Figure 4 Although the gates of Mn10 are not connected together, they act as current mirrors to each other during static operation.

[0027] However, in reality, due to the existence of the channel length modulation effect of the transistor, the transistor current in the saturation state has the following relationship with the source-drain voltage:

[0028]

[0029] Where λ is the modulation factor, which is affected by the process and the channel length L. The shorter the channel length, the larger the modulation factor.

[0030] Observe the output tube and its "mirror tube". Their source voltage and gate voltage are the same. However, since the common mode voltage at the output is limited to VCM, if the current is to be completely mirrored, then Figure 3The source and drain voltages of the NMOS tube Mn6 and the PMOS tube Mp2 are both VCM. Obviously, this will cause Mn6 and Mp2 to be turned off, which means that in the working state, there must be a deviation in the drain voltage of the output tube and its "mirror tube". The difference in Vds will bring about a channel length modulation effect, which will cause a mismatch in the current mirror. This mismatch increases with the increase in the ratio of the number of parallel MOS tubes of the "mirror tube" to the number of output tubes.

[0031] In order to eliminate this error, the present invention proposes Figure 5 The circuit structure shown is used to generate Figure 3 The first bias voltage and the second bias voltage in.

[0032] The first bias voltage generating circuit is intended to Figure 3 PMOS tube Mp2 mirror in Figure 5 The PMOS tube Mp16 in Figure 3 PMOS tube Mp8 mirror in Figure 5 The PMOS tube MP17 in the Figure 3 Mp8 and Figure 5 The gate, source and drain voltages of Mp17 are the same.

[0033] The following describes the setting ideas for the first bias voltage:

[0034] like Figure 5 As shown in the first bias voltage generating circuit, the gate terminal of NMOS transistor Mn13 is the input common mode voltage VCM, and the gate terminal input of NMOS transistor Mn14 is connected to the drain terminal output of PMOS transistor Mp16. When balanced, Mn13 and Mn14 each share 1 / 2 of the tail current (10uA in this example). The branch current flowing through Mn13 and Mn14 passes through the diode-connected PMOS transistors Mp13 and Mp14 (here, Mp13 and Mp14 have exactly the same size) to generate a certain gate voltage V G,Mp , this voltage is used to bias the gate voltage of the PMOS tube Mp15 in the right branch, so that the current of Mp15 during operation is approximately Ib. The mirror PMOS tube Mp16 adopts a diode connection form and is connected in series below Mp15. According to the above analysis, when a certain current Ib flows through Mp16, a certain gate-source voltage will be generated. The gate voltage of Mp16 is set to the first bias voltage output by the circuit, which is given to Figure 3 At the same time, since the current flowing through the tube Mp2 is about 40uA (that is, one time Ib), it is only necessary to make Mp2 and Mp16 use 1:1 mirroring to obtain the same gate-source voltage Vgs. As a result, the source voltage of Mp2 and Mp16 is close to the same, that is, Figure 3 The output tube Mp8 and Figure 5The gate voltage of the "mirror tube" MP17 in the figure is the same, and the source voltage of both is VDD, which is also the same.

[0035] Now watch Figure 5 The tail current source of the branch where MP17 is located is set to Ib. In this example, the quiescent current of the Class-AB output stage is set to 12×Ib, so Figure 5 The mirror tube MP17 and Figure 3 The output tube Mp8 uses the same unit tube, and the ratio of parallel unit tubes is 1:12. Figure 5 The drain output of Mp17 is connected to the gate of NMOS tube Mn14, and the circuit forms a closed loop. Observing the circuit, it can be found that from the gate input of Mn14 to the drain output of Mp17, it can be considered that there are three common source outputs. Each common source output will reverse the signal polarity. Therefore, when the drain output of Mp17 is connected to the gate input of Mn14, a closed loop negative feedback is formed. Under the action of this feedback, the gate input voltages of Mn13 and Mn14 should be close to the same when the final balance is reached, that is, the drain voltage of Mp17 is clamped to VCM, and Figure 3 The drain output of MP8 is also clamped to VCM by the common mode feedback circuit CMFB. Figure 3 The output tube Mp8 and Figure 5 The gate, source, and drain voltages of the mirror tube MP17 are the same, and the output current in static state will also be close to the same, and the mirror error caused by the channel length modulation effect is greatly reduced.

[0036] The idea of ​​setting the second bias voltage is the same as the above principle. Figure 5 As shown, the gate terminal of PMOS tube Mp18 inputs the common mode voltage VCM, and the gate terminal input of PMOS tube Mp19 is connected to the drain terminal output of NMOS tube Mn25. When balanced, Mp18 and Mp19 each share 1 / 2 of the tail current (10uA in this example). The branch current flowing through Mp18 and Mp19 passes through the diode-connected NMOS tubes Mn21 and Mn22 (here Mn21 and Mn22 have exactly the same size) to generate a certain gate voltage V G,Mn , this voltage is used to bias the gate voltage of the NMOS transistor Mn23 in the right branch, so that the current of Mn23 during operation is approximately Ib. The mirror NMOS transistor Mn24 is connected in series above Mn23 using a diode. According to the above analysis, when a certain current Ib flows through Mn24, a certain gate-source voltage Vgs will be generated. The gate voltage of Mn4 is set to the second bias voltage of the output, which is given to Figure 3 At the same time, due to the flow through the gate end of the NMOS tube Mn6. Figure 3 The current of the NMOS tube Mn6 is about 40uA (that is, twice Ib), so we only need to make Figure 3 The NMOS tube Mn6 and Figure 6 The same gate-source voltage can be obtained by using a 1:1 mirror image of Mn24 in Figure 3 The source terminal of the NMOS tube Mn6 is connected to Figure 5 The voltage at the source terminal of Mn24 in the Figure 3 The output tube Mn8 and Figure 5 The gate voltage of the NMOS tube Mn25 in the same, the source terminals of both are grounded, and the voltage is the same. Figure 5 The tail current source of the branch where Mn25 is located is set to Ib. In this example, the quiescent current of the Class-AB output stage is set to 12×Ib, so Figure 5 The "mirror tube" Mn25 and Figure 3 The output tube Mn8 uses the same unit tube, and the ratio of parallel unit tubes is also 1:12. Figure 5 The drain output of the NMOS transistor Mn5 is connected to the gate of the PMOS transistor Mp19, and the circuit forms a closed loop. Observing the circuit, it can be found that from the input at the gate of Mp19 to the output at the drain of Mn25, it can be considered that there are three common source outputs. Each common source output will reverse the signal polarity. Therefore, when the drain output of Mn5 is connected to the gate of the PMOS transistor Mp19, a closed loop negative feedback is formed. Under the action of this feedback, the gate input voltages of Mp18 and Mp19 should be close to the same when the final balance is reached, that is, the drain voltage of Mn25 is clamped to VCM, and Figure 3 The drain output of Mn8 is also clamped to VCM by the common mode feedback circuit CMFB. Figure 3 The output tube Mn8 and Figure 5 The gate, source, and drain voltages of the mirror tube Mn25 are the same, and the output current in static state will also be nearly consistent.

[0037] Table 1 shows the comparison of the output stage static current simulation results of the traditional structure and the structure of the present invention under different mirror ratios. Table 1 shows the comparison of the output stage current obtained by the traditional bias and the present invention under different mirror ratios when the common mode voltage is determined.

[0038] Mirror tube bias current Ib (uA) Mirror ratio of mirror tube and output tube Iout(uA) Tradition 39.92 1：1 40.87 This structure 40.02 1：1 40.03 Tradition 39.92 1：6 245.2 This structure 40.02 1：6 240.2 Tradition 39.92 1：12 490.4 This structure 40.02 1：12 480.3

[0039] It can be seen that the mirror error of the structure of the present invention is only 0.01uA at a mirror ratio of 1:1. Even at a mirror ratio of 1:12, the difference from the ideal mirror ratio output current (480.24uA) is only 0.2uA, while the traditional structure has a current mismatch of more than 10uA at this time.

[0040] In the structure of the present invention, when the common mode voltage VCM changes upward by ΔVCM, through negative feedback, Figure 5The drain voltage of Mp16 will also produce a change of approximately ΔVCM. The specific analysis is: assuming that VCM suddenly changes upward by ΔVCM, the current flowing through Mn13 will increase, and the current flowing through Mn14 will decrease. The voltage drop generated by the diode load Mp13 will decrease, which is manifested as an increase in the gate voltage of Mp13 and Mp14. Mp14 is a single common-source transistor, so the output node, that is, the gate voltage of Mp16, will decrease. Since Mp16 is also a single common-source transistor, the drain output voltage (that is, the gate voltage of Mn14) will increase, and the current of the input transistor Mn14 branch will increase again. Under the continuous negative feedback, the input transistors Mn13 and Mn14 will eventually divide the current of the tail current source equally again, and the drain voltage of the mirror transistor Mp16 will be consistent with the drain voltage of the output transistor Mp8 again. Figure 5 The drain voltage of Mn25 will also become VCM+ΔVCM, which will not be repeated here.

[0041] Figure 6 and Figure 7 Schematic diagram of DC simulation results of the output stage quiescent current of the conventional structure and the structure of the present invention when the common mode voltage VCM change ΔVCM is within -400mV to +400mV. Figure 8 The two were compared side by side. Because the common-mode feedback structure CMFB connected to the output stage in this example is a source-follower type, the maximum downward change in VCM is approximately 400mV. The results show that within the same range, the conventional structure produces a change of 3.5uA, while the output stage quiescent current change of the present invention's structure is only 0.6uA.

[0042] Thus, the Class-AB output stage bias circuit of the present invention effectively solves the current mirror mismatch problem caused by the channel length modulation effect in the second-order effect of the transistor. When the common-mode voltage changes, the bias voltage can be adjusted in a timely manner so that the output stage current is less affected by the change in the common-mode voltage.

Claims

1. A low mismatch Class-AB output stage bias circuit, characterized in that: comprising a first bias voltage generating circuit and a second bias voltage generating circuit; The first bias voltage generating circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first resistor, a second resistor and a third resistor; wherein, the source of the first PMOS transistor is connected to a power supply, and the gate and drain thereof are interconnected; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, and the gate of the first NMOS transistor is connected to a common mode voltage; the source of the second PMOS transistor is connected to a power supply, and the gate and drain thereof are interconnected; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the second NMOS transistor is connected to the drain of the fifth PMOS transistor; the drain of the third NMOS transistor is connected to the source of the first NMOS transistor and the source of the second NMOS transistor, and the gate of the third NMOS transistor is connected to a first external bias voltage; the drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor, and the gate of the fourth NMOS transistor is connected to the first external bias voltage The source of the fourth NMOS transistor is connected to ground after passing through the first resistor; the source of the third PMOS transistor is connected to the power supply, and the gate of the third PMOS transistor is connected to the drain of the second PMOS transistor; the source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, and the gate and drain of the fourth PMOS transistor are interconnected; the drain of the fifth NMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the fifth NMOS transistor is connected to the first external bias voltage; the drain of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor, and the gate of the sixth NMOS transistor is connected to the first external bias voltage, and the source of the sixth NMOS transistor is connected to ground after passing through the second resistor; the source of the fifth PMOS transistor is connected to the power supply, and the gate of the fifth PMOS transistor is connected to the drain of the third PMOS transistor; the drain of the seventh NMOS transistor is connected to the drain of the fifth PMOS transistor, and the gate of the seventh NMOS transistor is connected to the first external bias voltage; the drain of the eighth NMOS transistor is connected to the source of the seventh NMOS transistor, and the gate of the eighth NMOS transistor is connected to the first external bias voltage, and the source of the eighth NMOS transistor is connected to ground after passing through the third resistor; the drain of the fourth PMOS transistor is the output end of the first bias voltage generating circuit; The second bias voltage generating circuit includes an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, and a thirteenth PMOS transistor; wherein the source of the eighth NMOS transistor is grounded, and its gate and drain are interconnected; the drain of the sixth PMOS transistor is connected to the drain of the eighth NMOS transistor, and the gate of the sixth PMOS transistor is connected to a common mode voltage; the source of the ninth NMOS transistor is grounded, and its gate and drain are interconnected; the drain of the seventh PMOS transistor is connected to the drain of the ninth NMOS transistor, and the gate of the eighth PMOS transistor is connected to the drain of the twelfth NMOS transistor; the drain of the eighth PMOS transistor is connected to the source of the sixth PMOS transistor and the source of the seventh PMOS transistor, and the gate of the eighth PMOS transistor is connected to the second external bias voltage; the drain of the ninth PMOS transistor is connected to the source of the eighth PMOS transistor, and the gate of the ninth PMOS transistor is connected to the third external bias voltage. The source of the ninth PMOS transistor is connected to a power supply; the source of the tenth NMOS transistor is grounded, and the gate of the tenth NMOS transistor is connected to the drain of the ninth NMOS transistor; the source of the eleventh NMOS transistor is connected to the drain of the tenth NMOS transistor, and the gate and drain of the eleventh NMOS transistor are interconnected; the drain of the tenth PMOS transistor is connected to the drain of the eleventh NMOS transistor, and the gate of the tenth PMOS transistor is connected to the second external bias voltage; the drain of the eleventh PMOS transistor is connected to the source of the tenth PMOS transistor, and the gate of the eleventh PMOS transistor is connected to the third external bias voltage, and the source of the eleventh PMOS transistor is connected to the power supply; the source of the twelfth NMOS transistor is grounded, and the gate of the twelfth NMOS transistor is connected to the drain of the tenth NMOS transistor; the drain of the twelfth PMOS transistor is connected to the drain of the twelfth NMOS transistor, and the gate of the twelfth PMOS transistor is connected to the second external bias voltage; the drain of the thirteenth PMOS transistor is connected to the source of the twelfth PMOS transistor, and the gate of the twelfth PMOS transistor is connected to the third external bias voltage, and the source of the twelfth PMOS transistor is connected to the power supply; the drain of the eleventh NMOS transistor is the output end of the second bias voltage generating circuit.

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