Wireless Communication Co-Processing Method Applied to Gateway Device and Gateway Device

Abstract

The present application provides a wireless communication co - processing method applied to a gateway device and the gateway device. The wireless communication co - processing method is applied to the gateway device, and the gateway device includes a first communication chip and a second communication chip based on a first communication protocol. The computing power of the first communication chip is greater than that of the second communication chip. The wireless communication co - processing method includes: the second communication chip encapsulates the signal received by the terminal into a data frame based on the physical layer and the MAC control sub - layer in the first communication protocol stack, and sends the data frame to the first communication chip; and the first communication chip encapsulates the data frame based on the other layers in the first communication protocol stack except the physical layer and the MAC control sub - layer, and sends the encapsulated data packet to the target network. This can improve the gateway performance.

Description

Technical Field

[0001] The present invention relates to the technical field of the Internet of Things, and in particular to a wireless communication co - processing method applied to a gateway device and the gateway device. Background Art

[0002] As an application device in the transmission layer of Internet of Things technology, the underlying logic of the Internet of Things gateway is to connect various sensing devices / electrical signals to the gateway through wired interfaces (I2C, USB, RS232, Ethernet, etc.) or wireless (WIFI, Bluetooth, ZigBee, OpenThread, etc.) to collect data / information and convert the collected information into useful information through the core device of the gateway and then upload it to the Internet side. It can also combine with the intelligent processing layer to realize automatic device control. Currently, the performance of some gateway devices still needs to be improved. Summary of the Invention

[0003] This application provides a wireless communication co - processing method applied to a gateway device and the gateway device, which can improve the performance of the gateway device.

[0004] This application provides a wireless communication co - processing method applied to a gateway device. The wireless communication co - processing method is applied to a gateway device, which includes a first communication chip and a second communication chip based on a first communication protocol. The computing power of the first communication chip is greater than that of the second communication chip. The wireless communication co - processing method includes:

[0005] The second communication chip encapsulates the signal received from the terminal into a data frame based on the physical layer and the MAC control sub - layer in the first communication protocol stack, and sends the data frame to the first communication chip; and

[0006] The first communication chip encapsulates the data frame based on the other layers in the first communication protocol stack except the physical layer and the MAC control sub - layer, and sends the encapsulated data packet to the target network.

[0007] Further, the encapsulating the signal received from the terminal into a data frame and sending the data frame to the first communication chip includes:

[0008] The second communication chip encapsulates the data frame based on the inter - chip communication protocol and sends the encapsulated data frame to the first communication chip;

[0009] The encapsulating the data frame based on the other layers in the first communication protocol stack except the physical layer and the MAC control sub - layer includes:

[0010] The first communication chip unpacks the received data frame based on the communication protocol between the chips, and encapsulates the unpacked data frame based on the other layers in the first communication protocol stack except the physical layer and the MAC control sublayer.

[0011] Further, the communication protocol between the chips includes the Spinel protocol.

[0012] Further, an Internet of Things operating system is compiled in the second communication chip, and the physical layer and the MAC control sublayer in the first communication protocol stack are integrated into the Internet of Things operating system.

[0013] Further, the Internet of Things operating system includes a real-time operating system.

[0014] Further, sending the encapsulated data packet includes:

[0015] Among multiple network connection methods between the gateway device and the target network, determine the target network connection method, where the network performance of connecting to the target network through the target network connection method is better than that of connecting to the target network through other network connection methods;

[0016] Send the encapsulated data packet to the target network through the target network connection method.

[0017] Further, the gateway device is an Internet of Things gateway device; and / or

[0018] The first communication protocol is an IP-based wireless network protocol.

[0019] Further, the first communication protocol is the OpenThread protocol.

[0020] This application provides a gateway device, which includes a first communication chip and a second communication chip based on a first communication protocol. The computing power of the first communication chip is greater than that of the second communication chip, where:

[0021] The second communication chip is used to encapsulate the signal received from the terminal into a data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, and send the data frame to the first communication chip;

[0022] The first communication chip is used to encapsulate the data frame based on the other layers in the first communication protocol stack except the physical layer and the MAC control sublayer, and send the encapsulated data packet.

[0023] Further, the gateway device is an Internet of Things gateway device; and / or

[0024] The first communication protocol is an IP-based wireless network protocol.

[0025] Furthermore, the first communication protocol is the OpenThread protocol.

[0026] In some embodiments of the present application, in the wireless communication protocol processing method of the present application, the protocol stack core of the first communication protocol stack (such as the OpenThread protocol stack) runs on the first communication chip with relatively strong computing power, and only the MAC control sub-layer and the physical layer run on the second communication chip. Based on the relatively strong computing power of the first communication chip, the performance of the gateway device can be significantly improved, such as throughput performance and the number of connectable terminals. Description of the Drawings

[0027] Figure 1 is a circuit block diagram of a gateway circuit provided by an embodiment of the present application;

[0028] Figure 2 is Figure 1 a circuit diagram of the power supply circuit included in the gateway circuit in

[0029] Figure 3 is a schematic diagram of a gateway device provided by an embodiment of the present application;

[0030] Figure 4 is a flowchart of a wireless communication protocol processing method provided by an embodiment of the present application;

[0031] Figure 5 is a software architecture block diagram of a gateway device provided by an embodiment of the present application;

[0032] Figure 6 is a flowchart of a wireless communication protocol processing method provided by an embodiment of the present application;

[0033] Figure 7 is a flowchart of a data transmission method provided by an embodiment of the present application;

[0034] Figure 8 is a schematic structural diagram of a gateway device provided by an embodiment of the present application. Detailed Description of the Embodiments

[0035] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with one or more embodiments of this specification. On the contrary, they are merely examples of devices and methods consistent with some aspects of one or more embodiments of this specification as detailed in the appended claims.

[0036] It should be noted that: in other embodiments, the steps of the corresponding method are not necessarily executed in the order shown and described in this specification. In some other embodiments, the steps included in the method may be more or less than those described in this specification. In addition, a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may also be combined into a single step for description in other embodiments.

[0037] Figure 1 It is a circuit block diagram of a gateway circuit 100 provided by an embodiment of the present application.

[0038] See Figure 1 , the gateway circuit 100 includes a communication circuit 13, a first communication chip 11, and a second communication chip 12. Among them, the communication circuit 13 includes a first communication circuit 130 for information interaction with the target network, and a second communication circuit 134 for information interaction with the terminal. The first communication chip 11 includes a first port UART1 and a first operation processing unit 110 connected to the first port UART1, and the first operation processing unit 110 is connected to the first communication circuit 130. The second communication chip 12 includes a second port UART2 and a second operation processing unit 120 connected to the second port UART2, the second operation processing unit 120 is connected to the second communication circuit 134, the first port UART1 is connected to the second port UART2, and the computing power of the first operation processing unit 110 is greater than that of the second operation processing unit 120, that is, the computing power of the first communication chip 11 is greater than that of the second communication chip 12. The signal received by the second communication circuit 134 from the terminal is processed by the second operation processing unit 120 and the first operation processing unit 110 and then sent to the target network through the first communication circuit 130.

[0039] In some embodiments, the target network may be the Internet.

[0040] In some embodiments, the first operation processing unit 110 and the second operation processing unit 120 include resources such as a CPU and storage, so that an embedded operating system can be compiled in the first operation processing unit 110 and the second operation processing unit 120, and then a communication protocol stack can be integrated through the embedded operating system. For specific details, please refer to the subsequent relevant descriptions and will not be elaborated here.

[0041] In some embodiments, the second communication chip 12 is a chip based on a first communication protocol. Specifically, the first communication protocol may be an IP-based wireless network protocol. In this embodiment, the first communication protocol is the OpenThread protocol. The second communication chip 12 can establish a wireless connection with terminals of the OpenThread network and perform information interaction with these terminals.

[0042] In some embodiments, the first port UART1 and the second port UART2 are serial interfaces. The first communication chip 11 and the second communication chip 12 communicate based on a communication protocol between chips. Specifically, the communication protocol between chips includes the Spinel protocol. A signal received by the second communication circuit 134 from a terminal is partially processed by the second operation processing unit 120. The second communication chip 12 sends the signal processed by the second operation processing unit 120 to the first communication chip 11 based on the Spinel protocol. After the first operation processing unit 110 further processes the signal, it is sent to the target network through the first communication circuit 130. Among them, the first operation processing unit 110 and the second operation processing unit 120 process the signal based on an integrated communication protocol stack. For specific details, refer to the subsequent related descriptions and will not be elaborated here.

[0043] In some embodiments of the present application, the gateway circuit 100 includes two communication chips. Both communication chips include operation processing units, and the computing power of the first communication chip 11 is greater than that of the second communication chip 12. This enables, after the second communication circuit 134 receives a signal from a terminal, that not all processing of the signal needs to be completed by the second communication chip 12. Instead, the second communication chip 12 can complete partial processing of the signal and then send it to the first communication chip 11 with better computing power for continued processing, thereby improving the performance of the gateway circuit 100, such as throughput performance and the number of connectable terminals.

[0044] In some embodiments, the first communication circuit 130 includes a plurality of different communication sub-circuits 131, 132, 133. The plurality of different communication sub-circuits 131, 132, 133 are respectively connected to the first operation processing unit 110. After a signal received by the second communication circuit 134 from a terminal is processed by the second operation processing unit 120 and the first operation processing unit 110, it is sent to the target network through one of the communication sub-circuits 131, 132, 133.

[0045] In some embodiments, the communication sub-circuits 131, 132, 133 include at least one of a WiFi communication sub-circuit 131, a 4G communication sub-circuit 132, and an Ethernet communication sub-circuit 133. In this embodiment, the communication sub-circuits 131, 132, 133 include a WiFi communication sub-circuit 131, a 4G communication sub-circuit 132, and an Ethernet communication sub-circuit 133.

[0046] In some embodiments, the first communication chip 11 includes an IPEX interface. The WiFi communication sub-circuit 131 includes a WiFi radio frequency circuit 1311 and a WiFi antenna 1312. The WiFi radio frequency circuit 1311 is built into the first communication chip 11 and is connected to the first arithmetic processing unit 110. The WiFi antenna 1312 is disposed outside the first communication chip 110, and the WiFi radio frequency circuit 1311 and the WiFi antenna 1312 are connected through the IPEX interface. The signal output by the first arithmetic processing unit 110 can be sent to the target network through the WiFi radio frequency circuit 1311 and the WiFi antenna 1312.

[0047] In some embodiments, the first communication chip 11 includes a USB interface. The 4G communication sub-circuit 132 is disposed outside the first communication chip 11 and includes a 4G antenna 1322 and a 4G radio frequency circuit 1321. The 4G antenna 1322 is connected to the 4G radio frequency circuit 1321, and the 4G radio frequency circuit 1321 is connected to the first arithmetic processing unit 110 through the USB interface. The signal output by the first arithmetic processing unit 110 can be sent to the target network through the 4G radio frequency circuit 1321 and the 4G antenna 1322.

[0048] In some embodiments, the first communication chip 11 includes a WAN interface and a LAN interface. The Ethernet communication sub-circuit 133 is built into the first communication chip 11 and is respectively connected to the WAN interface, the LAN interface, and the first arithmetic processing unit 110. The WAN interface is used to connect to the target network, such as the Internet. The signal output by the first arithmetic processing unit 110 can be sent to the target network through the Ethernet communication sub-circuit 133 and the WAN interface.

[0049] In some embodiments, the second communication circuit 134 includes an OpenThread antenna 1342 and an OpenThread radio frequency circuit 1341. The OpenThread antenna 1342 is disposed outside the second communication chip 12, the OpenThread radio frequency circuit 1341 is built into the second communication chip 12, the OpenThread antenna 1342 is connected to the OpenThread radio frequency circuit 1341, and the OpenThread radio frequency circuit 1341 is connected to the second arithmetic processing unit 120. The second communication chip 12 can receive the terminal signals of the OpenThread network through the OpenThread antenna 1342 and the OpenThread radio frequency circuit 1341.

[0050] In some embodiments, the above-mentioned WiFi radio frequency circuit 1311, 4G radio frequency circuit 1321, and OpenThread radio frequency circuit 1341 include baseband circuits, radio frequency circuits, etc. for processing wireless signals.

[0051] In some embodiments, the first communication chip 11 is an MTK system-on-chip, and the second communication chip 12 is an nRF system-on-chip. In the subsequent description of this application, the MTK system-on-chip and the nRF system-on-chip are taken as examples for illustration.

[0052] In some embodiments, the gateway circuit 100 includes a power supply circuit 17. The power supply circuit 17 is respectively connected to the communication circuit 13, the first communication chip 11, and the second communication chip 12, and is used to supply power to the communication circuit 13, the first communication chip 11, and the second communication chip 12.

[0053] Figure 2 is Figure 1 The circuit diagram of the power supply circuit 17 included in the gateway circuit 100 in

[0054] The power supply circuit 17 includes a power input terminal 1701, a power output terminal 1702, a switch circuit 171, a voltage regulation circuit 172, and a power supply terminal 1724. The switch circuit 171 is connected between the power input terminal 1701 and the power output terminal 1702, and the voltage regulation circuit 172 is connected between the power output terminal 1702 and the power supply terminal 1724. The power input terminal 1701 is used to connect to a power supply. The switch circuit 171 is used to control the on / off between the power input terminal 1701 and the power output terminal 1702. When the power input terminal 1701 and the power output terminal 1702 are connected, the voltage regulation circuit 172 converts the voltage output by the power supply into a power supply voltage to supply power to the communication circuit 13, the first communication chip 11, and the second communication chip 12.

[0055] Further, the switch circuit 171 includes a controller 1711, a transistor switch Q1, a triode switch Q2, a control switch S1, a voltage terminal 1703, a first diode D1, a second diode D2, a first voltage-dividing resistor R5, a second voltage-dividing resistor R6, a third voltage-dividing resistor R2, a fourth voltage-dividing resistor R1, and a fifth voltage-dividing resistor R4, where:

[0056] The source and drain of the transistor switch Q1 are connected between the power input terminal 1701 and the power output terminal 1702. The gate of the transistor switch Q1 is grounded through the control switch S1 and the triode switch Q2 respectively. The anode of the first diode D1 is connected to the power input terminal 1701 and the gate of the transistor switch Q1, and the cathode of the first diode D1 is grounded through the control switch S1. The voltage terminal 1703 is connected to the power supply terminal 1724. The first voltage dividing resistor R5 and the second voltage dividing resistor R6 are connected in series between the voltage terminal 1703 and the ground. The first voltage dividing resistor R5 is connected between the voltage terminal 1703 and the second voltage dividing resistor R6. The anode of the second diode D2 is connected between the voltage terminal 1703 and the first voltage dividing resistor R5, and the cathode of the second diode D2 is grounded through the control switch S1. The controller 1711 includes a control input terminal POWER_KEY_IN and a control output terminal POWER_ON. The control input terminal POWER_KEY_IN is connected between the first voltage dividing resistor R5 and the second voltage dividing resistor R6, and the control output terminal POWER_ON is connected to the base of the triode switch Q2. The third voltage dividing resistor R2 and the fourth voltage dividing resistor R1 are connected in series between the power input terminal 1701 and the ground. The anode of the first diode D1 and the gate of the transistor switch Q1 are connected between the third voltage dividing resistor R2 and the fourth voltage dividing resistor R1. The fifth voltage dividing resistor R4 is connected in series between the voltage terminal 1703 and the first voltage dividing resistor R5, and the anode of the second diode D2 is connected between the first voltage dividing resistor R5 and the fifth voltage dividing resistor R4.

[0057] In this embodiment, the voltage regulation circuit 172 includes a first voltage regulation circuit 1721, a second voltage regulation circuit 1722, and a third voltage regulation circuit 1723. The voltage input from the power input terminal 1701 is 12V. The first voltage regulation circuit 1721 is connected to the power output terminal 1702, and the second voltage regulation circuit 1722 and the third voltage regulation circuit 1723 are respectively connected to the output terminal of the first voltage regulation circuit 1721. When the power input terminal 1701 and the power output terminal 1702 are connected, the first voltage regulation circuit 1721 converts the 12V voltage into a 5V voltage; the second voltage regulation circuit 1722 converts the 5V voltage into a 3.3V voltage and outputs it through the corresponding power supply terminal 1724; the third voltage regulation circuit 1723 converts the 5V voltage into a 3.6V voltage and outputs it through the corresponding power supply terminal 1724. In this way, it supplies power to the communication circuit 13, the first communication chip 11, and the second communication chip 12 with different power supply requirements.

[0058] Here, taking the voltage terminal 1703 connected to the power supply terminal 1724 of the second voltage regulation circuit 1722 as an example to illustrate the working principle of the power supply circuit 17. Assume that the transistor switch Q1 is a P-type transistor and the triode Q2 is an NPN-type triode.

[0059] Press the control switch S1 and hold it for a few seconds. The first diode D1 conducts, and the second diode D2 is in the cut-off state. The gate of the transistor switch Q1 is grounded through the first diode D1, and the gate voltage of the transistor switch Q1 is at a low level. The transistor switch Q1 conducts, and the voltage output from the power output terminal 1702 is 12V. The first voltage regulation circuit 1721 converts the 12V voltage into a 5V voltage; the second voltage regulation circuit 1722 converts the 5V voltage into a 3.3V voltage. By reasonably setting the resistance values of the resistors R4, R5, and R6, the 3.3V voltage can be divided by the resistors R4, R5, and R6 to raise the potential of the control input terminal POWER_KEY_IN to a high level. The controller 1711 can be set to: when the potential of the control input terminal POWER_KEY_IN is at a high level, make the control output terminal POWER_ON output a high level. In this way, the triode switch Q2 conducts. At this time, release the control switch S1. The gate voltage of the transistor switch Q1 is the divided voltage of the resistors R1 and R2. By reasonably setting the resistance values of the resistors R1 and R2, the gate of the transistor switch Q1 can be kept at a low level, that is, even if the transistor switch Q1 is in the conducting state. At this time, the communication circuit 13, the first communication chip 11, and the second communication chip 12 in the gateway circuit 100 are powered on and work.

[0060] Press the control switch S1 again and hold it for a few seconds. At this time, the second diode D2 conducts, and the potential of the control input terminal POWER_KEY_IN is pulled down to a low level. The controller 1711 can be set to: when the potential of the control input terminal POWER_KEY_IN is at a low level, make the control output terminal POWER_ON output a low level. At this time, the triode switch Q2 turns off, and the transistor switch Q1 turns off. At this time, the communication circuit 13, the first communication chip 11, and the second communication chip 12 in the gateway circuit 100 are powered off and stop working.

[0061] Figure 3 It is a schematic diagram of the gateway device 200 provided by an embodiment of the present application.

[0062] See Figure 3 The gateway device 200 includes a gateway circuit 100.

[0063] In some embodiments, the gateway device 200 is an Internet of Things gateway device. Specifically, the Internet of Things gateway device is a gateway device based on the OpenThread protocol. The above power supply circuit 17 can provide a hard start mode for the gateway device 200.

[0064] The working principle of the gateway device 200 will be described below.

[0065] Figure 4 It is a flowchart of a wireless communication co-processing method provided by an embodiment of the present application. Figure 5It is a software architecture block diagram of the gateway device 200 provided by an embodiment of the present application.

[0066] Refer to Figure 4 and Figure 5 , the wireless communication co-processing method can be applied to the gateway device 200, including step S41 and step S42.

[0067] In step S41, the second communication chip 12 encapsulates the signal received from the terminal into a data frame based on the physical layer and the MAC control sub-layer in the first communication protocol stack, and sends the data frame to the first communication chip 11.

[0068] In some embodiments, the first communication protocol stack includes an IP-based wireless network protocol stack. Specifically, the first communication protocol stack can be an OpenThread protocol stack. Taking the OpenThread protocol stack as an example, the following describes how to integrate the physical layer and the MAC control sub-layer in the first communication protocol stack in the second communication chip 12.

[0069] In some embodiments, the second communication chip 12 can be a chip with a standard network architecture, such as an nRF system-on-chip. By compiling the Internet of Things operating system in the second communication chip 12, the physical layer and the MAC control sub-layer in the first communication protocol stack can be integrated into the Internet of Things operating system. Here, integrating the physical layer and the MAC control sub-layer in the first communication protocol stack into the Internet of Things operating system means selectively integrating only the physical layer and the MAC control sub-layer in the first communication protocol stack in the second communication chip 12, and not integrating other layers except the physical layer and the MAC control sub-layer.

[0070] In some embodiments, the Internet of Things operating system may include a real-time operating system. Specifically, the real-time operating system may further include the Zephyr embedded real-time operating system. The MAC control sublayer in the OpenThread protocol stack and the IEEE 802.15.4 radio driver of Nordic nRF (i.e., the physical layer of the OpenThread protocol stack) can be integrated based on the L2 network technology layer of the Zephyr embedded real-time operating system. In some embodiments, the RX connection of the IEEE 802.15.4 radio driver is established through an interrupt handler. The interrupt handler is registered using the mechanism of Zephyr. The registered interrupt handler uses the FIFO of Zephyr to transfer the frames of the IEEE 802.15.4 radio driver. The RX connection of the IEEE 802.15.4 radio driver runs with the highest cooperation priority and waits for this FIFO. When a new frame appears, the thread continues to process. The TX connection of the IEEE 802.15.4 radio driver uses a work queue, which calls the IEEE 802.15.4 radio driver to schedule the transmission and then sends the frame using the RTC IRQ. In this way, the embedded porting (i.e., integration) of OpenThread in the Zephyr embedded real-time operating system is achieved. And CMake rules are defined in the porting development to implement the abstract layer interface of OpenThread and verify the hardware ports of the second communication chip 12. For Figure 5 the software architecture box Zephyr intergration of the second communication chip 12 represents the integrated part of the Zephyr embedded real-time operating system described above running in the second communication chip 12; the software architecture boxes OpenthreadController and IEEE 802.15.4PHY represent the MAC control sublayer in the integrated OpenThread protocol stack in the Zephyr embedded real-time operating system and the IEEE 802.15.4 radio driver of Nordic nRF (i.e., the physical layer of the OpenThread protocol stack) respectively, and the software architecture box Multiprotocol Severvice layer represents the IEEE802.15.4 multi-protocol service library.

[0071] In some embodiments, integrating the MAC control sublayer in the OpenThread protocol stack and the IEEE 802.15.4 radio driver of Nordic nRF based on the L2 network technology layer of the Zephyr embedded real-time operating system enables the terminals of the OpenThread network connected to the gateway device 200 to selectively use the IP protocol stack of Zephyr or directly use the OpenThread API and the IPv6 protocol stack.

[0072] In some embodiments, the above-mentioned Zephyr embedded real-time operating system, as well as the MAC control sublayer and the physical layer in the OpenThread protocol stack, can run in Figure 1 the second arithmetic processing unit 120. The second arithmetic processing unit 120 includes hardware resources such as a CPU and storage, providing hardware support for compiling the Zephyr embedded real-time operating system in the second communication chip 12 and integrating the MAC control sublayer and the physical layer in the OpenThread protocol stack.

[0073] Further, in some embodiments, the above-mentioned encapsulating the signal received from the terminal into a data frame and sending the data frame to the first communication chip 11 includes:

[0074] The second communication chip 12 encapsulates the data frame based on the inter-chip communication protocol and sends the encapsulated data frame to the first communication chip 11. Among them, the inter-chip communication protocol includes the Spinel protocol. That is, the second communication chip 12 encapsulates the data frame based on the Spinel protocol. In Figure 5 it, the software architecture box Spinel of the second communication chip 12 means that the second communication chip 12 encapsulates the data frame based on the Spinel protocol and then sends the encapsulated data frame to the first communication chip 11 through the serial interface.

[0075] Step S42, the first communication chip 11 encapsulates the data frame based on the other layers except the physical layer and the MAC control sublayer in the first communication protocol stack and sends the encapsulated data packet to the target network.

[0076] In some embodiments, taking the first communication protocol stack as the OpenThread protocol stack and the first communication chip 11 as an MTK chip as an example. The other layers except the physical layer and the MAC control sublayer in the OpenThread protocol stack can be compiled based on the embedded operating system (such as the OpenWrt operating system) built in the first communication chip 11. Figure 5Among them, the software architecture block IEE802.15.4 MAC in the first communication chip 11 represents other layers in the data link layer of the OpenThread protocol stack except the MAC control sublayer; the software architecture block 6LoWPAN / IPv6 represents the network layer in the OpenThread protocol stack; the software architecture block UDP represents the transport layer in the OpenThread protocol stack; the software architecture blocks CoAP / MLE / DHCPv6 / MeshCop represent the application layer in the OpenThread protocol stack.

[0077] Specifically, the embedded operating system and other layers in the OpenThread protocol stack except the physical layer and the MAC control sublayer can run in Figure 1 the first arithmetic processing unit 110 in. The first arithmetic processing unit 110 includes hardware resources such as a CPU and storage, providing hardware support for running the embedded operating system and other layers in the OpenThread protocol stack except the physical layer and the MAC control sublayer.

[0078] In some embodiments, after the first communication chip 11 receives a data frame sent by the second communication chip 12, it can perform decapsulation on the received data frame based on the inter-chip communication protocol, and perform encapsulation on the decapsulated data frame based on other layers in the first communication protocol stack except the physical layer and the MAC control sublayer. Specifically, in this embodiment, after the first communication chip 11 receives a data frame sent by the second communication chip 12, it can perform decapsulation on the received data frame based on the Spinel communication protocol, and perform encapsulation on the decapsulated data frame based on other layers in the OpenThread protocol stack except the physical layer and the MAC control sublayer, and then send the encapsulated data packet.

[0079] In some embodiments of the present application, the wireless communication co-processing method of the present application runs the protocol stack core of the first communication protocol stack (such as the OpenThread protocol stack) on the first communication chip 11 with stronger computing power. Only the MAC control sublayer and the physical layer are run on the second communication chip. Based on the stronger computing power of the first communication chip 11, the performance of the gateway device 200 can be significantly improved, such as throughput performance and the number of connectable terminals.

[0080] Further, the above-mentioned encapsulated data packet can be sent by the gateway device 200 to the target network through one of the WiFi network, 4G network, and Ethernet network, such as the Internet. In the first arithmetic processing unit 110 of the first communication chip 11, the WiFi protocol stack ( Figure 5 the Wi-Fi stack in) and the 4G protocol stack ( Figure 54G stack) and Ethernet protocol stack ( Figure 5 in the Ethemet stack) for supporting WiFi network function, 4G network function and Ethernet network function.

[0081] Correspondingly, the present application further provides a wireless communication co-processing method. After encapsulating the data packet to be sent to the target network, the gateway device 200 can automatically select the network connection with the optimal network performance and send the data packet to the target network, such as the Internet.

[0082] Figure 6 is a flowchart of the wireless communication co-processing method provided by an embodiment of the present application. The wireless communication co-processing method can be applied to the gateway device 200 and includes step S61 and step S63.

[0083] Step S61, monitor the network performance of each connected network in the gateway device 200.

[0084] In some embodiments, the network performance includes at least one of network transmission rate and network latency. Among them, the faster the network transmission rate per unit time or the smaller the network latency per unit time, the better the network performance of the connected network.

[0085] In some embodiments, the network load optimizer can be used to monitor the network performance of each connected network.

[0086] In some embodiments, the status information of each network interface can be queried through the network management tool ifconfig to confirm whether the network interface is available, and at the same time, the ping command is used to check the network connectivity of each network interface. When the network interface is available and the network is connected, it can be determined that the gateway device already has a physical network path and a software communication interface for connecting to the target network.

[0087] Step S62, determine the load amount allocated to each connected network according to the monitored network performance of each connected network, where the network performance is positively correlated with the load amount. For example, assume that the connected networks of the gateway device 200 include Ethernet, WiFi, and 4G. Among them, the network performance of Ethernet is the best, followed by WiFi, and finally 4G. Then, the load amount allocated to each connected network can be set according to actual needs. For example, the load amount of Ethernet is set to 80, the load amount of WiFi is set to 15, and the load amount of 4G is set to 5. The above 80, 15, 5 (i.e., the load amount) represents the percentage of the data volume of the data to be sent to the target network that needs to be sent through each connected network. For example, assume that there is 100M of data to be sent, then 80M is sent through Ethernet, 15M is sent through WiFi, and 5M is sent through 4G.

[0088] Step S63: Allocate the data volume to be sent through each connected network according to the load of each connected network and the data volume of the data to be sent to the target network. Among them, the larger the load of the connected network, the larger the data volume to be sent.

[0089] In some embodiments of the present application, among the connected networks of the gateway device 200, determine the data volume to be sent through each connected network according to the network performance of each connected network and the data volume of the data to be sent to the target network. More data volume can be sent through the network with better network performance. The network reliability of the gateway device 200 is higher.

[0090] In some embodiments, every preset time period, monitor the network performance of each connected network in the connected networks of the gateway device 200, and re-determine the load of each connected network each time the network performance of each connected network is monitored. In this way, according to the change of the network environment of the gateway device 200, adjust the load of the connected networks of the gateway device 200 in time, and further improve the network reliability.

[0091] Figure 7 It is a flowchart of the data transmission method provided by an embodiment of the present application. The data transmission method can be applied to the gateway device 200 and includes step S71 and step S73.

[0092] Step S71: If a data packet sent by the network management platform to the terminal is received, store the data packet, and return a response message indicating that the terminal has received the data packet to the network management platform. In some embodiments, the network management platform can be an Internet of Things monitoring platform. Specifically, it can be a platform for monitoring and managing terminals for the OpenThread network. The network management platform communicates with the terminal through the gateway device 200.

[0093] In some embodiments, the terminal is a low-power terminal, and this type of terminal has a sleep cycle. During the sleep cycle, this type of terminal will disconnect from the gateway device 200 until the terminal wakes up and sends a heartbeat signal to the gateway device 200 to establish a network connection.

[0094] Step S72: Based on the time when the heartbeat signal sent by the terminal was received last time and the heartbeat period with the terminal, determine the next heartbeat time point when the heartbeat signal sent by the terminal is received next time. For example, assume that the terminal sends a heartbeat signal to the gateway device 200 every 24 hours (that is, the heartbeat period is 24 hours), and the time point when the heartbeat signal of the terminal was received last time was 8 o'clock in the morning the day before yesterday. Then the time point when the heartbeat signal of the terminal is received next time should be 8 o'clock in the morning the day after tomorrow. This time point is the next heartbeat time point.

[0095] Step S73, if a heartbeat signal sent by the terminal is received at the next heartbeat time point, the data packet is sent to the terminal. In some embodiments, if a heartbeat signal sent by the terminal is not received at the next heartbeat time point, it is determined that the terminal is abnormal, and a message indicating that the terminal is abnormal is sent to the network management platform, so as to facilitate the network management platform to manage the terminal. Further, in some embodiments, after the gateway device 200 determines that the terminal is abnormal, the data packet is discarded. In this way, the storage space can be saved.

[0096] In some embodiments of the present application, after the gateway device 200 receives the data packet sent by the network management platform to the terminal, it stores the data packet and returns a response message indicating that the terminal has received the data packet to the network management platform. In this way, after the network management platform sends the data packet to the terminal, it can receive the response message in time, reducing the probability that the network management platform misjudges the terminal as abnormal due to not receiving the response message in time; on the other hand, the gateway device 200 stores the data packet and sends the data packet to the terminal when it receives the heartbeat signal sent by the terminal, so that the terminal does not need to remain awake, which is beneficial to reducing the power consumption of the terminals connected to the gateway device 200.

[0097] In some embodiments, sending the data packet to the terminal includes:

[0098] The first communication chip decapsulates the data packet based on other layers in the first communication protocol stack except the physical layer and the MAC control sublayer to obtain a data frame, and sends the data frame to the second communication chip.

[0099] The second communication chip decapsulates the data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, and sends the signal obtained by decapsulation to the terminal.

[0100] Decapsulating the data packet to obtain a data frame and sending the data frame to the second communication chip includes:

[0101] The first communication chip encapsulates the data frame based on the inter-chip communication protocol, and sends the encapsulated data frame to the second communication chip.

[0102] Decapsulating the data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack includes:

[0103] The second communication chip decapsulates the received data frame based on the inter-chip communication protocol, and decapsulates the decapsulated data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack.

[0104] Among them, the process of sending the data packet to the terminal is a process opposite to the above Figure 4 and the specific details can be referred to Figure 4The related descriptions are not elaborated here.

[0105] Figure 8 It is a schematic structural diagram of a gateway device 800 provided by an embodiment of the present application.

[0106] In some embodiments, the gateway device 800 includes a first communication chip 81 and a second communication chip 82 based on a first communication protocol. The computing power of the first communication chip 81 is greater than that of the second communication chip 82, where:

[0107] In some embodiments, the second communication chip 82 is used to encapsulate the signal received from the terminal into a data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, and send the data frame to the first communication chip 81. The first communication chip 81 is used to encapsulate the data frame based on the other layers in the first communication protocol stack except the physical layer and the MAC control sublayer, and send the encapsulated data packet.

[0108] In some embodiments, the first communication chip 81 is used to store the data packet if it receives the data packet sent by the network management platform to the terminal, and return a response message indicating that the terminal has received the data packet to the network management platform; and determine the next heartbeat time point when the next heartbeat signal sent by the terminal is received based on the time when the last heartbeat signal sent by the terminal is received and the heartbeat period between the terminal and the first communication chip 81; and at the next heartbeat time point, when receiving the heartbeat signal sent by the terminal, send the data packet to the terminal through the second communication chip 82. Further, the first communication chip 81 is specifically used to de-encapsulate the data packet based on the other layers in the first communication protocol stack except the physical layer and the MAC control sublayer to obtain a data frame, and send the data frame to the second communication chip 82; the second communication chip 82 is specifically used to de-encapsulate the data frame based on the physical layer and the MAC control sublayer in the first communication protocol stack, and send the de-encapsulated signal to the terminal.

[0109] In some embodiments, the first communication chip 81 is configured to monitor the network performance of each of the accessed networks in the gateway device 800's accessed network; and determine the load amount allocated to each of the accessed networks according to the monitored network performance of each of the accessed networks, where the network performance is positively correlated with the load amount; and allocate the data amount to be sent through each of the accessed networks according to the load amount of each of the accessed networks and the data amount of the data to be sent to the target network, where the larger the load amount of the accessed network, the larger the data amount to be sent. Further, the first communication chip 81 is specifically configured to monitor the network performance of each of the accessed networks in the gateway device 800's accessed network every preset time period. And when the network performance of each of the accessed networks is monitored each time, the load amount of each of the accessed networks is re-determined. Further, the gateway device 800 further includes a second communication chip of the first communication protocol, and the computing power of the first communication chip is greater than that of the second communication chip, where: the second communication chip is configured to encapsulate the signal received from the terminal into a data frame based on the physical layer and the MAC control sub-layer in the first communication protocol stack, and send the data frame to the first communication chip; and the first communication chip is further configured to encapsulate the data frame based on the other layers in the first communication protocol stack except the physical layer and the MAC control sub-layer to obtain the data to be sent to the target network.

[0110] The above are only the preferred embodiments of this specification and are not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification shall be included within the scope of protection of this specification.

[0111] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, commodity or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, commodity or device comprising the said element.

Claims

1. A wireless communication co - processing method applied to a gateway device, characterized in that, The wireless communication co - processing method is applied to a gateway device, which includes a first communication chip and a second communication chip based on a first communication protocol. The computing power of the first communication chip is greater than that of the second communication chip. The wireless communication co - processing method includes: The second communication chip encapsulates the signal received from the terminal into a data frame based on the physical layer and the MAC control sub - layer in the first communication protocol stack, and sends the data frame to the first communication chip; and The first communication chip encapsulates the data frame based on the other layers in the first communication protocol stack except the physical layer and the MAC control sub - layer, and sends the encapsulated data packet to the target network.

2. The wireless communication co - processing method according to claim 1, wherein, The step of encapsulating the signal received from the terminal into a data frame and sending the data frame to the first communication chip includes: The second communication chip encapsulates the data frame based on the inter - chip communication protocol and sends the encapsulated data frame to the first communication chip; The step of encapsulating the data frame based on the other layers in the first communication protocol stack except the physical layer and the MAC control sub - layer includes: The first communication chip decapsulates the received data frame based on the inter - chip communication protocol, and encapsulates the decapsulated data frame based on the other layers in the first communication protocol stack except the physical layer and the MAC control sub - layer.

3. The wireless communication co - processing method according to claim 2, wherein, The inter - chip communication protocol includes the Spinel protocol.

4. The wireless communication co - processing method according to claim 1, wherein The Internet of Things operating system is compiled in the second communication chip, and the physical layer and the MAC control sub - layer in the first communication protocol stack are integrated into the Internet of Things operating system.

5. The wireless communication co - processing method according to claim 4, wherein The Internet of Things operating system includes a real - time operating system.

6. The wireless communication co - processing method according to claim 1, wherein, The step of sending the encapsulated data packet includes: Among multiple network connection methods between the gateway device and the target network, determine the target network connection method, where the network performance of connecting to the target network through the target network connection method is better than that of connecting to the target network through other network connection methods; Send the encapsulated data packet to the target network through the target network connection method.

7. The wireless communication co - processing method according to claim 1, wherein, The gateway device is an Internet of Things gateway device; and / or The first communication protocol is an IP - based wireless network protocol.

8. The wireless communication co - processing method according to claim 7, wherein, The first communication protocol is the OpenThread protocol.

9. A gateway device, characterized in that, The gateway device includes a first communication chip and a second communication chip based on a first communication protocol. The computing power of the first communication chip is greater than that of the second communication chip, where: The second communication chip is used to encapsulate the signal received from the terminal into a data frame based on the physical layer and the MAC control sub - layer in the first communication protocol stack, and send the data frame to the first communication chip; The first communication chip is used to encapsulate the data frame based on the other layers in the first communication protocol stack except the physical layer and the MAC control sub - layer, and send the encapsulated data packet.

10. The gateway device according to claim 9, wherein, The gateway device is an Internet of Things gateway device; and / or The first communication protocol is an IP - based wireless network protocol.

11. The gateway device according to claim 10, characterized in that, The first communication protocol is the OpenThread protocol.

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