Multi-port IIC data transmission method and device, power module and storage medium

Abstract

The application is suitable for the technical field of data transmission, and provides a multi-port IIC data transmission method, device, power module and storage medium, the method comprising: receiving at least one read-write operation information of a user; configuring a first cache area in a preset IIC driver linked list node according to each read-write operation information, each node of the IIC driver linked list corresponding to a port and having pre-registered port information; traversing the first cache area in each IIC driver linked list node; and performing read-write operation of data according to the cache area content and port information corresponding to each node. The application can ensure that the control functions of various peripheral hardware are sequentially performed without interference during the storage process. Meanwhile, the IIC function and the peripheral hardware function are decoupled, and the code reusability is enhanced.

Description

Technical Field

[0001] This invention belongs to the field of data transmission technology, and particularly relates to a multi-port IIC data transmission method, device, power module, and storage medium. Background Technology

[0002] In the power modules of electric vehicles and their charging piles, IIC bus is typically used for data transmission. For chips with multiple IIC ports, each port may be connected to different peripheral hardware to handle different functions. For example, the IIC bus is usually connected to EEPROM (Electrically Erasable Programmable Read-Only Memory) as a communication peripheral for data storage. The IIC bus is also connected to timers for timing the vehicle's self-wake-up.

[0003] Traditionally, for multi-port chips with multiple IIC buses, when each port connects to different peripheral hardware, the IIC ports are designed to be coupled with the peripheral hardware modules, or each IIC port is designed without mutual decoupling, which will result in poor code reusability and make it difficult to use independently. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a multi-port IIC data transmission method, apparatus, power module, and storage medium to solve the problem of poor code reusability caused by the coupling of the multi-port IIC function of the power module with peripheral hardware in the prior art.

[0005] A first aspect of this invention provides a multi-port IIC data transmission method, comprising:

[0006] Receive at least one read / write operation information from the user;

[0007] Configure the first cache area in the preset IIC driver linked list node according to each read and write operation information, wherein each node of the IIC driver linked list corresponds to a port and has pre-registered port information;

[0008] Iterate through the first buffer in each IIC driver linked list node;

[0009] Data read and write operations are performed based on the cache contents and port information of each node.

[0010] In conjunction with the first aspect, in one possible implementation of the first aspect, the port information includes the device port name and the device driver;

[0011] Each node in the IIC-driven linked list also includes: the write index value of the first buffer, the read index value of the first buffer, the maximum data sending length, and the maximum data receiving length.

[0012] In conjunction with the first aspect, in one possible implementation of the first aspect, the first cache area contains multiple structures; the first cache area in the preset IIC driver linked list node is configured according to each read / write operation information, including:

[0013] Load the device address, data pointer, data length, and error / failure callback function of the communication hardware into the structure indicated by the current write index value of the corresponding first buffer.

[0014] After loading is complete, update the write index value of the first cache.

[0015] In conjunction with the first aspect, in one possible implementation of the first aspect, the first buffer in each IIC driver linked list node is traversed, and data read and write operations are performed according to the buffer content and port information corresponding to each node, including:

[0016] Iterate through all nodes and determine whether the read and write index values ​​in the first cache of each node are equal;

[0017] If the read and write index values ​​in the first cache of any node are not equal, then according to the content of the structure indicated by the current read index value of the first cache and the port information corresponding to the node, the read and write operations of the structure data are performed, and the read index value of the first cache is updated after the read and write operations are completed.

[0018] Continue performing read and write operations based on the updated read index value until the read and write index values ​​are equal.

[0019] In conjunction with the first aspect, one possible implementation of the first aspect, which configures the first cache area in the preset IIC driver linked list node according to each read / write operation information, further includes:

[0020] Load the read / write interval into the structure indicated by the current write index value of the corresponding first cache area;

[0021] Before continuing read and write operations based on the updated read index value, the following steps are also included:

[0022] Determine if the interval between the current time and the completion time of the previous read / write operation has reached the read / write interval. If it has, continue the read / write operation based on the updated read index value; otherwise, do not execute.

[0023] In conjunction with the first aspect, one possible implementation of the first aspect, which configures the first cache area in the preset IIC driver linked list node according to each read / write operation information, further includes:

[0024] Load the status pointer into the structure indicated by the current write index value of the corresponding first buffer;

[0025] The status pointer is used to indicate whether the first buffer is currently busy.

[0026] In conjunction with the first aspect, one possible implementation of the first aspect, which configures the first cache area in the preset IIC driver linked list node according to each read / write operation information, further includes:

[0027] Load the read / write flags into the structure indicated by the current write index value of the corresponding first cache area;

[0028] The read / write flag is used to indicate whether the current operation is a read or a write operation.

[0029] A second aspect of the present invention provides a multi-port IIC data transmission device, comprising:

[0030] The receiving module is used to receive at least one read / write operation information from the user;

[0031] The configuration module is used to configure the first buffer in the preset IIC driver linked list node according to each read and write operation information. Each node of the IIC driver linked list corresponds to a port and has pre-registered port information.

[0032] The traversal module is used to traverse the first buffer in each IIC driver linked list node, and to perform data read and write operations based on the buffer content and port information of each node.

[0033] A third aspect of the present invention provides a power module including an electronic device. The electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the multi-port IIC data transmission method as described in the first aspect or any possible implementation of the first aspect.

[0034] A fourth aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the multi-port IIC data transmission method as described in the first aspect or any possible implementation thereof.

[0035] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows:

[0036] This invention registers the different IIC port information used by different peripheral hardware devices into the IIC driver information linked list nodes. When read / write operation information is received, all linked list nodes are traversed and processed cyclically without interference. Simultaneously, each IIC driver linked list node has a first buffer. This buffer is primarily designed to prevent redundancy when multiple read / write requests exist simultaneously, facilitating the orderly processing of multiple requests within the buffer. This invention ensures that the control functions of each peripheral hardware device operate in an orderly manner during storage, without interference. Furthermore, the IIC function is decoupled from the peripheral hardware function, enhancing code reusability. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a flowchart illustrating the multi-port IIC data transmission method provided in an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of the structure provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the overall processing flow provided in the embodiments of the present invention;

[0041] Figure 4 This is a schematic diagram of the structure of the multi-port IIC data transmission device provided in an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0043] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0044] To illustrate the technical solution described in this invention, specific embodiments are described below.

[0045] The IIC bus (Inter-Integrated Circuit) is a simple, bidirectional, two-wire, synchronous serial bus. It's a multi-directional control bus where multiple devices (slave devices) can be simultaneously connected to a single bus controlled by a master. Each device connected to the bus communicates with other devices through a unique address, and the roles of master and slave are interchangeable. IIC buses are commonly used for data transmission in the power modules of electric vehicles and their charging stations. Traditionally, for multi-port chips with multiple IIC buses, where each port connects to different peripheral hardware, the IIC module and the peripheral hardware module are designed together, or each IIC port is not decoupled from the others. This results in poor code reusability and difficulty in using the code independently.

[0046] The embodiments of the present invention mainly solve the following problems:

[0047] (1) How to decouple the functions of each IIC port so that each IIC communication can proceed in an orderly manner without interfering with each other.

[0048] (2) How to ensure that multiple read and write operations do not miss or overwrite each other on the same IIC port at a specific time, i.e., solve the redundancy problem.

[0049] (3) Operations on the IIC bus are nothing more than reading and writing data. How to ensure that the reading and writing operations are carried out in an orderly manner and do not interfere with each other?

[0050] To address the above problems, embodiments of the present invention provide a multi-port IIC data transmission method, see [link to relevant documentation]. Figure 1 As shown, it includes:

[0051] Step S101: Receive at least one read / write operation information from the user.

[0052] In this embodiment, the user can perform read or write operations on the power module. Furthermore, multiple read / write requests may occur simultaneously, requiring coordinated processing.

[0053] Step S102: Configure the first buffer in the preset IIC driver linked list node according to each read / write operation information. Each node of the IIC driver linked list corresponds to a port and has port information pre-registered.

[0054] As one possible implementation, port information includes the device port name and device driver. Each node in the IIC driver linked list also includes: the write index value of the first buffer, the read index value of the first buffer, the maximum data transmission length, and the maximum data reception length.

[0055] In this embodiment, it is considered that the chip may contain multiple IIC ports. Different communication hardware may need to use different IIC ports. Therefore, different registrations are required for using different IIC ports for different communication peripherals, i.e., registering IIC0, IIC1...IICn. During the registration process, the user needs to carry the "underlying communication port number required by this communication hardware" information to register to the node in the IIC driver information chain list.

[0056] Each node in the IIC driver information linked list can contain the following information:

[0057] Information 1: Device Port Name.

[0058] Information 2, device driver, is information 2 found using information 1.

[0059] Information 3: Structure 1 type data cache area, i.e., the first cache area. The length of this cache area is set according to the user's needs.

[0060] Information 4: Write index value of the cache area in Information 3.

[0061] Information 5: Read index value of the cache area of ​​Information 3.

[0062] Information 6: The maximum data length supported by the underlying registers of this chip. For example, if the maximum data length to be transmitted is 16 8-bit data bytes, then the maximum data length to be transmitted is set to 16.

[0063] Information 7: The maximum received data length supported by the chip's underlying registers. For example, if the maximum received data length is 16 8-bit data bytes, then the maximum transmitted data length is set to 16.

[0064] It should be noted that the user registration process only requires information one, and registration only occurs when different IICs are used in the communication hardware. Each time a user registers, they automatically allocate a fixed-length buffer for information three, initialize the read / write indexes for information four and five, and set the maximum sending and receiving lengths for information six and seven. The detailed registration process flowchart is not provided here.

[0065] Step S103: Traverse the first buffer in each IIC driver linked list node; perform data read and write operations according to the buffer content and port information of each node.

[0066] In this embodiment, multiple read and write operations for a specific port are sequentially placed into the first buffer of the node corresponding to that port. Each read and write operation is achieved by iterating through each node and its buffer contents. Since different peripheral hardware uses different IIC port information registered in the IIC driver information linked list, the outer loop will traverse all linked list nodes during data processing, performing cyclical processing without interference. Simultaneously, within each node, an inner loop iterates through the information in the first buffer for read and write operations, facilitating the orderly processing of multiple requests within the buffer.

[0067] As can be seen, this embodiment of the invention registers the different IIC port information used by different peripheral hardware devices into the IIC driver information linked list nodes. When read / write operation information is received, all linked list nodes will be traversed and processed in a loop without interference. Simultaneously, each IIC driver linked list node is equipped with a first buffer. This buffer is mainly used to prevent redundancy when multiple read / write requests exist simultaneously, facilitating the orderly processing of multiple requests within the buffer. This embodiment of the invention ensures that the control functions of each peripheral hardware device operate in an orderly manner during storage, without interference. Furthermore, the IIC function is decoupled from the peripheral hardware function, enhancing code reusability.

[0068] As one possible implementation, the first cache contains multiple structures. Step S102, configuring the first cache in the preset IIC driver linked list node according to each read / write operation information, can be detailed as follows:

[0069] Load the device address, data pointer, data length, and error / failure callback function of the communication hardware into the structure indicated by the current write index value of the corresponding first buffer.

[0070] After loading is complete, update the write index value of the first cache.

[0071] In this embodiment, each structure corresponds to a read / write operation, and the inner loop iterates through each structure in the cache. Each structure has read and write index values. Each time a structure is loaded, the write index value of the first cache is updated, pointing to the next location. Similarly, each time a read / write operation of a structure is processed, the read index value of the structure is updated, pointing to the next location.

[0072] The definitions of each parameter are as follows:

[0073] Device address of communication hardware: The slave device address of the communication hardware that will write or read data.

[0074] The data pointer points to a memory space that will store the read data if the current operation is a read operation; if the current operation is a write operation, the memory space that will store the data to be written will be stored.

[0075] Data length refers to the length of the data to be stored or read, expressed in 8-bit units. If the data is 64-bit, the data length is 8.

[0076] Error and failure callback functions require users to write their own IIC communication error handling logic.

[0077] As one possible implementation, in step S103, the first buffer in each IIC driver linked list node is traversed, and data read and write operations are performed according to the buffer content and port information corresponding to each node. This can be described in detail as follows:

[0078] Iterate through all nodes and determine whether the read and write index values ​​in the first cache of each node are equal;

[0079] If the read and write index values ​​in the first cache of any node are not equal, then according to the content of the structure indicated by the current read index value of the first cache and the port information corresponding to the node, the read and write operations of the structure data are performed, and the read index value of the first cache is updated after the read and write operations are completed.

[0080] Continue performing read and write operations based on the updated read index value until the read and write index values ​​are equal.

[0081] In this embodiment, as can be seen from the above, when the read and write index values ​​of the first cache are not equal, it indicates that there are unprocessed structures in the cache; when the read and write index values ​​are equal, it indicates that the processing is complete.

[0082] As one possible implementation, step S102, which configures the first cache area in the preset IIC driver linked list node according to each read / write operation information, further includes:

[0083] The read / write interval is loaded into the structure indicated by the current write index value of the corresponding first cache.

[0084] Before continuing read and write operations based on the updated read index value, the following steps are also included:

[0085] Determine if the interval between the current time and the completion time of the previous read / write operation has reached the read / write interval. If it has, continue the read / write operation based on the updated read index value; otherwise, do not execute.

[0086] In this embodiment, a certain time interval needs to be maintained between two adjacent read and write operations. The purpose of setting the read and write interval is to allow sufficient time for data in the cache to be read and written.

[0087] As one possible implementation, step S102, which configures the first cache area in the preset IIC driver linked list node according to each read / write operation information, further includes:

[0088] Load the status pointer into the structure indicated by the current write index value of the corresponding first buffer;

[0089] The status pointer is used to indicate whether the first buffer is currently busy.

[0090] In this embodiment, the status pointer is used to indicate whether the data in the first buffer has been processed.

[0091] As one possible implementation, step S102, which configures the first cache area in the preset IIC driver linked list node according to each read / write operation information, further includes:

[0092] Load the read / write flags into the structure indicated by the current write index value of the corresponding first cache area;

[0093] The read / write flag is used to indicate whether the current operation is a read or a write operation.

[0094] In this embodiment, since the relevant information for both read and write operations is stored in the data cache area of ​​structure type 1, it is necessary to distinguish between read and write operations using read and write flags.

[0095] In one embodiment, please refer to [the following text is also included] Figure 2 and Figure 3 As shown, the structure within the first cache area is defined as structure type 1, including:

[0096] The parameters include: slave address (i.e., slave device address, i.e., the device address of the communication hardware), data pointer, data length, read / write interval, read / write flag, status pointer, and error / failure callback function.

[0097] This embodiment also provides a Structure 2 type. Structure 1 type contains all the data types of Structure 2 type. The purpose of setting up Structure 2 type is mainly to provide users with an encapsulated type, which can be used conveniently when users use the IIC read interface function and write interface function. Structure 2 type includes: slave address, data pointer, data length, read / write interval, and status pointer.

[0098] The user read / write operation process is essentially the process of loading data from structure 2 into the cache area of ​​structure 1. The specific process is as follows:

[0099] (1) Load the data in the structure 2 provided by the user into the current write index position of the structure 1 cache area.

[0100] (2) After loading, set the status flag under the current write index value of the data type cache of structure1 to busy.

[0101] (3) Load the read / write flags under the current write index value of the data cache of structure type 1 according to the user's read / write operation.

[0102] (4) Load the user's error failure function into the error failure function under the current write index value of the data cache of structure type 1.

[0103] (5) Update the write index of the data cache of structure type 1.

[0104] The data processing procedure involves retrieving and reading / writing data from the structure 1 cache one by one. The specific process is as follows:

[0105] (1) Set the current node as the initial node.

[0106] (2) Traverse all nodes and accumulate the timeout. If the timeout occurs, it is considered that all cache data of all nodes has been traversed, and the entire loop is exited. If the timeout does not occur, proceed to step 3.

[0107] (3) Determine whether the read and write index values ​​of the cache area of ​​structure 1 of this node are equal. If they are equal, exit the current loop and enter the next node. If they are not equal, proceed to step 4.

[0108] (4) Determine whether the time interval between the current group of data and the next group of data under the current read index of the structure 1 type cache of this node is greater than 0. If it is greater than 0, the time interval is reduced cumulatively, indicating that the data processing time at the current read index value position of the structure 1 cache has not yet arrived. Therefore, all data in the structure 1 cache is not processed and is in a waiting state. Proceed to the next node and continue to determine the next node. If the time interval is not less than 0, it indicates that the processing time of the data at the current read index value position of the structure 1 cache has arrived. Continue to step 5.

[0109] (5) Perform read and write operations on the IIC bus according to the read index value of the buffer of structure 1 of this node.

[0110] (6) Update the read index value of the cache under the current node, continue to execute step 3, and perform the cache loop operation of structure 1 of this node.

[0111] This process includes two traversals. The outer traversal is the traversal of the entire IIC driver information linked list nodes; the inner traversal is the traversal of the current node's buffer. This means that the next node can only proceed if the read and write indices of the buffer are equal, or if the interval is insufficient, all data in the buffer of Structure 1 under this node will not be processed before proceeding to the next node. Specifically, in step 5, the IIC read and write operations, since the IIC bus reads and writes 8 bits at a time, will cyclically read 2, 4, and 8 times for 16-bit, 32-bit, and 64-bit data, respectively. This cyclic reading process is encapsulated within the IIC bus read and write operation and will not be described in detail.

[0112] This solution ensures that the control functions of each peripheral hardware device operate in an orderly manner during the storage process without interfering with each other. At the same time, the IIC function is decoupled from the peripheral hardware function, enhancing code reusability.

[0113] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0114] This invention provides a multi-port IIC data transmission device, see [link to documentation]. Figure 4 As shown, the device 40 includes:

[0115] The receiving module 41 is used to receive at least one read / write operation information from the user.

[0116] Configuration module 42 is used to configure the first buffer in the preset IIC driver linked list node according to each read and write operation information. Each node of the IIC driver linked list corresponds to a port and has pre-registered port information.

[0117] Traversal module 43 is used to traverse the first buffer in each IIC driver linked list node, and to perform data read and write operations based on the buffer content and port information of each node.

[0118] As one possible implementation, port information includes the device port name and device driver. Each node in the IIC driver linked list also includes: the write index value of the first buffer, the read index value of the first buffer, the maximum data transmission length, and the maximum data reception length.

[0119] As one possible implementation, the first cache contains multiple structures; the configuration module 42 is specifically used for:

[0120] Load the device address, data pointer, data length, and error / failure callback function of the communication hardware into the structure indicated by the current write index value of the corresponding first buffer.

[0121] After loading is complete, update the write index value of the first cache.

[0122] As one possible implementation, traversal module 43 is specifically used for:

[0123] Iterate through all nodes and determine whether the read and write index values ​​in the first cache of each node are equal;

[0124] If the read and write index values ​​in the first cache of any node are not equal, then according to the content of the structure indicated by the current read index value of the first cache and the port information corresponding to the node, the read and write operations of the structure data are performed, and the read index value of the first cache is updated after the read and write operations are completed.

[0125] Continue performing read and write operations based on the updated read index value until the read and write index values ​​are equal.

[0126] As one possible implementation, configuration module 42 is also specifically used for:

[0127] The read / write interval is loaded into the structure indicated by the current write index value of the corresponding first cache.

[0128] Before continuing read / write operations based on the updated read index value, it is determined whether the interval between the current time and the completion time of the previous read / write operation has reached the read / write interval. If it has, the read / write operation continues based on the updated read index value; otherwise, it is not executed.

[0129] As one possible implementation, configuration module 42 is also specifically used for:

[0130] Load the status pointer into the structure indicated by the current write index value of the corresponding first buffer;

[0131] The status pointer is used to indicate whether the first buffer is currently busy.

[0132] As one possible implementation, configuration module 42 is also specifically used for:

[0133] Load the read / write flags into the structure indicated by the current write index value of the corresponding first cache area;

[0134] The read / write flag is used to indicate whether the current operation is a read or a write operation.

[0135] This invention provides a power module, including an electronic device. The electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the multi-port IIC data transmission method described above.

[0136] Figure 5This is a schematic diagram of an electronic device 50 provided in an embodiment of the present invention. For example... Figure 5 As shown, the electronic device 50 of this embodiment includes: a processor 51, a memory 52, and a computer program 53 stored in the memory 52 and executable on the processor 51, such as a multi-port IIC data transmission program. When the processor 51 executes the computer program 53, it implements the steps in the various multi-port IIC data transmission method embodiments described above, for example... Figure 1 Steps S101 to S103 are shown. Alternatively, when processor 51 executes computer program 53, it implements the functions of each module in the above-described device embodiments, for example... Figure 4 The functions of modules 41 to 43 are shown.

[0137] For example, computer program 53 may be divided into one or more modules / units, one or more of which are stored in memory 52 and executed by processor 51 to complete the present invention. One or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of computer program 53 in electronic device 50.

[0138] Electronic device 50 can be a desktop computer, laptop, handheld computer, cloud server, or other computing device. Electronic device 50 may include, but is not limited to, a processor 51 and a memory 52. ​​Those skilled in the art will understand that... Figure 5 This is merely an example of electronic device 50 and does not constitute a limitation on electronic device 50. It may include more or fewer components than shown, or combine certain components, or different components. For example, electronic device 50 may also include input / output devices, network access devices, buses, etc.

[0139] The processor 51 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0140] The memory 52 can be an internal storage unit of the electronic device 50, such as a hard disk or RAM of the electronic device 50. The memory 52 can also be an external storage device of the electronic device 50, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the electronic device 50. Furthermore, the memory 52 can include both internal and external storage units of the electronic device 50. The memory 52 is used to store computer programs and other programs and data required by the electronic device 50. The memory 52 can also be used to temporarily store data that has been output or will be output.

[0141] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0142] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0143] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0144] In the embodiments provided by this invention, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0145] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0146] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0147] If integrated modules / units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0148] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A multi-port IIC data transmission method, characterized in that, include: Receive at least one read / write operation information from the user; Configure the first cache area in the preset IIC driver linked list node according to each read and write operation information, wherein each node of the IIC driver linked list corresponds to a port and has pre-registered port information; Iterate through the first buffer in each IIC driver linked list node; Perform data read and write operations based on the cache content and port information of each node; The port information includes the device port name and device driver; each node of the IIC driver linked list also includes: the write index value of the first buffer, the read index value of the first buffer, the maximum data transmission length, and the maximum data reception length; The first buffer contains multiple structures; the first buffer in the preset IIC driver linked list node is configured according to each read and write operation information, including: loading the device address, data pointer, data length and error failure callback function of the communication hardware into the structure indicated by the current write index value of the corresponding first buffer; after loading, the write index value of the first buffer is updated.

2. The multi-port IIC data transmission method as described in claim 1, characterized in that, Iterate through the first buffer in each node of the IIC driver linked list, and perform data read and write operations based on the buffer content and port information of each node, including: Iterate through all nodes and determine whether the read and write index values ​​in the first cache of each node are equal; If the read and write index values ​​in the first cache of any node are not equal, then according to the content of the structure indicated by the current read index value of the first cache and the port information corresponding to the node, the read and write operations of the structure data are performed, and the read index value of the first cache is updated after the read and write operations are completed. Continue performing read and write operations based on the updated read index value until the read and write index values ​​are equal.

3. The multi-port IIC data transmission method as described in claim 2, characterized in that, The first cache area in the preset IIC driver linked list node is configured according to each read / write operation information, and also includes: Load the read / write interval into the structure indicated by the current write index value of the corresponding first cache area; Before continuing read and write operations based on the updated read index value, the following steps are also included: Determine whether the interval between the current time and the completion time of the previous read / write operation has reached the read / write interval. If it has, continue to execute the read / write operation based on the updated read index value; otherwise, do not execute.

4. The multi-port IIC data transmission method as described in claim 1, characterized in that, The first cache area in the preset IIC driver linked list node is configured according to each read / write operation information, and also includes: Load the status pointer into the structure indicated by the current write index value of the corresponding first buffer; The status pointer is used to indicate whether the first buffer is currently busy.

5. The multi-port IIC data transmission method as described in claim 1, characterized in that, The first cache area in the preset IIC driver linked list node is configured according to each read / write operation information, and also includes: Load the read / write flags into the structure indicated by the current write index value of the corresponding first cache area; The read / write flag is used to indicate whether the current operation is a read or a write operation.

6. A multi-port IIC data transmission device, characterized in that, For implementing the steps of the method as described in any one of claims 1 to 5; the apparatus includes: The receiving module is used to receive at least one read / write operation information from the user; The configuration module is used to configure the first buffer in the preset IIC driver linked list node according to each read and write operation information. Each node of the IIC driver linked list corresponds to a port and has pre-registered port information. The traversal module is used to traverse the first buffer in each IIC driver linked list node, and to perform data read and write operations based on the buffer content and port information of each node.

7. A power module comprising an electronic device, the electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 5.

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