Data control circuit and memory device

Abstract

A data control circuit includes a first latch circuit, a self-blocking circuit, a second latch circuit, a third latch circuit, a first data timing mark signal generating circuit, and a second data timing mark signal generating circuit. The first latch circuit is configured to receive a data window signal. The self-blocking circuit is coupled to the first latch circuit and configured to generate a protection signal. The second latch circuit is coupled to the self-blocking circuit and configured to output a first data timing mark signal. The third latch circuit is coupled to the second latch circuit and configured to output a second data timing mark signal. The first data timing mark signal generating circuit is configured to generate a third data timing mark signal. The second data timing mark signal generating circuit is configured to generate a fourth data timing mark signal.

Description

Technical Field

[0001] This invention relates to double data rate synchronous dynamic random access memory (DDR SDRAM), and more particularly to a data control circuit for increasing the maximum and minimum tolerance values ​​of skew between the data strobe (DQS) signal and the clock pulse signal during write operations, and related memory devices. Background Technology

[0002] With the development of DDR SDRAM and the increasing speed of data transmission, the tDQSS (True Difference of Quality Specs) was defined in the DDR SDRAM specifications. This tDQSS limits the relative relationship between the rising edge of the data strobe signal and the rising edge of the clock pulse signal during a write operation. In other words, tDQSS represents the maximum and minimum tolerance values ​​for skew between the data strobe signal and the clock pulse signal during a write operation. By limiting the size of tDQSS, DDR SDRAM can operate correctly and prevent erroneous data from being written to it. However, to accommodate the increasingly faster data transmission speeds of DDR SDRAM, the value of tDQSS in the DDR SDRAM specifications has been increased. The DDR2 SDRAM specifications require a tDQSS value greater than ±0.25 * clock cycle time (tCK). In the DDR3 SDRAM specifications, the tDQSS value is increased to ±0.27 * tCK. In the later development of DDR4 SDRAM, tDQSS2 was defined when DDR4 SDRAM was operated in 2-clock preamble mode, and the value of tDQSS2 could reach ±0.5*tCK.

[0003] DDR SDRAM manufacturers set design targets for tDQSS that are greater than the tDQSS defined in the DDR SDRAM specification. In prior art, tDQSS values ​​up to ±0.4*tCK were manageable. However, with the advent of tDQSS2, prior art could not meet the requirements of the DDR4 SDRAM specification. Furthermore, prior art typically required precise achievement of the tDQSS design target, resulting in limited design flexibility. Therefore, there is an urgent need for a data control circuit that increases the maximum and minimum tolerance values ​​for the deviation between the data strobe signal and the clock pulse signal during data writing, and related to the memory device. Summary of the Invention

[0004] Therefore, one of the objectives of this invention is to provide a data control circuit that increases the maximum and minimum tolerance values ​​of the deviation between the data strobe signal and the clock pulse signal during data writing, as well as the associated memory device, to solve the above-mentioned problems.

[0005] According to one embodiment of the present invention, a data control circuit is provided to increase the maximum and minimum tolerance values ​​of the deviation between a data strobe signal and a clock pulse signal during data writing. The data control circuit may include a first latch circuit, a self-resisting circuit, a second latch circuit, a third latch circuit, a first data timing mark signal generation circuit, and a second data timing mark signal generation circuit. The first latch circuit has a first clock pulse port, a first input port, and a first output port, wherein the first clock pulse port is used to receive a first clock pulse obtained from the data strobe signal, and the first input port is used to receive a data window signal. The self-resisting circuit may be coupled to the first output port of the first latch circuit and is used to generate a protection signal based on the output of the first output port of the first latch circuit and the self-resisting signal. The second latch circuit has a second clock pulse port, a second input port, and a second output port. The second clock pulse port receives a second clock pulse, which is obtained from a data strobe signal. The first clock pulse is the inverted signal of the second clock pulse. The second input port is coupled to a self-resistance circuit and is used to receive a protection signal. The second output port is used to output a first data timing mark signal. The third latch circuit has a third clock pulse port, a third input port, and a third output port. The third clock pulse port receives the first clock pulse. The third input port is coupled to the second output port of the second latch circuit and is used to receive the first data timing mark signal. The third output port is used to output a second data timing mark signal. A first data timing mark signal generation circuit can be coupled to the third output port of the third latch circuit and is used to generate a third data timing mark signal based on the second data timing mark signal. A second data timing mark signal generation circuit can be coupled to the first data timing mark signal generation circuit and is used to generate a fourth data timing mark signal based on the third data timing mark signal.

[0006] According to an embodiment of the present invention, a memory device is provided. The memory device may include a command input interface, a command decoder, a memory cell circuit, a data input / output interface, and a data processing circuit. The command input interface is used to receive multiple command signals. The command decoder is coupled to the command input interface and is used to receive and decode the multiple command signals to generate a data window signal and a control signal, wherein the data window signal corresponds to a write command. The memory cell circuit is coupled to the command decoder and has multiple memory banks, wherein the memory cell circuit is controlled by the control signal. The data input / output interface is used to receive multiple data signals and a data strobe signal, wherein the multiple data signals correspond to multiple data to be written and are transmitted in a sequential communication manner. The data processing circuit may include a sequence-to-parallel circuit and a data control circuit. The sequence-to-parallel circuit is coupled to the data input / output interface and the memory cell circuit and is used to convert the multiple data signals into multiple data input signals according to the data strobe signal, a second data timing marker signal, and a fourth data timing marker signal, wherein the multiple data input signals are transmitted to the memory cell circuit in a parallel communication manner. The data control circuitry can be coupled to the command decoder, data input / output interface, and sequence-to-parallel circuitry.

[0007] One advantage of this invention is that by utilizing the data control circuit provided by this invention, the maximum and minimum tolerance values ​​for the skew between the data strobe signals during write operations can be increased, and the size requirement of tDQSS2 as defined in the DDR4 SDRAM specification can be achieved. Furthermore, regarding the tDQSS case, in the prior art, the pulse width of the data window signal could reach 1*tCK, which could handle tDQSS values ​​up to ±0.4*tCK in the DDR SDRAM specification. In practice, it is difficult to precisely make the pulse width of the data window signal exactly 1*tCK. However, once the pulse width of the data window signal is greater than 1*tCK, DDR SDRAM manufacturers can easily manufacture DDR SDRAM. By utilizing the data control circuit provided by this invention, a pulse width of the data window signal greater than 1*tCK can be easily achieved, and multiple pulse widths are available (e.g., 1.3*tCK, 1.4*tCK, or 1.5*tCK). Therefore, this invention offers high design flexibility. Attached Figure Description

[0008] Figure 1 This is a block diagram of a memory device according to an embodiment of the present invention.

[0009] Figure 2 According to one embodiment of the present invention Figure 1 The block diagram of the data processing circuit shown is shown.

[0010] Figure 3 According to one embodiment of the present invention Figure 2 The diagram shows a schematic of the data control circuit.

[0011] Figure 4 According to an embodiment of the present invention, in the tDQSS2 case, by Figure 3 The timing diagram shown is of the clock pulse signal, data strobe signal, data window signal, and multiple data timing marker signals obtained by the data control circuit.

[0012] Figure 5 According to an embodiment of the present invention, in the tDQSS2 case, by Figure 3 The timing diagram shown includes the clock pulse signal, data strobe signal (which rises for the first time after the write command operation timing), data window signal, and multiple data timing marker signals obtained by the data control circuit.

[0013] Figure 6 According to an embodiment of the present invention, in the tDQSS2 case, by Figure 3 The timing diagram shown includes the clock pulse signal, data strobe signal (which rises for the first time before the write command operation timing), data window signal, and multiple data timing marker signals obtained by the data control circuit.

[0014] Figure 7 According to an embodiment of the present invention, under the tDQSS case, Figure 3 The timing diagram shown is of the clock pulse signal, data strobe signal, data window signal, and multiple data timing marker signals obtained by the data control circuit.

[0015] Figure 8 According to an embodiment of the present invention, under the tDQSS case, Figure 3 The timing diagram shown includes the clock pulse signal, data strobe signal (which rises for the first time after the write command operation timing), data window signal, and multiple data timing marker signals obtained by the data control circuit.

[0016] Figure 9 According to an embodiment of the present invention, under the tDQSS case, Figure 3 The timing diagram shown includes the clock pulse signal, data strobe signal (which rises for the first time before the write command operation timing), data window signal, and multiple data timing marker signals obtained by the data control circuit.

[0017] Figure 10 According to another embodiment of the present invention, in the tDQSS2 case, by Figure 3The timing diagram shown is of the clock pulse signal, data strobe signal, data window signal, and multiple data timing marker signals obtained by the data control circuit. Detailed Implementation

[0018] Figure 1 This is a block diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100, such as double data rate synchronous dynamic random access memory (DDR SDRAM), may include a command input interface 10, a command decoder 12, memory cell circuitry 14, an input / output (I / O) interface 16, and data processing circuitry 18. The command input interface 10 can be used to receive multiple command signals COMMAND_SIGNAL, wherein the command signals COMMAND_SIGNAL may include a write command WR, a differential pair of memory clock pulse signals (i.e., a true clock pulse signal CK_t and a complementary clock pulse signal CK_c), a clock pulse enable signal CKE, a chip select signal CS_n, and multiple address signals (e.g., BG0, BG1, BA0, BA1, and A0 to A13), etc. Command decoder 12 can be coupled to command input interface 10 and can be used to receive and decode command signal COMMAND_SIGNAL to generate data window signal CAIWSP (which corresponds to write command WR) and control signal CS. The data window signal CAIWSP can be used to notify data processing circuit 18 that memory device 100 is operated in write mode, control the data path, and represent the maximum and minimum tolerance values ​​of skew between data strobe (DQS) signal and clock pulse signal (e.g., real clock pulse signal CK_t). The control signal CS is generated based on multiple address signals.

[0019] The memory cell circuit 14 can be coupled to the command decoder 12 and the data processing circuit 18, and can have multiple memory banks BANK_0 to BANK_N. The memory cell circuit 14 is controlled by the control signal CS, which can be used to determine the memory address of one of the memory banks BANK_0 to BANK_N, and the write operation corresponding to the write command WR can be performed at that memory address. The data input / output interface 16 can be used to receive multiple data (DQ) signals DQ0 to DQ7, multiple data signals DQ8 to DQ15, differential pairs of upper data strobe signals (i.e., upper real data strobe signal UDQS_t and upper complementary data strobe signal UDQS_c), and differential pairs of lower data strobe signals (i.e., lower real data strobe signal LDQS_t and lower complementary data strobe signal LDQS_c). The differential pairs of upper and lower data strobe signals correspond to data signals DQ8 to DQ15 and data signals DQ0 to DQ7, respectively, and the data signals DQ0 to DQ7 and data signals DQ8 to DQ15 correspond to multiple data to be written. The data processing circuit 18 can be coupled to the command decoder 12, the memory cell circuit 14, and the data input / output interface 16, and can be used to receive the data window signal CAIWSP, data signals DQ0 to DQ7, data signals DQ8 to DQ15, differential pairs of upper data strobe signals, and differential pairs of lower data strobe signals, and to write multiple data to be written to the memory cell circuit 14 (especially the memory cell at the memory address determined by the control signal CS) according to the data window signal CAIWSP.

[0020] Figure 2 According to one embodiment of the present invention Figure 1 The block diagram of the data processing circuit 18 shown is as follows. Figure 2 As shown, Figure 1The data processing circuit 18 shown may include a data control circuit 200 and a serial-to-parallel circuit 202, wherein the data control circuit 200 is coupled to the serial-to-parallel circuit 202. In this embodiment, data signals DQ0 to DQ7 can be transmitted to the serial-to-parallel circuit 202, and the lower data strobe signal LDQS can be transmitted to the data control circuit 200 and the serial-to-parallel circuit 202. The data signals DQ0 to DQ7 are transmitted in a serial communication manner, and the lower data strobe signal LDQS can be generated by transmitting the lower real data strobe signal LDQS_t through the input buffer of the data input / output interface 16 to the data control circuit 200 and the serial-to-parallel circuit 202, but the present invention is not limited thereto. In some embodiments, data signals DQ8 to DQ15 may be transmitted to the sequence-to-parallel circuit 202, and an upper data strobe signal UDQS may be transmitted to the data control circuit 200 and the sequence-to-parallel circuit 202. The upper data strobe signal UDQS may be generated by transmitting the upper real data strobe signal UDQS_t through the input buffer of the data input / output interface 16 to the data control circuit 200 and the sequence-to-parallel circuit 202.

[0021] In this embodiment, the data control circuit 200 can generate a second data timing mark signal Q05 and a fourth data timing mark signal Q25 according to the lower data strobe signal LDQS, and transmit the second data timing mark signal Q05 and the fourth data timing mark signal Q25 to the sequence-to-parallel circuit 202, wherein the timing of multiple data to be written is marked by the second data timing mark signal Q05 and the fourth data timing mark signal Q25 respectively. The sequence-to-parallel circuit 202 can be used to convert data signals DQ0 to DQ7 transmitted in sequence communication into multiple data input signals DATA0 to DATA63 transmitted in parallel communication according to the data strobe signal LDQS, the second data timing mark signal Q05, and the fourth data timing mark signal Q25, and transmit the data input signals DATA0 to DATA63 to the memory unit circuit 14. For example, data signal DQ0 is converted into multiple data input signals DATA0 to DATA7 in the data input signals DATA0 to DATA63, and data signal DQ1 is converted into multiple data input signals DATA8 to DATA15 in the data input signals DATA0 to DATA63. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0022] Figure 3 According to one embodiment of the present invention Figure 2 The schematic diagram of the data control circuit 200 shown is as follows: Figure 2 The data control circuit 200 shown can be controlled via Figure 3 The data control circuit 300 shown is used to implement this. In this embodiment, the data control circuit 300 can be used to generate a first data timing mark signal Q00, a second data timing mark signal Q05, a third data timing mark signal Q15, and a fourth data timing mark signal Q25 based on the real clock pulse signal CK_t and the lower data strobe signal LDQS. The real clock pulse signal CK_t belongs to the clock-domain, and the lower data strobe signal LDQS, the first data timing mark signal Q00, the second data timing mark signal Q05, the third data timing mark signal Q15, and the fourth data timing mark signal Q25 belong to the data strobe domain. However, this invention is not limited thereto. Furthermore, the data control circuit 300 can be used to convert the data window signal CAIWSP (which corresponds to the write command WR) from the clock-domain to the data strobe domain.

[0023] like Figure 3 As shown, the data control circuit 300 may include multiple latch circuits 20, 24, and 26, a self-blocking circuit 22, and two data timing marker signal generation circuits 28 and 30. The latch circuit 20 has a first clock pulse port, a first input port D, and a first output port Q, wherein the first clock pulse port can be used to receive the inverted signal of the lower data strobe signal LDQS (in...). Figure 3 The Chinese label is marked as "(LDQS)". - The first input port D can be used to receive the data window signal CAIWSP. The self-resisting circuit 22 can be coupled to the first output port Q of the latch circuit 20 and can be used to adjust the output of the latch circuit 20 based on the output of the first output port Q (which is located at...). Figure 3 The signal is marked as "PQ05" (hereinafter referred to as signal PQ05) and the self-resistance signal SBS to generate the protection signal PS. The self-resistance signal SBS is generated based on the second data timing mark signal Q05, the third data timing mark signal Q15 and the fourth data timing mark signal Q25.

[0024] For example, in this embodiment, the self-resistance circuit 22 may include a NOR gate circuit 21 and an AND gate circuit 23. The NOR gate circuit 21 can be used to receive the second data timing mark signal Q05, the third data timing mark signal Q15 and the fourth data timing mark signal Q25 to generate the self-resistance signal SBS. The AND gate circuit 23 can be coupled to the first output port Q of the latch circuit 20 and the NOR gate circuit 21, and can be used to receive the signal PQ05 and the self-resistance signal SBS to generate the protection signal PS.

[0025] The latch circuit 24 has a second clock pulse port, a second input port D, and a second output port Q. The second clock pulse port can be used to receive the lower data strobe signal LDQS. The second input port D can be coupled to the self-resistance circuit 22 and can be used to receive the protection signal PS. The second output port Q can be used to output the first data timing mark signal Q00. The latch circuit 26 has a third clock pulse port, a third input port D, and a third output port Q. The third clock pulse port can be used to receive the inverted signal of the lower data strobe signal LDQS. The third input port D can be coupled to the second output port Q of the latch circuit 24 and can be used to receive the first data timing mark signal Q00. The third output port Q can be used to output the second data timing mark signal Q05.

[0026] The data timing mark signal generation circuit 28 can be coupled to the third output port Q of the latch circuit 26, and can be used to generate the third data timing mark signal Q15 according to the second data timing mark signal Q05. In this embodiment, the data timing mark signal generation circuit 28 may include two latch circuits 27 and 29. The latch circuit 27 has a fourth clock pulse port, a fourth input port D and a fourth output port Q, wherein the fourth clock pulse port can be used to receive the lower data strobe signal LDQS, and the fourth input port D can be coupled to the third output port Q of the latch circuit 26, and can be used to receive the second data timing mark signal Q05. The latch circuit 29 has a fifth clock pulse port, a fifth input port D, and a fifth output port Q. The fifth clock pulse port can be used to receive the inverted signal of the lower data strobe signal LDQS. The fifth input port D can be coupled to the fourth output port Q of the latch circuit 27 and can be used to receive the output at the fourth output port Q of the latch circuit 27. The fifth output port Q can be used to output the third data timing mark signal Q15.

[0027] The data timing mark signal generation circuit 30 can be coupled to the data timing mark signal generation circuit 28 and can be used to generate the fourth data timing mark signal Q25 according to the third data timing mark signal Q15. In this embodiment, the data timing mark signal generation circuit 30 may include two latch circuits 31 and 32. The latch circuit 31 has a sixth clock pulse port, a sixth input port D and a sixth output port Q. The sixth clock pulse port can be used to receive the lower data strobe signal LDQS, and the sixth input port D can be coupled to the data timing mark signal generation circuit 28 (especially the fifth output port Q of the latch circuit 29 in the data timing mark signal generation circuit 28) and can be used to receive the third data timing mark signal Q15. The latch circuit 32 has a seventh clock pulse port, a seventh input port D, and a seventh output port Q. The seventh clock pulse port can be used to receive the inverted signal of the lower data strobe signal LDQS. The seventh input port D can be coupled to the sixth output port Q of the latch circuit 31 and can be used to receive the output at the sixth output port Q of the latch circuit 31. The seventh output port Q can be used to output the fourth data timing mark signal Q25.

[0028] Furthermore, it should be noted that each of latch circuits 20, 24, 26, 27, 29, 31, and 32 is a D-type latch circuit, but the present invention is not limited thereto.

[0029] Figure 4 According to an embodiment of the present invention, in the tDQSS2 case, by Figure 3 The timing diagram shown illustrates the clock pulse signal, data strobe signal, data window signal, and multiple data timing marker signals acquired by the data control circuit 300. Assume that after the write command WR is executed, data signals DQ0 to DQ7 (in...) Figure 4 (DQ1 to DQ7 are not shown in the table), which correspond to 8 write data entries (in... Figure 4 The data (marked as "D1~D8") is transmitted to the data processing circuit 18. It should be noted that during one period from time point T9 to time point T13, the eight write data are transmitted to the data processing circuit 18 in a sequential communication manner, and the timing of the eight write data is marked by the second data timing mark signal Q05 and the fourth data timing mark signal Q25, respectively. However, after time point T13, the eight write data are transmitted to the memory cell circuit 14 in a parallel communication manner.

[0030] like Figure 4As shown, a write command WR is issued at time T0, and the write latency WL is equal to 9 (that is, the write command WR is first operated at time T9, and data signals DQ0 to DQ7 begin to be transmitted at time T9). In this embodiment, the column-to-column delay time (tCCD) is equal to 4, meaning that the time interval between the operation timings of two adjacent write commands is 4 * clock cycle time (tCK). Furthermore, the block signal BLOCK is the sum of the second data timing marker signal Q05, the third data timing marker signal Q15, and the fourth data timing marker signal Q25 (e.g., the result of an OR operation on the second data timing marker signal Q05, the third data timing marker signal Q15, and the fourth data timing marker signal Q25), and is the inverse signal of the self-blocking signal SBS. The signals shown above the dashed line L1 (i.e., the real clock pulse signal CK_t and the lower real data strobe signal LDQS_t) are external signals of the memory device 100, and the signals shown below the dashed line L1 (i.e., the data window signal CAIWSP, the lower data strobe signal LDQS, the signal PQ05, the protection signal PS, the first data timing mark signal Q00, the second data timing mark signal Q05, the third data timing mark signal Q15, the fourth data timing mark signal Q25, and the blocking signal BLOCK) are internal signals of the data control circuit 300.

[0031] Furthermore, the pulse width of the data window signal CAIWSP is 2*tCK, and the lower data strobe signal LDQS consists of 8 write data points toggled 4 times every 4 time cycles (e.g., from time point T9 to time point T13) (i.e., switching from low level to high level 4 times). Ideally, the rising edge of the lower data strobe signal LDQS should strobe the data window signal CAIWSP exactly at time point T9. However, since the lower data strobe signal LDQS may be generated by transmitting the lower real data strobe signal LDQS_t to the data control circuit 300 through the input buffer, the rising edge of the lower data strobe signal LDQS strobes the data window signal CAIWSP closer to time point T9.

[0032] Considering the case where latch circuit 24 is directly coupled to latch circuit 20 (i.e., the case where data control circuit 300 is modified to remove self-resistance circuit 22), since signal PQ05 is selected at a high level by the lower data strobe signal LDQS and... Figure 4As shown at position A, signal PQ05 is at a high level, therefore the first data timing marker signal Q00 will remain at a high level until a time point T11, which may cause 8 write data to be written to memory cell circuit 14 at incorrect timing. That is, the timing of the second data timing marker signal Q05, the third data timing marker signal Q15, and the fourth data timing marker signal Q25 may be incorrect. In addition, since signal PQ05 is selected by the high level of the lower data strobe signal LDQS and... Figure 4 At position B, signal PQ05 is at a high level, so the first data timing marker signal Q00 will remain at a high level until time point T15, which may also cause 8 write data to be written to memory cell circuit 14 at the wrong timing.

[0033] In this embodiment, which has a self-resisting circuit 22 implemented in the data control circuit 300, the blocking signal BLOCK can be used to avoid the above situation. Figure 4 As shown in positions C and D, signal PQ05 is blocked, meaning that the protection signal PS (obtained by performing an AND operation on signal PQ05 and the inverse signal of the blocking signal BLOCK, i.e., the self-blocking signal SBS) has a low level in the timing region covered by positions C and D. Since the protection signal PS has a low level in positions A and B and is selected by the high level of the lower data strobe signal LDQS, the level of the first data timing marker signal Q00 will be low in positions A and B. Thus, the timing of the first data timing marker signal Q00, the second data timing marker signal Q05, the third data timing marker signal Q15, and the fourth data timing marker signal Q25 can be correct, and the data control circuit 300 of the present invention can be used to correctly write eight write data values ​​to the memory cell circuit 14.

[0034] Figure 5 According to an embodiment of the present invention, in the tDQSS2 case, by Figure 3 The timing diagram shown is of the clock pulse signal, data strobe signal (which rises for the first time after the operation timing of the write command), data window signal, and multiple data timing marker signals obtained by the data control circuit 300. Figure 4 and Figure 5 The difference lies in Figure 5 The first rising edge of the data strobe signal LDQS is the intermediate timing between time points T9 and T10 (which is still within the range of the data window signal CAIWSP), not close to time point T9. For the sake of brevity, similar content will not be described again here. If the data control circuit 300 is modified to remove the self-resistance circuit 22, in Figure 5At position A, since signal PQ05 is a high-level signal and is selected by the high-level lower data strobe signal LDQS, the level of the first data timing mark signal Q00 will change from low to high before the correct timing (i.e., the timing between the intermediate timing point T13 and T14), which may cause 8 write data to be written to the memory cell circuit 14 at the wrong timing.

[0035] In this embodiment, which has a self-resisting circuit 22 implemented in the data control circuit 300, since the blocking signal BLOCK is at a high level at position A, the protection signal PS (which is obtained by performing an AND operation on the signal PQ05 and the inverse signal of the blocking signal BLOCK (i.e., the self-resisting signal SBS)) will remain at a low level at position A. This causes the first data timing marker signal Q00 to remain at a low level until the correct timing (i.e., the timing of the intermediate timing between time point T13 and time point T14). In this way, the timing of the second data timing marker signal Q05, the third data timing marker signal Q15, and the fourth data timing marker signal Q25 can be correct, and the data control circuit 300 of the present invention can be used to correctly write eight write data to the memory cell circuit 14.

[0036] Figure 6 According to an embodiment of the present invention, in the tDQSS2 case, by Figure 3 The timing diagram shown includes the clock pulse signal, data strobe signal (which rises for the first time before the write command operation timing), data window signal, and multiple data timing marker signals obtained by the data control circuit. Figure 4 and Figure 6 The difference lies in Figure 6 The first rising edge of the lower data strobe signal LDQS is near the intermediate timing between time points T8 and T9 (which is still within the range of the data window signal CAIWSP), not near time point T9. For the sake of brevity, similar content will not be described again here. If the data control circuit 300 is modified to remove the self-resistance circuit 22, in Figure 6 At position A, since signal PQ05 is a high-level signal and is selected at a high level by the lower data strobe signal LDQS, the first data timing marker signal Q00 will remain high until it approaches the intermediate timing between time point T10 and time point T11. This may cause 8 write data to be written to memory cell circuit 14 at incorrect timing. That is, the timing of the second data timing marker signal Q05, the third data timing marker signal Q15, and the fourth data timing marker signal Q25 may be incorrect. Furthermore, in Figure 6At position B, since signal PQ05 is a high-level signal and is selected at a high level by the lower data strobe signal LDQS, the first data timing mark signal Q00 will remain at a high level until it approaches the intermediate timing between time point T14 and time point T15. This may also cause 8 write data to be written to memory cell circuit 14 at incorrect timing.

[0037] In this embodiment, which has a self-resisting circuit 22 implemented in the data control circuit 300, since the blocking signal BLOCK is at a high level at positions A and B, the protection signal PS (which is obtained by performing an AND operation on the signal PQ05 and the inverse signal of the blocking signal BLOCK (i.e., the self-resisting signal SBS)) is at a low level at positions A and B. This causes the first data timing mark signal Q00 to be a low level signal at positions A and B. In this way, the timing of the second data timing mark signal Q05, the third data timing mark signal Q15, and the fourth data timing mark signal Q25 can be correct, and the data control circuit 300 of the present invention can be used to correctly write eight write data to the memory cell circuit 14.

[0038] In the case of tDQSS, in the prior art, the pulse width of the data window signal could reach 1*tCK, which could handle the value of tDQSS in the DDR SDRAM specification up to ±0.4*tCK. In reality, it is difficult to make the pulse width of the data window signal exactly 1*tCK. Figure 7 According to an embodiment of the present invention, under the tDQSS case, Figure 3 The diagram shows the timing of the clock pulse signal, data strobe signal, data window signal, and multiple data timing marker signals acquired by the data control circuit 300. In this embodiment, the pulse width of the data window signal CAIWSP is increased to 1.5*tCK. Once the pulse width of the data window signal is greater than 1*tCK, DDR SDRAM manufacturers can more easily manufacture DDR SDRAM. It should be noted that 1.5*tCK is only used as an example to illustrate the pulse width of the data window signal CAIWSP achievable by the data control circuit 300 of this invention. In reality, the pulse width of the data window signal CAIWSP can be other tCK lengths (e.g., 1.3*tCK or 1.4*tCK). Therefore, the design flexibility of this invention is higher than that of the prior art. Figure 7 The detailed information of the signals shown has been described in the above embodiments, and for the sake of brevity, similar content will not be repeated here.

[0039] In this embodiment, at positions C and D, signal PQ05 is blocked by the blocking signal BLOCK. That is, in the timing region covered by positions C and D, the protection signal PS (obtained by performing an AND operation on the inverse signal of signal PQ05 and the blocking signal BLOCK, i.e., the self-blocking signal SBS) is a low-level signal. At positions A and B, since the protection signal PS is a low-level signal and is selected at a high level by the lower data strobe signal LDQS, the first data timing marker signal Q00 is also a low-level signal. As a result, the timing of the first data timing marker signal Q00, the second data timing marker signal Q05, the third data timing marker signal Q15, and the fourth data timing marker signal Q25 can be correct, and the data control circuit 300 of the present invention can be used to correctly write eight write data to the memory cell circuit 14.

[0040] Figure 8 According to an embodiment of the present invention, under the tDQSS case, Figure 3 The timing diagram shown is of the clock pulse signal, data strobe signal (which rises for the first time after the operation timing of the write command), data window signal, and multiple data timing marker signals obtained by the data control circuit 300. Figure 7 and Figure 8 The difference lies in Figure 8 The first rising edge of the data strobe signal LDQS is the intermediate timing between time points T9 and T10 (which is still within the range of the data window signal CAIWSP), not close to time point T9. For the sake of brevity, similar content will not be described again here. If the data control circuit 300 is modified to remove the self-resistance circuit 22, in Figure 8 At position A, since signal PQ05 is a high-level signal and is selected by the high-level lower data strobe signal LDQS, the level of the first data timing mark signal Q00 will change from low to high before the correct timing (i.e., the timing between the intermediate timing point T13 and T14), which may cause 8 write data to be written to the memory cell circuit 14 at the wrong timing.

[0041] In this embodiment, which has a self-resisting circuit 22 implemented in the data control circuit 300, since the blocking signal BLOCK is at a high level at position A, the protection signal PS (which is obtained by performing an AND operation on the signal PQ05 and the inverse signal of the blocking signal BLOCK (i.e., the self-resisting signal SBS)) will remain at a low level at position A. This causes the first data timing marker signal Q00 to remain at a low level until the correct timing (i.e., the timing of the intermediate timing between time point T13 and time point T14). In this way, the timing of the second data timing marker signal Q05, the third data timing marker signal Q15, and the fourth data timing marker signal Q25 can be correct, and the data control circuit 300 of the present invention can be used to correctly write eight write data to the memory cell circuit 14.

[0042] Figure 9 According to an embodiment of the present invention, under the tDQSS case, Figure 3 The timing diagram shown is of the clock pulse signal, data strobe signal (which rises for the first time before the operation timing of the write command), data window signal, and multiple data timing marker signals obtained by the data control circuit 300. Figure 7 and Figure 9 The difference lies in Figure 9 The first rising edge of the lower data strobe signal LDQS is near the intermediate timing between time points T8 and T9 (which is still within the range of the data window signal CAIWSP), not near time point T9. For the sake of brevity, similar content will not be described again here. If the data control circuit 300 is modified to remove the self-resistance circuit 22, in Figure 9 At position A, since signal PQ05 is a high-level signal and is selected at a high level by the lower data strobe signal LDQS, the first data timing marker signal Q00 will remain high until it approaches the intermediate timing between time point T10 and time point T11. This may cause 8 write data to be written to memory cell circuit 14 at incorrect timing. That is, the timing of the second data timing marker signal Q05, the third data timing marker signal Q15, and the fourth data timing marker signal Q25 may be incorrect. Furthermore, in Figure 9 At position B, since signal PQ05 is a high-level signal and is selected at a high level by the lower data strobe signal LDQS, the first data timing mark signal Q00 will remain at a high level until it approaches the intermediate timing between time point T14 and time point T15. This may also cause 8 write data to be written to memory cell circuit 14 at incorrect timing.

[0043] In this embodiment, which has a self-resisting circuit 22 implemented in the data control circuit 300, since the blocking signal BLOCK is at a high level at positions A and B, the protection signal PS (which is obtained by performing an AND operation on the signal PQ05 and the inverse signal of the blocking signal BLOCK (i.e., the self-resisting signal SBS)) is at a low level at positions A and B. This causes the first data timing mark signal Q00 to be a low level signal at positions A and B. In this way, the timing of the second data timing mark signal Q05, the third data timing mark signal Q15, and the fourth data timing mark signal Q25 can be correct, and the data control circuit 300 of the present invention can be used to correctly write eight write data to the memory cell circuit 14.

[0044] Table 1

[0045] Write format Blocking signal width BL4 1*tCK BL8 3*tCK BL4 in CRC mode 4*tCK BL8 in CRC mode 4*tCK

[0046] For different burst lengths, the write formats of DDR4 SDRAM (e.g., BL4, BL8, BL4 in cyclic redundancy check (CRC) mode, or BL8 in CRC mode) can all be applied by the data control circuit provided by this invention. For example, a write command corresponding to four write data points for write format BL4 can be applied by the data control circuit provided by this invention. Table 1 illustrates the width of the block signal BLOCK used in the data control circuit of this invention for different write formats of DDR4 SDRAM. For write format BL4, the lower data strobe signal LDQS is 4 write data switches 2 times and the width of the block signal BLOCK is 1*tCK; for write format BL8 (which is applied in the above embodiments), the lower data strobe signal LDQS is 8 write data switches 4 times and the width of the block signal BLOCK is 3*tCK; and for BL4 in CRC mode and BL8 in CRC mode, the lower data strobe signal LDQS is 9 write data switches 5 times and the width of the block signal BLOCK is 4*tCK.

[0047] Figure 10 According to another embodiment of the present invention, in the tDQSS2 case, by Figure 3 The timing diagram shown is of the clock pulse signal, data strobe signal, data window signal, and multiple data timing marker signals acquired by the data control circuit 300. Assume data signals DQ0~DQ7 (in...) Figure 10 (DQ1 to DQ7 are not shown in the text), which correspond to four write data (i.e., write format BL4) that are transmitted to the data control circuit 300, wherein... Figure 10 The four written data entries are labeled "D1" to "D4". For example... Figure 10 As shown, at time point T0, a write command WR corresponding to the write format BL4 is issued, and the write delay WL is equal to 9. During the period from time point T9 to time point T13, only the second data timing mark signal Q05 is used to mark 4 write data (that is, the constant levels of the third data timing mark signal Q15 and the fourth data timing mark signal Q25 are both equal to 0), and due to the OR operation, the blocking signal BLOCK is equal to the second data timing mark signal Q05.

[0048] In this embodiment, which includes a self-resisting circuit 22 implemented in the data control circuit 300, since the blocking signal BLOCK is at a high level at position A, the protection signal PS (obtained by performing an AND operation on signal PQ05 and the inverse signal of the blocking signal BLOCK, i.e., the self-resisting signal SBS) is at a low level at position A. This causes the first data timing marker signal Q00 to be a low-level signal at position A. As a result, the timing of the second data timing marker signal Q05, the third data timing marker signal Q15, and the fourth data timing marker signal Q25 can be correct, and the four write data can be correctly written to the memory cell circuit 14 using the data control circuit 300 of the present invention. After time point T13, the write format changes from write format BL4 to write format BL8. For the sake of brevity, similar content will not be described again here.

[0049] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

[0050] [Symbol Explanation]

[0051] 100: Memory device

[0052] 10: Command Input Interface

[0053] 12: Command Decoder

[0054] 14: Memory cell circuit

[0055] 16: Data Input / Output Interface

[0056] 18: Data processing circuit

[0057] COMMAND_SIGNAL: Command signal

[0058] CS: Control signal

[0059] CAIWSP: Data Window Signal

[0060] BANK_0~BANK_N: Memory libraries

[0061] DQ0~DQ7, DQ8~DQ15: Data signals

[0062] LDQS_t: Lower real data strobe signal

[0063] LDQS_c: Lower complementary data strobe signal

[0064] UDQS_t: Upper real data strobe signal

[0065] UDQS_c: Upper complementary data strobe signal

[0066] 200, 300: Data control circuit

[0067] 202: Sequence-to-Parallel Circuits

[0068] Q00, Q05, Q15, Q25: Data timing marker signals

[0069] DATA0~DATA63: Data input signals

[0070] LDQS: Lower Data Strobe Signal

[0071] 20, 24, 26, 27, 29, 31, 32: Latch circuits

[0072] 21: NOT OR gate circuit

[0073] 22: Self-resistance circuit

[0074] 23: AND gate circuit

[0075] 28, 30: Data timing mark signal generation circuit

[0076] SBS: Self-blocking signal

[0077] PS: Protection signal

[0078] CK_t: Real clock pulse signal

[0079] BLOCK: Block signal

Claims

1. A data control circuit, comprising: The first latch circuit has a first clock pulse port, a first input port and a first output port, wherein the first clock pulse port is used to receive a first clock pulse obtained from a data strobe signal, and the first input port is used to receive a data window signal. A self-resisting circuit is coupled to the first output port of the first latch circuit and is used to generate a protection signal based on the output of the first output port of the first latch circuit and the self-resisting signal. The second latch circuit has a second clock pulse port, a second input port and a second output port, wherein the second clock pulse port is used to receive a second clock pulse, which is obtained from the data strobe signal, the first clock pulse is the inverted signal of the second clock pulse, the second input port is coupled to the self-resistance circuit and is used to receive the protection signal, and the second output port is used to output a first data timing mark signal. The third latch circuit has a third clock pulse port, a third input port and a third output port, wherein the third clock pulse port is used to receive the first clock pulse, the third input port is coupled to the second output port of the second latch circuit and is used to receive the first data timing mark signal, and the third output port is used to output the second data timing mark signal. The first data timing mark signal generation circuit is coupled to the third output port of the third latch circuit and is used to generate a third data timing mark signal based on the second data timing mark signal. as well as The second data timing mark signal generation circuit is coupled to the first data timing mark signal generation circuit and is used to generate a fourth data timing mark signal based on the third data timing mark signal.

2. The data control circuit as claimed in claim 1, wherein the data window signal represents the maximum and minimum tolerance values ​​for the skew between the memory clock pulse signal and the data strobe signal.

3. The data control circuit as claimed in claim 1, wherein the timing of the plurality of data to be written transmitted to the memory cell circuit is sequentially marked by the second data timing mark signal and the fourth data timing mark signal.

4. The data control circuit as claimed in claim 1, wherein the self-resistance circuit is further configured to generate the self-resistance signal based on the second data timing mark signal, the third data timing mark signal, and the fourth data timing mark signal.

5. The data control circuit as described in claim 4, wherein the self-resistance circuit comprises: A NOT OR gate circuit is used to receive the second data timing mark signal, the third data timing mark signal, and the fourth data timing mark signal to generate the self-resistance signal; and An AND gate circuit is coupled to the first output port of the first latch circuit and the NOT OR gate circuit, and is used to receive the output of the first output port of the first latch circuit and the self-resistance signal to generate the protection signal.

6. The data control circuit as claimed in claim 1, wherein each of the first latch circuit, the second latch circuit, and the third latch circuit is a D-type latch circuit.

7. The data control circuit as claimed in claim 1, wherein the first data timing mark signal generation circuit comprises: The fourth latch circuit has a fourth clock pulse port, a fourth input port, and a fourth output port, wherein the fourth clock pulse port is used to receive the second clock pulse, and the fourth input port is coupled to the third output port of the third latch circuit and used to receive the second data timing mark signal; and The fifth latch circuit has a fifth clock pulse port, a fifth input port, and a fifth output port. The fifth clock pulse port is used to receive the first clock pulse. The fifth input port is coupled to the fourth output port of the fourth latch circuit and is used to receive the output of the fourth output port of the fourth latch circuit. The fifth output port is used to output the third data timing mark signal.

8. The data control circuit as claimed in claim 7, wherein each of the first latch circuit, the second latch circuit, the third latch circuit, the fourth latch circuit, and the fifth latch circuit is a D-type latch circuit.

9. The data control circuit as claimed in claim 1, wherein the second data timing mark signal generation circuit comprises: The fourth latch circuit has a fourth clock pulse port, a fourth input port, and a fourth output port, wherein the fourth clock pulse port is used to receive the second clock pulse, and the fourth input port is coupled to the first data timing mark signal generation circuit and used to receive the third data timing mark signal; and The fifth latch circuit has a fifth clock pulse port, a fifth input port, and a fifth output port. The fifth clock pulse port is used to receive the first clock pulse. The fifth input port is coupled to the fourth output port of the fourth latch circuit and is used to receive the output of the fourth output port of the fourth latch circuit. The fifth output port is used to output the fourth data timing mark signal.

10. The data control circuit of claim 9, wherein each of the first latch circuit, the second latch circuit, the third latch circuit, the fourth latch circuit, and the fifth latch circuit is a D-type latch circuit.

11. The data control circuit of claim 1, wherein the first clock pulse is the inverted signal of the data strobe signal, and the second clock pulse is the data strobe signal.

12. A memory device comprising: Command input interface, used to receive multiple command signals; A command decoder, coupled to the command input interface, is used to receive and decode the multiple command signals to generate a data window signal and a control signal, wherein the data window signal corresponds to a write command; A memory cell circuit, coupled to the command decoder, and having multiple memory banks, wherein the memory cell circuit is controlled by the control signal; A data input / output interface for receiving multiple data signals and a data strobe signal, wherein the multiple data signals correspond to multiple data to be written and are transmitted in a sequential communication manner; and The data processing circuit includes: A sequence-to-parallel circuit is coupled to the data input / output interface and the memory cell circuit, and is used to convert the plurality of data signals into a plurality of data input signals according to the data strobe signal, the second data timing mark signal and the fourth data timing mark signal, wherein the plurality of data input signals are transmitted to the memory cell circuit in a parallel communication manner. as well as A data control circuit, coupled to the command decoder, the data input / output interface, and the sequence-to-parallel circuit, and comprising: The first latch circuit has a first clock pulse port, a first input port and a first output port, wherein the first clock pulse port is used to receive a first clock pulse, which is obtained from the data strobe signal, and the first input port is used to receive the data window signal. A self-resisting circuit is coupled to the first output port of the first latch circuit and is used to generate a protection signal based on the output of the first output port of the first latch circuit and the self-resisting signal. The second latch circuit has a second clock pulse port, a second input port and a second output port, wherein the second clock pulse port is used to receive a second clock pulse, which is obtained from the data strobe signal, the first clock pulse is the inverted signal of the second clock pulse, the second input port is coupled to the self-resistance circuit and is used to receive the protection signal, and the second output port is used to output a first data timing mark signal. The third latch circuit has a third clock pulse port, a third input port and a third output port, wherein the third clock pulse port is used to receive the first clock pulse, the third input port is coupled to the second output port of the second latch circuit and is used to receive the first data timing mark signal, and the third output port is used to output the second data timing mark signal. The first data timing mark signal generation circuit is coupled to the third output port of the third latch circuit and is used to generate a third data timing mark signal based on the second data timing mark signal. as well as The second data timing mark signal generation circuit is coupled to the first data timing mark signal generation circuit and is used to generate the fourth data timing mark signal based on the third data timing mark signal.

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