Low voltage high performance organic light emitting transistor based on full layer heterojunction

Abstract

The application discloses a kind of low-voltage high-performance organic light-emitting transistor (OLETs) based on full-layer heterojunction.The OLET of the application adopts full-layer heterojunction structure, comprising drain electrode, drain electrode modification layer, electron transport layer, light-emitting layer, source electrode, source electrode modification layer, hole transport layer, insulating layer, gate electrode and glass substrate in turn from top to bottom.The OLET of the application adopts the device structure of non-planar asymmetric electrode, the gate electrode adopts the double-layer heterojunction structure of high-conductivity material and high-transparency material;The insulating layer adopts the double-layer heterojunction structure of high-dielectric constant material and high-hydrophobic material;The transport layer adopts the double-layer heterojunction structure of high-charge transport material and energy level matching material;The light-emitting layer adopts the double-layer heterojunction structure of P-type host-guest doping and N-type host-guest doping.The OLET of the full-layer heterojunction simultaneously realizes low-voltage, high brightness, high external quantum efficiency, large aperture ratio, high stability and performance uniform OLETs.

Description

Technical Field

[0001] This invention relates to the field of organic optoelectronic device technology, and in particular to a low-voltage, high-performance, fully heterojunction organic light-emitting transistor. Background Technology

[0002] Over the past few decades, organic semiconductor materials have made significant progress in the field of photoelectric conversion. Organic optoelectronic materials are a class of photoelectrically active materials widely used in various optoelectronic devices such as organic light-emitting diodes (OLEDs), organic field-effect transistors (OFETs), organic solar cells (OPVs), organic memories, and sensors, and have long been highly valued by the scientific and industrial communities. Organic light-emitting transistors (OLETs) are a new type of organic optoelectronic device developed in recent years. They combine the switching function of OFETs with the light-emitting function of OLEDs, and have the advantages of simple fabrication process, high current density, and high integration. They have great application prospects in next-generation display technology, multifunctional devices, solid-state lighting, and organic electrically pumped lasers. Currently, mainstream AMOLED screens are thinner and consume less power due to the absence of a backlight and their self-emissive characteristics. However, this device structure is composed of individual thin-film transistors controlling each light-emitting pixel, resulting in a complex structure, difficult fabrication process, and high cost. OLETs, which integrate the switching function of OFETs and the light-emitting characteristics of OLEDs, are expected to further simplify the device structure of AMOLEDs.

[0003] In recent years, Ebinazar B. Namdas et al. have significantly improved the brightness, EQE, and aperture ratio of their devices by using non-planar device structures and hybrid light-emitting transistor (OLED) structures. Gianluca Generali et al. have significantly reduced the operating voltage of their devices by using insulating layers with high dielectric constants. To date, although OLEDs have made significant progress in some optoelectronic properties, OLED technology is still far from practical application in displays. The key issue is that low-voltage, high-brightness, high-EQE, large aperture ratio, high stability, and uniform performance organic light-emitting transistors have not been achieved in a single device, failing to meet the requirements of practical applications. Therefore, the fabrication of low-voltage, high-performance, high-stability, and uniform performance organic light-emitting transistors has significant research significance and commercial value. Summary of the Invention

[0004] This invention employs a full-layer heterojunction organic light-emitting transistor (AHOLETs). Its purpose is to reduce the operating voltage of the AHOLETs and improve device stability by using a composite insulating layer composed of high dielectric constant and highly hydrophobic materials. The full-layer heterojunction device structure increases carrier concentration and exciton recombination efficiency, thereby improving device brightness and external quantum efficiency (EQE). Simultaneously, the use of silver nanowires and PEDOT:PSS as gate electrodes enhances device transparency, reduces exciton quenching by the electrodes, lowers light loss, and improves the device's optical performance.

[0005] The low-voltage, high-performance organic light-emitting transistors (AHOLETs) based on a full-layer heterojunction provided by this invention are shown in the schematic diagram below. Figure 1 As shown. Its structure, from bottom to top, includes a substrate ①, gate electrodes ② and ③, insulating layers ④ and ⑤, hole transport layers ⑥ and ⑦, source electrode modification layer ⑧, source electrode ⑨, and light-emitting layer ⑩ and... Electron transport layer and Drain electrode modification layer and drain electrode

[0006] The substrate may specifically be a glass substrate.

[0007] The gate electrode material is selected from one or two of ITO, PEDOT:PSS, and silver nanowires, preferably silver nanowires and PEDOT:PSS. Specifically, gate electrode ② is silver nanowires; gate electrode ③ is PEDOT:PSS. The silver nanowire and PEDOT:PSS dispersion is dispersed in methanol, ethanol, isopropanol, or water, preferably isopropanol; the dispersion degree of the silver nanowire and PEDOT:PSS dispersion is 0.05-0.6 mg / mL, preferably 0.1-0.3 mg / mL.

[0008] The insulating layer material is selected from one or two of PMMA, PVA, perfluorinated resin (CYTOP), and P(VDF-TrFE-CFE), preferably P(VDF-TrFE-CFE) (molecular weight: ~600,000 Daltons) and CYTOP (molecular weight: ~200,000 Daltons). Specifically, insulating layer ④ is P(VDF-TrFE-CFE), and insulating layer ⑤ is CYTOP. The P(VDF-TrFE-CFE) is dissolved in acetone, cyclopentanone, N-methylpyrrolidone, dimethylacetamide, dimethylformamide, or dimethyl sulfoxide; preferably acetone or cyclopentanone. The concentration of the P(VDF-TrFE-CFE) solution is 30-80 mg / mL, preferably 50-70 mg / mL. The CYTOP insulating layer is dissolved in a special fluorinated solvent, with a solute-to-solvent volume ratio of (1:3), (1:5), (1:10), or (1:12), preferably (1:5) or (1:10).

[0009] The hole transport layer material is selected from one or two of the following: pentane, 2,7-dioctyl[1]benzothiophene[3,2-B]benzothiophene (C8-BTBT), N,N'-diphenyl-N,N'-(1-naphthyl)-1,1'-biphenyl-4,4'-diamine (NPB), 4-[1-[4-[di(4-methylphenyl)amino]phenyl]cyclohexyl]-N-(3-methylphenyl)-N-(4-methylphenyl)aniline (TAPC), and 4,4',4”-tris(carbazole-9-yl)triphenylamine (TCTA), preferably 2,7-dioctyl[1]benzothiophene[3,2-B]benzothiophene (C8-BTBT) and 4,4',4”-tris(carbazole-9-yl)triphenylamine (TCTA).

[0010] Specifically, the hole transport layer ⑥ is C8-BTBT, with a thickness of 20-100nm, preferably 30-60nm; the hole transport layer ⑦ is TCTA, with a thickness of 1-20nm, preferably 5-10nm.

[0011] The source electrode modification material is molybdenum oxide (MoO3).

[0012] The source electrode material is gold (Au).

[0013] The guest material of the light-emitting layer is iridium bis(2-phenylpyridine)acetylacetonate (Ir(ppy)2(acac)). The host material of the light-emitting layer is selected from one or two of 4,4'-bis(9-carbazole)biphenyl (CBP), 3,3-bis(9H-carbazole-9-yl)biphenyl (mCBP), 4-[1-[4-[bis(4-methylphenyl)amino]phenyl]cyclohexyl]-N-(3-methylphenyl)-N-(4-methylphenyl)aniline (TAPC), 4,4',4”-tris(carbazole-9-yl)triphenylamine (TCTA), and 1,3,5-tris(1-phenyl-1H-benzimidazole-2-yl)benzene (TPBi), preferably 4,4',4”-tris(carbazole-9-yl)triphenylamine (TCTA) and 1,3,5-tris(1-phenyl-1H-benzimidazole-2-yl)benzene (TPBi).

[0014] Specifically, the light-emitting layer includes a P-type doped light-emitting layer (10) and an N-type doped light-emitting layer (10). The P-type doped luminescent layer ⑩ specifically uses TCTA as the P-type doping host material; the N-type doped luminescent layer The N-type doped host material used is TPBi.

[0015] The electron transport layer material is selected from 3,3'-[5'-[3-(3-pyridyl)phenyl][1,1':3',1”-terphenyl]-3,3”-diyl]pyridine (TmPyPB), 4,6-bis(3,5-bis(3-pyridyl)phenyl)-2-methylpyrimidine (B3PYMPM), 4,7-diphenyl-1,10-phenanthroline (Bphen), 2,2'-(1,3-phenyl)bis[5-(4-tert-butylphenyl)-1,3,4-oxadiazole] (OXD-7) and N,N-tetracarboxydiimide (PTCDI-C). 13 H 27 One or two of the following, preferably 4,6-bis(3,5-di(3-pyridylphenyl)-2-methylpyrimidine (B3PYMPM) and N,N-tetracarboxylic acid-3,4,9,10-tetracarboxydiimide (PTCDI-C) 13 H 27 ).

[0016] Specifically, the electron transport layer B3PYMPM, electron transport layer For PTCDI-C 13 H 27 .

[0017] The drain electrode modification material is selected from any one of lithium fluoride (LiF), cesium fluoride (CsF), cesium carbonate (Cs2O3) or 8-hydroxyquinoline-lithium (Liq), with lithium fluoride (LiF) being preferred;

[0018] The drain electrode material is selected from one or two of aluminum (Al), silver (Ag) and calcium (Ca), with aluminum (Al) being preferred.

[0019] Furthermore, in the low-voltage high-performance organic light-emitting transistor based on a full-layer heterojunction described in this invention, the drain electrode modification layer is located at one end above the electron transport layer, and the drain electrode is located above the drain electrode modification layer and covers the drain electrode modification layer.

[0020] The source electrode modification layer is located at one end above the hole transport layer, and the source electrode is located above and covers the source electrode modification layer; the light-emitting layer is located above the electron transport layer and covers the source electrode, forming a stepped light-emitting layer.

[0021] Furthermore, the drain electrode and the source electrode are located at opposite ends.

[0022] The method for fabricating a low-voltage, high-performance organic light-emitting transistor based on a full-layer heterojunction provided by this invention includes the following steps:

[0023] (1) A gate electrode is prepared on a substrate by spraying.

[0024] (2) An insulating layer is prepared on the gate electrode prepared in step (1) by spin coating, drop coating, scraping coating, spraying or brushing.

[0025] (3) A hole transport layer is prepared on the insulating layer prepared in step (2) by vacuum evaporation.

[0026] (4) A source electrode modification layer is prepared on the hole transport layer prepared in step (3) by vacuum evaporation.

[0027] (5) The source electrode is prepared on the source electrode modification layer prepared in step (4) by vacuum evaporation.

[0028] (6) A light-emitting layer is prepared on the source electrode prepared in step (5) by vacuum evaporation.

[0029] (7) An electron transport layer is prepared on the light-emitting layer prepared in step (6) by vacuum evaporation.

[0030] (8) A drain electrode modification layer is prepared on the electron transport layer prepared in step (7) by vacuum evaporation.

[0031] (9) A drain electrode is prepared on the drain electrode modification layer prepared in step (8) by vacuum evaporation.

[0032] In step (1) of the above method, the substrate is any one of glass, ceramic, silicon wafer or polymer; before use, the substrate is ultrasonically cleaned in sequence with detergent solution, tap water, deionized water, acetone and ethanol; the ultrasonic power is 20-100 watts and the ultrasonic time is 1-30 minutes.

[0033] In step (1) of the above method, the spraying conditions for the silver nanowire gate electrode ② are as follows: the spraying rate is 0.1-5 mL / min, preferably 0.3-1 mL / min; the distance between the spray gun and the substrate is 3-15 cm, preferably 6-10 cm; and the annealing temperature is 40-180℃, preferably 80-120℃.

[0034] In step (1) of the above method, the spraying conditions for the PEDOT:PSS gate electrode ③ are as follows: the spraying rate is 0.1-5 mL / min, preferably 0.3-1 mL / min; the distance between the spray gun and the substrate is 3-15 cm, preferably 3-6 cm; and the substrate heating temperature during spraying is 20-180℃, preferably 60-80℃.

[0035] In step (2) of the above method, the insulating layer ④P (VDF-TrFE-CFE) is prepared by any of the following methods: spin coating, drop coating, blade coating, or brush coating. The thickness of the insulating layer is 100-1000 nm, preferably 400-600 nm.

[0036] In step (2) of the above method, the insulating layer ⑤CYTOP is prepared by any of the following methods: spin coating, drop coating, blade coating, or brush coating. The thickness of the insulating layer is 5-30 nm, preferably 10-20 nm.

[0037] In step (3) of the above method, the hole transport layer is prepared by vacuum evaporation; the evaporation conditions are: vacuum degree of 10 -4 -10 -7 Pascal, preferably 6×10 -6 -10 -7 Pascal; the evaporation rate is 0.1-1 Å / s, preferably 0.1-0.5 Å / s; the thickness of the hole transport layer ⑥ is 20-100 nm, preferably 30-60 nm; the thickness of the hole transport layer ⑦ is 1-20 nm, preferably 5-10 nm.

[0038] In step (4) of the above method, the source electrode modification layer is prepared by vacuum evaporation; the evaporation conditions are: vacuum degree of 10 -4 -10 -7 Pascal, preferably 3-5 × 10 -4 Pascal; evaporation rate of 0.1-1 Å / s, preferably 0.1-0.2 Å / s; thickness of source electrode modification layer ⑧ of 1-20 nm, preferably 1-10 nm.

[0039] In step (5) of the above method, the source electrode is prepared by vacuum evaporation; the evaporation conditions are: vacuum degree of 10 -4 -10 -7 Pascal, preferably 3-5 × 10 -4 Pascal; evaporation rate of 0.1-1 Å / s, preferably 0.1-0.2 Å / s; thickness of source electrode ⑨ of 15-40 nm, preferably 20-30 nm.

[0040] In step (6) of the above method, the host and guest dopants in the light-emitting layer are prepared by vacuum evaporation; the evaporation conditions are: vacuum degree of 10 -4 -10 -7 Pascal, preferably 6×10 -6 -10 -7 Pascal; the evaporation rate of the host material is 0.1-1 Å / s, preferably 0.5-1 Å / s; the evaporation rate of the guest material is 0.05-1 Å / s, preferably 0.05-0.2 Å / s; the thickness of the P-type doped emitting layer ⑩ is 20-150 nm, preferably 20-60 nm, and the N-type doped emitting layer... The thickness is 20-150nm, preferably 20-60nm.

[0041] In step (7) of the above method, the electron transport layer is prepared by vacuum evaporation; the evaporation conditions are: vacuum degree of 10 -4 -10 -7 Pascal, preferably 6×10 -6 -10 -7 Pascal; evaporation rate of 0.1-1 Å / s, preferably 0.1-0.5 Å / s; electron transport layer The thickness is 1-20nm, preferably 5-10nm; electron transport layer The thickness is 20-100nm, preferably 20-60nm.

[0042] In step (8) of the above method, the drain electrode modification layer is prepared by vacuum evaporation; the evaporation conditions are: vacuum degree of 10 -4 -10 -7 Pascal, preferably 3-5 × 10 -4 Pascal; evaporation rate of 0.1-1 Å / s, preferably 0.1-0.2 Å / s; drain electrode modification layer The thickness is 1-20nm, preferably 3-10nm.

[0043] In step (9) of the above method, the drain electrode is prepared by vacuum evaporation; the evaporation conditions are: vacuum degree of 10 -4 -10 -7 Pascal, preferably 3-5 × 10-4 Pascal; evaporation rate of 1-5 Å / s, preferably 2-3 Å / s; drain electrode The thickness is 20-300nm, preferably 80-150nm.

[0044] This invention discloses a low-voltage, high-performance organic light-emitting transistor (AHOLET) based on a full-layer heterojunction. By designing a full-layer heterojunction structure, high-brightness, high-EQE, stable and uniform organic light-emitting transistors are obtained; demonstrating that this method has excellent application prospects in flexible displays, multifunctional devices, solid-state lighting, optical communication, smart pixels, integrated optoelectronic systems, and organic electrically pumped lasers. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the structure of a low-voltage, high-performance organic light-emitting transistor based on a full-layer heterojunction provided by the present invention.

[0046] Figure 2 The energy level diagram is shown for the low-voltage, high-performance organic light-emitting transistor based on a full-layer heterojunction prepared in Example 1.

[0047] Figure 3 The photoelectric transfer characteristic curves of the low-voltage high-performance organic light-emitting transistor based on a full-layer heterojunction prepared in Example 1 are shown.

[0048] Figure 4 The photoelectric output characteristic curves of the low-voltage high-performance organic light-emitting transistor based on a full-layer heterojunction prepared in Example 1 are shown.

[0049] Figure 5 The EQE and luminance diagrams of the low-voltage high-performance organic light-emitting transistor based on a full-layer heterojunction prepared in Example 1 are shown.

[0050] Figure 6 The light emission patterns are for the low-voltage, high-performance organic light-emitting transistors based on full-layer heterojunctions prepared in Examples 1 and 2. Detailed Implementation

[0051] The low-voltage, high-performance organic light-emitting transistors (AHOLETs) based on a full-layer heterojunction provided by this invention employ a non-planar, asymmetric electrode device structure, comprising, from top to bottom, a drain electrode, a drain electrode modification layer, an electron transport layer, a light-emitting layer, a source electrode, a source electrode modification layer, a hole transport layer, an insulating layer, a gate electrode, and a glass substrate, as shown in the figure. Figure 1 As shown. The non-planarity refers to the source electrode and drain electrode not being on the same layer; the asymmetry refers to using different materials as the source electrode (LiF / Al or LiF / Al / Ag) and drain electrode (MoO). X / Au)

[0052] The fabrication of the aforementioned low-voltage, high-performance organic light-emitting transistors (AHOLETs) based on a full-layer heterojunction includes the following steps:

[0053] The first step is cleaning the substrate.

[0054] The substrate is cleaned using a traditional method, sequentially ultrasonically cleaned with detergent, tap water, recycled water, acetone and ethanol, dried with a nitrogen gun, and then treated with an ultraviolet ozonolysis or vacuum plasma surface treatment system to obtain a clean substrate.

[0055] The second step is the fabrication of the gate electrode.

[0056] A gate electrode is prepared on the cleaned substrate by spray coating.

[0057] The third step is the preparation of the insulating layer.

[0058] An insulating layer with a thickness of 100-2000 nm is obtained on the gate electrode obtained in the second step by spin coating, drop coating, blade coating, spray coating or brush coating.

[0059] Step 4: Fabrication of the hole transport layer

[0060] A hole transport layer with a thickness of 20-100 nm was prepared on the insulating layer obtained in the third step by vacuum evaporation.

[0061] Step 5: Fabrication of the source electrode

[0062] A source electrode with a thickness of 15-40 nm was prepared on the hole transport layer obtained in the fourth step by vacuum evaporation.

[0063] Step 6: Fabrication of the light-emitting layer

[0064] A light-emitting layer with a thickness of 20-150 nm was prepared on the source electrode obtained in the fifth step by vacuum evaporation.

[0065] Step 7: Fabrication of the electron transport layer

[0066] An electron transport layer with a thickness of 20-100 nm was prepared on the light-emitting layer obtained in step 6 by vacuum evaporation.

[0067] Step 8: Fabrication of the drain electrode

[0068] A drain electrode with a thickness of 20-300 nm was prepared on the electron transport layer obtained in step 7 by vacuum evaporation.

[0069] The present invention will be further described below with reference to specific embodiments, but the present invention is not limited to the following embodiments.

[0070] Unless otherwise specified, the experimental methods described in the following examples are conventional methods; unless otherwise specified, the reagents and materials described are commercially available.

[0071] In this invention, the electrical and optical properties of the organic light-emitting transistor based on a fully heterojunction were tested in a glove box.

[0072] Example 1:

[0073] In this embodiment 1, a low-voltage, high-performance organic light-emitting transistor based on a full-layer heterojunction is fabricated according to the following steps:

[0074] 1) Using a glass substrate as a base, clean it sequentially with detergent, tap water, recycled water, acetone and ethanol under an ultrasonic power of 60 watts for 10 minutes, dry it with a nitrogen gun, and then treat the glass substrate with a vacuum plasma surface treatment system for 10 minutes to obtain a clean substrate.

[0075] 2) A solution of silver nanowires in isopropanol (concentration 0.1 mg / mL) was sprayed onto the cleaned glass substrate to obtain the silver nanowire gate electrode ②. The spraying conditions were as follows: spraying rate 0.5 mL / min, distance between spray gun and substrate 6 cm, annealing temperature 120 °C, and annealing time 20 min.

[0076] 3) The glass substrate with the silver nanowire gate electrode ② obtained above was placed on a hot stage at 60°C, and then a PEDOT:PSS isopropanol solution (concentration of 0.1 mg / mL) was sprayed to obtain the PEDOT:PSS gate electrode ③. The spraying conditions were: spraying rate of 0.5 mL / min and distance between the spray gun and the substrate of 10 cm.

[0077] 4) On the composite gate electrode glass substrate with silver nanowires and PEDOT:PSS obtained above, a 50 mg / mL P(VDF-TrFE-CFE) cyclopentanone solution was spin-coated at 500 rpm for 1 minute, and then annealed at 60 °C for 180 minutes on a hot stage to obtain insulating layer ④P(VDF-TrFE-CFE).

[0078] 5) On the glass substrate with insulating layer ④ obtained above, CYTOP is dissolved in a special fluorinated solvent with a solute to solvent volume ratio of 1:10. The mixture is spin-coated at 5000 rpm for 1 minute and then annealed at 100°C for 30 minutes on a hot plate to obtain insulating layer ⑤CYTOP.

[0079] 6) Place the glass substrate with the composite insulating layer obtained above into a vacuum coating machine, and evacuate the vacuum to 6×10⁻⁶. -6 -10 -7Pascal used thermal evaporation to deposit a hole transport layer ⑥C8-BTBT at a rate of 0.5 Å / s to a thickness of 50 nm.

[0080] 7) Place the glass substrate with the hole transport layer ⑥ obtained above into a vacuum coating machine, and evacuate the vacuum to 6×10⁻⁶. -6 -10 -7 Pascal deposited a hole transport layer ⑦TCTA at a rate of 0.1 Å / s to a thickness of 10 nm using thermal evaporation.

[0081] 8) Place the glass substrate with the hole transport layer obtained above in a vacuum coating machine, and evacuate the vacuum to 3-5 × 10⁻⁵. -4 Pascal used thermal evaporation to deposit a source electrode modification layer ⑧MoO3 at a rate of 0.1 Å / s to a thickness of 5 nm.

[0082] 9) Place the glass substrate with the active electrode modification layer ⑧ obtained above in a vacuum coating machine, and evacuate the vacuum to 3-5×10 -4 Pascal used thermal evaporation to deposit the source electrode Au at a rate of 0.1 Å / s to a thickness of 25 nm.

[0083] 10) Place the glass substrate with the active electrode obtained above into a vacuum coating machine and evacuate the vacuum to 6 × 10⁻⁶. -6 -10 -7 Pascal deposited the P-type doped host material TCTA and the N-type doped host material TPBi in the luminescent layer at a rate of 1 Å / s using thermal evaporation, and deposited the guest material (Ir(ppy)2(acac)) in the luminescent layer at a rate of 0.08 Å / s. This resulted in both the P-type doped luminescent layer and the N-type doped luminescent layer. The thicknesses are 16nm and 24nm. Experimental comparisons revealed that an 8% host-guest doping concentration is optimal.

[0084] 11) Place the glass substrate with the light-emitting layer obtained above into a vacuum coating machine, and evacuate the vacuum to 6×10⁻⁶. -6 -10 -7 Pascal deposited an electron transport layer at a rate of 0.1 Å / s using thermal evaporation. B3PYMPM, with a thickness of 10nm.

[0085] 12) The above-obtained electron transport layer The glass substrate is placed in a vacuum coating machine, and the vacuum level is evacuated to 6×10⁻⁶. -6 -10 -7 Pascal deposited an electron transport layer at a rate of 0.5 Å / s using thermal evaporation. PTCDI-C13 H 27 The thickness is 20nm.

[0086] 13) Place the glass substrate with the electron transport layer obtained above in a vacuum coating machine and evacuate the vacuum to 3-5 × 10⁻⁵. -4 Pascal deposited the drain electrode modification layer at a rate of 0.1 Å / s using thermal evaporation. LiF, with a thickness of 1 nm.

[0087] 14) The above-obtained modified layer with drain electrode The glass substrate is placed in a vacuum coating machine, and the vacuum level is evacuated to 3-5×10⁻⁶. -4 Pascal deposits the drain electrode at a rate of 2 Å / s using thermal evaporation. Al was used to obtain an organic light-emitting transistor with a thickness of 150 nm based on a full-layer heterojunction.

[0088] Example 2:

[0089] Following the same preparation method as in Example 1, except that the drain electrode in step 14) is replaced by depositing drain electrodes Al and Ag at a rate of 0.1 Å / s with thicknesses of 2 nm and 27 nm respectively, an organic light-emitting transistor based on a full-layer heterojunction can be obtained.

[0090] Based on the above device structure, the optoelectronic performance of the low-voltage, high-performance OLET based on a full-layer heterojunction was studied in an inert atmosphere. Figure 2 The diagram shows the energy level plots of low-voltage, high-performance OLETs in full-layer heterostructures, specifically C8-BTBT and PTCDI-C. 13 H 27 It has a balanced carrier transport capability, and TCTA and B3PYMPM have good carrier blocking and buffering effects and good energy level matching capabilities. Figure 3 and Figure 4 The transfer and output curves of the low-voltage, high-performance OLET based on a full-layer heterojunction in Example 1 are shown. The carrier mobility and threshold voltage of this device are 0.1 cm⁻¹. 2 V -1 s -1 and -2.4V; furthermore, it showed 1060 cd m at a drive voltage of -20V. -2 Maximum brightness. Figure 5 This indicates that the device is at 700 cd m -2 The EQE reaches its peak at the specified brightness, with a maximum EQE of 0.85%. Figure 6Illustration (a) is a light emission diagram of the device in Example 1, showing that light emission originates from the bottom of the drain. To more clearly visualize the light-emitting area of ​​the device, Example 2 was designed by replacing the drain electrode with Ag, which has good light transmittance. Figure 6 Illustration (b) shows the emission pattern of the device in Example 2, demonstrating surface emission from the entire drain electrode. This high performance is likely attributed to: 1) silver nanowires and PEDOT:PSS as gate electrodes, enhancing device transparency, reducing exciton quenching, lowering optical loss, and improving optical performance; 2) a composite insulating layer composed of high dielectric constant material P(VDF-TrFE-CFE) and highly hydrophobic material CYTOP, reducing the operating voltage of OLETs and improving device stability; 3) a highly efficient host-guest system formed by a P-type and N-type host-guest doped bilayer heterojunction structure in the emission layer, increasing carrier concentration and exciton recombination efficiency; and 4) a bilayer heterojunction structure composed of high charge transport materials and energy level matching materials in the transport layer, enabling the device to have high carrier mobility and the ability to confine electrons and holes within the emission layer.

Claims

1. A low-voltage, high-performance organic light-emitting transistor based on a full-layer heterojunction, which adopts a full-layer heterojunction structure, and its structure includes, from top to bottom, a drain electrode, a drain electrode modification layer, an electron transport layer, a light-emitting layer, a source electrode, a source electrode modification layer, a hole transport layer, an insulating layer, a gate electrode, and a substrate. The drain electrode modification layer is located at one end above the electron transport layer, and the drain electrode is located above and covers the drain electrode modification layer; The source electrode modification layer is located at one end above the hole transport layer, and the source electrode is located above and covers the source electrode modification layer; the light-emitting layer is located above the hole transport layer and covers the source electrode, forming a stepped light-emitting layer. Furthermore, the drain electrode and the source electrode are located at opposite ends; The gate electrode consists of two layers: a silver nanowire layer and a PEDOT:PSS layer, with the silver nanowire layer in contact with the substrate. The insulating layer consists of two layers: a P(VDF-TrFE-CFE) layer and a CYTOP layer, wherein the P(VDF-TrFE-CFE) layer is in contact with the PEDOT:PSS layer. The hole transport layer material is selected from 2,7-dioctyl[1]benzothiophene[3,2-B]benzothiophene (C8-BTBT) and 4,4',4''-tris(carbazole-9-yl)triphenylamine (TCTA); The hole transport layer consists of two layers: a C8-BTBT layer and a TCTA layer; the C8-BTBT layer is in contact with the CYTOP layer. The main material of the light-emitting layer is selected from 4,4',4''-tris(carbazole-9-yl)triphenylamine (TCTA) and 1,3,5-tris(1-phenyl-1H-benzimidazol-2-yl)benzene (TPBi). The light-emitting layer consists of two layers: a P-type doped light-emitting layer and an N-type doped light-emitting layer. The P-type doping host material used in the P-type doped light-emitting layer is TCTA; the N-type doping host material used in the N-type doped light-emitting layer is TPBi; the P-type doped light-emitting layer is in contact with the TCTA layer. The electron transport layer material is selected from 4,6-bis(3,5-di(3-pyridylphenyl)-2-methylpyrimidine (B3PYMPM) and N,N-tetracarboxylic acid diimide (PTCDI-C). 13 H 27 ); The electron transport layer consists of two layers: the B3PYMPM layer and the PTCDI-C layer. 13 H 27 The B3PYMPM layer is in contact with the N-type doped light-emitting layer.

2. The low-voltage, high-performance organic light-emitting transistor based on a full-layer heterojunction according to claim 1, characterized in that: The molecular weight of P(VDF-TrFE-CFE) is 600,000 Daltons, and the molecular weight of CYTOP is 200,000 Daltons. The thickness of the insulating layer is 100-2000 nm.

3. The low-voltage, high-performance organic light-emitting transistor based on a full-layer heterojunction according to claim 1, characterized in that: The hole transport layer has a thickness of 20-100 nm.

4. The low-voltage, high-performance organic light-emitting transistor based on a full-layer heterojunction according to claim 1, characterized in that: The source electrode modification material is molybdenum oxide, and the thickness of the source electrode modification layer is 1-10 nm; the source electrode material is gold, and the thickness of the source electrode is 20-50 nm.

5. The low-voltage, high-performance organic light-emitting transistor based on a full-layer heterojunction according to claim 1, characterized in that: The guest material of the light-emitting layer is bis(2-phenylpyridine)iridium acetylacetonate (Ir(ppy)2(acac)). The thickness of the light-emitting layer is 20-150 nm; The thickness of the electron transport layer is 20-100 nm.

6. The low-voltage, high-performance organic light-emitting transistor based on a full-layer heterojunction according to claim 1, characterized in that: The source electrode modification material is molybdenum oxide, and the thickness of the source electrode modification layer is 1-10 nm; the source electrode material is gold, and the thickness of the source electrode is 20-50 nm; the drain electrode modification material is selected from any one of lithium fluoride, cesium fluoride, cesium carbonate, and 8-hydroxyquinoline-lithium, and the thickness of the drain electrode modification layer is 0.5-10 nm; the drain electrode material is selected from one or two of aluminum, silver, and calcium, and the thickness of the drain electrode is 20-300 nm.

7. The method for fabricating a low-voltage, high-performance organic light-emitting transistor based on a full-layer heterojunction as described in any one of claims 1-6, comprising the following steps: (1) The gate electrode is prepared on the substrate by spray coating; (2) An insulating layer is prepared on the gate electrode prepared in step (1) by spin coating, drop coating, scraping coating, spraying or brushing. (3) A hole transport layer is prepared on the insulating layer prepared in step (2) by vacuum evaporation. (4) A source electrode modification layer is prepared on the hole transport layer prepared in step (3) by vacuum evaporation. (5) The source electrode is prepared on the source electrode modification layer prepared in step (4) by vacuum evaporation. (6) A light-emitting layer is prepared on the source electrode prepared in step (5) by vacuum evaporation. (7) An electron transport layer is prepared on the light-emitting layer prepared in step (6) by vacuum evaporation; (8) A drain electrode modification layer is prepared on the electron transport layer prepared in step (7) by vacuum evaporation. (9) A drain electrode is prepared on the drain electrode modification layer prepared in step (8) by vacuum evaporation.

8. The preparation method according to claim 7, characterized in that: In step (1), the gate electrode material silver nanowires and PEDOT:PSS dispersion are both dispersed in methanol, ethanol, isopropanol or water, with a dispersion of 0.05-0.5 mg / mL. The spraying conditions are: spraying rate of 0.1-5 mL / min, distance between spray gun and substrate of 3-15 cm, annealing temperature of silver nanowires of 60-180 ℃, and substrate heating temperature of 20-180 ℃ during PEDOT:PSS spraying. In step (2), the insulating layer P (VDF-TrFE-CFE) is dissolved in any solvent such as acetone, cyclopentanone, N-methylpyrrolidone, dimethylacetamide, dimethylformamide or dimethyl sulfoxide; the preparation method is spin coating, drop coating, blade coating or brush coating. In step (2), the insulating layer CYTOP is dissolved in a fluorine-containing solvent with a solute to solvent volume ratio of 1:3-12; the preparation method is spin coating, drop coating, blade coating or brush film method. In steps (3)-(9), the transport layer, the light-emitting layer, and the electrodes are all prepared by vacuum evaporation; the vacuum degree is 10. -4 -10 -7 Pascal, evaporation rate of 0.1-5 angstroms / second.

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