Combined imaging array and stripe and pixel noise cancellation system

Abstract

Some system embodiments include a plurality of: pixels; data lines coupled to the pixels; switches coupling the pixels to the data lines; readout circuits coupled to the data lines. The system also includes control logic coupled to the readout circuits, the control logic being configured to, for one of the pixels: obtain a first value of the pixel when the corresponding switch is in an off state; reset the corresponding readout circuit corresponding to the pixel; obtain a second value of the pixel after resetting the readout circuit; turn on the corresponding switch; obtain a third value of the pixel after turning on the corresponding switch; and combine the values ​​into a combined pixel value. Some system embodiments include: a housing; an imaging array in the housing; an imaging strip in the housing; a first readout circuit coupled to the imaging array; a second readout circuit coupled to the imaging strip; and a common electronic device coupled to the first readout circuit and the second readout circuit and configured to generate image data in response to at least one of the first and second readout circuits.

Description

[0001] The x-ray imaging array can be used to generate a two-dimensional image or video in response to incident x-rays. The imaging strip can be panned about an axis to generate a panoramic image.

[0002] Noise can accumulate in the pixels of an imaging array. Although various techniques such as correlated double sampling can reduce or remove noise caused by other components in the chain from pixel to image, noise in the pixel itself may still exist. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram of an imaging system including an imaging array and an imaging strip, according to some embodiments.

[0004] Figure 2 is a flow chart of the operation of an imaging system according to some embodiments.

[0005] Figure 3 is a block diagram of an imaging system including a substrate, according to some embodiments.

[0006] Figure 4 is a block diagram of an imaging system with separate row drivers according to some embodiments.

[0007] Figure 5 is a block diagram of an imaging system according to some embodiments, wherein an imaging strip is a subset of an imaging array.

[0008] Figure 6 is a block diagram of an imaging system with split data lines according to some embodiments.

[0009] Figure 7A-7B is a block diagram of an imaging system with selectively couplable split data lines according to some embodiments.

[0010] Figure 8A-B is a block diagram of an imaging system with multiple data lines according to some embodiments.

[0011] Fig. 9A is a block diagram of pixels and associated electronics in an imaging system according to some embodiments.

[0012] Fig. 9B is a block diagram of an imaging array and associated electronics in an imaging system according to some embodiments.

[0013] FIG10 is a timing diagram of a double sampling operation.

[0014] Fig.11A is a timing diagram according to some embodiments.

[0015] Fig. 11Bis a flow chart of the operation of an imaging system according to some embodiments.

[0016] Fig. 12A is a timing diagram according to some embodiments.

[0017] Fig. 12B is a flow chart of the operation of an imaging system according to some embodiments.

[0018] Fig.13A is a timing diagram according to some embodiments.

[0019] Fig. 13B is a flow chart of the operation of an imaging system according to some embodiments.

[0020] Fig. 13C is a timing diagram according to some other embodiments.

[0021] Fig.13D is a timing diagram according to some other embodiments.

[0022] Fig.14 is a flow chart of a technique for operating an imaging system, according to some embodiments.

[0023] Fig.15 is a block diagram of a 2D x-ray imaging system according to some embodiments. DETAILED DESCRIPTION

[0024] Some embodiments relate to an imaging system including an imaging array and an imaging strip. The system can be operated in different modes to acquire two-dimensional (2D) images using the imaging array and to acquire panoramic images using the imaging strip.

[0025] Imaging systems used in dental panels can perform a panoramic imaging operation in which an imaging strip is illuminated as the detector rotates around the patient's head. The imaging strip can be integrated as part of a large format flat panel detector. The image is generated by quickly scanning the unused rows of the detector (an operation called "brushing") and only turning on specific rows of the panel for image readout. This approach suffers from two problems. First, the frame rate is limited by the time required to brush the unused pixels. Second, in certain applications such as medical imaging, imaging may be dose rate limited, and therefore background electronic noise has a greater impact on image quality due to the lower available signal.

[0026] Typically, the size of the array can be about 16 x 16 centimeters (cm), with a pixel size of about 100 microns (μm). The pixel matrix is ​​addressed by a set of gate drivers and read out by a set of orthogonal readout charge amplifiers. A full-size image can be obtained by sequentially turning on each row of TFTs and simultaneously reading out the pixel charge on each data line of the array. For panoramic mode, the row driver is controlled to quickly scan the first part of the matrix until the first row of the imaging strip. The row driver is controlled to slow down to the normal readout rate within the duration of the row of the imaging strip, which may be about 60-100 rows, and then quickly scan the remaining gate lines to scrub the rest of the imager. Charge readout is usually performed using the timing in which the gate turn-on pulse of each pixel is compensated by the gate cut-off pulse of the previous row of pixels. Other readout methods are possible, but this approach can increase the gate turn-on time to reduce hysteresis and provide a relatively flat dark image. Due to the relatively long length of the data line, the charge amplifier is set to high power in order to minimize the noise from the data line capacitance.

[0027] As will be described in further detail below, embodiments include different configurations of imaging arrays and imaging bars. In some embodiments, separate imaging arrays and separate imaging bars may be disposed in the same housing and share common electronics. In other embodiments, the imaging arrays and imaging bars may be disposed on the same substrate. In other embodiments, the imaging bars may be a subset of the imaging arrays with various connection configurations within the imaging arrays.

[0028] Figure 1 1 is a block diagram of an imaging system including an imaging array and an imaging bar according to some embodiments. The imaging system 100 includes an imaging array 102 and an imaging bar 104. The imaging array 102 and the imaging bar 104 are disposed in the same housing 110.

[0029] The imaging array 102 may be a two-dimensional (2D) pixel array. For example, the imaging array 102 may include a 1600 x 1600 pixel array. Although an imaging array 102 having the same number of pixels in rows and columns has been used as an example, in other embodiments, the number of rows and columns may be different. Although a specific number of pixels has been used as an example, in other embodiments, the number of pixels may be different. The aspect ratio of the shorter dimension to the longer dimension in pixels is greater than 0.3, 0.5, 0.75, etc. or is equal to 1.

[0030] Imaging strip (or linear imaging array or linear array) 104 is an array of pixels having a relatively low aspect ratio, which may or may not be a 2D array. For example, imaging strip 104 may include an array of 1 pixel by 1600 pixels. In other embodiments, imaging strip 104 may include an array of approximately 80 pixels by 1600 pixels. In other embodiments, the aspect ratio of the shorter dimension to the longer dimension is less than about 0.05, 0.1, or 0.3.

[0031] Imaging array 102 and imaging bars 104 may be based on the same, similar, or different technologies. For example, imaging array 102 may include an amorphous silicon (a-Si) based array, while imaging bars may be based on higher cost and / or higher resolution complementary metal oxide semiconductor (CMOS), indium gallium zinc oxide (IGZO), or photon counting technologies such as cadmium telluride (CdTe), cadmium zinc telluride (CdZnTe or CZT), selenium photodetectors, etc. In some embodiments, one or both of imaging array 102 and imaging bars 104 may be based on IGZO.

[0032] In some embodiments, one or both of the imaging array 102 and the imaging strip 104 may be associated with one or more scintillators. The one or more scintillators may include a variety of materials configured to convert x-ray photons into photons that can be detected by the corresponding imaging array 102 or imaging strip 104. For example, the scintillator may include cesium iodide (CsI), cadmium tungstate (CdWO), or a combination thereof. 4 ), polyvinyl toluene (PVT), etc. Other examples of scintillators include gadolinium oxysulfide (Gd 2 O 2 S; GOS; Gadox), gadolinium oxysulfide doped with terbium (Gd 2 O 2 In some implementations, one or both of the imaging array 102 and the imaging strips may not include a scintillator, but may include a direct conversion material including CdTe, CdZnTe or CZT, selenium, or the like.

[0033] The pixels of imaging array 102 and imaging strips 104 may be the same, similar, or different. One or more of the size, layout, spacing, internal components, internal electrical connections, etc. of the pixels may be the same or different. For example, imaging array 102 may include 50 micrometer (μm) pixels for better single-shot accuracy, while imaging strips 104 may have 100 μm pixels for better signal-to-noise ratio and / or faster speed. In another example, one of imaging array 102 and imaging strips 104 may have 1T pixels and the other has 4T pixels. Although specific examples of differences between pixels have been used as examples, in other embodiments, the pixels may have other differences.

[0034] Imaging system 100 includes readout circuitry 106-1 coupled to imaging array 102. Readout circuitry 106-1 may include one or more amplifiers (e.g., charge amplifiers) for columns of imaging array 102. In some embodiments, readout circuitry 106-1 may include a charge amplifier for each column of imaging array 102. As will be described in further detail below, each pixel of a column may be coupled to a data line that is coupled to an input of one of the charge amplifiers of readout circuitry 106-1.

[0035] Imaging system 100 includes readout circuitry 106-2 coupled to imaging strip 104. Readout circuitry 106-2 may include one or more charge amplifiers for columns of imaging strip 104. In some embodiments, readout circuitry 106-2 may include a charge amplifier for each column of imaging array 102. As will be described in further detail below, each pixel of a column may be coupled to a data line coupled to an input of one of the charge amplifiers of readout circuitry 106-2.

[0036] Readout circuitry 106-1 may be different from readout circuitry 106-2. For example, data lines coupling pixels of imaging array 102 to readout circuitry 106-1 may be longer than data lines coupling pixels of imaging strips 104 to readout circuitry 106-2 (e.g., due to a larger number of pixel rows). Thus, readout circuitry 106-2 may have a different configuration, may operate differently, etc. due to a lower capacitance of the associated data lines. Although the length of the data lines has been used as an example of why readout circuitry 106-2 may be different, readout circuitry 106-2 may be different for other reasons.

[0037] The imaging system 100 includes a common electronic device 108 coupled to a first readout circuit 106-1 and a second readout circuit 106-2. The common electronic device 108 is configured to generate image data in response to at least one of the first readout circuit 106-1 and the second readout circuit 106-2. In some operations, the common electronic device 108 generates image data based on data from the readout circuit 106-1. In other operations, the common electronic device 108 is configured to generate image data based on data from the readout circuit 106-2. In other operations, the common electronic device 108 is configured to generate image data based on data from the readout circuit 106-1 and data from the readout circuit 106-2.

[0038] Common electronics 108 may include a variety of different circuits shared between imaging array 102 and imaging bar 104 and between readout circuits 106-1 and 106-2. For example, common electronics 108 may include a power supply configured to generate power for imaging array 102 and imaging bar 104 and readout circuits 106-1 and 106-2. Common electronics 108 may include a processor 109 configured to control the various operations described herein. Such a processor 109 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit, a microcontroller, a programmable logic device, a discrete circuit, a combination of such devices, and the like. Processor 109 may include internal parts such as registers, cache memory, a processing core, and the like, and may also include external interfaces such as address and data bus interfaces, interrupt interfaces, and the like. Although only one processor 109 is shown in common electronics 108, multiple processors 109 may exist. In addition, other interface devices such as logic chipsets, hubs, memory controllers, communication interfaces, etc. may be part of the system common electronics 108 to connect the processor 109 to internal and external components such as the imaging array 102 and imaging strips 104, readout circuits 106-1 and 106-2, and an external computer 115.

[0039] The external computer 115 is an example of a device that can be coupled (e.g., via a wired, optical, or wireless connection) to the imaging system 100 to receive image data from the common electronics 108. The common electronics 108 can be configured to receive commands from the external computer 115 and, in response to the commands, exchange data with the external computer 115, etc. The external computer 115 can take a variety of forms, such as a desktop computer, a server, a workstation, a tablet computer, a mobile device, a user interface terminal, etc.

[0040] In some embodiments, the imaging array 102 and the imaging strip 104 are separate. The imaging array 102 and the imaging strip 104 can be disposed on separate substrates that are each attached to the housing 110. The imaging array 102 and the imaging strip 104 can be disposed so that incident radiation can enter a common window or opening 112 and be detected by the imaging array 102 or the imaging strip 104.

[0041] In some embodiments, imaging bar 104 may have a configuration that results in lower noise, higher frame rate, higher resolution, etc. than imaging array 102. Thus, imaging array 102 and imaging bar 104 may be used for different applications. Since imaging array 102 and imaging bar 104 are disposed in the same housing 110, a user may use a single imaging system 100 for different applications, or a user may use a detector in a single housing 110 in a variety of imaging systems.

[0042] In some embodiments, imaging array 102 and imaging strip 104 may not operate simultaneously. As a result, common electronics 108 may be dedicated to the operation of one of imaging array 102 and imaging strip 104 at a time. The operation of common electronics 108 may be different for each of imaging array 102 and imaging strip 104. For example, common electronics 108 may drive the row drivers of imaging strip 104 at a faster rate than the row drivers associated with imaging array 102.

[0043] Figure 2 is a flow chart of the operation of an imaging system according to some embodiments. Figure 1 and Figure 2 , and using imaging system 100 as an example, in some embodiments, first data is read from imaging array 102 using readout circuit 106-1 in 200. For example, row drivers associated with imaging array 102 may be sequentially activated to read out data from imaging array 102 row by row using readout circuit 106-1. Common electronics 108 may be configured to control row drivers and readout circuit 106-1 to read out desired data.

[0044] At 202, second data is read from imaging strip 104 using readout circuit 106-2. For example, row drivers associated with imaging strip 104 may be sequentially activated to read out data row by row from imaging strip 104 using readout circuit 106-2. Common electronics 108 may also be configured to control the row drivers and readout circuit 106-2 to read out the desired data.

[0045] In 204 and 206, data from imaging array 102 and imaging strip 104 are processed in common electronics 108 to generate different sets of image data, respectively. The processing in common electronics 108 in 204 and 206 may be the same, similar, or different. For example, data from imaging strip 104 may be processed in a manner that generates image data that results in reduced noise compared to processing data from imaging array 102. In other examples, data from imaging array 102 may be used to generate a video stream, while data from imaging strip 104 may be used to generate a panoramic image. The processing in 204 and 206 may be performed simultaneously, in parallel, sequentially, etc.

[0046] Although a specific order of operations has been used as Figure 2 , but in some embodiments, the order may be different. For example, 204 may be performed before 202. In another example, 200 and 204 may be performed after 206.

[0047] Figure 3 is a block diagram of an imaging system including a substrate according to some embodiments. The imaging system 300 may be similar to Figure 1The imaging system 100 of the present invention and includes the same or similar components. Some components are omitted for clarity, but may be present. As described above, in some embodiments, the imaging array 102 and the imaging bars 104 may be separate and formed on different substrates. In some embodiments, the imaging system 300 includes a substrate 114. The substrate 114 may be a single substrate formed of, for example, glass, plastic or polymer, ceramic, organic or inorganic semiconductor, etc. The imaging array 102 and the imaging bars 104 may be formed in or on the substrate 114. For example, the imaging array 102 and the imaging bars 104 may be separate integrated circuit dies attached to the substrate 114. In other embodiments, the imaging array 102 and the imaging bars 104 may be formed in different portions of the same integrated circuit die, such as in different portions of a semiconductor substrate.

[0048] In some embodiments, imaging array 102 and imaging bars 104 may still be separate electronic devices even if imaging array 102 and imaging bars 104 are located in close proximity to each other on the same semiconductor substrate. That is, imaging array 102 and imaging bars 104 may have no electrical connections to each other except for parasitic connections through the substrate and / or connections through readout circuits 106-1 and 106-2 and common electronics 108.

[0049] In some implementations, readout circuitry 106-1 and 106-2 can be formed on a substrate different from substrate 114. However, in other implementations, one or both of readout circuitry 106-1 and 106-2 can be formed on substrate 114.

[0050] Figure 4 4 is a block diagram of an imaging system with separate row drivers according to some embodiments. Imaging system 400 can be similar to imaging systems 100 and 300 described above. However, imaging array 102 is coupled to row driver 416b, and imaging bar 104 is coupled to row driver 416a. In some embodiments, row drivers 416a and 416b are separate circuits, while in other embodiments, row drivers 416a and 416b are part of the same integrated circuit as corresponding imaging bar 104 or imaging array 102, or both. Row drivers 416a and 416b can be coupled to and controlled by common electronics 108.

[0051] Row drivers 416a are configured to be activated sequentially to read out row-by-row imaging strips 104. Row drivers 416b are configured to be activated sequentially to read out row-by-row imaging array 102. Common electronics 108 may be configured to change signals, timing, etc. when controlling row drivers 416a compared to when controlling row drivers 416b.

[0052] Figure 5is a block diagram of an imaging system according to some embodiments, wherein the imaging strips are a subset of the imaging array. Imaging system 500 may be similar to imaging systems 100, 300, and 400 described above. However, imaging strips 104 are a subset of imaging array 102. In some embodiments, imaging strips 104 may be disposed on an edge of imaging array 102. For example, imaging array 102 may have a size of 1600 pixels by 1600 pixels. The imaging strips may include the top 80 rows of pixels of the array having a size of 1600 pixels by 80 pixels. Although a particular size of imaging strips 104 has been used as an example, the size may vary while maintaining the aspect ratio described above.

[0053] In some embodiments, imaging array 102 can be coupled to row drivers 516. Row drivers 516 that are coupled to portions of imaging strips 104 of imaging array 102 can be shared. When imaging strips 104 are used to generate an image, the associated row select lines 516a can be used. When imaging array 102 is used to generate an image, all of row select lines 516a and 516b can be used.

[0054] In some embodiments, the pixels of imaging strips 104 may be the same as and formed identically to the pixels of the rest of imaging array 102. For example, the pixels of imaging strips 104 may have the same size, shape, pitch, etc. In general, pitch refers to the length or width of a pixel and the spacing between pixels. As a result, when an image is generated using imaging array 102, artifacts may not appear due to the discontinuity between imaging strips 104 and the rest of imaging array 102.

[0055] In some implementations, when reading imaging array 102 , row driver 516 is configured to gradually activate row select lines 516 a and 516 b across imaging array 102 .

[0056] Figure 6 6 is a block diagram of an imaging system with split data lines according to some embodiments. Imaging system 600 can be similar to imaging system 500, etc., as described above. Imaging system 600 includes split data lines 618. Data lines 618 are split into two groups, data lines 618a and data lines 618b. Data lines 618a are coupled to the imaging strips 104 portion of imaging array 102 and to readout circuit 106-2. Data lines 618b are coupled to the remainder of imaging array 102 and to readout circuit 106-1.

[0057] The split location between data lines 618a and 618b may be in a plurality of locations. In some embodiments, the split is approximately 30% of the length of the column, with data line 618a coupled to 30% of the pixels in the column and data line 618b coupled to 70% of the pixels in the column. Although 30% is used as an example, in other embodiments, the location may be different, such as splitting at 1%, 5%, 10%, 20%, etc. In other embodiments, the split may be at a specific number of pixels from the edge, such as approximately 80 pixels or less, but still less than 30% of the number of pixels in the column of the imaging array 102. In some embodiments, the split may be positioned so that only the pixels of the imaging strip 104 are coupled to the data line 618a, while the pixels outside the imaging strip 104 are coupled to the data line 618b. In other embodiments, some pixels outside the imaging strip 104 are coupled to the data line 618a, but the total number of pixels in the column coupled to the data line 618a may be less than approximately 30%.

[0058] The split provides benefits to the imaging strip 104 at less than about 30%. In some embodiments, because the data line 618a is shorter than the data line 618b, the noise may be less. In some embodiments, the lower noise may cause artifacts to appear in images generated using the imaging array 102; however, as will be described in further detail below, when the entire imaging array 102 is used to generate an image, additional noise or the equivalent may be added to the data generated by the imaging strip 104. In some embodiments, the downstream processing may be different. For example, a different dark level matching operation may be performed compared to the rest of the imaging array 102.

[0059] In some embodiments, the amount of noise reduction and / or increase in signal-to-noise ratio can be about 10%, 20%, 40%, 50%, or more. For example, shorter data lines 618a result in lower data line capacitance and resistance, which can reduce electronic readout noise. In a specific example, the charge amplifier can have about 200 electrons (e - ) which increases linearly with increasing data line capacitance. The slope of the noise is controlled by the power applied to the charge amplifier and the bandwidth setting of the associated sample and hold circuit. In addition, the resistance of the data line produces thermal noise or Johnson noise which is multiplied by the data line capacitance. This Johnson noise increases with length but is negligible for shorter data lines such as data line 618a coupled to imaging strip 104. The resulting noise may be close to the kTC noise of the minimum noise combined pixel of the charge amplifier. This noise (estimated to be 400e - ) may be less noisy than an array of the same size without splitting the data lines (about 700e -) is about 40% lower. The term kTC noise refers to the noise generated by temperature (T) and capacitance (C) multiplied by the Boltzmann constant (k), such as thermal noise multiplied by data line capacitance and the Boltzmann constant. The Boltzmann constant (k) is a proportionality factor that relates the average relative kinetic energy of a particle to the thermodynamic temperature of the particle.

[0060] The shorter length may also increase the readout speed. For example, fewer rows may be read during a read operation of the pixels of the imaging strip 104. It is not necessary to scrub the rest of the imaging array 102 to read the pixels of the imaging strip 104. Using 80 rows of pixels of the imaging strip 104 as an example, the control logic 103 may continue to pass tokens (i.e., signals that propagate along the row driver 616 to activate the row) to the row driver 616 every 80 gated clocks to activate the row select signal 616a. These tokens may pass through the remaining row drivers 616 and scrub the rest of the imaging array 102 using the row select signal 616b without interfering with the readout of the imaging strip 104. This may increase the readout speed of the imaging strip 104. For example, assuming a rate of scrubbing pixels of approximately 1 microsecond (μs) per row, the time required to scrub the imaging array (approximately 1520 rows) of the 1600 rows of the imaging array 102 outside of the 80 rows of the imaging strip 104 is approximately 1.52 milliseconds (ms). Assuming that each row of the imaging strip 104 is read out for about 16 μs, 80 rows of the imaging strip 104 require 1.28 ms to read out. The total time is about 2.8 ms, resulting in a maximum frame rate of 357 fps. In the case of a dedicated imaging strip 104, the readout time is only 1.28 ms, resulting in a frame rate of about 780 fps. During the readout of a predetermined number of frames, such as 19 frames (24 ms), the remaining pixels in the array can be scrubbed.

[0061] In some embodiments, readout circuits 106-1 and 106-2 may be identical and / or operate in the same manner, while in other embodiments, readout circuits 106-1 and 106-2 may be different and / or operate in different manners. For example, readout circuits 106-1 and 106-2 may be identical. In other embodiments, readout circuits 106-1 and 106-2 are identical but operate differently, such as having different gains, currents, capacitances, etc. In other embodiments, readout circuits 106-1 and 106-2 may be different, wherein readout circuit 106-2 is optimized for use with shorter data lines 618a.

[0062] refer to Figure 2 and Figure 6 In some embodiments, at 200, reading first data from imaging array 102 includes reading first data from imaging array 102 via data line 618b. At 202, reading second data from imaging strips 104 includes reading second data from imaging strips 104 using data line 618a different from data line 618b.

[0063] Figure 7A-7B is a block diagram of an imaging system with selectively couplable split data lines according to some embodiments. Fig. 7A , imaging system 700a may be similar to imaging system 600 described above. However, system 700a includes data lines 718a coupled to imaging strips 104, data lines 718b coupled to the remainder of imaging array 102. Data lines 718a and 718b are separate but selectively coupled by switches 722. Each switch 722 may selectively couple one of data lines 718a to a corresponding data line 718b.

[0064] In some embodiments, switch 722 may include one or more transistors that couple data lines 718a and 718b. Switch 722 may be controlled by control logic 103 such that when imaging strips 104 are being read, switch 722 is open. As a result, lower capacitance from data line 718a is provided to readout circuit 106-2 alone. However, when reading imaging array 102, data lines 718a and 718b may be coupled together to function as a single data line. Data from imaging array 102 may be read by readout circuit 106-1 via coupled data lines 718a and 718b.

[0065] refer to Figure 7B , imaging system 700b may be similar to imaging system 700a. However, the data lines associated with imaging array 102 may include data lines 718a, 718c, and 718d. In some embodiments, the split between data lines 718c and 718d may be at 50% of the distance along imaging array 102. For example, 50% of the pixel rows may be on one side of the split between data lines 718c and 718d and 50% of the pixel rows may be on the other side of the split.

[0066] In response to control logic 103, data lines 718a and 718c may be selectively coupled by switch 722. In some embodiments, imaging strip 104 may be read by decoupling data lines 718a and 718c using switch 722 and reading through data line 718a using readout circuit 106-2. When reading imaging array 102, data lines 718a and 718c may be coupled by switch 722 and read through a combination of data lines 718a and 718c using readout circuit 106-2. The remainder of imaging array 102 may be read through data line 718d using readout circuit 106-1. Coupling of data lines 718a and 718c may occur at less than 50% of the pixel rows, or data line 718a may cover less than 30% of the entire imaging array 102.

[0067] Thus, in various embodiments, a portion of the data lines of the entire imaging array 102 may be decoupled from the data lines 718a associated with the imaging strip 104. The portion may be a subset of the remainder outside of the imaging strip 104, or the entire remainder as in the imaging systems 700a and 700b.

[0068] refer to Figure 2 , Fig. 7A and Figure 7B In some embodiments, at 200, reading first data from imaging array 102 includes electrically coupling first data line 718a or 718c to second data line 718b when reading the first data from imaging array 102. At 202, reading second data from imaging strip 104 includes electrically decoupling first data line 718a or 718c from second data line 718b when reading the second data from imaging strip 104.

[0069] Figure 8A-B 8 is a block diagram of an imaging system with multiple data lines according to some embodiments. Imaging system 800a can be similar to imaging systems 500 and 600 described above. However, imaging system 800a includes data lines 818a and 818e. Data line 818a is coupled to pixels of imaging strip 104. Data line 818e is coupled to pixels of entire imaging array 102 including pixels of imaging strip 104. Thus, at least two data lines 818a and 818e are coupled to each pixel of imaging strip 104. Thus, data line 818a is used when reading imaging strip 104, and data line 818e is used when reading imaging array 102.

[0070] refer to Figure 8B , in some embodiments, imaging system 800b can be similar to imaging system 800a. In some embodiments, the data lines for imaging array 102 can include split data lines 818d and 818f that are split midway along imaging array 102. Readout circuit 106-2 can include separate inputs for data lines 818a and 818f. Readout circuit 106-1 can be coupled to data line 818d. Thus, data line 818a is used when reading imaging strips 104, while data lines 818d and 818f are used when reading imaging array 102.

[0071] As described above, in various embodiments, the amount of noise present in the data read from imaging strips 104 may be less than the amount of noise present in the data read from the rest of imaging array 102. For example, the data lines used to read data from imaging strips 104 may be shorter than the data lines used to read data from imaging array 102. These data lines may have less capacitance and contribute less noise. In some applications, it may be desirable to reduce noise. For example, the reduced noise that occurs when reading imaging strips 104 may allow for the use of a lower dose for the same signal-to-noise ratio in the resulting image, a higher signal for the same dose, a different trade-off between various factors of the two, etc.

[0072] If data from imaging strip 104 is combined with data from imaging array 102, artifacts may occur due to different noise levels even if the pixels of each have the same characteristics. To compensate for this, readout circuit 106-2 may operate in a manner that increases the amount of noise read from imaging strip 104. For example, built-in test capacitors, external capacitors, or other capacitors may be selectively coupled to the input of readout circuit 106-2, the power of one or more amplifiers may be reduced, and / or the bandwidth of components of readout circuit 106-2 such as amplifiers and / or sample and hold circuits may be increased. These operations may increase electronic noise and may be adjusted to match the overall noise between imaging strip 104 and the rest of imaging array 102. For example, a typical 20 μs line time may use a 40 kilohertz (kHz) low pass filter for noise reduction. For most image readouts on data lines with capacitance on the order of tens of picofarads (pF), the electronic noise is approximately 600-800 μs with readout circuit 106-1 set to high power low noise conditions. e- To achieve this level of noise for imaging strip 104, a low power normal noise operating mode may be used, a test capacitor having a capacitance similar to that of the data line built into readout circuit 106-2 may be coupled to the data line, and / or the bandwidth may be increased to 105 kHz. This operation gives approximately 600-800 e in imaging strip 104. - Although specific examples of techniques for adding noise, simulating noise, equalizing noise, etc. have been described above, in other embodiments, other operations may be performed to reduce or remove artifacts in the image due to lower noise of imaging strip 104.

[0073] In some embodiments, the above-described imaging systems 400, 600, 700a, 700b, 800a, 800b, etc. may be operated in a mode in which power can be dynamically managed. For example, in operation, the control logic 103 may be configured to control the amplifier of the readout circuit 106-1 or 106-2 to operate in a higher power mode to reduce noise when reading the entire imaging array 102. However, when reading the imaging strip 104, the amplifier of the readout circuit 106-2 may be operated in a lower power mode. Although the lower power mode of operation may increase the relative amount of noise and / or reduce the signal-to-noise ratio (SNR), the power consumption is lower. In addition, the amplifier of the readout circuit 106-1 may be turned off, enter a sleep mode with significantly lower power consumption, etc. When the entire imaging array 102 can be read, the readout circuits 106-1 and 106-2 may be placed in a higher power mode to reduce the effects of noise. Dynamically switching between these operating modes may reduce power consumption, reduce temperature, and / or improve reliability of the imaging system 500, 600, 700a, 700b, 800a, 800b, etc.

[0074] In some embodiments, the effect of pixel kTC noise in the image can be reduced. As a result, a lower dose can be used to achieve a desired resolution, the frame rate can be increased, and so on.

[0075] Fig. 9A is a block diagram of pixels and associated electronics in an imaging system according to some embodiments. Fig. 9B is a block diagram of an imaging array and associated electronics in an imaging system according to some embodiments. Fig. 9A and Fig. 9B , imaging system 900 includes pixels 902 arranged in rows and columns.

[0076] Pixel 902 includes a photodetector 904 (e.g., a photodiode) and a transistor 906 (i.e., a switch). Transistor 906 is configured to selectively couple photodetector 904 to a data line 908 in response to a row select signal (RSS). Multiple pixels 902 may be coupled to a single data line 908 in a column.

[0077] The data line 908 is coupled to an amplifier 910. In some embodiments, the amplifier 910 is an integrating amplifier including a reset transistor (or reset switch) 910a and a charge storage device 910b such as a capacitor. The reset transistor 910a is configured to reset the amplifier 910 in response to a reset signal "RESET". The output of the amplifier 910 can be selectively coupled to an analog-to-digital converter (ADC) 912 through a selection transistor 911 in response to a sampling signal "SAMPLE". The digitized signal can be processed by a field programmable gate array (FPGA) 914, stored in a memory 916, and / or further processed by a processor 918 or other downstream system.

[0078] The control logic 903 may be coupled to the various components described above. For example, the control logic 903 may be coupled to the row driver 901. The control logic may be configured to control the row driver 901 to generate a row select signal RSS for a row of pixels 902. The control logic 903 may be configured to configure and control the operation of the ADC 912, the FPGA 914, the processor 918, etc. The control logic 903 may include a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit, a microcontroller, a programmable logic device, a discrete circuit, a combination of such devices, etc. The control logic 903 may include internal parts such as registers, cache memories, processing cores, etc., and may also include external interfaces such as address and data bus interfaces, interrupt interfaces, etc. In addition, other interface devices such as a logic chipset, a hub, a memory controller, a communication interface, etc. may be part of the imaging system 900 to connect the control logic 903 to internal and external components.

[0079] Although control logic 903 is shown as separate from FPGA 914, processor 918, etc., control logic 903 may be integrated with such components. For example, control and / or execution of the operations described herein may be distributed across FPGA 914, processor 918, a combination of such components, etc.

[0080] Figure 10 is a timing diagram for double sampling operation. Fig. 9A , Fig. 9B 10, system 900 may operate according to the timing diagram of FIG. 10. For example, transistor 910a may be enabled in response to a pulse on reset signal RESET to reset amplifier 910. During this operation, transistor (or switch) 906 is disabled as row select signal RSS is disabled. While row select signal RSS is disabled, sampling signal SAMPLE is activated to sample the reset value at the output of amplifier 910 as R 1 . In getting the value R 1 After that, the sampling signal “Sampling” is deactivated. After deactivating the sampling signal “Sampling”, the row selection signal RSS is enabled, thereby enabling transistor 906. As a result, the charge from the photodetector 904 is accumulated in the amplifier 910. The sampling signal “Sampling” is enabled to generate a value S at the output terminal of the amplifier 910. 1 Take samples.

[0081] Equations 1 and 2 show that the sampled value R 1 and S 1 The weight of V 重置 is the sampled reset voltage, which includes the noise contributed by amplifier 910. V 信号,像素 is the desired signal from pixel 902. V kTC(N-1) is the pixel kTC noise left over from the previous reading of pixel 902. 数据线 The noise is noise caused by the data line 908 .

[0082] R 1 =V 重置 (1)

[0083] S 1 =V 重置 +V 信号，像素 -V kTC (N-1)+V 数据线噪声 (2)

[0084] Equation 3 is R 1 With S 1 The difference between p1 (N). The result includes the expected signal V 信号,像素 and pixel kTC noise V kTC (N-1) and data line noise V 数据线 .

[0085] V p1 (N) = S 1 -R 1 =V 信号，像素 -V kTC (N-1)+V 数据线噪声 (3)

[0086] The operation of Equation 3 can be performed in a variety of ways, such as by analog correlated double sampling (ACDS), digital correlated double sampling (DCDS), or by subtracting the signal R 1 and S 1 other processes.

[0087] Fixed pattern noise sources may be caused by variations from pixel to pixel or amplifier to amplifier. Fixed pattern noise may not vary from frame to frame. However, pixel kTC noise is generated by the resistance in the pixel semiconductor switch and stored on the capacitance of the photodetector 904. Pixel kTC noise may vary from frame to frame. Fixed pattern noise can be reduced by manufacturing control. Reduction of pixel kTC noise can be achieved by reducing the size of the photodetector 904 to reduce the capacitance of the photodetector 904; however, reducing the size of the photodetector 904 may reduce other factors such as sensitivity, efficiency, etc.

[0088] The result in equation 3 still has pixel kTC noise. Pixel kTC noise can be reduced by changing the pixel design such as adding additional transistors. However, for pixels formed using some semiconductor technologies, such as in amorphous silicon (a-Si), the size of the transistors may be prohibitive. For example, for a given pixel size, a single transistor may occupy a large percentage of the pixel. Adding more transistors will significantly reduce the pixel area available for photodetector 904, thereby reducing the efficiency of system 900.

[0089] As will be described in further detail below, the system 900 may operate differently to reduce pixel kTC noise. In some embodiments, a measurement may be performed in which the pixel kTC noise may be acquired and used to reduce or remove the pixel kTC noise from the signal measurement. Although the pixel kTC noise varies from frame to frame, after acquiring a signal sample and disabling transistor 906 by disabling the row select signal RSS, the pixel noise kTC noise is presented to the input of amplifier 910 (and subsequently output) from amplifier 910. At this point in the operation, a sample may be acquired to capture the kTC noise. This sample may be stored and then used to reduce or remove the pixel kTC noise of the signal from pixel 902 in the next frame.

[0090] The measurements can then be used to remove or reduce the pixel kTC noise in the final value. Thus, the measurements from the previous frame are used to reduce or eliminate the pixel kTC noise in the current frame. Although the embodiments described herein may be applicable to systems using an a-Si process or other process where the size of the transistors may be relatively large compared to the size of the pixel, in other embodiments, the system may be formed using other processes such as a complementary metal oxide semiconductor (CMOS) process.

[0091] Fig.11A is a timing diagram according to some embodiments. Fig. 11B is a flow chart of the operation of an imaging system according to some embodiments. Fig. 9A , Fig. 9B , Fig.11A and Fig. 11B , in 1100, a first value of a pixel 902 coupled to a data line 908 via a switch is acquired using a readout circuit when the switch is in an off state. Here, transistor 906 is an example of a switch, and the readout circuit includes an amplifier 910 and at least some downstream components. This first value, sample R / S, is acquired in frame N-1 while transistor 906 is disabled. Subsequent processing may occur before subsequent operations are performed on frame N.

[0092] The readout circuit is reset in 1102. In this example, amplifier 910 is reset. However, in other embodiments, additional components may be reset. Resetting amplifier 910 may include discharging charge storage device 910b by activating a reset signal "RESET".

[0093] At 1104, a second value of pixel 902 is obtained after resetting the readout circuit. In this example, the value R is obtained after resetting amplifier 910. 1 .

[0094] At 1106, the switch is turned on. Here, the row select signal RSS is activated, turning on transistor 906. As a result, the charge from pixel 902 can be transferred to amplifier 910.

[0095] At 1108, a third value of pixel 902 is obtained after the switch is turned on. In this example, the value S is obtained after transistor 906 is turned on. 1 .

[0096] At 1110, the first value, the second value, and the third value are combined into a combined value for pixel 902. In this example, the three values ​​R 1 , S 1 and R / S are combined into a combined value for pixel 920. As will be described in more detail below, the three values ​​R may be combined in various ways. 1 , S 1 and R / S to reduce or remove pixel kTC noise. Depending on the particular combining technique for combining the first value, the second value, and the third value together to reduce or remove kTC noise, the various values ​​combined together may include other values.

[0097] In some embodiments, at 1101, a stored value based on the first value is stored. For example, a value based on the value R / S may be stored in FPGA 914, memory 916, processor 920, or another downstream system. The stored value is based on a value from a previous frame N-1. The stored value may be compared to the value R from the current frame N. 1 and S 1 Thus, the combination in 1110 may include combining the first value with a stored value based on the first value. In some embodiments, the R / S value or derivative value for the entire frame may be stored for each pixel 902. The value R / S for the entire frame 1 and S 1 , either individually or in combination, can be combined with the stored R / S values.

[0098] The operations described herein involve acquiring additional samples during the readout process. Because this additional sample takes additional time, the readout time is increased. However, noise can be reduced, thereby potentially increasing the signal-to-noise ratio, thereby allowing lower doses, etc. Therefore, in some embodiments, the increase in readout time can be traded for a reduction in noise, a lower dose, etc.

[0099] In some implementations, when the data line 908 capacitance is smaller, the noise reduction benefit has a greater impact. When the values ​​are combined, the noise from the data line 908 capacitance increases by the square root of 2. In some implementations, binning can be implemented during the capture of signals from the pixels 902. For example, in a 2x2 binning mode, four pixels 902 are combined to operate as a single pixel. Relative to reading out a single pixel 902, the data line 908 noise may be doubled, while the pixel kTC noise would otherwise be four times. However, the pixel kTC noise can be reduced or removed. Therefore, the operations described herein may have a greater impact when performing binning.

[0100] Fig. 12A is a timing diagram according to some embodiments. Fig. 12B is a flow chart of the operation of an imaging system according to some embodiments. Fig. 9A , Fig. 9B , Fig. 12A and Fig. 12B , the operations may be similar to those including operations 1100, 1101 (optional), 1102, 1104, 1106, and 1108. Fig.11A and Fig. 11B The operation is similar to the above Fig. 11B At 1200, before acquiring the first value of pixel 902, the readout circuit is reset. For example, amplifier 910 may be reset with a pulse on reset signal RESET. This operation may be the same or similar to the reset performed later in 1102.

[0101] In 1202, a fourth value of the pixel 902 is obtained when the switch is in the on state. For example, after resetting the amplifier 910, the value R is obtained when the switch 906 is in the on state. 2 .

[0102] The operation continues similar to Fig. 11B operation, where R 3 is the value R / S. In 1204, the value S 1 , R 1 , R 2 and R 3 are combined to generate a combined value for pixel 902. Equations 4-6 show the sampled value R similar to equations 1-3 above. 1 , S1 and V p1 (N) component. 重置1 is the reset voltage sampled after resetting amplifier 910.

[0103] R 1 =V 重置1 (4)

[0104] S 1 =V 重置1 +V 信号，像素 -V kTC (N-1)+V 数据线噪声1 (5)

[0105] V p1 (N) = S 1 -R 1 =V 信号，像素 -V kTC (N-1)+V 数据线噪声1 (6)

[0106] Equation 7 is the sample value R 2 . Value R 2 After the amplifier 910 is reset and the switch 906 is in the on state, it is sampled. Equation 8 is the sampled value R 3 . Value R 3 is sampled after switch 906 is switched to the off state. Equation 9 is R 2 With R 3 Equation 10 is the difference between V 像素 (N), that is, V p1 (N) and V p2 (N-1). Although different data line noise V is added 数据线噪声1 and V 数据线噪声2 , but the resulting combination is actually the square root of two times the common data line noise level.

[0107] R 2 =V 重置2 (7)

[0108] R 3 =V 重置2 +V kTC (N-1)+V 数据线噪声2 (8)

[0109] V p2 (N-1) = R 3 -R 2 =V kTC (N-1)+V 数据线噪声2 (9)

[0110]

[0111] The value R sampled at the previous frame N-1 2 and R 3 With pixel kTC noise from the previous frame. To explain R from the previous frame N-1 2 and R 3 The value of will explain the operation in frame N. Amplifier 910 is reset and a sample is taken after the reset. This generates the value R 1 Pixel 902 is turned on by turning on switch 906 and another sample of the signal is taken, generating a value S 1 . Then subtract the two samples R as before 1 and S 1 .

[0112] In performing the sampling of the signal to generate the value S 1 After that, transistor 906 is not turned off, but remains in the on state. Amplifier 910 is reset by a pulse on reset signal RESET and a sample, i.e., value R is acquired. 2 This sample comprises the reset value for amplifier 910. When switch 906 is turned off in response to deactivating row select signal RSS, pixel kTC noise is transferred and integrated by amplifier 910. Specifically, when transistor 906 is turned off, some charge remains in pixel 902 and an equal and opposite amount is integrated by amplifier 910. This integrated amount is opposite to the pixel kTC noise that will appear the next time pixel 902 is read.

[0113] The output of amplifier 910 is sampled again to obtain the value R 3 , which includes the reset value, pixel kTC noise, and data line 908 noise. Pixel kTC noise is the pixel kTC noise that will appear the next time pixel 902 is read in the next frame. Therefore, when this operation is performed in frame N-1, the value R 2 and R 3 Or a combination of these values ​​may be used for the next frame N.

[0114] In some embodiments, the operations of Equations 6 and 9 may be performed using a correlated double sampling technique. For example, whether analog or digital, the correlated double sampling technique may be used to generate R 2 With R 3 The difference between , as shown in Equation 9. Similarly, at different times, the correlated double sampling technique can be used to generate R 1 With S 1 The difference between , as shown in Equation 6. Therefore, different values ​​can be combined into two different related values. These related values ​​can be combined as shown in Equation 10. Therefore, in some embodiments, the value V can be generated using existing hardware by controlling various signals such as the reset signal "Reset" and the row selection signal RSS.p1 (N) and V p2 (N-1). Instead of performing two correlated double sampling operations to ultimately generate two frames of image data, two correlated double sampling operations may be performed to ultimately generate one frame of image data.

[0115] refer to Fig. 9A , Fig. 9B and Figure 12A-12C , Fig. 12B 1204 may be replaced with 1208 and subsequent processing. After operations 1200 to 1108, in 1208, the first value and the fourth value may be combined into a first correlation value. As described above, the value R 2 and R 3 The second value and the third value may be combined into a second correlation value at 1210. As described above, R 1 and S 1 The combination may be performed by a correlated double sampling technique. In 1212, the first correlation value and the second correlation value are combined into a combined value of the pixel 902. The combination may be performed by a variety of devices such as FPGA 914, processor 918, control logic 903, external computer 913, etc.

[0116] Fig.13A is a timing diagram according to some embodiments. Fig. 13B is a flow chart of the operation of an imaging system according to some embodiments. Fig. 9A , Fig. 9B , Fig.13A and Fig. 13B , in some embodiments, generates a value R 1 and S 1 The signals of may be similar to those described above. However, based on the third value S of the previous frame 2 Combine with those values.

[0117] In 1302 to 1308, the operations are Fig. 11B 1102 to 1108 are the same or similar to generate the value R 1 and S 1 These operations are for the previous frame N-1. In 1300, similar to 1100, the first value of pixel 902 for the subsequent frame is obtained without resetting the corresponding readout circuit. For example, when the first value is obtained, the switch is in an off state. Therefore, after 1306, the row select signal RSS is disabled, turning off transistor 906. Then the value S is obtained. 2 as the first value for the subsequent frame N. At a later time in frame N, operations 1302 to 1308 are repeated, thereby generating a value R for frame N 1 and S 1Operation 1310 similar to operation 1110 is performed to combine the first value, the second value, and the third value. Operation 1300 may be performed to generate a value S for frame N. 2 For use in frame N+1.

[0118] In a specific example, for the previous frame N-1, Equations 11 and 12 give R 1 (N-1) and S 1 (N-1) components.

[0119] R 1 (N-1) = V 重置1 (11)

[0120] S 1(N-1) =V 重置1 +V 信号，像素 -V kTC (N-2)+V 数据线噪声1 (12)

[0121] However, when obtaining the value S for the previous frame N-1 1 Then get the value S 2 The value S 2 is obtained after turning off transistor 906 and without resetting amplifier 910. Therefore, the resulting value S 2 Including the previous integrated value S expressed by Equation 13 and simplified in Equation 14 1 Add pixel kTC noise to both.

[0122] S 2 (N-1) = V 重置1 +V 信号，像素 -V kTC (N-2)+V kTC (N-1)+V 数据线噪声2 (13)

[0123] S 2 (N-1) = S 1 (N-1)+V kTC (N-1)+V 数据线噪声2 (14) From S 2 Subtract S 1 The pixel kTC noise of the previous frame N-1 is obtained as shown in Equation 15.

[0124] B p，kTC (N-1) = S 2 -S 1 =V kTC (N-1)+V 数据线噪声2 (15) At the current frame N, get the value R1 and S 1 and Combine them as shown in Equations 16-18. The pixel kTC noise from Equation 15 was generated previously. It can be added to V p1 (N) to remove the pixel kTC noise from the previous frame N-1.

[0125] R 1 (N) = V 重置1 (16)

[0126] S 1 (N) = V 重置1 +V 信号，像素 -V kTC (N-1)+V 数据线噪声1 (17)

[0127] V p1 (N) = S 1 -R 1 =V 信号，像素- V kTC (N-1)+V 数据线噪声1 (18)

[0128]

[0129] Since only three values ​​are acquired, the processing speed of one frame of data can be improved over the processing speed of the above-mentioned data acquired with four values. As a result, the frame rate can be increased. However, hardware different from the existing correlated double sampling hardware can be used. That is, although the correlated double sampling technique can be used to combine S 1 and R 1 to generate a single value representing the difference, but the value S 2 Different electronic devices may be used to generate the values. In addition, the sampling circuit may be configured to respectively 1 , S 1 and S 2 The samples are taken and combined in the FPGA 914, processor 918, external computer 913 or other downstream system.

[0130] Fig. 13C is a timing diagram according to some embodiments. Fig. 9A , Fig. 9B , Fig. 13B and Fig. 13C In some implementations, a digital correlated double sampling technique may be used. In response to an ASIC shift in the signal (ASIN), the signal to be sampled may be shifted to a sampling capacitor or other sample storage device. The operation may be similar to Fig.13AIn some embodiments, the sampling capacitor may be a set of sampling capacitors, where the use of the capacitors is rotated between sampling operations. The sampling signal "take" may be activated as described above to take a value R 1 , S 1 and S 2 Sampling is performed. However, the sampling capacitor bank may include an even number of sampling capacitors. A fourth sampling signal 1350 or an additional sampling signal may be activated to ensure that the associated pixels 902 see the same sampling capacitor. Although one sampling signal 1350 is used as an example, there may be more sampling signals as needed. The sampling value may not matter. Therefore, ASIN may not be activated. Therefore, in some embodiments, the number of times the signal is shifted in for sampling may be less than the number of times the sampling signal "Sampling" is activated.

[0131] Fig.13D is a timing diagram according to some embodiments. Fig. 9A , Fig. 9B , Fig. 13B and Fig.13D In some embodiments, the operation may be performed using analog correlated double sampling. In response to the clamp signal “CLAMP”, the reset value R 1 The sampling capacitor may be coupled to an analog subtraction device such as a differential amplifier that performs analog subtraction associated with analog correlated double sampling.

[0132] In some embodiments, the two measurements are digitized as intermediate values. As described above, in equations 12 and 13, S 1 and S 2 All include reset value R 1 . It is not to directly subtract S 1 and S 2 , but rather from S through an analog correlated double sampling operation before digitizing the samples 1 and S 2 Subtract R from 1 Therefore, the subsequent operations that can be performed digitally can be expressed by equations 20-22, where S' 1 is in the differential amplifier from S 1 Subtract R 1 After the digitization value, and S' 2 Similarly, from S 2 Subtract R 1 The resulting V in Equation 22 can be used as described above. p,kTC .

[0133] S′ 1 (N-1) = S 1 -R 1 (20)

[0134] S′ 2 (N-1) = S 2 -R 1 (twenty one)

[0135] V p，kTC (N-1) = S′ 2 -S′ 1 =V kTC (N-1) (22)

[0136] Thus, in various embodiments, the acquisition operations of 1300, 1304, 1308 and the combining operation of 1310 may be performed in various combinations of hardware and digital signal processing.

[0137] Fig.14 is a flow chart of a technique for operating an imaging system according to some embodiments. At 1400, an operating mode is selected. In a first operating mode, operations similar to those described above may be performed. Fig. 11B , Fig. 12B , Fig. 12C , Fig. 13B The operation described in the above description may be performed. As a result, lower noise data may be obtained. However, some applications may require a higher frame rate. Therefore, the additional delay caused by the additional samples in the lower noise operation may be undesirable. Therefore, a second operating mode may be selected, wherein in 1402, a correlated double sampling operation is performed. In this mode, obtaining the first value is not performed. Therefore, the operation of the system can be switched from the lower noise mode to the higher frame rate mode.

[0138] In a specific example, the second mode may be selected when the imaging system is used for fluoroscopy or other applications that may require a higher frame rate. Once the region of interest is identified, the first mode may be selected to generate an image with lower noise, lower dose, etc. In another example, where binning is performed, such as 2x2, 3x3, 4x4 or larger binning, pixel kTC noise may be better than data line correlated noise. The imaging system may operate in the first mode to reduce pixel kTC noise.

[0139] In some embodiments, the data frame may not be available and / or may be discarded. For example, the first frame data of frame N-1 can be used to generate the first value and other values. The frame data cannot be used to generate an image or video signal frame. Instead, the data can be used to initialize the above-mentioned processing so that each subsequent frame can have an available value from the previous frame to perform the above-mentioned lower noise processing.

[0140] In some embodiments, the above-described operations for reducing or removing pixel kTC noise can be applied to the above-described imaging bar 104. Specifically, the imaging bar 104 can have relatively shorter data lines coupling the imaging bar 104 to the readout circuit 106-2. The common electronics 108 and the readout circuit 106-2 can be configured as described above to reduce kTC noise.

[0141] In some embodiments, the display may be switched based on whether the imaging strip 104 is read. Fig.14 The described operation mode. For example, if imaging strip 104 is part of imaging array 102 and the entire imaging array 102 is being read, the above operations for reducing pixel kTC noise may not be performed. Because there are two measurements per data line, the background noise from the data line is also measured twice. For imaging arrays 102 with longer data lines, this data line noise may dominate over the pixel kTC noise.

[0142] Fig.15 1 is a block diagram of a 2D x-ray imaging system according to some embodiments. 2D x-ray imaging system 1500 includes an x-ray source 1502 and a detector 1510. Detector 1510 may include imaging systems 100, 200, 400, 500, 600, 700a, 700b, 800a, 800b, 900, etc. as described above. X-ray source 1502 is disposed relative to detector 1510 so that x-rays 1520 may be generated that pass through specimen 1522 and are detected by detector 1510. In some embodiments, detector 1510 is part of a medical imaging system. In other embodiments, 2D x-ray imaging system 1500 may include a portable vehicle scanning system as part of a cargo scanning system.

[0143] Some embodiments include a system comprising: a housing 110; an imaging array 102, which is disposed within the housing 110; an imaging bar 104, which is disposed within the housing 110; a first readout circuit 106-1, which is coupled to the imaging array 102; a second readout circuit 106-2, which is coupled to the imaging bar 104; and a common electronic device 108, which is coupled to the first readout circuit 106-1 and the second readout circuit 106-2 and is configured to generate image data in response to at least one of the first readout circuit 106-1 and the second readout circuit 106-2.

[0144] In some embodiments, the imaging array 102 and the imaging strips 104 are separate.

[0145] In some embodiments, the imaging array 102 and the imaging strips 104 are separate and formed on the same substrate 114 .

[0146] In some implementations, at least one of the size, layout, resolution, and internal components of the pixels of the imaging array 102 is different from the corresponding at least one of the size, layout, resolution, and internal components of the pixels of the imaging strip 104 .

[0147] In some embodiments, the imaging strips 104 are a subset of the imaging array 102 .

[0148] In some embodiments, the imaging strips 104 are less than 30% of the imaging array 102 .

[0149] In some embodiments, the system further includes data lines 618 , 718 , 818 coupled to the imaging array 102 and the imaging strip 104 .

[0150] In some embodiments, the system also includes: a plurality of switches 722, which divide the data lines 718 into a plurality of first data lines 718b coupled to the imaging strip 104 and a plurality of second data lines 718b coupled to the remaining portion of the imaging array 102 outside the imaging strip 104.

[0151] In some embodiments, the system also includes: a plurality of first data lines 618a, which are coupled to the subset of the imaging array 102 including the imaging strips 104; and a plurality of second data lines 618b, which are separated from the first data lines 618a and coupled to the imaging array 102 outside the imaging strips 104.

[0152] In some embodiments, the system also includes: an x-ray source configured to generate an x-ray beam; a detector configured to receive the x-ray beam and including the housing 110, the imaging array 102, the imaging strip 104, the first readout circuit 106-1, the second readout circuit 106-2 and the common electronic device 108.

[0153] Some embodiments include a method comprising: reading first data from an imaging array 102 disposed within a housing 110 using at least a first readout circuit 106-1; reading second data from an imaging strip 104 disposed within the housing 110 using at least a second readout circuit 106-2; processing the first data in a common electronic device 108 to generate first image data; and processing the second data in the common electronic device 108 to generate second image data.

[0154] In some embodiments, the imaging array 102 and the imaging strips 104 are separate.

[0155] In some embodiments, the imaging array 102 and the imaging strips 104 are formed on the same substrate 114 .

[0156] In some implementations, the pixel size of the pixels of the imaging array 102 is different than the pixel size of the pixels of the imaging strips 104 .

[0157] In some embodiments, the imaging strips 104 are a subset of the imaging array 102 .

[0158] In some embodiments, the imaging strips 104 are less than 30% of the imaging array 102 .

[0159] In some embodiments, reading the first data from the imaging array 102 disposed within the housing 110 using at least the first readout circuit 106-1 includes reading the first data from the imaging array 102 through first data lines 618, 718, 818; and reading the second data from the imaging strip 104 disposed within the housing 110 using at least the second readout circuit 106-2 includes reading the second data from the imaging strip 104 using second data lines 618, 718, 818 different from the first data lines 618, 718, 818.

[0160] In some embodiments, reading the first data from the imaging array 102 disposed within the housing 110 using at least the first readout circuit 106-1 includes reading the first data from the imaging array 102 through first data lines 618, 718, 818; and reading the second data from the imaging strip 104 disposed within the housing 110 using at least the second readout circuit 106-2 includes reading the second data from the imaging strip 104 using second data lines 618, 718, 818; and also includes electrically coupling the first data lines 618, 718, 818 to the second data lines 618, 718, 818 when reading the first data from the imaging array 102.

[0161] Some embodiments include a system comprising: a device for reading first data from an imaging array disposed within a housing; a device for reading second data from an imaging strip disposed within the housing; a device for processing the first data in a common electronic device 108 to generate first image data; and a device for processing the second data in the common electronic device 108 to generate second image data.

[0162] The example of means for reading first data from an imaging array disposed within the housing includes readout circuitry 106 - 1 and associated data lines.

[0163] The example of the means for reading the second data from the imaging bar disposed within the housing includes readout circuit 106 - 2 and associated data lines.

[0164] An example of the means for processing the first data in a common electronic device to generate first image data includes the common electronic device 108 .

[0165] Examples of the means for processing the second data in the common electronic device to generate second image data include the common electronic device 108 .

[0166] In some embodiments, the imaging strips 104 are a subset of the imaging array 102 .

[0167] Some embodiments include a system comprising: a plurality of pixels 902; a plurality of data lines 908, the plurality of data lines being coupled to the pixels 902; a plurality of switches 906, the plurality of switches coupling the pixels 902 to the data lines 908; a plurality of readout circuits 910-918, the plurality of readout circuits being coupled to the data lines 908; a control logic 903, the control logic being coupled to the readout circuits 910-918, the control logic 903 being configured to, for one of the pixels 902: obtain a first value of the pixel 902 when the corresponding switch 906 is in an off state; reset the corresponding readout circuit 910-918 corresponding to the pixel; obtain a second value of the pixel 902 after resetting the readout circuit; turn on the corresponding switch 906; obtain a third value of the pixel 902 after turning on the corresponding switch 906; and combine the first value, the second value, and the third value into a combined value of the pixel 902.

[0168] In some embodiments, the control logic 903 is further configured to, for one of the pixels 902: store a storage value of the pixel 902 based on the first value; and combine the second value, the third value and the storage value into the combined value of the pixel 902.

[0169] In some embodiments, the control logic 903 is also configured to, for one pixel in the pixel 902: before obtaining the first value of the pixel: reset the corresponding readout circuit; obtain a fourth value of the pixel 902 when the corresponding switch 906 is in an on state; and combine the first value, the second value, the third value and the fourth value into the combined value of the pixel 902.

[0170] In some embodiments, the control logic 903 is further configured to, for one pixel in the pixel 902: add the third value minus the second value and the first value minus the fourth value to combine the first value, the second value, the third value and the fourth value into the combined value of the pixel 902.

[0171] In some embodiments, the control logic 903 is also configured to, for a pixel in the pixel 902: combine the first value and the fourth value into a first correlation value; combine the second value and the third value into a second correlation value; and combine the first correlation value and the second correlation value into the combined value of the pixel 902.

[0172] In some embodiments, the control logic 903 is further configured to, for one of the pixels 902 , obtain a first value of the pixel 902 for a subsequent frame without resetting the corresponding readout circuit.

[0173] In some embodiments, the control logic 903 is further configured to, for one of the pixels 902 , subtract the first value and the second value from the third value to combine the first value, the second value, and the third value into the combined value of the pixel 902 .

[0174] In some embodiments, the control logic 903 is also configured to, for one of the pixels 902: switch 906 between the following modes: a first operating mode, in which the first value, the second value, and the third value are combined into the combined value of the pixel; and a second operating mode, in which the second value and the third value are combined into the combined value of the pixel 902, and obtaining the first value of the pixel 902 is not performed when the corresponding switch 906 is in the off state.

[0175] In some embodiments, the system further includes: an x-ray source configured to generate an x-ray beam; and a detector including the pixels 902 and configured to receive the x-ray beam.

[0176] Some embodiments include a method comprising: when switch 906 is in an off state, using a readout circuit 910-918 to obtain a first value of a pixel 902 coupled to a data line through the switch 906; resetting the readout circuit; obtaining a second value of the pixel 902 after resetting the readout circuit; turning on the switch 906; obtaining a third value of the pixel 902 after turning on the switch 906; and combining the first value, the second value, and the third value into a combined value of the pixel 902.

[0177] In some embodiments, the method also includes: storing a storage value of the pixel 902 based on the first value; and wherein combining the first value, the second value and the third value into the combined value of the pixel 902 includes: combining the second value, the third value and the storage value into the combined value of the pixel 902.

[0178] In some embodiments, the method also includes: before obtaining the first value of the pixel: resetting the readout circuit; and obtaining a fourth value of the pixel 902 when the switch 906 is in an on state; and wherein combining the first value, the second value and the third value into the combined value of the pixel 902 includes: combining the first value, the second value, the third value and the fourth value into the combined value of the pixel 902.

[0179] In some embodiments, combining the first value, the second value, the third value, and the fourth value into the combined value of the pixel 902 includes adding the third value minus the second value and the first value minus the fourth value.

[0180] In some embodiments, the method further includes: combining the first value and the fourth value into a first correlation value; combining the second value and the third value into a second correlation value; and combining the first correlation value and the second correlation value into the combined value of the pixel 902.

[0181] In some embodiments, the method further includes acquiring a first value of the pixel 902 for a subsequent frame without resetting the corresponding readout circuit.

[0182] In some embodiments, combining the first value, the second value, and the third value into the combined value of the pixel 902 includes: subtracting the first value and the second value from the third value.

[0183] In some embodiments, the method also includes: switching between: a first operating mode, in which the first value, the second value, and the third value are combined into the combined value of the pixel; and a second operating mode, in which the second value and the third value are combined into the combined value of the pixel 902, and obtaining the first value of the pixel 902 is not performed when the corresponding switch 906 is in the disconnected state.

[0184] In some embodiments, the method further comprises: generating an x-ray beam using an x-ray source; and generating an image using a detector including the pixels 902 configured to receive the x-ray beam.

[0185] Some embodiments include a system comprising: a device for obtaining a first value of a pixel coupled to a data line through a switch using a readout circuit when the switch is in an off state; a device for resetting the readout circuit; a device for obtaining a second value of the pixel after resetting the readout circuit; a device for turning on the switch; a device for obtaining a third value of the pixel after turning on the switch; and a device for combining the first value, the second value, and the third value into a combined value of the pixel.

[0186] The example of the means for acquiring a first value of a pixel coupled to a data line through a switch using a readout circuit when the switch is in an open state includes a switch 906 , a row driver 901 , a data line 908 , and readout circuits 910 - 918 .

[0187] The example of the means for resetting the readout circuit includes a switch 910 a and a control logic 903 .

[0188] The example of the means for obtaining the second value of the pixel after resetting the readout circuit includes the switch 906, the row driver 901, the data line 908 and the readout circuits 910-918.

[0189] An example of the means for turning on the switch includes the control logic 903 .

[0190] An example of the means for acquiring the third value of the pixel after turning on the switch includes the switch 906 , the row driver 901 , the data line 908 , and the readout circuits 910 - 918 .

[0191] An example of the means for combining the first value, the second value and the third value into a combined value of the pixel includes the switch 906 , the row driver 901 , the data line 908 , the readout circuits 910 - 918 and an external computer 913 .

[0192] In some embodiments, the system further includes: means for acquiring the first value of the pixel for a subsequent frame without resetting the corresponding readout circuit. An example of the means for acquiring the first value of the pixel for a subsequent frame without resetting the corresponding readout circuit includes the switch 906, the row driver 901, the data line 908, and the readout circuits 910-918.

[0193] Although specific examples of means for performing particular functions have been described above, in other embodiments, the particular functions may be performed by other means described herein.

[0194] Although structures, devices, methods and systems have been described according to specific embodiments, those skilled in the art will readily recognize that many variations to the specific embodiments are possible, and therefore, any variation should be considered to be within the spirit and scope disclosed herein. Therefore, many modifications may be made by those skilled in the art without departing from the spirit and scope of the appended claims.

[0195] The claims accompanying this written disclosure are hereby expressly incorporated into this written disclosure, wherein each claim may stand on its own as a separate embodiment. This disclosure includes all permutations of individual claims and their dependent claims. In addition, additional embodiments that can be derived from the accompanying individual and dependent claims are also expressly incorporated into this written specification. These additional embodiments are identified by replacing the dependency of a given dependent claim with the phrase "any of the claims beginning with claim [x] and ending with the claim immediately preceding said claim", wherein the term "[x]" in brackets is replaced with the number of the most recently cited independent claim. For example, for the first claim set beginning with independent claim 1, claim 4 may be dependent on any of claim 1 and claim 3, wherein these separate dependencies result in two different embodiments; claim 5 may be dependent on any of claim 1, claim 3, or claim 4, wherein these separate dependencies result in three different embodiments; claim 6 may be dependent on any of claim 1, claim 3, claim 4, or claim 5, wherein these separate dependencies result in four different embodiments; and so on.

[0196] The recitation of a claim with respect to the term "first" for a feature or element does not necessarily imply the presence of second or additional such features or elements. Embodiments of the invention claiming exclusive attributes or characteristics are defined as follows.

Claims

1. An imaging system, comprising: Multiple pixels; Multiple data lines; a plurality of switches coupling the pixels to the data lines, wherein each of the pixels is coupled to a corresponding one of the data lines through a corresponding one of the switches; a plurality of readout circuits coupled to the data lines, wherein each of the data lines is coupled to a corresponding one of the readout circuits; control logic coupled to the readout circuit, the control logic comprising a processor configured to, for one of the pixels: acquiring a first value of the pixel when the corresponding switch is in an off state; resetting the corresponding readout circuit; obtaining a second value of the pixel after resetting the readout circuit; Turning on the corresponding switch; acquiring a third value of the pixel after turning on the corresponding switch; and The first value, the second value, and the third value are combined into a combined value for the pixel.

2. The system of claim 1 , wherein the processor is further configured to, for the one of the pixels: storing a stored value for the pixel based on the first value; and The second value, the third value, and the stored value are combined into the combined value for the pixel.

3. The system of claim 1 , wherein the processor is further configured to, for the one of the pixels: Before obtaining the first value of the pixel: resetting the corresponding readout circuit; and A fourth value of the pixel is acquired when the corresponding switch is in an on state; and the first value, the second value, the third value and the fourth value are combined into the combined value of the pixel.

4. The system of claim 3, wherein the processor is further configured to, for the one of the pixels: The third value minus the second value is added to the first value minus the fourth value to combine the first value, the second value, the third value, and the fourth value into the combined value of the pixel.

5. The system of claim 3, wherein the processor is further configured to, for the one of the pixels: combining the first value and the fourth value into a first correlation value; combining the second value and the third value into a second correlation value; and The first correlation value and the second correlation value are combined into the combined value of the pixel.

6. The system of claim 1 , wherein the processor is further configured to, for the one of the pixels: The first value of the pixel for a subsequent frame is acquired without resetting the corresponding readout circuit.

7. The system of claim 1 , wherein the processor is further configured to, for the one of the pixels: The first value and the second value are subtracted from the third value to combine the first value, the second value, and the third value into the combined value of the pixel.

8. The system of claim 1 , wherein the processor is further configured to, for the one of the pixels: Switch between the following modes: a first operating mode in which the first value, the second value, and the third value are combined into the combined value for the pixel; and A second operation mode, in which the second value and the third value are combined into the combined value of the pixel, and obtaining the first value of the pixel is not performed when the corresponding switch is in the off state.

9. The system of claim 1, further comprising: an x-ray source configured to generate an x-ray beam; A detector includes the pixels and is configured to receive the x-ray beam.

10. An imaging method, comprising: When the switch is in an off state, obtaining a first value of a pixel coupled to the data line through the switch using a readout circuit; resetting the readout circuit; obtaining a second value of the pixel after resetting the readout circuit; Turning on the switch; acquiring a third value of the pixel after turning on the switch; and The first value, the second value, and the third value are combined into a combined value for the pixel.

11. The method of claim 10, further comprising: storing a stored value of the pixel based on the first value; and Combining the first value, the second value and the third value into the combined value of the pixel includes: combining the second value, the third value and the stored value into the combined value of the pixel.

12. The method of claim 10, further comprising: Before obtaining the first value of the pixel: resetting the readout circuit; and acquiring a fourth value of the pixel when the switch is in an on state; and Combining the first value, the second value, and the third value into the combined value of the pixel includes: combining the first value, the second value, the third value, and the fourth value into the combined value of the pixel.

13. The method of claim 12, wherein combining the first value, the second value, the third value, and the fourth value into the combined value of the pixel comprises: The third value minus the second value is added to the first value minus the fourth value.

14. The method of claim 12, further comprising: combining the first value and the fourth value into a first correlation value; combining the second value and the third value into a second correlation value; as well as The first correlation value and the second correlation value are combined into the combined value of the pixel.

15. The method of claim 10, further comprising: The first value of the pixel for a subsequent frame is acquired without resetting the readout circuit.

16. The method of claim 10, wherein combining the first value, the second value, and the third value into the combined value of the pixel comprises: The first value and the second value are subtracted from the third value.

17. The method of claim 10, further comprising: Switch between the following modes: a first operating mode in which the first value, the second value, and the third value are combined into the combined value of the pixel; as well as a second operation mode in which the second value and the third value are combined into the combined value of the pixel, and acquiring the first value of the pixel is not performed when the switch is in the off state.

18. The method of claim 10, further comprising: generating an x-ray beam using an x-ray source; and An image is generated using a detector including the pixels arranged to receive the x-ray beam.

19. An imaging system comprising: means for acquiring, using a readout circuit, a first value of a pixel coupled to a data line through the switch when the switch is in an open state; means for resetting said readout circuit; means for obtaining a second value of the pixel after resetting the readout circuit; means for switching on said switch; means for acquiring a third value of the pixel after turning on the switch; and means for combining the first value, the second value and the third value into a combined value for the pixel.

20. The system of claim 19, further comprising: Means for acquiring the first value of the pixel for a subsequent frame without resetting the readout circuit.

Images