Current biasing circuit, chip and corresponding electronic device
By introducing a charge-sharing mechanism combining capacitors and switches into the current bias circuit, the problems of slow start-up speed and high power consumption in traditional current bias circuits are solved, achieving fast start-up and low power consumption current biasing effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2023-04-28
- Publication Date
- 2026-05-12
AI Technical Summary
In traditional current-biased circuits, the parasitic capacitance of the MOSFET causes the current to grow slowly, which slows down the circuit startup speed, especially in applications with high power consumption requirements.
P-type and N-type MOSFET current mirror modules and a fast start-up module are introduced into the current bias circuit. By combining multiple capacitors and switches, the charge sharing between capacitors is used to accelerate the start-up speed of the current mirror module. The voltage establishment value is adjusted by adjusting the size and ratio of the capacitors, providing a larger voltage space to ensure that the circuit can operate under low power supply voltage.
It accelerates the start-up speed of the current bias circuit, reduces current overshoot, lowers power consumption, and maintains the robustness of the circuit under low supply voltage.
Smart Images
Figure CN116501127B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, specifically to a current bias circuit, a chip, and a corresponding electronic device. Background Technology
[0002] In analog circuits such as comparators and amplifiers, multiple current biases are required. Bias circuits provide bias current to commonly used analog circuit modules such as comparators and amplifiers. However, in practical applications with high power consumption requirements, such as battery-powered chips and multi-stage digital-to-analog converters, the bias circuits need to be able to start up in a very short time.
[0003] The conventional current biasing circuit provided in the related technology has a large parasitic capacitance in the metal-oxide-semiconductor field-effect transistor (MOSFET), which makes the current increase slow during the startup process, thus slowing down the startup speed of the subsequent biased circuit. Summary of the Invention
[0004] To address the problems in the related technologies, this disclosure provides a current biasing circuit, a chip, and a corresponding electronic device.
[0005] In a first aspect, embodiments of this disclosure provide a current biasing circuit, including:
[0006] The P-type MOSFET current mirror module has a first terminal connected to the power supply voltage, a second terminal connected to the first bias voltage, a third terminal connected to the P-type fast start module, and a fourth terminal outputting the P-type bias current through the first switch group.
[0007] The P-type fast start module is connected to the fifth terminal of the P-type fast start module via a first control switch, and includes multiple capacitors and multiple switches. The P-type fast start module is used to accelerate the start-up speed of the P-type MOSFET current mirror module through the multiple capacitors and multiple switches.
[0008] The N-type MOSFET current mirror module has its first terminal connected to the ground terminal, its second terminal connected to the second bias voltage, its third terminal connected to the N-type fast start module, its fourth terminal outputting the N-type bias current through the second switch group, and its fifth terminal connected to the sixth terminal of the P-type MOSFET current mirror module through the second control switch.
[0009] The N-type fast start module is connected to the fifth terminal of the N-type MOSFET current mirror module via the second control switch, and includes multiple capacitors and multiple switches. The N-type fast start module is used to accelerate the start-up speed of the N-type MOSFET current mirror module through the multiple capacitors and multiple switches.
[0010] In one possible implementation of this disclosure, the fifth terminal of the P-type MOSFET current mirror module is also connected to the ground terminal via the first control switch and the first resistor.
[0011] In one possible implementation of this disclosure, the P-type fast-start module includes: a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch, wherein:
[0012] The first terminal of the first capacitor is connected to the power supply voltage via a third switch, connected to the third terminal of the P-type MOSFET current mirror module via a second switch, and connected to the ground terminal via a first switch.
[0013] The second terminal of the first capacitor is connected to the ground terminal via the fourth switch, and to the ground terminal via the fifth and sixth switches. It is also connected to the first terminal of the second capacitor via the fifth switch, and to the fifth terminal of the P-type fast start module via the fifth switch and the first control switch.
[0014] The second terminal of the second capacitor is connected to the third terminal of the P-type MOSFET current mirror module.
[0015] In one possible implementation of this disclosure, the N-type fast-start module includes: a third capacitor, a fourth capacitor, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, and a twelfth switch, wherein:
[0016] The first terminal of the third capacitor is connected to the power supply voltage via the ninth switch, the fifth terminal of the N-type MOSFET current mirror module is connected to the power supply voltage via the eighth switch, and the seventh terminal is connected to the power supply voltage.
[0017] The second terminal of the third capacitor is connected to the ground terminal via the tenth switch, and connected to the power supply voltage via the eleventh and twelfth switches. It is also connected to the first terminal of the fourth capacitor and the third terminal of the N-type MOSFET current mirror module via the eleventh switch.
[0018] The second terminal of the fourth capacitor is connected to the fifth terminal of the N-type MOSFET current mirror module via the second control switch.
[0019] In one possible implementation of this disclosure, when the current bias circuit is started, the first switch, the third switch, the seventh switch, and the ninth switch switch from a closed state to an open state, and after a first preset time delay, the fourth switch, the sixth switch, the tenth switch, and the twelfth switch switch from a closed state to an open state. At the same time, the first control switch, the second control switch, the first switch group, and the second switch group switch from an open state to a closed state, and after a second preset time delay, the second switch, the fifth switch, the eighth switch, and the eleventh switch switch from an open state to a closed state.
[0020] In one possible implementation of this disclosure, the P-type MOSFET current mirror module includes:
[0021] The first group of P-type MOSFETs has its source connected to the first terminal of the P-type MOSFET current mirror module, and its gate connected to the first terminal of the P-type MOSFET current mirror module via a first parasitic capacitance. The gate of the first P-type MOSFET in the first group of P-type MOSFETs is connected to the third terminal of the P-type MOSFET current mirror module.
[0022] The second group of P-type MOSFETs has its gates connected to the second terminal of the P-type MOSFET current mirror module, and the source of each P-type MOSFET in the second group is connected to the drain of a corresponding P-type MOSFET in the first group of P-type MOSFETs. The drain of the first P-type MOSFET in the second group of P-type MOSFETs is connected to the fifth terminal of the P-type MOSFET current mirror module, and the drain of the second P-type MOSFET in the second group of P-type MOSFETs is connected to the sixth terminal of the P-type MOSFET current mirror module.
[0023] In this group of P-type MOSFETs, the drains of the other P-type MOSFETs (excluding the first and second P-type MOSFETs) are connected to the fourth terminal of the P-type MOSFET current mirror module, and different P-type bias currents are output through a corresponding switch in the first switch group.
[0024] In one possible implementation of this disclosure, the N-type MOSFET current mirror module includes:
[0025] The first group of N-type MOSFETs has its sources connected to the first terminal of the N-type MOSFET current mirror module, and its gates connected to the first terminal of the N-type MOSFET current mirror module via a second parasitic capacitance. The gate of the first N-type MOSFET in the first group of N-type MOSFETs is connected to the third terminal of the N-type MOSFET current mirror module.
[0026] The second group of N-type MOSFETs has its gates connected to the second terminal of the N-type MOSFET current mirror module, and the source of each N-type MOSFET in the second group is connected to the drain of a corresponding N-type MOSFET in the first group of N-type MOSFETs. The drain of the first N-type MOSFET in the second group of N-type MOSFETs is connected to the fifth terminal of the N-type MOSFET current mirror module.
[0027] In this group of N-type MOSFETs, the drains of the other N-type MOSFETs (excluding the first N-type MOSFET) are connected to the fourth terminal of the N-type MOSFET current mirror module, and different N-type bias currents are output through a corresponding switch in the second group of switches.
[0028] Secondly, this disclosure provides a current biasing circuit, including:
[0029] The P-type MOSFET current mirror module has a first terminal connected to the power supply voltage, a second terminal connected to the third bias voltage, a third terminal connected to the ground terminal via a first target switch, and a fourth terminal outputting P-type bias current via a third switch group.
[0030] The N-type MOSFET current mirror module has a first terminal connected to the ground terminal, a second terminal connected to the fourth bias voltage, a third terminal connected to the power supply voltage via the second target switch, a fourth terminal outputting N-type bias current via the fourth switch group, and a fifth terminal connected to the fifth terminal of the P-type MOSFET current mirror module via the third control switch.
[0031] The sixth terminal of the P-type MOSFET current mirror module is connected to the ground terminal via the fourth control switch, the third target switch, and the second resistor, and is connected to the third terminal of the P-type MOSFET current mirror module via the fourth control switch; the sixth terminal of the N-type MOSFET current mirror module is connected to the fifth terminal of the N-type MOSFET current mirror module via the third control switch.
[0032] In one possible implementation of this disclosure, when the current bias circuit is started, the first target switch and the second target switch switch switch from a closed state to an open state, and at the same time, the third control switch, the fourth control switch and the third target switch switch from an open state to a closed state, and after a third preset time delay, the third switch group and the fourth switch group switch from an open state to a closed state.
[0033] In one possible implementation of this disclosure, both the P-type MOSFET current mirror module and the N-type MOSFET current mirror module are common-source, common-gate current mirrors.
[0034] Thirdly, this disclosure provides a current biasing circuit, including:
[0035] A P-type MOSFET module and an N-type MOSFET module, wherein the P-type MOSFET module includes M P-type MOSFETs and a fifth parasitic capacitor, and the N-type MOSFET module includes S N-type MOSFETs and a sixth parasitic capacitor; wherein M is an integer greater than 2, and S is an integer greater than or equal to 2;
[0036] The sources of all M P-type MOSFETs are connected to the power supply voltage, and the gates of all M P-type MOSFETs are connected to the power supply voltage through the first parasitic capacitance. The gate of the first P-type MOSFET is connected to the ground terminal through the fourth target switch, and the drain is connected to the gate of the first P-type MOSFET through the fifth target switch, and connected to the ground terminal through the third resistor and the sixth target switch.
[0037] The sources of all S N-type MOSFETs are connected to the ground terminal, and the gates of all S N-type MOSFETs are connected to the ground terminal via the sixth parasitic capacitance. The gate of the first N-type MOSFET among the S N-type MOSFETs is connected to the power supply voltage via the seventh target switch, and the drain is connected to the gate of the first N-type MOSFET via the eighth target switch, and is also connected to the drain of the second P-type MOSFET among the M P-type MOSFETs.
[0038] Among the M P-type MOSFETs, the drain of each P-type MOSFET other than the first P-type MOSFET and the second P-type MOSFET outputs a different P-type bias current through the corresponding switch in the fifth switch group; among the S N-type MOSFETs, the drain of each N-type MOSFET other than the first N-type MOSFET outputs a different N-type bias current through the corresponding switch in the sixth switch group.
[0039] In one possible implementation of this disclosure, when the current bias circuit is started, the fourth target switch and the seventh target switch switch switch from the closed state to the open state, and at the same time, the fifth target switch, the eighth target switch, and the sixth target switch switch switch from the open state to the closed state. After a delay of a fourth preset time, the fifth switch group and the sixth switch group switch from the open state to the closed state.
[0040] Fourthly, this disclosure provides a chip that includes circuitry in any of the possible implementations of the first to third aspects described above.
[0041] Fifthly, this disclosure provides an electronic device including the chip described in the fourth aspect.
[0042] According to the current biasing circuit provided in this disclosure embodiment, the circuit includes: a P-type MOSFET current mirror module, a P-type fast startup module, an N-type MOSFET current mirror module, and an N-type fast startup module. By adding multiple capacitors to the current biasing circuit including the cascode current mirror, the charge sharing effect among these capacitors can rapidly establish the critical node to near the target value, accelerating the startup speed while reducing current overshoot. Furthermore, the voltage establishment value can be adjusted by regulating the size and ratio of the capacitors, providing a larger voltage headroom for the cascode MOSFET and ensuring it operates in the saturation region. This ensures the robustness of the circuit under low supply voltage, and due to the voltage difference stored on the capacitors, the resistance can be reduced in low-power scenarios.
[0043] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0044] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:
[0045] Figure 1 A schematic diagram of one of the current biasing circuits according to an embodiment of the present disclosure is shown;
[0046] Figure 2 A second schematic diagram of a current biasing circuit according to an embodiment of the present disclosure is shown;
[0047] Figure 3 One of the schematic diagrams of the switching timing according to an embodiment of the present disclosure is shown;
[0048] Figure 4 A third schematic diagram of a current biasing circuit according to an embodiment of the present disclosure is shown;
[0049] Figure 5 A second schematic diagram of the switching timing according to an embodiment of the present disclosure is shown;
[0050] Figure 6 A fourth schematic diagram of a current biasing circuit according to an embodiment of the present disclosure is shown;
[0051] Figure 7 A third schematic diagram illustrating the switching timing according to an embodiment of the present disclosure is shown;
[0052] Figure 8 Fifth schematic diagram of a current bias circuit according to an embodiment of the present disclosure. Detailed Implementation
[0053] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement them. Furthermore, for clarity, portions unrelated to the description of exemplary embodiments have been omitted from the drawings.
[0054] In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, figures, steps, behaviors, components, parts or combinations thereof.
[0055] It should also be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.
[0056] In this disclosure, any operation involving the acquisition of user information or user data, or the display of user information or user data to others, is an operation authorized or confirmed by the user, or actively selected by the user.
[0057] As mentioned above, multiple current biases are required in analog circuits such as comparators and amplifiers. Bias circuits provide bias current to commonly used analog circuit modules such as comparators and amplifiers. However, in practical applications with high power consumption requirements, such as battery-powered chips and multi-stage digital-to-analog converters, the bias circuits need to be able to start up in a very short time.
[0058] The conventional current biasing circuit provided in the related technology has a large parasitic capacitance in the metal-oxide-semiconductor field-effect transistor (MOSFET), which makes the current increase in the circuit relatively slow during the startup process. This slows down the startup speed of the subsequent biased circuit, resulting in high power consumption.
[0059] To address the aforementioned technical deficiencies, this disclosure provides a current biasing circuit comprising: a P-type MOSFET current mirror module, a P-type fast start-up module, an N-type MOSFET current mirror module, and an N-type fast start-up module. By incorporating multiple capacitors into the current biasing circuit including the cascode current mirror, the charge sharing among these capacitors can rapidly establish the critical node near the target value, thereby accelerating the start-up speed while reducing current overshoot.
[0060] Furthermore, the voltage establishment value can be adjusted by changing the size and ratio of the capacitor in the circuit, while providing a larger voltage space for the cascode MOS to ensure that it is in the saturation region. This ensures the robustness of the circuit when operating at low power supply voltage. Also, due to the voltage difference stored on the capacitor, the size of the resistor can be reduced in low power consumption scenarios.
[0061] This disclosure provides a current biasing circuit, which includes:
[0062] The P-type metal-oxide-semiconductor field-effect transistor (MOSFET) current mirror module has a first terminal connected to the power supply voltage, a second terminal connected to a first bias voltage, a third terminal connected to a P-type fast start module, and a fourth terminal outputting a P-type bias current via a first switch group.
[0063] The P-type fast start module is connected to the fifth terminal of the P-type fast start module via a first control switch. The P-type fast start module includes multiple capacitors and multiple switches. The P-type fast start module is used to accelerate the start-up speed of the P-type MOSFET current mirror module through the multiple capacitors and multiple switches.
[0064] The N-type MOSFET current mirror module has its first terminal connected to the ground terminal, its second terminal connected to the second bias voltage, its third terminal connected to the N-type fast start module, its fourth terminal outputting an N-type bias current via a second switch group, and its fifth terminal connected to the sixth terminal of the P-type MOSFET current mirror module via a second control switch.
[0065] The N-type fast start module is connected to the fifth terminal of the N-type MOSFET current mirror module via the second control switch. The N-type fast start module includes multiple capacitors and multiple switches. The N-type fast start module is used to accelerate the start-up speed of the N-type MOSFET current mirror module through the multiple capacitors and multiple switches.
[0066] For example, Figure 1 A schematic diagram of a current biasing circuit according to an embodiment of the present disclosure is shown. (As shown) Figure 1 As shown, the current bias circuit includes: a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) current mirror module 100, a P-type fast start-up module 200, an N-type MOSFET current mirror module 300, and an N-type fast start-up module 400.
[0067] The first terminal L1 of the P-type MOSFET current mirror module 100 is connected to the power supply voltage V. dd The second terminal L2 of the P-type MOSFET current mirror module is connected to the first bias voltage vp_cas1, the third terminal L3 of the P-type MOSFET current mirror module is connected to the P-type fast start module 200, and the fourth terminal L4 of the P-type MOSFET current mirror module outputs P-type bias current through the first switch group SW_P1.
[0068] The P-type fast start module 200 includes: a first capacitor C1, a second capacitor C2, a first switch EN1, a second switch EN1, a third switch EN2, a fourth switch EN3, a fifth switch EN2, and a sixth switch EN4; wherein the first terminal L5 of the first capacitor is connected to the power supply voltage V via the third switch. dd Furthermore, the first terminal L5 of the first capacitor is connected to the third terminal L3 of the P-type MOSFET current mirror module 100 via the second switch EN1, and is also connected to the ground terminal V via the first switch EN1. ss The second terminal L6 of the first capacitor is connected to the ground terminal V via the fourth switch ~EN3. ss Furthermore, the second terminal L6 of the first capacitor is connected to the ground terminal V via the fifth switch EN2 and the sixth switch ~EN4.ss The second terminal L6 of the first capacitor is connected to the first terminal L7 of the second capacitor C2 via the fifth switch EN2. The second terminal L6 of the first capacitor is connected to the fifth terminal L8 of the P-type fast start module via the fifth switch EN2 and the first control switch EN5. The second terminal L9 of the second capacitor C2 is connected to the third terminal L3 of the P-type MOSFET current mirror module.
[0069] Among them, the first terminal L of the N-type MOSFET current mirror module 300 10 Connected to the grounding terminal V ss The second terminal L of the N-type MOSFET current mirror module 11 The third terminal L of the N-type MOSFET current mirror module is connected to the second bias voltage vn_cas1. 12 Connected to the N-type fast start module 400, the fourth terminal L of the N-type MOSFET current mirror module 13 The second switch group SW_N1 outputs an N-type bias current, and the fifth terminal L of the N-type MOSFET current mirror module... 14 The second control switch EN6 is connected to the sixth terminal L of the P-type MOSFET current mirror module. 15 .
[0070] The N-type fast start module 400 includes: a third capacitor C3, a fourth capacitor C4, a seventh switch (EN5), an eighth switch (EN3), a ninth switch (EN6), a tenth switch (EN7), an eleventh switch (EN4), and a twelfth switch (EN8); wherein the first terminal L of the third capacitor C3... 16 Connected to power supply voltage V via the ninth switch ~EN6 dd And the first terminal L of the third capacitor 16 The eighth switch EN3 is connected to the fifth terminal L of the N-type MOSFET current mirror module. 14 And connected to the power supply voltage V via the seventh switch ~EN5. dd The second terminal L of the third capacitor 17 Connected to ground terminal V via the tenth switch ~EN7 ss And the second terminal L of the third capacitor 17 Connected to the power supply voltage V via the eleventh switch EN4 and the twelfth switches ~EN8. dd and the second terminal L of the third capacitor 17 The eleventh switch EN4 is connected to the first terminal L of the fourth capacitor C4. 18 and the third terminal L of the N-type MOSFET current mirror module 12 The second terminal L of the fourth capacitor 19The second control switch EN6 is connected to the fifth terminal L of the N-type MOSFET current mirror module. 14 .
[0071] In one embodiment of this disclosure, the fifth terminal L8 of the P-type MOSFET current mirror module is also connected to the ground terminal V via the first control switch EN5 and the first resistor Rb1. ss .
[0072] In one embodiment of this disclosure, both the P-type MOSFET current mirror module 100 and the N-type MOSFET current mirror module 300 can be common source cascode current mirrors.
[0073] Combination Figure 1 , Figure 2 Another schematic diagram of a current bias circuit according to an embodiment of the present disclosure is shown.
[0074] like Figure 2 As shown, the P-type MOSFET current mirror module 100 includes: a first group of P-type MOSFETs and a second group of P-type MOSFETs.
[0075] In this configuration, the sources of the first group of P-type MOSFETs are all connected to the first terminal L1 of the P-type MOSFET current mirror module, and the gates of the first group of P-type MOSFETs are all connected to the first terminal L1 of the P-type MOSFET current mirror module via the first parasitic capacitance CP_pmos1. The gate of the first P-type MOSFET (denoted as Mpb1) in the first group of P-type MOSFETs is connected to the third terminal L3 of the P-type MOSFET current mirror module.
[0076] In this configuration, the gates of all P-type MOSFETs in the second group are connected to the second terminal L2 of the P-type MOSFET current mirror module, and the source of each P-type MOSFET in the second group is connected to the drain of a corresponding P-type MOSFET in the first group. The drain of the first P-type MOSFET (denoted as Mpcas1) in the second group is connected to the fifth terminal L8 of the P-type MOSFET current mirror module, and the drain of the second P-type MOSFET (denoted as Mpb2) in the second group is connected to the sixth terminal L8 of the P-type MOSFET current mirror module. 15 ;
[0077] In this group of P-type MOSFETs, the drains of the other P-type MOSFETs (denoted as Mp1, Mp2, ..., Mpn) besides the first and second P-type MOSFETs are respectively connected to the fourth terminal L4 of the P-type MOSFET current mirror module, and different P-type bias currents are output through a corresponding switch in the first switch group SW_P.
[0078] In one embodiment of this disclosure, the first group of P-type MOSFETs includes the same number of P-type MOSFETs as the second group of P-type MOSFETs.
[0079] In one embodiment of this disclosure, the N-type MOSFET current mirror module 300 is a common-source, common-gate current mirror. Specifically, as follows... Figure 2 As shown, the N-type MOSFET current mirror module 300 includes: a first group of N-type MOSFETs and a second group of N-type MOSFETs.
[0080] In this configuration, the sources of the first group of N-type MOSFETs are all connected to the first terminal L of the N-type MOSFET current mirror module. 10 Furthermore, the gates of the first group of N-type MOSFETs are all connected to and via the second parasitic capacitor CP_nmos1 to the first terminal L of the N-type MOSFET current mirror module 300. 10 The gate of the first N-type MOSFET (denoted as Mnb1) in the first group of N-type MOSFETs is connected to the third terminal L of the N-type MOSFET current mirror module. 12 .
[0081] In this configuration, the gates of the second group of N-type MOSFETs are all connected to the second terminal L of the N-type MOSFET current mirror module. 11 Furthermore, the source of each N-type MOSFET in the second group is connected to the drain of a corresponding N-type MOSFET in the first group, and the drain of the first N-type MOSFET (denoted as Mncas1) in the second group is connected to the fifth terminal L of the N-type MOSFET current mirror module 300. 14 ;
[0082] In this group of N-type MOSFETs, the drains of the other N-type MOSFETs (denoted as Mn1, Mn2, ..., Mnm) besides the first N-type MOSFET are respectively connected to the fourth terminal L of the N-type MOSFET current mirror module. 13 Furthermore, different N-type bias currents are output through one of the corresponding switches in the second switch group SW_N.
[0083] In one embodiment of this disclosure, the number of N-type MOSFETs included in the first group of N-type MOSFETs is the same as the number of N-type MOSFETs included in the second group of N-type MOSFETs.
[0084] It should be noted that in practical applications, the number of MOSFETs included in the P-type MOSFET current mirror module and the N-type MOSFET current mirror module may be the same or different, and the specific number can be determined according to the usage situation. This disclosure does not limit this.
[0085] In one embodiment of this disclosure, such as Figure 3 The switching timing diagram shown indicates that when the current bias circuit is started, the first switch ~EN1, the third switch ~EN2, the seventh switch ~EN5, and the ninth switch ~EN6 all switch from the closed state to the open state. After a delay of a first preset time t1, the fourth switch ~EN3, the sixth switch ~EN4, the tenth switch ~EN7, and the twelfth switch ~EN8 switch from the closed state to the open state. At the same time, the first control switch EN5, the second control switch EN6, the first switch group SW_P1, and the second switch group SW_N1 switch from the open state to the closed state. After a delay of a second preset time t2, the second switch EN1, the fifth switch EN2, the eighth switch EN3, and the eleventh switch EN4 switch from the open state to the closed state.
[0086] Based on the above Figure 3 The switching timing diagram above Figure 2 The working principle of the current bias circuit shown is as follows:
[0087] When the current bias circuit is off, ~EN1, ~EN2, ~EN3, ~EN4, ~EN5, ~EN6, ~EN7, and ~EN8 are all closed, while EN1 to EN6, as well as SW_P1 and SW_N1, are open. At this time, the enable is off. For the PMOS bias branch, the gate of Mpb1 is pulled to ground, the upper plate of C1 (i.e., the first terminal L5) is pulled to the power supply voltage, the lower plate of C1 (i.e., the second terminal L6) is pulled to ground, and the upper and lower plates of C2 are both pulled to ground. The switch blocks the current in the branch. For the NMOS bias branch, the switch pulls the gate of Mnb1 to the power supply, while the upper plate of C3 (i.e., the first terminal L6) is pulled to ground. 16 The circuit is pulled to the power supply, and the lower-level board of C3 (i.e., the second terminal L) 17 When C4 is pulled to the ground terminal, both the upper and lower plates of C4 are pulled to the ground terminal. That is to say, C1 and C3 have charge, while C2 and C4 have no charge, and neither the first switch group SW_P1 nor the second switch group SW_N1 provides bias current to the outside.
[0088] After starting the current bias circuit, the first switch ~EN1, the third switch ~EN2, the seventh switch ~EN5, and the ninth switch ~EN6 are first disconnected, that is, the first switch ~EN1, the third switch ~EN2, the seventh switch ~EN5, and the ninth switch ~EN6 are all switched from the closed state to the open state; then, after a delay of the first preset time t1, the fourth switch ~EN3, the sixth switch ~EN4, the tenth switch ~EN7, and the twelfth switch ~EN8 can be disconnected, that is, the fourth switch ~EN3, the sixth switch ~EN4, the tenth switch ~EN7, and the twelfth switch ~EN8. The system switches from the closed state to the open state, and simultaneously closes the first control switch EN5 and the second control switch EN6, as well as the first switch group SW_P1 and the second switch group SW_N1, meaning that the first switch group SW_P1 and the second switch group SW_N1 switch from the open state to the closed state; and after a delay of the second preset time t2, closes the second switch EN1, the fifth switch EN2, the eighth switch EN3 and the eleventh switch EN4, meaning that the second switch EN1, the fifth switch EN2, the eighth switch EN3 and the eleventh switch EN4 all switch from the open state to the closed state.
[0089] Taking the PMOS bias branch as an example, after the enable is activated, when each switch is turned on according to the above timing sequence, the charge on C1 can be shared with C2 and CP_pmos1, so that the gate voltage of Mpb1 approaches the final stable state in an instant, thereby speeding up the start-up of the bias circuit.
[0090] Taking the capacitors around Mpb1 as an example, let's analyze the role of the capacitors when the enable is turned on. Specifically, the total charge on C1, C2, and Cp_pmos1 is:
[0091] Q = Vdd·C1 + (0 - Vdd)·C P_Pm os1
[0092] Once enabled, the switch is turned on (i.e. closed) or off according to the above timing sequence. At this time, assuming the voltage at the gate of Mpb1 is Vc, the total charge on C1, C2, and Cp_pmos1 is:
[0093] Q = Vc·(C1+C2)+(Vc-Vdd)·C P_Pm os1
[0094] Thus, V can be obtained. c :
[0095]
[0096] It should be noted that, due to the rapid charge sharing speed between capacitors, after the EN1 and EN2 signals are activated, the gate voltage of Mpb1 will be quickly established on Vc. In other words, after the enable is turned on, the gate voltage of Mpb1 can quickly jump to a value close to the normal operating voltage, thereby speeding up the start-up speed of the bias circuit.
[0097] Furthermore, since the bias circuit is already operating at a current very close to that of normal operation, the magnitude and duration of the current overshoot in the circuit are both small.
[0098] It should be understood that, in practical applications, V can be adjusted by adjusting the values of C1 and C2 in the circuit. c The value can be set, and C1, C2 >> Cp_pmos1 can be set.
[0099] During the subsequent voltage build-up process, the voltage across the capacitor will remain essentially constant. Assuming the gate voltage of Mpb1 is Vg at the final steady state, then the voltage across Rb1 at steady state is Vg - Vc. Since there is a voltage difference between the gate voltage of Mpb1 and the voltage across Rb1 at this point, more headroom is provided for Mpb1 and Mpbcas1 transistors to operate in the saturation region. This increases the output impedance of the current source, ensuring a more stable output bias current.
[0100] In one embodiment of this disclosure, the final steady-state current I of the PMOS bias branch can be obtained by the following formula:
[0101]
[0102] Where μ is the mobility of the field-effect transistor, and C ox V is the gate capacitance of the field-effect transistor (FET), W is the width of the FET, L is the length of the FET, Vdd is the power supply voltage, Vth is the threshold voltage of the FET, Vg is the gate voltage of Mpb1 in steady state, Vc is the instantaneous gate voltage of Mpb1, and R is the resistance of Rb1.
[0103] It should be noted that, compared to traditional bias circuits, R can be chosen to have a smaller value due to the presence of Vc.
[0104] Furthermore, the operating principle of the NMOS bias branch is similar to that of the PMOS bias branch. For the NMOS bias branch, when the circuit is turned on, the charge of C4 and CP_nmos1 is shared with C3, causing the voltage at the gate of Mnb1 to rapidly drop from Vdd to near the target value, and then gradually decrease from that voltage to the target value. This accelerates the start-up speed of the bias circuit.
[0105] Based on the above current formula, the gate voltage Vg of Mpb1 can be obtained, and the unique current of this path can be determined.
[0106] It should be noted that the second branch, Mpb2, mirrors the current of Mpb1 and supplies it to Mnb1; that is, the current in Mnb1 is the same as the current in Mpb2. The mirror relationship of the current mirrors satisfies the following formula:
[0107]
[0108] Where I is the current, W is the width of the field-effect transistor, and L is the length of the long-term transistor.
[0109] The subsequent current mirrors mirror the currents Mpb1 and Mnb1 respectively, providing p-type bias currents ibp1 to ibpx and N-type bias currents ibn1 to ibny for the subsequent circuit. Of course, the p-type bias current and N-type bias current provided by the subsequent circuit can be obtained based on the mirror relationship formulas of the current mirrors mentioned above.
[0110] Thus, since the dimensions of Mp1 to Mpn may be different, a switch is used to output a p-type bias current of different magnitudes based on the drains of Mp1 to Mpn in proportion. For example, the drain of Mp1 outputs ibp1 through a switch, and the drain of Mpn outputs ibpx through a switch. Of course, the situation is similar for Mn1 to Mnm, and will not be described in detail in the embodiments of this disclosure.
[0111] The current bias circuit provided in this embodiment can quickly establish critical nodes near the target value by adding multiple capacitors to the current bias circuit. Based on the charge sharing effect among the multiple capacitors, the current overshoot is reduced while speeding up the startup speed, thereby reducing power consumption.
[0112] Furthermore, the voltage establishment value can be adjusted by changing the size and ratio of the capacitor in the circuit, while providing a larger voltage space for the cascode MOS to ensure that it is in the saturation region. This ensures the robustness of the circuit when operating at low power supply voltage. Also, due to the voltage difference stored on the capacitor, the size of the resistor can be reduced in low power consumption scenarios.
[0113] This disclosure provides another current biasing circuit. Figure 4 A schematic diagram of a current biasing circuit according to an embodiment of the present disclosure is shown. (As shown) Figure 4 As shown, the current bias circuit includes a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) current mirror module 500 and an N-type MOSFET current mirror module 600.
[0114] The first terminal T1 of the P-type MOSFET current mirror module 500 is connected to the power supply voltage V. dd The second terminal T2 of the P-type MOSFET current mirror module 500 is connected to the third bias voltage vp_cas2, and the third terminal T3 of the P-type MOSFET current mirror module 500 is connected to the ground terminal V via the first target switch SW1. ss The fourth terminal T4 of the P-type MOSFET current mirror module 500 outputs a P-type bias current through the third switch group SW_P2;
[0115] The first terminal T5 of the N-type MOSFET current mirror module 600 is connected to the ground terminal V. ss The second terminal T6 of the N-type MOSFET current mirror module 600 is connected to the fourth bias voltage vn_cas2, and the third terminal T7 of the N-type MOSFET current mirror module 600 is connected to the power supply voltage V via the second target switch SW2. dd The fourth terminal T8 of the N-type MOSFET current mirror module 600 outputs an N-type bias current via the fourth switch group SW_N2, and the fifth terminal T9 of the N-type MOSFET current mirror module 600 is connected to the fifth terminal T of the P-type MOSFET current mirror module 600 via the third control switch ~SW1. 10 ;
[0116] Among them, the sixth terminal T of the P-type MOSFET current mirror module 500 11 The fourth control switch SW2, the third target switch SW3, and the second resistor Rb2 are connected to the ground terminal V. ss And the sixth terminal T of the P-type MOSFET current mirror module 500 11 The fourth control switch ~SW2 is also connected to the third terminal T3 of the P-type MOSFET current mirror module 500; the sixth terminal T of the N-type MOSFET current mirror module 600... 12 The third control switch ~SW1 is connected to the fifth terminal T9 of the N-type MOSFET current mirror module 600.
[0117] In one embodiment of this disclosure, both the P-type MOSFET current mirror module 500 and the N-type MOSFET current mirror module 600 are common-source, common-gate current mirrors. Specifically, as follows... Figure 4The diagram shows the structure of a P-type MOSFET current mirror module 500 and an N-type MOSFET current mirror module 600. The P-type MOSFET current mirror module 500 includes two sets of P-type MOSFETs, each set containing the same number of P-type MOSFETs. The N-type MOSFET current mirror module 600 includes two sets of N-type MOSFETs, each set containing the same number of N-type MOSFETs.
[0118] like Figure 4 As shown, in the P-type MOSFET current mirror module 500, the first group of P-type MOSFETs is denoted as Mpb3, and the other P-type MOSFETs are denoted as Mpb4, Mp1, ..., Mpn, respectively. The third parasitic capacitance of the first group of P-type MOSFETs is denoted as CP_pmos2. In the N-type MOSFET current mirror module 600, the first group of N-type MOSFETs is denoted as Mnb3, and the other N-type MOSFETs are denoted as Mn1, ..., Mnm, respectively. The fourth parasitic capacitance of the first group of N-type MOSFETs is denoted as CP_nmos2. The specific connection relationships can be referred to in the above embodiments. Figure 2 The description of the embodiments disclosed herein will not be repeated.
[0119] It should be noted that in practical applications, the number of MOSFETs included in the P-type MOSFET current mirror module and the N-type MOSFET current mirror module may be the same or different, and the specific number can be determined according to the usage situation. This disclosure does not limit this.
[0120] In one embodiment of this disclosure, the above Figure 4 It can be viewed as a cascode-type bias circuit. The cascode structure can significantly increase the impedance of the current source, thereby preventing the bias current from fluctuating due to the influence of the load voltage.
[0121] In one embodiment of this disclosure, such as Figure 5 The diagram shows the switching timing. When the current bias circuit is started, the first target switch SW1 and the second target switch SW2 switch from the closed state to the open state. At the same time, the third control switch ~SW1, the fourth control switch ~SW2, and the third target switch SW3 switch from the open state to the closed state. After a delay of a third preset time t3, the third switch group SW_P2 and the fourth switch group SW_N2 switch from the open state to the closed state.
[0122] It should be noted that, in the above-mentioned... Figure 4 For the current bias circuit shown to operate, both Mp1 and Mp2 need to be in the saturation region, which means the following conditions must be met:
[0123] V ds(Mp1) >V dsat(Mp1)
[0124] V ds(Mp2) >V dsat(Mp2)
[0125] Where Vds is the drain and source voltage of the field-effect transistor, and Vdas is the saturation drain-source voltage of the field-effect transistor.
[0126] Meanwhile, to ensure that Mp1 is in the saturation region, the third bias voltage vp_cas2 needs to be relatively low, thus making the vds of Mp1 larger. However, in this case, the vds of Mp2 will decrease. Conversely, if the vp_cas2 point is relatively high, the vds of Mp1 will decrease, and the vds of Mp2 will increase. Thus, the selection of vp_cas2 in the circuit is very strict.
[0127] In one embodiment of this disclosure, the current I of Mpb3 when the final steady state is reached can be expressed by the following formula:
[0128]
[0129] Where μ is the mobility of the field-effect transistor, and C ox Vd is the gate capacitance of the field-effect transistor (FET), W is the width of the FET, L is the length of the FET, Vdd is the power supply voltage, Vth is the threshold voltage of the FET, Vg is the gate voltage of Mpb3 in steady state, and R is the resistance of Rb2.
[0130] Based on the above current formula, the gate voltage Vg of Mpb3 can be obtained, and the unique current of this path can be determined.
[0131] It should be noted that the second branch, Mpb4, mirrors the current of Mpb3 and supplies it to Mnb3; that is, the current in Mnb3 is the same as the current in Mpb4. The mirror relationship of the current mirror satisfies the following formula:
[0132]
[0133] Where W is the width of the field-effect transistor and L is the length of the long-term transistor.
[0134] The subsequent current mirrors mirror the currents of Mpb3 and Mnb3 respectively, providing p-type bias currents ibp1 to ibpx and N-type bias currents ibn1 to ibny for the subsequent circuits. Of course, the p-type and N-type bias currents provided by the subsequent circuits can be obtained based on the mirror relationship formulas described above.
[0135] Thus, since the dimensions of Mp1 to Mpn may be different, a switch is used to output a p-type bias current of different magnitudes based on the drains of Mp1 to Mpn in proportion. For example, the drain of Mp1 outputs ibp1 through a switch, and the drain of Mpn outputs ibpx through a switch. Of course, the situation is similar for Mn1 to Mnm, and will not be described in detail in the embodiments of this disclosure.
[0136] The current bias circuit provided in this embodiment starts charging and discharging from a high current state for all current source transistors, thereby improving the startup speed of the bias circuit.
[0137] This disclosure provides yet another current biasing circuit. Figure 6 A schematic diagram of a current biasing circuit according to an embodiment of the present disclosure is shown. (As shown) Figure 6 As shown, the current bias circuit includes a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) module 700 and an N-type MOSFET module 800. The P-type MOSFET module 700 includes M P-type MOSFETs and a fifth parasitic capacitance CP_pmos3, and the N-type MOSFET module 800 includes S N-type MOSFETs and a sixth parasitic capacitance CP_nmos3. Wherein, M is an integer greater than 2, and S is an integer greater than or equal to 2.
[0138] The sources of the M P-type MOSFETs are all connected to the power supply voltage V. dd Furthermore, the gates of all M P-type MOSFETs are connected to and via the first parasitic capacitance to the power supply voltage V. dd The gate of the first P-type MOSFET among the M P-type MOSFETs is connected to the ground terminal V via the fourth target switch SW4. ss The drain of the first P-type MOSFET (denoted as Mpb5) among the M P-type MOSFETs is connected to the gate of the first P-type MOSFET via the fifth target switch SW4, and is connected to the ground terminal V via the third resistor Rb3 and the sixth target switch SW5. ss .
[0139] The sources of the S N-type MOSFETs are all connected to the ground terminal V. ss Furthermore, the gates of all S N-type MOSFETs are connected to the ground terminal V via the sixth parasitic capacitor CP_nmos3. ss The gate of the first N-type MOSFET (denoted as Mpb5) among the S N-type MOSFETs is connected to the power supply voltage V via the seventh target switch SW6. ddThe drain of the first N-type MOSFET among the S N-type MOSFETs is connected to the gate of the first N-type MOSFET via the eighth target switch ~SW5, and is also connected to the drain of the second P-type MOSFET (denoted as Mpb6) among the M P-type MOSFETs.
[0140] Among the M P-type MOSFETs, the drain of each P-type MOSFET other than the first P-type MOSFET and the second P-type MOSFET outputs a different P-type bias current through a corresponding switch; among the S N-type MOSFETs, the drain of each N-type MOSFET other than the first N-type MOSFET outputs a different N-type bias current through a corresponding switch.
[0141] It should be noted that in practical applications, the number of M P-type MOSFETs and S N-type MOSFETs can be the same or different, and the specific number can be determined according to the usage situation. This disclosure does not limit this.
[0142] In one embodiment of this disclosure, such as Figure 7 The diagram shows the switching timing. The fourth target switch SW4 and the seventh target switch SW6 switch from the closed state to the open state. At the same time, the fifth target switch ~SW4, the eighth target switch ~SW5, and the sixth target switch SW5 switch from the open state to the closed state. After a delay of the fourth preset time, the fifth switch group SW_P3 and the sixth switch group SW_N3 switch from the open state to the closed state.
[0143] Based on the above Figure 6 The current bias circuit shown assumes that the multiple switches in the P-type MOSFET module used to output the P-type bias current (ibp1, ..., ibpx) are denoted as switch group SW_P3, and the multiple switches in the N-type MOSFET module used to output the N-type bias current (ibn1, ..., ibny) are denoted as switch group SW_N3. Its working principle is explained as follows:
[0144] During the turn-off process, SW4 and SW6 are in the closed state. At this time, in the PMOS bias branch, switch SW4 pulls the gate of Mpb3 to ground; conversely, in the NMOS bias branch, switch SW6 pulls the gate of Mnb3 to the power supply. Since both the NMOS and PMOS current sources are in the on state at this time, the circuit relies on SW4, SW5, SW_P3, and SW_N3 to cut off the current in the circuit.
[0145] During the opening process, such as Figure 7The diagram shows the switching timing. When the current bias circuit starts, the fourth target switch SW4 and the seventh target switch SW6 switch from the closed state to the open state. Simultaneously, the fifth target switch ~SW4, the eighth target switch ~SW5, and the sixth target switch SW5 switch from the open state to the closed state. After a fourth preset time delay, switch groups SW_P3 and SW_N3 switch from the open state to the closed state. All current source transistors begin charging and discharging from a high current state, thereby greatly shortening the start-up time of the bias circuit and thus improving the start-up speed of the bias circuit.
[0146] Furthermore, after the enable is turned on, the bias circuit is in the startup process within time t, resulting in a large current overshoot. To control the bias circuit from being affected by the current overshoot, the above... Figure 6 Each switch in the middle follows the switching sequence described above. Figure 7 This operation allows for the delay in opening SW_P3 and SW_N3, thus avoiding periods of excessive current and reducing current overshoot.
[0147] In one embodiment of this disclosure, when the bias circuit has been activated and is in its final stable state, since ~SW4 is closed, the gate and drain of Mpb5 are connected together, i.e., in a diode connection configuration. At this point, the current in this path can be determined based on Mpb5 and Rb3. Assuming the gate voltage of Mpb1 is Vg, the following two equations can be obtained:
[0148]
[0149] Where μ is the mobility of the field-effect transistor, Cox is the gate capacitance of the field-effect transistor, W is the width of the field-effect transistor, L is the length of the field-effect transistor, Vdd is the power supply voltage, and Vth is the threshold voltage of the field-effect transistor.
[0150]
[0151] Among them, R b Let Rb3 be the resistance.
[0152] Based on the two formulas above, the gate voltage Vg of Mpb5 can be obtained, and the unique current of this path can be determined.
[0153] It should be noted that the second branch, Mpb6, mirrors the current of Mpb5 and supplies it to Mnb5; that is, the current in Mnb5 is the same as the current in Mpb6. The mirror relationship of the current mirror satisfies the following formula:
[0154]
[0155] Where I5 is the current of Mpb5, I6 is the current of Mpb6, W is the width of the field-effect transistor, and L is the length of the long-term transistor.
[0156] The subsequent current mirrors mirror the currents of Mpb5 and Mnb5 respectively, providing p-type bias currents ibp1 to ibpx and N-type bias currents ibn1 to ibny for the subsequent circuit. Of course, the p-type bias current and N-type bias current provided by the subsequent circuit can be obtained based on the mirror relationship formulas of the current mirrors mentioned above.
[0157] Thus, since the dimensions of Mp1 to Mpn may be different, different p-type bias currents can be output proportionally through a switch based on the drains of Mp1 to Mpn. For example, the drain of Mp1 outputs ibp1 through a switch, and the drain of Mpn outputs ibpx through a switch. Of course, the situation for Mn1 to Mnm is similar, and will not be described in detail in the embodiments of this disclosure.
[0158] The current bias circuit provided in this embodiment can shut down unused modules in circuits such as multi-stage analog-to-digital converters and amplifiers with strict power consumption requirements. When in use, the bias circuit starts to start up faster because all current source transistors start charging and discharging from a high current state.
[0159] like Figure 8 As shown in the illustration, an embodiment of this disclosure provides a circuit that includes an amplifier circuit and a current bias circuit; alternatively, the circuit includes a comparator circuit and a current bias circuit; or furthermore, the circuit includes an amplifier circuit, a comparator circuit, and a current bias circuit. In this circuit, a bias current is provided to modules such as amplifiers or comparators through the current bias circuit.
[0160] It should be noted that all the current biasing circuits provided in the embodiments of this disclosure can also provide current for commonly used analog circuits such as oscillators, phase-locked loops, and linear regulators that require fast startup. Additionally, Figure 8 Rb1 in the equation can be replaced with a current source Ib to achieve the same effect.
[0161] This disclosure provides a chip including the current bias circuit described in the above embodiments.
[0162] This disclosure provides an electronic device, characterized in that it includes the chip described above.
[0163] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.
Claims
1. A current biasing circuit, characterized in that, The current biasing circuit includes: The P-type MOSFET current mirror module has a first terminal connected to the power supply voltage, a second terminal connected to the first bias voltage, a third terminal connected to the P-type fast start module, and a fourth terminal outputting the P-type bias current through the first switch group. The P-type fast start module is connected to the fifth terminal of the P-type fast start module via a first control switch, and includes multiple capacitors and multiple switches. The P-type fast start module is used to accelerate the start-up speed of the P-type MOSFET current mirror module through the multiple capacitors and multiple switches. The N-type MOSFET current mirror module has its first terminal connected to the ground terminal, its second terminal connected to the second bias voltage, its third terminal connected to the N-type fast start module, its fourth terminal outputting the N-type bias current through the second switch group, and its fifth terminal connected to the sixth terminal of the P-type MOSFET current mirror module through the second control switch. The N-type fast start module is connected to the fifth terminal of the N-type MOSFET current mirror module via the second control switch, and includes multiple capacitors and multiple switches. The N-type fast start module is used to accelerate the start-up speed of the N-type MOSFET current mirror module through the multiple capacitors and multiple switches. The P-type fast-start module includes: a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch. Specifically: the first terminal of the first capacitor is connected to the power supply voltage via the third switch, connected to the third terminal of the P-type MOSFET current mirror module via the second switch, and connected to the ground terminal via the first switch; the second terminal of the first capacitor is connected to the ground terminal via the fourth switch, the fifth switch, and the sixth switch, connected to the ground terminal, connected to the first terminal of the second capacitor via the fifth switch, and connected to the fifth terminal of the P-type fast-start module via the fifth switch and the first control switch; the second terminal of the second capacitor is connected to the third terminal of the P-type MOSFET current mirror module. When the current bias circuit is started, the first switch and the third switch switch from the closed state to the open state, and after a first preset time delay, the fourth switch and the sixth switch switch switch from the closed state to the open state. At the same time, the first control switch, the second control switch, the first switch group and the second switch group switch from the open state to the closed state, and after a second preset time delay, the second switch and the fifth switch switch switch from the open state to the closed state.
2. The circuit according to claim 1, characterized in that, The fifth terminal of the P-type MOSFET current mirror module is also connected to the ground terminal via the first control switch and the first resistor.
3. The circuit according to claim 1, characterized in that, The N-type fast-start module includes: a third capacitor, a fourth capacitor, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, and a twelfth switch, wherein: The first terminal of the third capacitor is connected to the power supply voltage via the ninth switch, the fifth terminal of the N-type MOSFET current mirror module is connected to the power supply voltage via the eighth switch, and the seventh terminal is connected to the power supply voltage. The second terminal of the third capacitor is connected to the ground terminal via the tenth switch, and connected to the power supply voltage via the eleventh and twelfth switches. It is also connected to the first terminal of the fourth capacitor and the third terminal of the N-type MOSFET current mirror module via the eleventh switch. The second terminal of the fourth capacitor is connected to the fifth terminal of the N-type MOSFET current mirror module via the second control switch.
4. The circuit according to claim 3, characterized in that, When the current bias circuit is started, the seventh switch and the ninth switch switch from the closed state to the open state, and after a first preset time delay, the tenth switch and the twelfth switch switch from the closed state to the open state. At the same time, the first control switch, the second control switch, the first switch group and the second switch group switch from the open state to the closed state, and after a second preset time delay, the eighth switch and the eleventh switch switch from the open state to the closed state.
5. The circuit according to any one of claims 1-4, characterized in that, The P-type MOSFET current mirror module includes: The first group of P-type MOSFETs has its source connected to the first terminal of the P-type MOSFET current mirror module, and its gate connected to the first terminal of the P-type MOSFET current mirror module via a first parasitic capacitance. The gate of the first P-type MOSFET in the first group of P-type MOSFETs is connected to the third terminal of the P-type MOSFET current mirror module. The second group of P-type MOSFETs has its gates connected to the second terminal of the P-type MOSFET current mirror module, and the source of each P-type MOSFET in the second group is connected to the drain of a corresponding P-type MOSFET in the first group of P-type MOSFETs. The drain of the first P-type MOSFET in the second group of P-type MOSFETs is connected to the fifth terminal of the P-type MOSFET current mirror module, and the drain of the second P-type MOSFET in the second group of P-type MOSFETs is connected to the sixth terminal of the P-type MOSFET current mirror module. In this group of P-type MOSFETs, the drains of the other P-type MOSFETs (excluding the first and second P-type MOSFETs) are connected to the fourth terminal of the P-type MOSFET current mirror module, and different P-type bias currents are output through a corresponding switch in the first switch group.
6. The circuit according to any one of claims 1-4, characterized in that, The N-type MOSFET current mirror module includes: The first group of N-type MOSFETs has its sources connected to the first terminal of the N-type MOSFET current mirror module, and its gates connected to the first terminal of the N-type MOSFET current mirror module via a second parasitic capacitance. The gate of the first N-type MOSFET in the first group of N-type MOSFETs is connected to the third terminal of the N-type MOSFET current mirror module. The second group of N-type MOSFETs has its gates connected to the second terminal of the N-type MOSFET current mirror module, and the source of each N-type MOSFET in the second group is connected to the drain of a corresponding N-type MOSFET in the first group of N-type MOSFETs. The drain of the first N-type MOSFET in the second group of N-type MOSFETs is connected to the fifth terminal of the N-type MOSFET current mirror module. In this group of N-type MOSFETs, the drains of the other N-type MOSFETs (excluding the first N-type MOSFET) are connected to the fourth terminal of the N-type MOSFET current mirror module, and different N-type bias currents are output through a corresponding switch in the second group of switches.
7. A current biasing circuit, characterized in that, The current biasing circuit includes: The P-type MOSFET current mirror module has a first terminal connected to the power supply voltage, a second terminal connected to the third bias voltage, a third terminal connected to the ground terminal via a first target switch, and a fourth terminal outputting P-type bias current via a third switch group. The N-type MOSFET current mirror module has a first terminal connected to the ground terminal, a second terminal connected to the fourth bias voltage, a third terminal connected to the power supply voltage via the second target switch, a fourth terminal outputting N-type bias current via the fourth switch group, and a fifth terminal connected to the fifth terminal of the P-type MOSFET current mirror module via the third control switch. The sixth terminal of the P-type MOSFET current mirror module is connected to the ground terminal via the fourth control switch, the third target switch, and the second resistor, and is connected to the third terminal of the P-type MOSFET current mirror module via the fourth control switch; the sixth terminal of the N-type MOSFET current mirror module is connected to the fifth terminal of the N-type MOSFET current mirror module via the third control switch.
8. The circuit according to claim 7, characterized in that, When the current bias circuit is started, the first target switch and the second target switch switch switch from the closed state to the open state. At the same time, the third control switch, the fourth control switch and the third target switch switch switch from the open state to the closed state. After a delay of a third preset time, the third switch group and the fourth switch group switch from the open state to the closed state.
9. The circuit according to claim 7 or 8, characterized in that, Both the P-type MOSFET current mirror module and the N-type MOSFET current mirror module are common-source, common-gate current mirrors.
10. A current biasing circuit, characterized in that, The current bias circuit includes a P-type MOSFET module and an N-type MOSFET module. The P-type MOSFET module includes M P-type MOSFETs and a fifth parasitic capacitor, and the N-type MOSFET module includes S N-type MOSFETs and a sixth parasitic capacitor. Wherein, M is an integer greater than 2, and S is an integer greater than or equal to 2. The sources of all M P-type MOSFETs are connected to the power supply voltage, and the gates of all M P-type MOSFETs are connected to the power supply voltage via the first parasitic capacitance. The gate of the first P-type MOSFET is connected to the ground terminal via the fourth target switch, and the drain is connected to the gate of the first P-type MOSFET via the fifth target switch, and connected to the ground terminal via the third resistor and the sixth target switch. The sources of all S N-type MOSFETs are connected to the ground terminal, and the gates of all S N-type MOSFETs are connected to the ground terminal via the sixth parasitic capacitance. The gate of the first N-type MOSFET among the S N-type MOSFETs is connected to the power supply voltage via the seventh target switch, and the drain is connected to the gate of the first N-type MOSFET via the eighth target switch, and is also connected to the drain of the second P-type MOSFET among the M P-type MOSFETs. Among the M P-type MOSFETs, the drain of each P-type MOSFET other than the first P-type MOSFET and the second P-type MOSFET outputs a different P-type bias current through the corresponding switch in the fifth switch group; among the S N-type MOSFETs, the drain of each N-type MOSFET other than the first N-type MOSFET outputs a different N-type bias current through the corresponding switch in the sixth switch group.
11. The circuit according to claim 10, characterized in that, When the current bias circuit is started, the fourth target switch and the seventh target switch switch switch from the closed state to the open state. At the same time, the fifth target switch, the eighth target switch and the sixth target switch switch switch from the open state to the closed state. After a delay of a fourth preset time, the fifth switch group and the sixth switch group switch from the open state to the closed state.
12. A chip, characterized in that, Includes the current bias circuit as described in any one of claims 1 to 11.
13. An electronic device, characterized in that, Including the chip as described in claim 12.