A parsing method, parsing device, electronic device and computer storage medium

Abstract

The embodiments of the present disclosure provide a parsing method, a parsing device, an electronic device and a computer storage medium, the method comprising: during the parsing process of a target repository, determining the physical position relationship of the logical rows by performing a row hammer operation on the logical rows in the target repository; and repeatedly performing the step of determining the physical position relationship of the logical rows by performing a row hammer operation on the logical rows in the target repository until all the parsing of the plurality of logical rows is completed; determining a mapping relationship according to a linked list, the mapping relationship being used to record the physical position relationship of the plurality of logical rows; wherein determining the physical position relationship of the logical rows by performing a row hammer operation on the logical rows in the target repository comprises: obtaining the to-be-parsed logical rows of the target repository, the target repository comprising a plurality of logical rows; performing a row hammer operation on the to-be-parsed logical rows until at least one flipped logical row is obtained; and writing the at least one flipped logical row into the linked list.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a parsing method, a parsing device, an electronic device, and a computer storage medium. Background Art

[0002] In the Dynamic Random Access Memory (DRAM), there may be a DRAM logical address and a DRAM physical address. The DRAM logical address is the logical address used inside the DRAM, and the DRAM physical address is the physical address used inside the DRAM. Currently, the DRAM logical address can be obtained by converting the physical address of the operating system, and the DRAM logical address is converted to obtain the actual arrangement of the DRAM memory unit. Summary of the invention

[0003] The present disclosure provides a parsing method, a parsing device, an electronic device and a computer storage medium, which can correctly parse the physical position relationship of the logical rows of a memory, thereby realizing the conversion of the logical rows of the memory into the physical rows.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a parsing method, the method comprising:

[0006] During the parsing process of the target storage library, determining the physical position relationship of the logical rows in the target storage library by performing a row hammering operation on the logical rows;

[0007] Repeating the step of determining the physical position relationship of the logic rows by performing a row hammering operation on the logic rows in the target storage repository until all the plurality of logic rows are parsed;

[0008] Determine a mapping relationship according to the linked list, wherein the mapping relationship is used to record the physical position relationship of the plurality of logical rows;

[0009] The determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target storage library includes:

[0010] Obtaining a logic row to be parsed of the target repository, wherein the target repository includes a plurality of logic rows;

[0011] Performing a row hammering operation on the to-be-parsed logic row until at least one flipped logic row is obtained;

[0012] The at least one flipped logical row is written into the linked list.

[0013] In some embodiments, the method further comprises:

[0014] Obtaining the number of logical rows of the target repository;

[0015] The linked list structure of the linked list is determined according to the number of logical rows of the target storage library; wherein the linked list includes a plurality of nodes, and the number of the plurality of nodes is the same as the number of logical rows of the target storage library.

[0016] In some embodiments, writing the at least one flipped logic row into the linked list comprises:

[0017] If the at least one flip logic line only includes a first flip logic line, writing the first flip logic line into the linked list using a first parsing strategy;

[0018] If the at least one inverted logic row includes at least a first inverted logic row and a second inverted logic row, the first inverted logic row and the second inverted logic row are written into the linked list using a second parsing strategy.

[0019] In some embodiments, writing the first flip logic line into the linked list using a first parsing strategy includes:

[0020] If the first flipped logic row does not exist in the linked list, determining a node corresponding to the to-be-parsed logic row in the linked list as a to-be-parsed node;

[0021] Determine whether the successor node of the node to be parsed is empty;

[0022] If the successor node of the node to be resolved is empty, writing the row address of the first flip logic row into the successor node of the node to be resolved;

[0023] If the successor node of the node to be resolved is not empty, the row address of the first flip logic row is written into the predecessor node of the node to be resolved.

[0024] In some embodiments, the first flip logic row and the second flip logic row are two logic rows with the largest flip times among the at least one flip logic row, and the flip times of the first flip logic row are greater than or equal to the flip times of the second flip logic row;

[0025] Accordingly, the step of writing the first flip logic line and the second flip logic line into the linked list by using the second parsing strategy includes:

[0026] Determine whether the first flip logic row exists in the linked list;

[0027] If the first flip logic line does not exist in the linked list, writing the first flip logic line into the linked list;

[0028] If the first flip logic row exists in the linked list, determining whether the second flip logic row exists in the linked list;

[0029] If the second inverted logic line does not exist in the linked list, the second inverted logic line is written into the linked list.

[0030] In some embodiments, writing the first flip logic row into the linked list includes:

[0031] Determine the node corresponding to the to-be-parsed logic row in the linked list as the to-be-parsed node;

[0032] Determine whether the successor node of the node to be parsed is empty;

[0033] If the successor node of the node to be resolved is empty, writing the row address of the first flip logic row into the successor node of the node to be resolved;

[0034] If the successor node of the node to be resolved is not empty, the row address of the first flip logic row is written into the predecessor node of the node to be resolved.

[0035] In some embodiments, writing the second flip logic row into the linked list includes:

[0036] Determine the node corresponding to the to-be-parsed logic row in the linked list as the to-be-parsed node;

[0037] Determine whether the successor node of the node to be parsed is empty;

[0038] If the successor node of the node to be resolved is empty, writing the row address of the second flip logic row into the successor node of the node to be resolved;

[0039] If the successor node of the node to be resolved is not empty, the row address of the second flip logic row is written into the predecessor node of the node to be resolved.

[0040] In some embodiments, when the at least one flip logic row only includes a first flip logic row, and the first flip logic row does not exist in the linked list, the method further includes:

[0041] Counting the number of hammering operations performed on the logic line to be parsed;

[0042] Determine whether the hammering times is greater than or equal to a preset threshold; wherein the preset threshold is the maximum hammering times for performing a row hammering operation on the logic row to be analyzed;

[0043] If the hammering number is less than the preset threshold, continue to perform the row hammering operation on the to-be-analyzed logic row until at least one flipped logic row is obtained;

[0044] If the hammering times are greater than or equal to the preset threshold, the process returns to the step of obtaining the to-be-parsed logical line of the target storage library.

[0045] In some embodiments, obtaining the to-be-parsed logic line of the target storage repository includes:

[0046] The top element of the stack is popped from the preset stack to obtain the to-be-parsed logical line of the target storage library; wherein the top element of the stack represents the to-be-parsed logical line of the target storage library.

[0047] In some embodiments, when the to-be-parsed logic line is the first to-be-parsed logic line in the target storage library, before popping the top element from the preset stack to obtain the to-be-parsed logic line of the target storage library, the method further includes:

[0048] After the preset stack is initialized, a logic line is randomly selected from the target storage library as a logic line to be parsed, and the logic line to be parsed is pushed onto the top of the preset stack.

[0049] In some embodiments, in the process of writing the at least one flipped logic line into a linked list, the method further comprises:

[0050] The flip logic line written into the linked list is pushed into the top of the preset stack.

[0051] In some embodiments, before parsing the target repository, the method further includes:

[0052] Preset data are written into the plurality of logic rows respectively; wherein the preset data is used to determine whether the logic row is flipped.

[0053] In some embodiments, determining the mapping relationship according to the linked list includes:

[0054] Set the output file;

[0055] The linked list is traversed to the output file to obtain a target file of the target storage library; wherein the target file stores the physical position relationship of multiple logical rows of the mapping relationship record.

[0056] In some embodiments, the method is applied to a memory, the memory includes at least one storage repository, the target storage repository is any one of the at least one storage repository; the method further includes:

[0057] Determining whether all of the at least one repository has completed parsing;

[0058] If the at least one repository has completed parsing, then save the target files of all the repositories;

[0059] If there are unresolved repositories in the at least one repository, a target repository is determined from the unresolved repository, and the step of determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target repository is returned to execution until all of the at least one repository is resolved.

[0060] In a second aspect, an embodiment of the present disclosure provides a parsing device, the parsing device comprising:

[0061] A parsing unit is configured to determine the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target repository during the parsing process of the target repository; and repeatedly perform the step of determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target repository until all the multiple logical rows included in the target repository are parsed;

[0062] a determining unit, configured to determine a mapping relationship according to the linked list, wherein the mapping relationship is used to record the physical position relationship of the plurality of logical rows;

[0063] The analysis unit includes an acquisition unit, a hammer unit and a writing unit; wherein,

[0064] The acquisition unit is configured to acquire a to-be-parsed logical line of the target storage repository, wherein the target storage repository includes a plurality of logical lines;

[0065] The hammering unit is configured to perform a row hammering operation on the to-be-parsed logic row until at least one flipped logic row is obtained;

[0066] The writing unit is configured to write the at least one flipped logic row into the linked list.

[0067] In a third aspect, an embodiment of the present disclosure provides an electronic device, the electronic device comprising a memory and a processor, wherein:

[0068] A memory for storing a computer program that can be executed on the processor;

[0069] A processor is used to execute the parsing method as described in any one of the first aspects when running the computer program.

[0070] In a fourth aspect, an embodiment of the present disclosure provides a computer storage medium storing a computer program, wherein the computer program, when executed by at least one processor, implements the parsing method as described in any one of the first aspects.

[0071] The embodiments of the present disclosure provide a parsing method, a parsing device, an electronic device and a computer storage medium. In the process of parsing a target storage library, the physical position relationship of the logical rows is determined by performing a row hammering operation on the logical rows in the target storage library; and the step of determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target storage library is repeated until all the multiple logical rows are parsed; a mapping relationship is determined according to a linked list, and the mapping relationship is used to record the physical position relationship of the multiple logical rows; wherein, the physical position relationship of the logical rows is determined by performing a row hammering operation on the logical rows in the target storage library, including: obtaining the to-be-parsed logical rows of the target storage library, wherein the target storage library includes multiple logical rows; performing a row hammering operation on the to-be-parsed logical rows until at least one flipped logical row is obtained; and writing at least one flipped logical row into a linked list; thus, based on the characteristic that the row hammering operation will flip the physically adjacent rows of the hammered rows, the physical position relationship of the logical rows of the memory can be obtained by performing a row hammering operation on the to-be-parsed logical rows and writing the obtained flipped logical rows into the linked list, thereby achieving the correct parsing of the physical position relationship of the logical rows of the memory, and also achieving the conversion of the logical rows of the memory into the physical rows. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 A schematic diagram of address conversion of an operating system and DRAM provided in an embodiment of the present disclosure;

[0073] Figure 2 A schematic diagram of the correspondence between a DRAM logical row and a DRAM physical row provided in an embodiment of the present disclosure;

[0074] Figure 3 A schematic diagram of a process of analyzing the method provided in the embodiment of the present disclosure Figure 1 ;

[0075] Figure 4 A schematic diagram of a DRAM memory row refresh provided by an embodiment of the present disclosure;

[0076] Figure 5 A schematic diagram of the positional relationship between an aggressor row and a victim row provided in an embodiment of the present disclosure Figure 1 ;

[0077] Figure 6A schematic diagram of the positional relationship between an aggressor row and a victim row provided in an embodiment of the present disclosure Figure 2 ;

[0078] Figure 7 A detailed process diagram of an analysis method provided in the embodiment of the present disclosure Figure 1 ;

[0079] Figure 8 A detailed process diagram of an analysis method provided in the embodiment of the present disclosure Figure 2 ;

[0080] Fig. 9 A schematic diagram of the structure of a linked list provided in an embodiment of the present disclosure;

[0081] Fig.10 A schematic diagram of an element push / pop process provided by an embodiment of the present disclosure;

[0082] Fig.11 A schematic diagram of a process of analyzing the method provided in the embodiment of the present disclosure Figure 2 ;

[0083] Fig.12 A detailed process diagram of an analysis method provided in the embodiment of the present disclosure Figure 3 ;

[0084] Fig.13 A detailed process diagram of an analysis method provided in the embodiment of the present disclosure Figure 4 ;

[0085] Fig.14 A detailed process diagram of an analysis method provided in the embodiment of the present disclosure Figure 5 ;

[0086] Fig.15 A schematic diagram of the composition structure of an analysis device provided in an embodiment of the present disclosure;

[0087] Fig.16 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0088] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

[0089] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the present disclosure and are not intended to limit the present disclosure.

[0090] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0091] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0092] In computer addressing, the dynamic random access memory logical address (DRAM logical address) is the logical address used inside the DRAM, not the actual arrangement of DRAM memory cells; while the DRAM physical address (DRAM physical address) is the address used inside the DRAM, that is, the actual arrangement inside the DRAM.

[0093] It should be understood that there are four different computer addressing addresses: operating system virtual address, operating system physical address, DRAM logical address and DRAM physical address. Figure 1 As shown, it shows a schematic diagram of address conversion of an operating system and DRAM provided in an embodiment of the present disclosure.

[0094] like Figure 1 As shown, in the operating system, there may be an operating system virtual address and an operating system physical address. Among them, the operating system virtual address is the address directly allocated and used by the operating system, not the actual address of the memory unit; the operating system physical address is the actual address of the memory unit, and the operating system virtual address can be converted to the operating system physical address, and the conversion method is public.

[0095] like Figure 1As shown, in DRAM, DRAM logical address and DRAM physical address can be included. Among them, DRAM logical address is the logical address used inside DRAM, not the actual arrangement of DRAM memory cells; DRAM physical address is the address used inside DRAM, which represents the actual arrangement inside DRAM. Here, between the operating system and DRAM, the operating system physical address can be converted to the DRAM logical address; and between the DRAM logical address and the DRAM physical address, the DRAM logical address can be converted to the DRAM physical address, but the conversion method is unknown.

[0096] In addition, a DRAM logical row (abbreviated as logical row) specifically refers to a row obtained by a DRAM logical address, and a DRAM physical row (abbreviated as physical row) specifically refers to a row obtained by a DRAM physical address. DRAM logical rows and DRAM physical rows are one-to-one corresponding, that is, there is a certain mapping, but not necessarily one-to-one mapping, that is, two rows adjacent to logical rows are not necessarily two rows adjacent to physical rows.

[0097] That is, the DRAM logical address can be converted into the DRAM physical address, but the conversion method is unknown, resulting in an uncertain mapping relationship between the DRAM logical row and the DRAM physical row.

[0098] For example, see Figure 2 , which shows a schematic diagram of the correspondence between a DRAM logical row and a DRAM physical row provided by an embodiment of the present disclosure. Figure 2 As shown, there are DRAM logical rows 0, 1, 2...n in the DRAM logical address, and there are DRAM logical rows 0, 1, 2...n in the DRAM physical address. Among them, logical row 0 corresponds to physical row 1, logical row 1 corresponds to physical row 2, logical row 2 corresponds to physical row 0, and logical row n corresponds to physical row m; it can be seen that DRAM logical row 0 does not necessarily correspond to DRAM physical row 0.

[0099] Currently, technicians can study the circuit design or layout to infer the actual DRAM physical address from the DRAM logical address. However, in general, the complete circuit layout is often difficult to obtain, and due to the variability of the layout design, this method has many problems such as low efficiency and easy errors. It can be seen that there is currently no method that can efficiently decode the relationship between DRAM logical rows and DRAM physical rows.

[0100] Based on this, an embodiment of the present disclosure provides a parsing method, the basic idea of ​​which is: in the parsing process of a target storage library, the physical position relationship of the logical rows is determined by performing a row hammer operation on the logical rows in the target storage library; wherein, the physical position relationship of the logical rows is determined by performing a row hammer operation on the logical rows in the target storage library, including: obtaining the to-be-parsed logical rows of the target storage library, wherein the target storage library includes multiple logical rows; performing a row hammer operation on the to-be-parsed logical rows until at least one flipped logical row is obtained; writing at least one flipped logical row into a linked list; repeatedly performing the steps of determining the physical position relationship of the logical rows by performing a row hammer operation on the logical rows in the target storage library until all the multiple logical rows are parsed; determining a mapping relationship according to the linked list, the mapping relationship being used to record the physical position relationship of the multiple logical rows; in this way, based on the characteristic that the row hammer operation will cause the physically adjacent rows of the hammered rows to flip, by performing a row hammer operation on the to-be-parsed logical rows and writing the obtained flipped logical rows into the linked list, the physical position relationship of the logical rows of the memory can be obtained, thereby achieving correct parsing of the physical position relationship of the logical rows of the memory, thereby achieving conversion of the logical rows of the memory to the physical rows.

[0101] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0102] In one embodiment of the present disclosure, see Figure 3 , which shows a schematic diagram of a process of an analysis method provided by an embodiment of the present disclosure Figure 1 .like Figure 3 As shown, the method may include:

[0103] S301. During the parsing process of the target storage library, the physical position relationship of the logical rows in the target storage library is determined by performing a row hammering operation on the logical rows in the target storage library.

[0104] S302: Repeat the step of determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target storage library until all the multiple logical rows are parsed.

[0105] S303: Determine a mapping relationship according to the linked list, where the mapping relationship is used to record the physical position relationship of multiple logical rows.

[0106] It should be noted that the parsing method provided in the embodiments of the present disclosure can be applied to a parsing device, or an electronic device integrated with the parsing device. Here, the electronic device can be implemented in various forms, for example, the electronic device can be a device with storage function such as a computer, a smart phone, a tablet computer, a laptop computer, a PDA, a navigation device, a wearable device, a server, a memory, etc., without specific limitation.

[0107] It should also be noted that, taking a memory as an example, the parsing method provided in the embodiment of the present disclosure is mainly applied to the parsing of the logical address to the physical address of the memory (such as DRAM) to achieve decoding of the logical row of the memory to the physical row. The memory may include at least one bank, and the target bank is any one of the at least one bank. Each bank in the memory is parsed according to the parsing method provided in the embodiment of the present disclosure, so as to obtain the parsing result of the memory from the logical address to the physical address.

[0108] In the disclosed embodiment, for the parsing process of the target storage library, the physical position relationship of the logical lines in the storage library at the physical address can be determined by performing a row hammering operation on the logical lines to be parsed in the target storage library. The process is repeated until all the multiple logical lines in the target storage library are parsed. At this time, the position relationship of all the logical lines in the target storage library is recorded in the linked list, so that the mapping relationship can be determined according to the linked list, and the mapping relationship records the physical position relationship of the logical lines.

[0109] It should be noted that ACT-PRE (Active-Precharge) can refer to an access operation of a DRAM physical row, including row activation (Row activation, ACT), read (READ) or write (WRITE), precharge (Precharge, PRE) and other operations. Figure 4 , which shows a schematic diagram of a memory row refresh of a DRAM provided in an embodiment of the present disclosure.

[0110] like Figure 4 As shown, due to its structural principle, DRAM has the phenomenon of capacitor leakage, and the capacitor needs to be maintained for a period of time t REFW Refresh all memory rows within 1 second. REFW stands for refresh window. At high temperature, the refresh time is 32ms (milliseconds), at medium temperature, the refresh time is 64ms, and at low temperature, the refresh time is 128ms. n stands for one or more ACT-PRE command combinations.

[0111] Row hammer is a DRAM vulnerability. When a DRAM physical address row is continuously ACT-PRE (i.e. hammered) during a refresh cycle, the DRAM physical address adjacent rows of the row will have bit flips (referred to as flips). The hammered row is usually called the aggressor row, and its adjacent rows are called the victim row.

[0112] See also Figure 5 , which shows a schematic diagram of the positional relationship between an aggressor row and a victim row provided by an embodiment of the present disclosure Figure 1 .like Figure 5 As shown, hammering the aggressor row causes its adjacent +1 victim row and -1 victim row to flip.

[0113] Additionally, hammering an aggressor row may cause multiple adjacent victim rows to flip. Figure 6 , which shows a schematic diagram of the positional relationship between an aggressor row and a victim row provided by an embodiment of the present disclosure Figure 2 .like Figure 6 As shown, hammering the aggressor row causes its adjacent +1 victim row, -1 victim row, +2 victim row, and -2 victim row to flip.

[0114] Combination Figure 5 and Figure 6 , Figure 5 For single-row hammering, the attacking aggressor row is row 1, which may cause two adjacent victim rows, namely, row +1 and row -1, to flip; if the two adjacent victim rows with a distance of 2 from the aggressor row are both flipped, namely, row +2 and row -2 are both bit flipped, then row +1 and row -1 must be flipped, and the number of flips of row ±1 must be more than the number of flips of row ±2.

[0115] Based on the characteristics of row hammering, that is, when a row hammering operation is performed on a row, its adjacent row at the physical address will flip, the embodiment of the present disclosure proposes a method for decoding the relationship between DRAM logical rows and DRAM physical rows based on row hammering, so as to parse DRAM logical rows to obtain DRAM physical rows. That is, the physical position relationship of the logical rows is determined by performing a row hammering operation on the logical rows of the target storage library. Since a target storage library usually includes multiple logical rows, the embodiment of the present disclosure repeatedly performs the step of determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target storage library until all the multiple logical rows of the target storage library are parsed.

[0116] In some embodiments, see Figure 7 , which shows a detailed flow diagram of a parsing method provided by an embodiment of the present disclosure Figure 1 , Figure 7 Yes Figure 3 A detailed description of Figure 3 Step S301 in includes Figure 7 Steps S3011 to S3013 in FIG. Figure 7 As shown, the detailed process may include:

[0117] S301: During the parsing process of the target repository, execute:

[0118] S3011. Obtain the logic line to be parsed of the target repository.

[0119] S3012: Perform a row hammering operation on the logic row to be parsed until at least one flipped logic row is obtained.

[0120] S3013. Write at least one flipped logic row into the linked list.

[0121] S302. Repeat steps S3011 to S3013 until all the logic lines are parsed.

[0122] S303: Determine a mapping relationship according to the linked list, where the mapping relationship is used to record the physical position relationship of multiple logical rows.

[0123] It should be noted that if Figure 7 As shown, the parsing method provided by the embodiment of the present disclosure includes steps S301 to S303. For step S301, determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target storage library may specifically include steps S3011 to S3013.

[0124] It should also be noted that the target storage library may include multiple logical rows. First, the logical rows to be parsed of the target storage library are determined, and then row hammering operations are performed on the logical rows in the aforementioned manner until at least one flipped logical row is obtained, and at least one flipped logical row is written into a linked list, so that the physical position relationship between the logical rows to be parsed and the flipped logical rows can be obtained, thereby completing the parsing of the logical rows to be parsed.

[0125] It should also be noted that the embodiments of the present disclosure may use a linked list to store the physical position relationship of the logical rows. Figure 8 , which shows a detailed flow diagram of a parsing method provided by an embodiment of the present disclosure Figure 2 , Figure 8 is Figure 7 On the basis of Figure 3 For further details. Figure 8 As shown, the detailed process may include:

[0126] S801. Obtain the number of logical rows in the target storage repository.

[0127] S802: Determine the linked list structure of the linked list according to the number of logical rows of the target storage library.

[0128] S301: During the parsing process of the target repository, execute:

[0129] S3011. Obtain the logic line to be parsed of the target repository.

[0130] S3012: Perform a row hammering operation on the logic row to be parsed until at least one flipped logic row is obtained.

[0131] S3013. Write at least one flipped logic row into the linked list.

[0132] S302. Repeat steps S3011 to S3013 until all the logic lines are parsed.

[0133] S303: Determine a mapping relationship according to the linked list, where the mapping relationship is used to record the physical position relationship of multiple logical rows.

[0134] It should be noted that when parsing the target repository, the number of logical rows of the target repository is first obtained, and then the linked list structure of the linked list is determined according to the number of logical rows of the target repository, that is, the linked list is initialized first. The linked list includes multiple nodes, and the number of multiple nodes is the same as the number of logical rows of the target repository. Then, steps S301 to S302 are executed to complete the parsing of the target repository.

[0135] See also Fig. 9 , which shows a schematic diagram of the structure of a linked list provided by an embodiment of the present disclosure. Each element in the linked list is called a node, and the linked list is composed of a series of nodes. Fig. 9 As shown, it shows a linked list including M nodes (node ​​1, node 2, ..., node M), wherein the linked list includes multiple nodes, and the number of multiple nodes is the same as the number of logical rows of the target storage library. Each node includes three parts: a data field for storing data elements (here the row address of the DRAM logical row is stored), a pointer field for storing the address of the previous node, called the predecessor, and a pointer field for storing the address of the next node, called the successor. The content stored in the data field of the node can be dynamically generated at runtime. The data field of each node in the entire linked list and the order of the node in the linked list are the mapping relationship between the DRAM logical row and the DRAM physical row.

[0136] When determining the linked list structure of the linked list, the disclosed embodiment is determined according to the number of logical rows of the target storage library. The number of nodes of the linked list is the number of logical rows of the target storage library, and the data field of each node is used to store the row address of the logical row. In other words, after the linked list structure is determined, the order of each node on the linked list is fixed, and through subsequent steps, the row address of the logical row is written into the data field of the corresponding node, so that the physical position relationship of the logical row is recorded through the linked list.

[0137] It should also be noted that the embodiments of the present disclosure can store the logic lines that need to be parsed by presetting a stack. A stack, also known as a stack, is a last-in-first-out linear table data structure with limited operations. Its addition and deletion operations can only be performed at one end, which is called the top of the stack. Relatively speaking, the other end is called the bottom of the stack. Inserting a new element into a stack is also called pushing, pushing or pushing, that is, putting the new element on top of the top element of the stack to make it the new top element of the stack; deleting an element from a stack is also called making a stack or popping a stack, that is, deleting the top element of the stack to make the adjacent element the new top element of the stack.

[0138] For example, see Fig.10 , which shows a schematic diagram of an element stacking / popping process provided by an embodiment of the present disclosure. Fig.10 As shown, in Fig.10 In the left figure, the stack is empty, and then elements 1, 2, and 3 are pushed onto the top of the stack, so that from the bottom to the top of the stack, the elements are 1, 2, and 3, respectively. Fig.10 As shown in the middle figure, at this time, element 1 is the bottom element of the stack and element 3 is the top element of the stack; the top element of the stack is popped, that is, element 3 is popped. After the top element 3 is popped, element 2 becomes the new top element of the stack, as shown in Fig.10 as shown in the figure on the right.

[0139] When the preset stack is used to store the logic lines to be parsed, in some embodiments, obtaining the logic lines to be parsed of the target storage library may include:

[0140] The top element of the stack is popped from the preset stack to obtain the to-be-parsed logical line of the target storage library; wherein the top element of the stack represents the to-be-parsed logical line of the target storage library.

[0141] It should be noted that when obtaining the to-be-parsed logical line of the target storage library, the top element of the preset stack is popped. At this time, the popped element is the to-be-parsed logical line of the target storage library.

[0142] Furthermore, in some embodiments, when the to-be-parsed logical line is the first to-be-parsed logical line in the target storage library, before popping the top element from the preset stack to obtain the to-be-parsed logical line of the target storage library, the method may further include:

[0143] After the preset stack is initialized, a logic line is randomly selected from the target storage library as the logic line to be parsed, and the logic line to be parsed is pushed to the top of the preset stack.

[0144] It should be noted that, for the first parsed logic line in the target storage library, the method of determining the logic line to be parsed is as follows: after the preset stack is initialized, a logic line is randomly selected from the target storage library as the logic line to be parsed, and the randomly selected logic line to be parsed is pushed to the top of the preset stack. Then, during the parsing process of the target storage library, the logic line to be parsed is popped from the preset stack and subsequent operations are performed.

[0145] It should also be noted that, for the case where the to-be-parsed logical line is not the first to be parsed logical line in the target storage repository, in some embodiments, in the process of writing at least one flipped logical line into the linked list, the method may further include:

[0146] Push the flip logic line written into the linked list onto the top of the preset stack.

[0147] It should be noted that, in the embodiment of the present disclosure, when writing the flip logic line into the linked list, the flip logic line written into the linked list is also pushed into the top of the preset stack. In this way, each time a flip logic line is written into the linked list, the flip logic line is added to the preset stack, so that when parsing the next logic line, it is only necessary to pop the top element from the preset stack to obtain the logic line to be parsed, and it is no longer necessary to select from multiple logic lines in the target storage library, thereby achieving parsing of the logic lines in the target storage library.

[0148] In this way, the embodiment of the present disclosure can obtain the logic line to be parsed based on the preset stack, and after obtaining the logic line to be parsed, perform a row hammering operation on the logic line to be parsed until at least one flipped logic line is obtained.

[0149] That is, when hammering the logical row to be parsed, it is not necessarily possible that each hammering can cause the adjacent row of the logical row to be parsed to flip. Therefore, after the row hammering operation is performed on the logical row to be parsed, if the number of flipped logical rows is zero, the row hammering operation is continued to be performed on the logical row to be parsed until at least one flipped logical row is obtained. The at least one flipped logical row is a logical row adjacent to the logical row to be parsed in terms of physical address.

[0150] It can be understood that when performing the row hammering operation, the logic row to be analyzed is the aforementioned aggressor row, and the flipped logic row is the aforementioned victim row.

[0151] In addition, the embodiment of the present disclosure also provides a method for checking whether a logical line is flipped. In some embodiments, before parsing the target storage library, the method may further include:

[0152] Preset data are written into a plurality of logic rows respectively; wherein the preset data is used to determine whether a flip occurs in the logic row.

[0153] It should be noted that, before parsing the target storage library, preset data is written to multiple logical rows of the target storage library in advance to determine whether the logical row is flipped after the row hammering operation is performed. Here, the preset data is usually some easy-to-detect data values. Before the row hammering operation is performed, the preset data is written to the logical row. If the logical row is bit-flipped, the value of the preset data will change. It can be verified whether the preset data of other logical rows except the logical row to be parsed are equal before and after the row hammering operation is performed on the logical row to be parsed, so as to verify whether these logical rows are bit-flipped.

[0154] In this way, by writing preset data in the logic row in advance, it is possible to accurately check whether the logic row is flipped, so that when determining the physical position relationship of the logic row, the conversion result is accurate.

[0155] After obtaining at least one flipped logic row, writing at least one flipped logic row into a linked list.

[0156] In some embodiments, writing at least one flip logic line into a linked list may include:

[0157] If the at least one flip logic line includes only the first flip logic line, writing the first flip logic line into the linked list using the first parsing strategy;

[0158] If the at least one inverted logic row includes at least a first inverted logic row and a second inverted logic row, the first inverted logic row and the second inverted logic row are written into the linked list using a second parsing strategy.

[0159] It should be noted that, among the at least one flip logic row obtained by performing the row hammering operation on the logic row to be parsed, the number of the at least one flip logic row may be one, or may be greater than one. When the number of the at least one flip logic row is one, that is, only one first flip logic row is included, the first parsing strategy is used to write the first flip logic row into the linked list.

[0160] When the number of at least one flip logic line is greater than one, namely, including at least a first flip logic line and a second flip logic line, the first flip logic line and the second flip logic line are written into the linked list using a second parsing strategy.

[0161] It should also be noted that the two first flipped logic rows mentioned here do not necessarily represent two completely identical logic rows, but are mainly used to illustrate the number of logic rows where bit flipping occurs.

[0162] For the first parsing strategy, in some embodiments, using the first parsing strategy to write the first flip logic line into the linked list may include:

[0163] When the first flipped logic line does not exist in the linked list, a node corresponding to the to-be-parsed logic line in the linked list is determined as a to-be-parsed node;

[0164] Determine whether the successor node of the node to be parsed is empty;

[0165] If the successor node of the node to be parsed is empty, write the row address of the first flip logic row into the successor node of the node to be parsed;

[0166] If the successor node of the node to be parsed is not empty, the row address of the first flip logic row is written into the predecessor node of the node to be parsed.

[0167] It should be noted that if the at least one flip logic row includes only one first flip logic row, and the first flip logic row does not exist in the linked list, the first flip logic row needs to be written into the linked list.

[0168] Specifically, the node corresponding to the to-be-parsed logic line in the linked list is determined as the to-be-parsed node, and it is determined whether the successor node of the to-be-parsed node is empty. If it is not empty, it means that the to-be-parsed node already has a successor, and the row address of the first flipped logic line is written into the predecessor node of the to-be-parsed node; if the successor node of the to-be-parsed node is empty, it means that the to-be-parsed node does not have a successor, and the row address of the first flipped logic line is written into the successor node of the to-be-parsed node. Then, the next to-be-parsed logic line is returned to be parsed until all logic lines of the target storage library are parsed.

[0169] That is, writing the first flip logic line into the linked list means writing the row address of the first flip logic line into the predecessor node or successor node of the node to be parsed. Specifically, writing the row address of the first flip logic line into the data field of the predecessor node or successor node of the node to be parsed.

[0170] In this way, for each logical row referred to by a node in the linked list, its predecessor or successor is a node pointing to a logical row adjacent to it in physical address. Therefore, the order relationship of the nodes in the linked list is the order relationship of the physical rows corresponding to the logical rows, realizing the decoding of the physical position relationship of the logical rows.

[0171] It should also be noted that the node to be parsed is the node corresponding to the logical line to be parsed in the linked list. That is to say, before the logical line to be parsed is parsed, the logical line to be parsed has been written into the linked list.

[0172] For the first parsed logic line to be parsed in the target storage library, while it is pushed to the top of the preset stack, its row address is also written into a node in the linked list. The node can be any node in the linked list. In the process of parsing the first logic line to be parsed, the node serves as the node to be parsed.

[0173] In addition, after writing the row address of the first flipped logic row into the successor node or the predecessor node of the node to be parsed, the first flipped logic row is also pushed into the top of the preset stack. In this way, after completing the parsing of the logic row to be parsed, it is necessary to return to perform the parsing of the next logic row to be parsed, and the next logic row to be parsed is the top element of the preset stack, that is, the first flipped logic row.

[0174] Therefore, for the unparsed logical line that is not the first one to be parsed in the target storage repository, it has been written into the linked list before being determined as the unparsed logical line, that is, the node corresponding to the unparsed logical line already exists in the linked list.

[0175] In addition, in some embodiments, when the at least one flip logic row includes only the first flip logic row, and the first flip logic row does not exist in the linked list, the method may further include:

[0176] Count the number of hammering operations performed on the logical line to be parsed;

[0177] Determine whether the number of hammering is greater than or equal to a preset threshold; wherein the preset threshold is the maximum number of hammering operations performed on the logic line to be parsed;

[0178] If the hammering number is less than the preset threshold, continue to perform the row hammering operation on the logic row to be parsed until at least one flipped logic row is obtained;

[0179] If the number of hammering times is greater than or equal to the preset threshold, the process returns to the step of obtaining the to-be-parsed logical line of the target storage library.

[0180] It should be noted that when at least one flip logic line includes only the first flip logic line, the first flip logic line may already exist in the linked list, and in this case, there is no need to write the first flip logic line into the linked list. Since there is only one adjacent logic line (unless otherwise specified, adjacent means physically adjacent) for the first logic line and the last logic line in the physical position, if the number of flip logic lines is one, it means that the logic line to be parsed may be a logic line located at the boundary, or it may be a misjudgment caused by an operation error or other reasons.

[0181] Therefore, the embodiment of the present disclosure sets a preset threshold to improve the fault tolerance rate of determining whether the logic line to be analyzed is a boundary logic line. The preset threshold represents the maximum number of row hammering operations on the logic line to be analyzed, and is used when the number of flipped logic lines is one.

[0182] If the number of hammering times is less than the preset threshold, the row hammering operation will continue to be performed on the logic row to be parsed until at least one flipped logic row is obtained; if the number of hammering times is greater than or equal to the preset threshold, it means that the number of hammering times on the logic row to be parsed has reached the maximum number, and the operation will be returned to obtain the next logic row to be parsed, and the next logic row to be parsed will be parsed.

[0183] In this way, when the number of flipped logic rows is one and the flipped logic row already exists in the linked list, by comparing the cumulative hammering times with the preset threshold, it is determined whether it is necessary to continue to perform the row hammering operation on the logic row to be parsed, thereby avoiding misjudgment due to various factors and improving the accuracy of determining whether the logic row to be parsed is a boundary logic row.

[0184] For the second parsing strategy, in some embodiments, the first flip logic row and the second flip logic row are two logic rows with the largest number of flips in the at least one flip logic row, and the number of flips of the first flip logic row is greater than or equal to the number of flips of the second flip logic row;

[0185] Accordingly, using the second parsing strategy to write the first flip logic line and the second flip logic line into the linked list may include:

[0186] Determine whether the first flip logic row exists in the linked list;

[0187] If the first flip logic line does not exist in the linked list, write the first flip logic line into the linked list;

[0188] If the first flip logic line exists in the linked list, determine whether the second flip logic line exists in the linked list;

[0189] If the second inverted logic line does not exist in the linked list, the second inverted logic line is written into the linked list.

[0190] It should be noted that when the number of flip logic rows is greater than one, two of the flip logic rows with the largest number of flips are selected as the first flip logic row and the second flip logic row. According to the characteristics of row hammering, the flip number of the flip logic row closest to the logic row to be parsed must be greater than the flip number of the flip logic row that is next to or farther from the logic row to be parsed.

[0191] In this way, the first flipped logic line and the second flipped logic line are physically adjacent lines to the logic line to be analyzed, so that the physical position relationship between the logic lines can be obtained more accurately.

[0192] It should also be noted that the disclosed embodiment can write the flip logic line with more flip times among the two flip logic lines into the successor node of the logic line to be parsed, so the flip times of the first flip logic line is greater than or equal to the flip times of the second flip logic line. In the process of writing the first flip logic line and the second flip logic line into the linked list, first determine whether the first flip logic line exists in the linked list, if so, then determine whether the second flip logic line exists in the linked list; if the second flip logic line does not exist in the linked list, first write the first flip logic line into the linked list, and then determine whether the second flip logic line exists in the linked list.

[0193] The judgment of the second flipped logic line is similar. If it does not exist in the linked list, it is written into the linked list. If it exists in the linked list, it returns to parse the next logic line to be parsed until all logic lines of the target storage library are parsed.

[0194] In some embodiments, writing the first flip logic row into the linked list may include:

[0195] Determine the node corresponding to the to-be-parsed logic line in the linked list as the to-be-parsed node;

[0196] Determine whether the successor node of the node to be parsed is empty;

[0197] If the successor node of the node to be parsed is empty, write the row address of the first flip logic row into the successor node of the node to be parsed;

[0198] If the successor node of the node to be parsed is not empty, the row address of the first flip logic row is written into the predecessor node of the node to be parsed.

[0199] In some embodiments, writing the second flip logic row into the linked list may include:

[0200] Determine the node corresponding to the to-be-parsed logic line in the linked list as the to-be-parsed node;

[0201] Determine whether the successor node of the node to be parsed is empty;

[0202] If the successor node of the node to be parsed is empty, write the row address of the second flip logic row into the successor node of the node to be parsed;

[0203] If the successor node of the node to be parsed is not empty, the row address of the second flip logic row is written into the predecessor node of the node to be parsed.

[0204] It should be noted that the method of writing the first / second flipped logic line into the linked list is the same as the aforementioned method of writing the first flipped logic line into the linked list, which will not be repeated here.

[0205] It should be noted that after writing the first / second flip logic line into the linked list, the first / second flip logic line still needs to be pushed into the top of the preset stack. Here, if the first flip logic line and the second flip logic line are both written into the linked list, both will be pushed into the preset stack. At this time, since the first flip logic line is judged and written into the linked list first, the first flip logic line is pushed into the preset stack first, and the second flip logic line is pushed into the preset stack after the first flip logic line. At this time, the top element of the preset stack is the second flip logic line. Then, the next logical line to be parsed is the top element of the preset stack, that is, the second flip logic line.

[0206] It can be seen that after writing each flipped logic line into the linked list, the present disclosure also pushes it into the preset stack at the same time. In this way, for the analysis of the target storage library, it is only necessary to randomly select a logic line from the target storage library when determining the first logic line to be analyzed. For the subsequent logic lines to be analyzed, it is only necessary to pop the top element of the preset stack without selecting in the target storage library, and the analysis of all logic lines of the target storage library can be completed.

[0207] After all logical rows of the target storage library are parsed, a linked list storing the physical position relationship of the logical rows can be obtained. A mapping relationship is determined based on the linked list, wherein the mapping relationship is used to record the physical position relationship of multiple logical rows, thereby achieving the decoding of the physical position relationship of the logical rows.

[0208] In some embodiments, determining the mapping relationship according to the linked list may include:

[0209] Set the output file;

[0210] The linked list is traversed to the output file to obtain a target file of the target storage library; wherein the target file stores the physical position relationship of multiple logical rows of the mapping relationship records.

[0211] It should be noted that when determining the mapping relationship according to the linked list, an output file can be set, and then the linked list is traversed to the output file to obtain a target file of the target storage library. In the target file, the physical position relationship of multiple logical rows of the mapping relationship record is stored.

[0212] The method provided by the embodiment of the present disclosure may be applied to a memory including at least one storage repository. In some embodiments, the target storage repository is any one of the at least one storage repository. The method may further include:

[0213] Determine whether at least one repository has completed parsing;

[0214] If at least one repository has completed parsing, save the target files of all repositories;

[0215] If there are unresolved repositories in at least one repository, a target repository is determined from the unresolved repository, and the step of determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target repository is returned to be executed until at least one repository is fully resolved.

[0216] It should be noted that after the parsing of the target repository is completed, it is determined whether all the repositories in the memory have completed the parsing. If all the repositories in the memory have completed the parsing, the target files of all the repositories are saved, that is, the physical position relationship of all the logical lines of each repository in the memory is saved. If there are repositories that have not been parsed, a target repository is determined from the repositories that have not been parsed, and the target repository is parsed in the above manner until all the repositories have completed the parsing.

[0217] The disclosed embodiment provides a parsing method, during the parsing process of a target storage library, the physical position relationship of the logical rows is determined by performing a row hammer operation on the logical rows in the target storage library; and the step of determining the physical position relationship of the logical rows by performing a row hammer operation on the logical rows in the target storage library is repeated until all the multiple logical rows are parsed; a mapping relationship is determined according to a linked list, and the mapping relationship is used to record the physical position relationship of the multiple logical rows; wherein, the physical position relationship of the logical rows is determined by performing a row hammer operation on the logical rows in the target storage library, including: obtaining the to-be-parsed logical rows of the target storage library, wherein the target storage library includes multiple logical rows; performing a row hammer operation on the to-be-parsed logical rows until at least one flipped logical row is obtained; and writing at least one flipped logical row into a linked list; thus, based on the characteristic that the row hammer operation will cause the physically adjacent rows of the hammered rows to flip, by performing a row hammer operation on the to-be-parsed logical rows and writing the obtained flipped logical rows into a linked list, the physical position relationship of the logical rows of the memory can be obtained, and the correct parsing of the physical position relationship of the logical rows of the memory is achieved, thereby achieving the conversion of the logical rows of the memory into the physical rows.

[0218] In another embodiment of the present disclosure, see Fig.11 , which shows a schematic diagram of the process of an analysis method provided by the present disclosure Figure 2 .like Fig.11 As shown, the method may include:

[0219] S1001. Determine the number of storage repositories.

[0220] It should be noted that after the parsing algorithm starts, the total number of storage bins in the memory is first obtained.

[0221] S1002: Determine whether all storage repositories have completed parsing.

[0222] It should be noted that if the judgment result is yes, that is, all storage bins in the memory have been parsed, step S1005 is executed; if the judgment result is no, that is, there are storage bins that have not been parsed, step S1003 is executed.

[0223] S1003, parsing the target repository.

[0224] It should be noted that, when there are unresolved storage libraries in the memory, a target storage library is determined from the unresolved storage libraries, and the target storage library is resolved.

[0225] In simple terms, parsing the target repository consists mainly of repeatedly executing the following steps:

[0226] (1) Perform a row hammering operation to attack the logic line to be parsed, obtain one or two (or more) flipped logic lines with bit flips, and write the flipped logic lines into a linked list.

[0227] The flipped logic row is physically adjacent to the attacked logic row.

[0228] (2) Repeat step (1) until the number of logical lines parsed is equal to the total number of logical lines in the target repository.

[0229] (3) Save the parsing results of the logical line to be parsed.

[0230] Since the present disclosure stores the physical position relationship of the logical rows of the target storage library, the adjacent relationship of the nodes in the linked list is mapped to the adjacent relationship between the physical rows at the physical address. Therefore, the parsing result can also be understood as the result of parsing from logical rows to physical rows.

[0231] S1004: Save the parsing result of the target storage library.

[0232] It should be noted that after the target repository is parsed, the parsing result of the target repository is saved, that is, the parsing result of all logical rows to physical rows of the target repository is saved.

[0233] S1005. Save all data.

[0234] It should be noted that after the parsing of all storage bins in the memory is completed, all data is saved and the algorithm ends.

[0235] It should also be noted that the aforementioned steps S1001 to S1005 are only a general description of the analysis method, and the implementation process of steps S1003, S1004 and S1005 will be further described in detail.

[0236] For step S1003, see Fig.12 , which shows a detailed process diagram of an analysis method provided by the present disclosure Figure 3 , this detailed process is a specific description of step S1003. Fig.12 As shown, the detailed process may include:

[0237] S1003a, initialize the preset stack.

[0238] S1003b, initialize the linked list.

[0239] It should be noted that when parsing the target repository, N logical lines that need to be parsed can be obtained according to the target repository, and the N logical lines are stored in an array; at the same time, preset data can be written to each logical line to verify whether the logical line is flipped; where N represents the number of logical lines in the target repository.

[0240] Initialize the preset stack to be empty, initialize the linked list, and determine the linked list structure of the linked list. For the preset stack, in the embodiment of the present disclosure, the number of elements does not exceed three, which ensures the implementation of the deep traversal logic line.

[0241] The preset stack is used to store the logic lines to be parsed, and the linked list is used to save the physical position relationship of the logic lines, that is, the physical order relationship.

[0242] S1003c. Randomly push a logic line into a preset stack.

[0243] It should be noted that the first logical line to be parsed in the target storage is randomly determined. Here, a logical line can be randomly determined from the aforementioned array and pushed into the preset stack, and this randomly determined logical line is the first logical line to be parsed in the target storage.

[0244] It should also be noted that for the first parsed logical line, while it is pushed into the preset stack, it also needs to be written into the linked list, that is, the row address of the logical line is written into the data field of a node in the linked list to generate its corresponding node in the linked list.

[0245] S1003d, determine whether the preset stack is empty.

[0246] It should be noted that if the judgment result is yes, that is, the preset stack is empty, indicating that all logic lines of the target storage library have been parsed, the aforementioned step S1004 is executed to save the parsing result of the target storage library.

[0247] If the judgment result is no, that is, the preset stack is not empty, it means that there are unparsed logic lines in the target storage library, and step S1003e is executed.

[0248] S1003e, pop the logic line to be parsed from the top of the preset stack.

[0249] It should be noted that the top element of the preset stack is popped, and the top element popped is the logic line to be parsed.

[0250] S1003f. Perform row hammering operation on the logic row to be parsed.

[0251] S1003g. Obtain M flip logic rows.

[0252] S1003h, determine whether M is equal to 0.

[0253] It should be noted that by performing the row hammering operation on the logic row to be parsed, M flipped logic rows can be obtained. Here, for each hammering, the number M is uncertain.

[0254] First, determine whether M is 0. If the judgment result is yes, that is, M is 0, return to step S1003f and continue to perform row hammering operations on the logic line to be parsed until M is not 0; if the judgment result is no, that is, M is not 0, execute step S1003i.

[0255] S1003i. Determine whether M is less than 2.

[0256] It should be noted that when M is not 0, it is further determined whether M is less than 2. If the determination result is yes, that is, M is less than 2, that is, M is 1, step S1003j and subsequent steps are executed, that is, the first parsing strategy described in the aforementioned embodiment is executed.

[0257] If the judgment result is no, M is not less than 2, that is, M is greater than or equal to 2, the second parsing strategy in the aforementioned embodiment is executed. The second parsing strategy will be described in detail later.

[0258] S1003j. Determine whether the flip logic row exists in the linked list.

[0259] It should be noted that at this time, there is only one flip logic row, and it is determined whether the flip logic row exists in the linked list; if the judgment result is yes, that is, the flip logic row exists in the linked list, execute step S1003k; if the judgment result is no, that is, the flip logic row does not exist in the linked list, execute step S1003l.

[0260] S1003k, determine whether the number of hammering operations performed on the logic line to be analyzed is greater than or equal to a preset threshold.

[0261] It should be noted that the preset threshold refers to the maximum number of hammering times for performing a row hammering operation on the logic row to be parsed, and is used when M=1 to improve the error tolerance for determining whether the logic row to be parsed is a boundary logic row.

[0262] If the judgment result is yes, that is, the number of hammer strikes is greater than or equal to the preset threshold, return to step S1003d; if the judgment result is no, that is, the number of hammer strikes is less than the preset threshold, return to step S1003f.

[0263] S10031. Determine whether the successor node of the current node in the linked list is empty.

[0264] It should be noted that if the judgment result is yes, that is, the successor node of the current node in the linked list is empty, step S1003m is executed; if the judgment result is no, that is, the successor node of the current node in the linked list is not empty, step S1003n is executed.

[0265] S1003m. Add the flip logic row to the successor node of the current node in the linked list.

[0266] S1003n, add the flip logic row to the predecessor node of the current node in the linked list.

[0267] S1003o, push the flip logic row into the top of the preset stack.

[0268] It should be noted that the current node is the node corresponding to the node to be parsed in the linked list. After adding the flip logic line to the linked list, the flip logic line is also pushed into the top of the preset stack. Then return to execute step S1003d.

[0269] Further, after step S1003i, if the judgment result of step S1003i is no, that is, the number of flipped logic rows is greater than or equal to 2, the aforementioned second parsing strategy is executed on the multiple flipped logic rows. Fig.13 , which shows a detailed process diagram of an analysis method provided by the present disclosure Figure 4 , this detailed process is a specific description of the second parsing strategy. Fig.13 As shown, the detailed process may include:

[0270] S1003p, select the two flip logic lines with the most flip times: flip logic line a and flip logic line b.

[0271] It should be noted that when there are multiple flip logic lines, two logic lines with the most flip times are selected: flip logic line a and flip logic line b. The flip times of flip logic line a can be greater than the flip times of flip logic line b.

[0272] S1003q, determine whether the flip logic row a exists in the linked list.

[0273] It should be noted that if the judgment result is yes, that is, the flip logic row a exists in the linked list, step S1003v is executed; if the judgment result is no, that is, the flip logic row a does not exist in the linked list, step S1003r is executed.

[0274] S1003r, determine whether the successor node of the current node in the linked list is empty.

[0275] It should be noted that if the judgment result is yes, that is, the successor node of the current node in the linked list is empty, step S1003s is executed; if the judgment result is no, that is, the successor node of the current node in the linked list is not empty, step S1003t is executed.

[0276] S1003s. Add the flip logic row a to the successor node of the current node in the linked list.

[0277] S1003t, add the flip logic row a to the predecessor node of the current node in the linked list.

[0278] S1003u, push the flip logic line a into the top of the preset stack.

[0279] It should be noted that after the flip logic line a is added to the linked list, the flip logic line a is also pushed to the top of the preset stack.

[0280] S1003v, determine whether the flip logic line b exists in the linked list.

[0281] It should be noted that if the judgment result is yes, that is, the flip logic line b exists in the linked list, the aforementioned step S1003d is executed; if the judgment result is no, that is, the flip logic line b does not exist in the linked list, step S1003w is executed.

[0282] S1003w. Determine whether the successor node of the current node in the linked list is empty.

[0283] It should be noted that if the judgment result is yes, that is, the successor node of the current node in the linked list is empty, step S1003x is executed; if the judgment result is no, that is, the successor node of the current node in the linked list is not empty, step S1003y is executed.

[0284] S1003x, add the flip logic row b to the successor node of the current node in the linked list.

[0285] S1003y, add the flip logic line b to the predecessor node of the current node in the linked list.

[0286] S1003z, push the flip logic line b into the top of the preset stack.

[0287] It should be noted that after adding the flip logic line b to the linked list, the flip logic line b is also pushed to the top of the preset stack. Then the process returns to step S1003d.

[0288] In this way, steps S1003a to S1003z describe in detail the method of parsing the target repository.

[0289] Furthermore, for Fig.11 Step S1004 in Fig.14 , which shows a detailed flow diagram of a parsing method provided by an embodiment of the present disclosure Figure 5 , this detailed process is a specific description of step S1004. Fig.14 As shown, the detailed process may include:

[0290] S1004a. Set the output file.

[0291] S1004b, traverse the linked list to the output file.

[0292] S1004c. The target repository logical row to physical row parsing is completed.

[0293] It should be noted that after the target repository is parsed, the parsed structure is saved. An output file can be set, the linked list is traversed to the output file, the target repository logical line to physical line parsing is completed, and the target file of the target repository is obtained.

[0294] Accordingly, for Fig.11 In step 1005, after all target storage libraries of the memory are parsed, the target file of each storage library can be obtained, all target files are saved, and the mapping relationship from all logical lines to physical lines in the memory is obtained.

[0295] The embodiment of the present disclosure provides a parsing method, and the specific implementation of the aforementioned embodiment is elaborated in detail through the above embodiment. It can be seen that the parsing method proposed in the embodiment of the present disclosure parses the storage banks in the memory, and a single algorithm can obtain the physical position relationship of all logical rows of a storage bank; when parsing from logical rows to physical rows, the row address of the logical row based on is known; the number of logical rows that can be flipped in the boundary logical row (i.e., the first and last physical rows) in the linked list corresponding to a storage bank is one. This method innovatively realizes the conversion of the logical row of the storage bank to the physical row, and can effectively realize the conversion of all logical rows of all storage banks of the storage bank to the physical row.

[0296] In another embodiment of the present disclosure, see Fig.15, which shows a schematic diagram of the composition structure of an analysis device 40 provided in an embodiment of the present disclosure. Fig.15 As shown, the parsing device 40 may include:

[0297] The parsing unit 401 is configured to determine the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target repository during the parsing process of the target repository; and repeatedly perform the step of determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target repository until all the multiple logical rows included in the target repository are parsed;

[0298] A determining unit 402 is configured to determine a mapping relationship according to the linked list, where the mapping relationship is used to record the physical position relationship of multiple logical rows;

[0299] The parsing unit 401 includes an acquisition unit 4011, a hammering unit 4012 and a writing unit 4013; wherein,

[0300] An acquisition unit 4011 is configured to acquire a to-be-parsed logic line of a target storage repository, wherein the target storage repository includes a plurality of logic lines;

[0301] A hammering unit 4012 is configured to perform a row hammering operation on the logic row to be parsed until at least one flipped logic row is obtained;

[0302] The writing unit 4013 is configured to write at least one flipped logic row into the linked list.

[0303] In some embodiments, the determination unit 402 is further configured to obtain the number of logical rows of the target repository; and determine the linked list structure of the linked list based on the number of logical rows of the target repository; wherein the linked list includes multiple nodes, and the number of the multiple nodes is the same as the number of logical rows of the target repository.

[0304] In some embodiments, the write unit 4013 is specifically configured to write the first flip logic row into the linked list using a first parsing strategy if at least one flip logic row includes only a first flip logic row; and to write the first flip logic row and the second flip logic row into the linked list using a second parsing strategy if at least one flip logic row includes at least a first flip logic row and a second flip logic row.

[0305] In some embodiments, the write unit 4013 is further specifically configured to, when the first flip logic row does not exist in the linked list, determine the node corresponding to the to-be-parsed logic row in the linked list as the node to be parsed; and determine whether the successor node of the node to be parsed is empty; and if the successor node of the node to be parsed is empty, write the row address of the first flip logic row into the successor node of the node to be parsed; and if the successor node of the node to be parsed is not empty, write the row address of the first flip logic row into the predecessor node of the node to be parsed.

[0306] In some embodiments, the first flip logic row and the second flip logic row are the two logic rows with the most flip times among at least one flip logic row, and the flip times of the first flip logic row are greater than or equal to the flip times of the second flip logic row; the write unit 4013 is also specifically configured to determine whether the first flip logic row exists in the linked list; and if the first flip logic row does not exist in the linked list, write the first flip logic row to the linked list; and if the first flip logic row exists in the linked list, determine whether the second flip logic row exists in the linked list; and if the second flip logic row does not exist in the linked list, write the second flip logic row to the linked list.

[0307] In some embodiments, the write unit 4013 is further specifically configured to determine the node corresponding to the to-be-parsed logic row in the linked list as the to-be-parsed node; and determine whether the successor node of the to-be-parsed node is empty; and if the successor node of the node to be parsed is empty, write the row address of the first flipped logic row into the successor node of the node to be parsed; and if the successor node of the node to be parsed is not empty, write the row address of the first flipped logic row into the predecessor node of the node to be parsed.

[0308] In some embodiments, the write unit 4013 is further specifically configured to determine the node corresponding to the to-be-parsed logic row in the linked list as the to-be-parsed node; and determine whether the successor node of the to-be-parsed node is empty; and if the successor node of the node to be parsed is empty, write the row address of the second flipped logic row into the successor node of the node to be parsed; and if the successor node of the node to be parsed is not empty, write the row address of the second flipped logic row into the predecessor node of the node to be parsed.

[0309] In some embodiments, Fig.15As shown, the parsing unit 401 may also include a statistical unit 4014, configured to count the number of hammering operations performed on the logic line to be parsed, when the at least one flip logic line only includes the first flip logic line and the first flip logic line does not exist in the linked list; and determine whether the number of hammering operations is greater than or equal to a preset threshold; wherein the preset threshold is the maximum number of hammering operations performed on the logic line to be parsed; and if the number of hammering operations is less than the preset threshold, continue to perform the step of performing the row hammering operation on the logic line to be parsed until at least one flip logic line is obtained; and if the number of hammering operations is greater than or equal to the preset threshold, return to the step of obtaining the logic line to be parsed of the target repository.

[0310] In some embodiments, the acquisition unit 4011 is specifically configured to pop the top element of the stack from the preset stack to obtain the to-be-parsed logical line of the target storage library; wherein the top element of the stack represents the to-be-parsed logical line of the target storage library.

[0311] In some embodiments, when the logical line to be parsed is the first logical line to be parsed in the target storage library, the write unit 4013 is further specifically configured to randomly select a logical line from the target storage library as the logical line to be parsed after initializing the preset stack, and push the logical line to be parsed to the top of the preset stack.

[0312] In some embodiments, the write unit 4013 is further specifically configured to push the flip logic row in the write linked list into the top of a preset stack.

[0313] In some embodiments, Fig.15 As shown, the analysis device 40 may further include a verification unit 403 configured to write preset data to a plurality of logic rows respectively; wherein the preset data is used to determine whether a flip occurs in the logic row.

[0314] In some embodiments, the determination unit 402 is specifically configured to set an output file; and traverse the linked list to the output file to obtain a target file of the target repository; wherein the target file stores the physical location relationship of multiple logical rows of mapping relationship records.

[0315] In some embodiments, the parsing device 40 is applied to a memory, the memory includes at least one repository, and the target repository is any one of the at least one repository; accordingly, the determination unit 402 is also configured to determine whether the at least one repository has completed the parsing; and if at least one repository has completed the parsing, the target files of all the repositories are saved; and if there are unparsed repositories in at least one repository, the target repository is determined from the unparsed repositories, and the step of determining the physical position relationship of the logical lines by performing a row hammering operation on the logical lines in the target repository is returned to execute until at least one repository has completed the parsing.

[0316] It is understandable that in the present disclosure, a "unit" may be a part of a circuit, a part of a processor, a part of a program or software, etc., and of course, it may be a module or a non-modular one. Moreover, the components in the present disclosure may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional module.

[0317] If the integrated unit is implemented in the form of a software function module and is not sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) or a processor to perform all or part of the steps of the method described in the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc. Various media that can store program codes.

[0318] Therefore, the present disclosure provides a computer storage medium storing a computer program, which implements the steps of the parsing method described in any one of the aforementioned embodiments when the computer program is executed by at least one processor.

[0319] Based on the above computer storage medium, see Fig.16 , which shows a schematic diagram of the composition structure of an electronic device 50 provided by an embodiment of the present disclosure. Fig.16 As shown, it may include: a communication interface 501, a memory 502 and a processor 503; each component is coupled together via a bus system 504. It is understood that the bus system 504 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 504 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Fig.16 Various buses are labeled as bus system 504. Among them, the communication interface 501 is used for receiving and sending signals in the process of sending and receiving information between other external network elements;

[0320] A memory 502, used to store a computer program that can be run on the processor 503;

[0321] The processor 503 is configured to execute, when running the computer program:

[0322] During the parsing process of the target repository, the physical position relationship of the logical rows in the target repository is determined by performing a row hammering operation on the logical rows in the target repository; wherein the determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target repository may include:

[0323] Obtaining a to-be-parsed logical row of a target repository, wherein the target repository includes a plurality of logical rows;

[0324] Performing a row hammering operation on the logic row to be parsed until at least one flipped logic row is obtained;

[0325] Write at least one flip logic row into the linked list;

[0326] Repeat the step of determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target storage repository until all the multiple logical rows are parsed;

[0327] A mapping relationship is determined according to the linked list, where the mapping relationship is used to record the physical position relationship of the multiple logical rows.

[0328] It can be understood that the memory 502 in the present disclosure can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus random access memory (DRRAM). The memory 502 of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0329] The processor 503 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 503. The above processor 503 may be a general processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The various methods, steps and logic block diagrams in the present disclosure can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method in the present disclosure can be directly embodied as a hardware decoding processor to execute, or the hardware and software modules in the decoding processor are combined to execute. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 502, and the processor 503 reads the information in the memory 502 and completes the steps of the above method in combination with its hardware.

[0330] It is understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit may be implemented in one or more application specific integrated circuits (ASIC), digital signal processors (DSP), digital signal processing devices (DSPD), programmable logic devices (PLD), field programmable gate arrays (FPGA), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described in the present disclosure, or a combination thereof.

[0331] For software implementation, the techniques described herein can be implemented by modules (e.g., procedures, functions, etc.) that perform the functions described herein. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or outside the processor.

[0332] Optionally, as another embodiment, the processor 503 is further configured to execute the parsing method described in any one of the aforementioned embodiments when running the computer program.

[0333] In the embodiment of the present disclosure, the electronic device 50 can include the aforementioned parsing device 40, so that the physical position relationship of the logical row can be determined by performing a row hammering operation on the logical row in the target storage memory. In this way, the electronic device 50 can perform a row hammering operation on the logical row to be parsed, and write the obtained flipped logical row into the linked list, so as to obtain the physical position relationship of the logical row of the memory, realize the correct parsing of the physical position relationship of the logical row of the memory, and thus realize the conversion of the logical row of the memory to the physical row.

[0334] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0335] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0336] The above serial numbers of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0337] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0338] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0339] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0340] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A parsing method, characterized in that: The method comprises: During the parsing process of the target storage library, determining the physical position relationship of the logic rows by performing a row hammering operation on a plurality of logic rows in the target storage library; Repeating the step of determining the physical position relationship of the logic rows by performing a row hammering operation on the logic rows in the target storage repository until all the plurality of logic rows are parsed; Determine a mapping relationship according to the linked list, wherein the mapping relationship is used to record the physical position relationship of the plurality of logical rows; The determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target storage library includes: Obtaining a logic row to be parsed of the target repository, wherein the target repository includes a plurality of logic rows; Performing a row hammering operation on the to-be-parsed logic row until at least one flipped logic row is obtained; The at least one flipped logical row is written into the linked list.

2. The method according to claim 1, characterized in that: The method further comprises: Obtaining the number of logical rows of the target repository; The linked list structure of the linked list is determined according to the number of logical rows of the target storage library; wherein the linked list includes a plurality of nodes, and the number of the plurality of nodes is the same as the number of logical rows of the target storage library.

3. The method according to claim 1, characterized in that Writing the at least one flip logic line into the linked list comprises: If the at least one flip logic line only includes a first flip logic line, writing the first flip logic line into the linked list using a first parsing strategy; If the at least one inverted logic row includes at least a first inverted logic row and a second inverted logic row, the first inverted logic row and the second inverted logic row are written into the linked list using a second parsing strategy.

4. The method according to claim 3, characterized in that The step of writing the first flip logic line into the linked list by using the first parsing strategy includes: If the first flipped logic row does not exist in the linked list, determining a node corresponding to the to-be-parsed logic row in the linked list as a to-be-parsed node; Determine whether the successor node of the node to be parsed is empty; If the successor node of the node to be resolved is empty, writing the row address of the first flip logic row into the successor node of the node to be resolved; If the successor node of the node to be resolved is not empty, the row address of the first flip logic row is written into the predecessor node of the node to be resolved.

5. The method according to claim 3, characterized in that: The first flip logic row and the second flip logic row are two logic rows with the largest number of flips among the at least one flip logic row, and the number of flips of the first flip logic row is greater than or equal to the number of flips of the second flip logic row; Accordingly, the step of writing the first flip logic line and the second flip logic line into the linked list by using the second parsing strategy includes: Determine whether the first flip logic row exists in the linked list; If the first flip logic line does not exist in the linked list, writing the first flip logic line into the linked list; If the first flip logic row exists in the linked list, determining whether the second flip logic row exists in the linked list; If the second inverted logic line does not exist in the linked list, the second inverted logic line is written into the linked list.

6. The method according to claim 5, characterized in that The step of writing the first flip logic row into the linked list comprises: Determine the node corresponding to the to-be-parsed logic row in the linked list as the to-be-parsed node; Determine whether the successor node of the node to be parsed is empty; If the successor node of the node to be resolved is empty, writing the row address of the first flip logic row into the successor node of the node to be resolved; If the successor node of the node to be resolved is not empty, the row address of the first flip logic row is written into the predecessor node of the node to be resolved.

7. The method according to claim 5, characterized in that The step of writing the second flip logic line into the linked list comprises: Determine the node corresponding to the to-be-parsed logic row in the linked list as the to-be-parsed node; Determine whether the successor node of the node to be parsed is empty; If the successor node of the node to be resolved is empty, writing the row address of the second flip logic row into the successor node of the node to be resolved; If the successor node of the node to be resolved is not empty, the row address of the second flip logic row is written into the predecessor node of the node to be resolved.

8. The method according to claim 3, characterized in that In a case where the at least one flip logic row includes only a first flip logic row, and the first flip logic row does not exist in the linked list, the method further includes: Counting the number of hammering operations performed on the logic line to be parsed; Determine whether the hammering times is greater than or equal to a preset threshold; wherein the preset threshold is the maximum hammering times for performing a row hammering operation on the logic row to be analyzed; If the hammering number is less than the preset threshold, continue to perform the row hammering operation on the to-be-analyzed logic row until at least one flipped logic row is obtained; If the hammering times are greater than or equal to the preset threshold, the process returns to the step of obtaining the to-be-parsed logical line of the target storage library.

9. The method according to claim 1, characterized in that: The obtaining of the to-be-parsed logical line of the target storage repository includes: The top element of the stack is popped from the preset stack to obtain the to-be-parsed logical line of the target storage library; wherein the top element of the stack represents the to-be-parsed logical line of the target storage library.

10. The method according to claim 9, characterized in that When the to-be-parsed logic line is the first to-be-parsed logic line in the target storage library, before popping the top element from the preset stack to obtain the to-be-parsed logic line of the target storage library, the method further includes: After the preset stack is initialized, a logic line is randomly selected from the target storage library as a logic line to be parsed, and the logic line to be parsed is pushed onto the top of the preset stack.

11. The method according to claim 9, characterized in that In the process of writing the at least one flipped logic line into the linked list, the method further includes: The flip logic line written into the linked list is pushed into the top of the preset stack.

12. The method according to claim 1, characterized in that Before parsing the target repository, the method further includes: Preset data are written into the plurality of logic rows respectively; wherein the preset data is used to determine whether the logic row is flipped.

13. The method according to any one of claims 1 to 12, characterized in that: Determining the mapping relationship according to the linked list includes: Set the output file; The linked list is traversed to the output file to obtain a target file of the target storage library; wherein the target file stores the physical position relationship of multiple logical rows of the mapping relationship record.

14. The method according to claim 13, characterized in that The method is applied to a memory, the memory includes at least one storage library, the target storage library is any one of the at least one storage library; the method further includes: Determining whether all of the at least one repository has completed parsing; If the at least one repository has completed parsing, then save the target files of all the repositories; If there are unresolved repositories in the at least one repository, a target repository is determined from the unresolved repository, and the step of determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target repository is returned to execution until all of the at least one repository is resolved.

15. An analysis device, characterized in that: The analysis device comprises: A parsing unit is configured to determine the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target repository during the parsing process of the target repository; and repeatedly perform the step of determining the physical position relationship of the logical rows by performing a row hammering operation on the logical rows in the target repository until all the multiple logical rows included in the target repository are parsed; a determining unit, configured to determine a mapping relationship according to the linked list, wherein the mapping relationship is used to record the physical position relationship of the plurality of logical rows; The analysis unit includes an acquisition unit, a hammer unit and a writing unit; wherein, The acquisition unit is configured to acquire a to-be-parsed logical line of the target storage repository, wherein the target storage repository includes a plurality of logical lines; The hammering unit is configured to perform a row hammering operation on the to-be-parsed logic row until at least one flipped logic row is obtained; The writing unit is configured to write the at least one flipped logic row into the linked list.

16. An electronic device, comprising a memory and a processor, wherein: The memory is used to store a computer program that can be run on the processor; The processor is used to execute the parsing method according to any one of claims 1 to 14 when running the computer program.

17. A computer storage medium storing a computer program, wherein the computer program, when executed by at least one processor, implements the parsing method according to any one of claims 1 to 14.

Images