A WTA circuit based on LIF neurons

Abstract

This invention discloses a WTA circuit based on LIF neurons. It includes: a membrane potential accumulation circuit, a waveform shaping circuit, a leakage circuit, a pulse generation circuit, a refractory period circuit, a dual-switching circuit, and logic gate circuits. The memristor LIF neurons of this invention achieve adjustable excitation peak pulse width, peak potential magnitude, and refractory period duration through changes in the resistance of the memristor and the switching characteristics of the MOSFET. This invention controls the memristor LIF neurons through a dual-switching circuit and logic gate circuits to realize the WTA mechanism, effectively improving the speed and accuracy of time-encoded information, enhancing the noise robustness and stability of the nervous system, and performing better in the face of competition from a large number of neurons. Furthermore, the memristor LIF neuron circuit and its WTA circuit of this invention use very few components, which is beneficial for increasing the integration density of neuromorphic chips.

Description

Technical Field

[0001] This invention belongs to the field of spiking neural networks, specifically relating to a WTA circuit based on LIF neurons. Background Technology

[0002] As a third-generation neural network, spiking neural networks (SNNs) are closer to the working principles of biological systems than traditional artificial neural networks, effectively mimicking the connections and communication between biological neurons. In SNNs, the neuron serves as a basic unit, receiving pulse signals and generating spike pulses, forming a crucial foundation for complex spatiotemporal information processing. LIF neurons, modeled after biological neurons, effectively mimic the information transmission characteristics of biological neurons, such as the presence or absence of action potential spikes, cumulative firing, and refractory periods. However, due to the complexity of the excitation pulses of biological neurons, LIF neuron circuits constructed with traditional devices require numerous components, and the similarity between the excitation spike pulses of LIF neurons and those of biological neurons is low. This leads to problems such as low practicality, high power consumption, and difficulties in circuit integration. Memristors, as a novel component, increase or decrease their resistance value in response to an applied voltage. Since the nonlinearity of memristor resistance changes better approximates the nonlinearity of the switching resistance changes of ion channels in biological neurons, memristor-based LIF neuron circuits can effectively reduce the complexity of LIF circuits. This will help improve the integration density of neuromorphic chips and reduce their power consumption. However, most memristor LIF neurons currently have uncontrollable peak pulse width, peak intensity, and refractory period duration. These neurons limit the way information is encoded and the rate of transmission in spiking neural networks, resulting in a significant decrease in the flexibility of neural computation.

[0003] To effectively reduce the number of devices and power consumption, and to increase the encoding rate of neurons to transmit flexible spatiotemporal information in neural networks, constructing fully functional, concise, efficient memristor LIF neurons with adjustable excitation peak pulse width, peak intensity, and refractory period duration is of great significance for neuromorphic integrated chips.

[0004] In biological neurons, the WTA (Warning-Temporal Asynchrony) mechanism typically refers to the phenomenon where, when multiple neurons are simultaneously connected to the same target neuron, only the neuron with the highest activation value produces an output, while the outputs of other neurons are suppressed. In machine learning, WTA takes several forms, including a time-dependent WTA learning mechanism. In this mechanism, neurons compete based on time, meaning the activation of a neuron is determined by the temporal order of its activation. Time-dependent WTA mechanisms are commonly found in neural networks and temporal classification models. This mechanism helps neurons quickly adjust their activity levels upon receiving input signals, resulting in more accurate responses and the extraction of important information from the time series of input signals. Furthermore, time-dependent WTA learning mechanisms can improve the noise robustness and stability of the nervous system by suppressing unwanted signals, thereby enhancing the reliability and accuracy of information processing. However, current traditional time-dependent WTA circuits for neurons are mostly implemented using amplifiers. This approach is not only structurally complex but also fails to meet the high-speed and stability requirements of rate encoding in SNN computation when faced with competition from a large number of neurons. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a peak-range modulated memristor LIF (Leakage Integral and Ignition) neuron circuit and a time-rate-dependent WTA (Winner-Take-All) circuit. The technical solution of the present invention is as follows:

[0006] A WTA circuit based on LIF neurons is characterized by comprising multiple LIF neuron circuits competing simultaneously, a number of dual switching circuits equal to the number of LIF neuron circuits, and a logic gate circuit.

[0007] The LIF neuron circuit includes an input terminal, a membrane potential accumulation unit, a waveform shaping unit, a pulse generation unit, a refractory period unit, and an output terminal connected in sequence.

[0008] The input terminal is connected to the input terminal of the membrane potential accumulation unit, and the input current is integrated through the membrane potential accumulation unit;

[0009] The output of the membrane potential accumulation unit is connected to the input of the waveform shaping unit to output a voltage that reaches a preset threshold to the waveform shaping unit;

[0010] The output of the waveform shaping unit is connected to the pulse generation unit to output the digital signal obtained by converting and shaping the analog signal generated by the membrane potential accumulation unit. The waveform shaping unit includes a first-stage inverter and a second-stage inverter. The input of the first-stage inverter is connected to the membrane potential accumulation unit through a leakage unit, and immediately changes from outputting a positive voltage to outputting a zero voltage after receiving a voltage at a preset threshold, thereby outputting a square wave signal that switches between positive and zero voltage to the second-stage inverter. The second-stage inverter immediately changes from outputting a negative voltage to outputting a positive voltage after receiving a zero voltage, thereby outputting a square wave signal that switches between negative and positive voltage.

[0011] The output of the pulse generation unit serves as the output of the LIF neuron circuit to generate spike pulse outputs based on the received digital signals. It is also connected to the refractory period unit to control the refractory period unit.

[0012] The output of the refractory period unit is connected to the input of the membrane potential accumulation unit to control the on / off state of the input of the membrane potential accumulation unit.

[0013] The dual-switching circuit includes a first control terminal and a second control terminal. The first control terminal is connected to the output terminal of the first-stage inverter of the waveform shaping unit in the LIF neuron circuit, and the second control terminal is connected to the output terminal of the logic gate circuit. The output terminal of the dual-switching circuit is connected to the membrane potential accumulation unit to control the membrane potential accumulation unit to start or stop integration.

[0014] The input terminal of the logic gate circuit is connected to the output terminal of the waveform shaping circuit in all competing LIF neuron circuits, and the output terminal, together with each dual-switch circuit, controls the membrane potential accumulation unit of each LIF neuron circuit to start or stop integration.

[0015] The WTA circuit based on LIF neurons further includes a leakage unit, which is disposed between the membrane potential accumulation unit and the waveform shaping unit, so that the membrane potential accumulation unit outputs a voltage reaching a preset threshold to the waveform shaping unit through the leakage unit.

[0016] The WTA circuit based on LIF neurons includes a membrane potential accumulation unit comprising a capacitor, one end of which is connected between the current input terminal and the waveform shaping unit, and the other end of which is grounded; and a leakage unit comprising a leakage resistor, one end of which is connected between the membrane potential accumulation unit and the waveform shaping unit, and the other end of which is grounded.

[0017] The WTA circuit based on LIF neurons includes a first-stage inverter comprising a first NMOS transistor and a first PMOS transistor; the gates of the first NMOS transistor and the first PMOS transistor are interconnected and connected to a membrane potential accumulation unit through a leakage unit; the drains of the first NMOS transistor and the first PMOS transistor are connected; the source of the first NMOS transistor is grounded and the source of the first PMOS transistor is connected to a positive voltage.

[0018] The secondary inverter includes a second NMOS transistor and a second PMOS transistor; the gates of the second NMOS transistor and the second PMOS transistor are connected to each other and connected to the film potential accumulation unit through a leakage unit; the drain of the second NMOS transistor and the drain of the second PMOS transistor are connected; the source of the second NMOS transistor is connected to a negative voltage and the source of the second PMOS transistor is connected to a positive voltage.

[0019] The WTA circuit based on LIF neurons includes a pulse generation unit comprising a pulse unit memristor and a pulse unit resistor. The input terminal of the pulse unit memristor is connected to the output terminal of the waveform shaping unit, and the output terminal of the pulse unit memristor serves as a voltage output terminal and is connected to the refractory period unit. One end of the pulse unit resistor is connected to the output terminal of the pulse unit memristor, and the other end is connected to a positive voltage.

[0020] The WTA circuit based on LIF neurons includes a refractory period unit PMOS transistor. The gate of the refractory period unit PMOS transistor is connected to the pulse generation unit, the drain is connected between the current input terminal and the membrane potential accumulation unit, and the source is grounded.

[0021] The WTA circuit based on LIF neurons, wherein the dual-switching circuit includes a third NMOS transistor and a fourth NMOS transistor, the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor, the source of the third NMOS transistor is grounded, the drain of the fourth NMOS transistor is connected to a film potential accumulation unit, the gate of the third NMOS transistor is connected to the output of a logic gate circuit, and the gate of the fourth NMOS transistor is connected to the output of a first-stage inverter of the waveform shaping unit in the LIF neuron circuit.

[0022] The WTA circuit based on LIF neurons includes a logic gate circuit comprising diodes equal in number to the LIF neuron circuit and an OR gate; wherein the input terminal of each diode is connected to the output terminal of the second-level inverter of the waveform shaping unit in the corresponding LIF neuron circuit, and the output terminal is connected to one of the input terminals of the OR gate; the other input terminal of the OR gate is grounded, and the output terminal is connected to the second control terminal of the dual-switch circuit.

[0023] The technical advantages of this invention lie in the fact that the memristor LIF neuron of this invention achieves adjustable excitation peak pulse width, peak potential magnitude, and refractory period duration through changes in memristor resistance and the switching characteristics of MOSFETs. This memristor LIF neuron provides flexible and efficient spatiotemporal information for rate encoding and pulse amplitude encoding in spiking neural networks. In applications such as image classification and speech recognition using spiking neural networks, the neuron has a significant advantage in rate encoding or pulse amplitude encoding different features of the input image or speech. The WTA circuit of this invention, through digital logic circuit control, effectively improves the speed and accuracy of time-encoded information, enhances the noise robustness and stability of the nervous system, and performs better when facing competition from a large number of neurons. Furthermore, the memristor LIF neuron and WTA learning mechanism circuit of this invention use very few components, which is beneficial for increasing the integration density of neuromorphic chips. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is the LIF neuron circuit based on memristors in this embodiment, where N3, N4, E1 and their wires within the dashed box belong to part of the WTA circuit.

[0026] Figure 2 This is the packaged circuit of the memristor LIF neuron circuit in this embodiment.

[0027] Figure 3 This is the WTA circuit in this embodiment.

[0028] Figure 4 These are the input pulse and output spike pulse curves of the memristor LIF neuron in this embodiment.

[0029] Figure 5 This is the output pulse spike modulation curve of the memristor LIF neuron under different inputs in this embodiment.

[0030] Figure 6 This is the output pulse curve of the WTA circuit in this embodiment under the competition of three neurons. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] The purpose of this embodiment is to provide an integrated memristor LIF neuron circuit and WTA learning mechanism circuit that have low area cost after integration, good real-time performance, and adjustable excitation spike pulses and refractory periods.

[0033] This embodiment includes two circuits: a memristor LIF neuron circuit and a WTA circuit. The memristor LIF neuron circuit used for regulating the peak range of the spiking neural network includes: a membrane potential accumulation circuit, a waveform shaping circuit, a leakage circuit, a pulse generation circuit, and a refractory period circuit. The WTA learning mechanism circuit includes: a dual-switching circuit and logic gate circuits.

[0034] The memristor-controlled LIF neuron with excitation range modulation consists of one memristor, five MOS transistors, two resistors, and one capacitor. The WTA circuit in this embodiment consists of 1*N diodes, 2*N NMOS transistors, and one OR logic gate, where N represents the number of competing neurons.

[0035] In this embodiment, the membrane potential accumulation circuit in the LIF neuron circuit is connected to the leakage circuit. The output of the membrane potential accumulation circuit is connected to the input of the waveform shaping circuit. The waveform shaping circuit converts the analog signal generated by the membrane potential into a digital signal and shapes it. The output of the waveform shaping circuit is connected to the input of the pulse generation circuit. The output of the pulse generation circuit is connected to the refractory period circuit, and the output of the refractory period circuit is connected to the input of the membrane potential accumulation circuit.

[0036] Each memristor LIF neuron includes a current input terminal Iin and a voltage output terminal Vout.

[0037] In a memristor LIF neuron, the first-stage inverter consists of two MOS transistors, N1 and P1, and the second-stage inverter consists of two MOS transistors, N2 and P2.

[0038] The membrane potential accumulation circuit is implemented by a capacitor C1. The input signal is accumulated by the capacitor C1. When the membrane potential VC is accumulated to the voltage threshold of the N1 transistor in the first-stage inverter, N1 is turned on to generate a square wave signal.

[0039] The leakage circuit is implemented by resistor R1. When the capacitor voltage VC does not reach the voltage threshold of N1, the membrane voltage will leak to the resting potential or wait for the next signal.

[0040] The waveform shaping circuit consists of four MOSFETs: N1, P1, N2, and P2. N1 and P1 are connected to form a single-stage inverter. When the membrane potential is below the threshold voltage of N1, P1 is turned on, and the inverter output is high. When the membrane potential reaches the threshold voltage of N1, N1 is turned on, and the inverter output is low. This converts the analog voltage of the membrane potential into a square wave signal for the digital circuit. The output of the single-stage inverter is connected to the gates of N2 and P2, controlling their operating states. When the output of the single-stage inverter is high, N2 is turned on. Since the source of N2 is connected to a negative voltage, the waveform shaping circuit outputs a stable negative voltage. When the output of the single-stage inverter is low, P2 is turned on, and the waveform shaping circuit outputs a stable positive voltage.

[0041] The pulse generation circuit consists of a memristor M and a resistor R2. The memristor is a non-linear threshold memristor. The square wave voltage signal output by the waveform shaping circuit causes a change in the resistance of the memristor. When the resistance exceeds the positive threshold of the memristor, the resistance of M gradually decreases to a low-resistance state Ron. As the resistance of memristor M decreases, the voltage across resistor R2 gradually increases, and the output pulse potential Vout gradually increases, generating a spike pulse signal. This can be regarded as the rise of biological action potential, i.e., the depolarization process.

[0042] The refractory period circuit is implemented using a P3 transistor. When the pulse generation circuit does not output a spike pulse signal, the P3 transistor is not conducting, and the current at the neuron's input terminal flows to the membrane potential accumulation circuit. After the pulse generation circuit generates an output spike pulse signal, the P3 transistor conducts, and the current at the neuron's input terminal flows to ground. During the conduction period of the P3 transistor, the neuron's capacitance C1 does not integrate, similar to the refractory period of a biological neuron. The duration of the refractory period can be controlled by the threshold voltage of the P3 transistor.

[0043] The WTA circuit in this embodiment needs to be used in conjunction with memristor LIF neurons. The WTA circuit consists of a dual-switch circuit and logic gate circuits.

[0044] The dual-switching circuit consists of two MOSFETs, N3 and N4. The drain of MOSFET N3 is connected to the source of MOSFET N4. The gate of MOSFET N3 serves as the input of the dual switch, and the gate of MOSFET N4 is connected to the output of the inverter in the aforementioned neuron waveform shaping circuit.

[0045] The logic gate circuit consists of diodes and OR gates. The waveform shaping circuit in the competing neurons is connected to a diode and then to one input of the OR gate, while the other input of the OR gate is grounded. The output of the logic gate circuit is connected to the input of the double switch in the competing neurons.

[0046] The WTA circuit operates as follows: When the neuron is in a resting state, the output of the first-stage inverter of the waveform shaping circuit is at a high level, and the output of the waveform shaping circuit is at a low level. In the dual-switch circuit, transistor N4 is turned on. The control terminal of transistor N3 is jointly controlled by the output of the waveform shaping circuit of the competing neurons. Because one end of the OR logic gate in the above logic gate circuit is grounded and at a low level, the output of the OR logic gate and the output of the waveform shaping circuit of the neuron jointly control transistor N3. In the resting state, transistor N3 is not turned on.

[0047] When one of the competing neurons receives the signal first, the output of the inverter in that neuron changes from high to low, and transistor N4 is cut off. The output of the waveform shaping circuit in the neuron is high, the output of the logic gate circuit is high, and transistor N3 is turned on. Since the other competing neurons have not received the signal or have received the signal later, their transistors N4 and N3 are turned on, and the input current is directly grounded, so they cannot generate membrane potential integration and therefore will not generate a spike pulse signal.

[0048] Figure 1 This is a hardware implementation circuit diagram of the LIF neuron circuit based on memristors in this embodiment, as shown below. Figure 1 As shown, the potential across capacitor C1 is considered as the cell membrane potential of the neuron and is used to integrate the input current.

[0049] P1, P2, and P3 are P-type MOS transistors, while N1, N2, N3, and N4 are N-type MOS transistors. N1 and P1 form a first-stage inverter, and N2 and P2 form a second-stage inverter. The switching threshold of transistor N1 is the threshold of the neuron.

[0050] The output of the first-stage inverter serves as an external control terminal for the dual switch in the WTA circuit, determining the increase and cutoff of the neuron's membrane potential. The output voltage of the second-stage inverter affects the resistance of the memristor M. Resistor R2 is connected in series with the memristor, and the pulse voltage Vout obtained through voltage division is used as the neuron's output. The neuron's output voltage controls the on / off state of P3, determining the neuron's refractory period.

[0051] Figure 1In the circuit, the sources of P1 and P2 are connected to +Vcc, the source of N2 is connected to -Vdd, and one end of R2 is connected to the memristor M. The other end is connected to +Vcc. In the resting state, the potential across the capacitor is 0, P1 is turned on, and the output potential of the first-stage inverter is +Vcc. N2 is turned on, and the output potential of the second-stage inverter is -Vdd. The memristor M is in a high-resistance state Roff, and the voltage across resistor R2 is negligible. The output pulse Vout is almost 0V, and the voltage drop across M is approximately -Vdd, reaching the inversion threshold of the memristor. At this point, the memristor value has reached its maximum value and will not change. P2, P3, and N1 are in the off state, and the neuron membrane potential C1 waits for the signal to arrive and accumulates charge.

[0052] The input current Iin is the weighted sum of the inputs received by the neuron from its connected pre-neurons. When a signal enters the neuron Iin, as the charge is integrated across capacitor C1, the voltage across C1, if not exceeding the threshold of N1, will flow to ground through resistor R1. Figure 1 As shown in the third signal of the Iin curve, the capacitor voltage Vc slowly releases. If the voltage of capacitor C1 exceeds the threshold of N1, N1 will conduct, and the first-stage inverter will output a square wave signal from 0 to +Vcc, while the second-stage inverter will output a high level of approximately +Vcc. Here, the first-stage inverter outputs +Vcc when at rest and 0V after reaching the threshold, while the second-stage inverter outputs -Vdd when at rest and +Vcc after reaching the threshold. Then, the memristor will exceed the threshold voltage, and the resistance of memristor M will gradually decrease to the low-resistance state Ron. As the resistance of the memristor decreases, the voltage division of resistor R2 gradually increases, the potential of the output Vout gradually increases, and the neuron generates a spike pulse.

[0053] Figure 4 As shown, as the output pulse potential gradually increases, the capacitor charge is gradually released, and its potential gradually decreases. The potentials of the first and second stage inverters rapidly reverse, and the waveform shaping circuit outputs -Vdd. The instant of reversal forms a drop in the action potential. The voltage across the memristor M exceeds its reverse threshold, and the memristor value gradually increases to the high-resistivity state Roff. Simultaneously, the voltage across resistor R2 gradually decreases from its negative maximum value until it becomes negligible, and the output pulse Vout slowly rises from its negative minimum value until it returns to the initial potential. When the excitation spike reaches the threshold of P3, P3 conducts, and the capacitor charge is rapidly released. During the conduction of P3, when the neuron receives the Iin signal again, the capacitor no longer integrates the charge. This achieves the refractory period of the biological neuron. The neuron cannot respond to new inputs or generate new pulses. Finally, the circuit returns to the initial state, waiting for a new round of input. The duration of the refractory period is controlled by the threshold voltage of P3.

[0054] Figure 2 The image shows the... Figure 1The memristor LIF neuron circuit and part of the WTA circuit are packaged into a single circuit diagram. The aforementioned memristor LIF neuron has only two interfaces: input Iin and output Vout. Figure 1 N2 and N3 shown are examples of WTA circuit components. Interfaces D1 and E1 are also WTA circuit interfaces.

[0055] Figure 3 The diagram illustrates a WTA implementation scheme involving multiple neurons competing for power. When a neuron is in a resting state, the output of the first-stage inverter in the waveform shaping circuit is at +Vcc, and the output of the waveform shaping circuit is -Vdd. The N4 transistor in the dual-switch circuit is turned on, and the control terminal of the N3 transistor is jointly controlled by the outputs of the waveform shaping circuits of the competing neurons. Because one end of the OR logic gate in the logic gate circuit is grounded and at a low level, the output of the OR logic gate and the output of the waveform shaping circuit of the neuron jointly control the N3 transistor. In the resting state, the N3 transistor is not turned on. The neuron's capacitor C1 waits for a signal to arrive for integration. When one of the competing neurons receives a DC square wave current signal first, the output of the first-stage inverter in that neuron changes from +Vcc to 0V, and the N4 transistor is turned off. The output of the second-stage inverter changes from the resting -Vdd to +Vcc. The waveform shaping circuit and logic gate in the neuron both output +Vcc. When N3 is on, the winning neuron's N4 transistor is off, and N3 is on, allowing the neuron's capacitor to function normally. A diode at the E1 port of each competing neuron provides unidirectional conduction to prevent signal interference to other neurons' E1 ports. Since other neurons in the competition either do not receive a signal or receive a signal afterward, their N4 and N3 transistors are on, and the input current is directly grounded, preventing membrane potential integration and thus avoiding the generation of spike pulse signals.

[0056] Figure 4 It refers to the charging and discharging process of the neuron's capacitor voltage Vc and the voltage change process of the neuron's output peak Vout when the input signal is a DC square wave current Iin.

[0057] Figure 5 This describes the charging and discharging process of the neuron's capacitor voltage Vc, and the voltage change process of the neuron's output peak Vout, within the range of a DC square wave current input signal of 24us to 35us. The neuron's input signal needs to be within the range of a DC square wave current of 24us to 35us, but is not limited to what is shown in the figure.

[0058] Figure 6The diagram illustrates the three neurons competing for the first time: S1 receives a DC square wave current signal at 10µs, S2 at 20µs, and S3 at 15µs. Neuron S1, at 10µs, wins, firing a spike signal and inhibiting the firing of the other two neurons. In the second competition, S1 receives a DC square wave current signal at 170µs, S2 at 150µs, and S3 at 160µs. Neuron S2, at 150µs, wins, firing a spike signal and inhibiting the firing of the other two neurons. In the third competition, S1 receives a DC square wave current signal at 320µs, S2 at 310µs, and S3 at 300µs. Neuron S3, at 300µs, wins, firing a spike signal and inhibiting the firing of the other two neurons. Using this scheme as an example, the neuronal WTA learning mechanism of this invention requires the competing neurons to fire spike pulses of the same size, with an accuracy down to 1µs.

[0059] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A LIF neuron-based WTA circuit, characterized by, The LIF neuron circuit includes a plurality of simultaneously participating competitive LIF neuron circuits, a number of double switch circuits equal to the number of LIF neuron circuits, and a logic gate circuit. The LIF neuron circuit includes an input terminal, a membrane potential accumulation unit, a waveform shaping unit, a pulse generation unit, a refractory period unit and an output terminal connected in sequence. The input terminal of the input terminal is connected to the input terminal of the membrane potential accumulation unit, and the input current is integrated by the membrane potential accumulation unit. The output terminal of the membrane potential accumulation unit is connected to the input terminal of the waveform shaping unit to output the voltage reaching the preset threshold to the waveform shaping unit. The output terminal of the waveform shaping unit is connected to the pulse generation unit to output the digital signal converted and shaped from the analog signal generated by the membrane potential accumulation unit. The waveform shaping unit includes a first inverter and a second inverter. The input terminal of the first inverter is connected to the membrane potential accumulation unit through a leakage unit, and immediately changes from outputting positive voltage to outputting 0 voltage after receiving the voltage reaching the preset threshold, thereby outputting a square wave signal between positive voltage and 0 to the second inverter. The second inverter immediately changes from outputting negative voltage to outputting positive voltage after receiving 0 voltage, thereby outputting a square wave signal between negative voltage and positive voltage. The output terminal of the pulse generation unit serves as the output terminal of the LIF neuron circuit to generate a spike pulse output based on the received digital signal, and is also connected to the refractory period unit to control the refractory period unit. The output terminal of the refractory period unit is connected to the input terminal of the membrane potential accumulation unit to control the input of the membrane potential accumulation unit. The double switch circuit includes a first control terminal and a second control terminal, wherein the first control terminal is connected to the output terminal of the first inverter of the waveform shaping unit in the LIF neuron circuit, the second control terminal is connected to the output terminal of the logic gate circuit, and the output terminal of the double switch circuit is connected to the membrane potential accumulation unit to control the membrane potential accumulation unit to start or stop integration. The input terminal of the logic gate circuit is connected to the output terminal of the waveform shaping circuit in all participating competitive LIF neuron circuits, and the output terminal of the logic gate circuit controls the membrane potential accumulation unit of each LIF neuron circuit to start or stop integration together with each double switch circuit.

2. The WTA circuit based on LIF neuron according to claim 1, wherein, The leakage unit is arranged between the membrane potential accumulation unit and the waveform shaping unit to enable the membrane potential accumulation unit to output the voltage reaching the preset threshold to the waveform shaping unit through the leakage unit.

3. The LIF neuron-based WTA circuit according to claim 2, wherein, The membrane potential accumulation unit includes a capacitor, one end of the capacitor is connected between the current input terminal and the waveform shaping unit, and the other end is grounded; the leakage unit includes a leakage resistor, one end of the leakage resistor is connected between the membrane potential accumulation unit and the waveform shaping unit, and the other end is grounded.

4. The WTA circuit based on LIF neuron according to claim 2, wherein, The first inverter includes a first NMOS tube and a first PMOS tube; the gates of the first NMOS tube and the first PMOS tube are connected to each other and connected to the membrane potential accumulation unit through the leakage unit; the drain of the first NMOS tube and the drain of the first PMOS tube are connected; the source of the first NMOS tube is grounded, and the source of the first PMOS tube is connected to a positive voltage. The second inverter comprises a second NMOS transistor and a second PMOS transistor; the gates of the second NMOS transistor and the second PMOS transistor are connected to each other and connected to the membrane potential accumulation unit through a leakage unit; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor; the source of the second NMOS transistor is connected to a negative voltage, and the source of the second PMOS transistor is connected to a positive voltage.

5. The LIF neuron based WTA circuit according to claim 1, wherein, The pulse generation unit comprises a pulse unit memristor and a pulse unit resistor; the input end of the pulse unit memristor is connected to the output end of the waveform shaping unit; the output end of the pulse unit memristor is connected to the refractory period unit as a voltage output end; one end of the pulse unit resistor is connected to the output end of the pulse unit memristor, and the other end of the pulse unit resistor is connected to a positive voltage.

6. The LIF neuron-based WTA circuit according to claim 1, wherein, The refractory period unit comprises a refractory period unit PMOS transistor; the gate of the refractory period unit PMOS transistor is connected to the pulse generation unit; the drain of the refractory period unit PMOS transistor is connected between the current input end and the membrane potential accumulation unit; and the source of the refractory period unit PMOS transistor is connected to the ground.

7. The LIF neuron-based WTA circuit according to claim 1, wherein, The double switch circuit comprises a third NMOS transistor and a fourth NMOS transistor; the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor; the source of the third NMOS transistor is connected to the ground; the drain of the fourth NMOS transistor is connected to the membrane potential accumulation unit; the gate of the third NMOS transistor is connected to the output end of the logic gate circuit; and the gate of the fourth NMOS transistor is connected to the output end of the first inverter of the waveform shaping unit in the LIF neuron circuit.

8. The LIF neuron based WTA circuit according to claim 1, wherein, The logic gate circuit comprises a number of diodes equal to the number of LIF neuron circuits and a logic OR gate; the input end of each diode is connected to the output end of the second inverter of the waveform shaping unit in a corresponding LIF neuron circuit; the output end of each diode is connected to one of the input ends of the logic OR gate; the other input end of the logic OR gate is connected to the ground; and the output end of the logic OR gate is connected to the second control end of the double switch circuit.

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