LDMOS device and method of manufacturing the same

Abstract

The application discloses an LDMOS device and a manufacturing method thereof. The device comprises a high-resistance substrate of a first conductive type, a semiconductor layer, an insulating layer, a gate, a first metal layer and a second metal layer. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The second semiconductor layer comprises a body region, a drift region, a source region and a drain region. The source region is arranged in the body region and is in contact with the body contact region. The drain region is arranged in the drift region. The first semiconductor layer comprises a first region and a second region. The first region forms a pn junction with the substrate. The second region is distributed below the source region. The first metal layer is arranged on the insulating layer. The second metal layer is arranged on the second surface of the substrate. The first metal layer comprises source region metal and drain region metal which are electrically isolated from each other. The source region metal is further electrically connected with the second metal layer through a third conductive via. The third conductive via is electrically isolated from the first region. The device structure provided by the application effectively reduces the capacitance of the LDMOS device and reduces the leakage current.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, particularly to the field of power semiconductor devices used in communication base stations, industrial, scientific and medical instruments, radio frequency power equipment, etc., and especially relates to an LDMOS device and its fabrication method. Background Technology

[0002] Si-based LDMOS devices are currently the mainstream LDMOS devices. The bandgap of Si material is 1.1 eV, which is smaller than that of SiC material (3.2 eV). Therefore, the specific on-resistance and breakdown voltage of SiC-based LDMOS devices are significantly higher than those of Si-based LDMOS devices. Considering the same breakdown voltage design, the drift region length of SiC devices is greatly reduced, resulting in superior output capacitance density, output power density, and other performance characteristics compared to Si-based LDMOS devices. Simultaneously, the overall device size is also significantly reduced, leading to higher chip integration and lower cost per chip. The thermal conductivity of SiC material (4 W / cm·K⁻¹) is higher than that of Si material (1.3 W / cm·K⁻¹). Furthermore, SiC-based LDMOS utilizes a homoepitaxial process, avoiding heterogeneous interface thermal resistance. Therefore, SiC-based LDMOS devices exhibit excellent chip heat dissipation capabilities, offering significant advantages in high-power, high-current chip applications. Additionally, the high lattice quality produced by the homoepitaxial process greatly improves the yield and reliability of SiC-based LDMOS device applications.

[0003] However, current SiC-based LDMOS devices generally use n-type substrates. LDMOS devices prepared in this way typically have low n-type substrate resistance, large device capacitance, high device loss under high-frequency operating conditions, and a serious risk of leakage during operation. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide an LDMOS device and a method for fabricating the same.

[0005] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0006] In a first aspect, the present invention provides an LDMOS device, characterized in that it comprises a high-resistivity substrate of a first conductivity type, a semiconductor layer, an insulating layer, a gate, a first metal layer, and a second metal layer;

[0007] The semiconductor layer includes a first semiconductor layer and a second semiconductor layer sequentially disposed on a first surface of the substrate;

[0008] The second semiconductor layer includes a body region, a drift region, a source region, and a drain region. The source region is disposed within the body region and is in contact with the body contact region therein. The drain region is disposed within the drift region.

[0009] The first semiconductor layer includes a first region of a second conductivity type and a second region of a first conductivity type. The first region cooperates with the substrate to form a pn junction, and the second region is distributed below the source region and in contact with the substrate.

[0010] The gate is disposed within the insulating layer, the first metal layer is disposed on the insulating layer, and the second metal layer is disposed on the second surface of the substrate opposite to the first surface. The first metal layer includes a source metal and a drain metal that are electrically isolated from each other. The source metal is electrically connected to both the source region and the body contact region through a first conductive via penetrating the insulating layer. The source metal is also electrically connected to the second metal layer through a third conductive via that continuously penetrates the insulating layer, the semiconductor layer, and the substrate along the thickness direction. The drain metal is electrically connected to the drain region through a second conductive via penetrating the insulating layer.

[0011] The third conductive via is electrically isolated from the first region.

[0012] Secondly, the present invention also provides a method for fabricating the above-mentioned LDMOS device, comprising:

[0013] In the step of fabricating a first semiconductor layer on a first surface of a substrate of a first conductivity type, the first semiconductor layer includes a first region of a second conductivity type and a second region of the same first conductivity type. The first region forms a pn junction with the substrate, and the second region is distributed below the source region and in contact with the substrate.

[0014] The step of fabricating a second semiconductor layer on the first semiconductor layer.

[0015] The step of fabricating the gate on the second semiconductor layer

[0016] The steps of forming a body region, a drift region, a source region, a body contact region, and a drain region in the second semiconductor layer.

[0017] The step of forming an insulating layer on the second semiconductor layer

[0018] The steps of fabricating a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via in the insulating layer.

[0019] The step of forming the first metal layer on the insulating layer,

[0020] The step of forming a second metal layer on the second surface of the substrate.

[0021] Based on the above technical solution, compared with the prior art, the beneficial effects of the present invention include at least the following:

[0022] The LDMOS device provided by this invention employs a semi-insulating, high-resistivity substrate, effectively reducing device capacitance and high-frequency losses. A first semiconductor layer, forming a reverse pn junction with the substrate, is disposed between the substrate and the second semiconductor layer, effectively reducing leakage current in the substrate direction. Simultaneously, the second region can assist in depleting the n-type epitaxial layer of the first region under high voltage conditions, increasing the device's breakdown voltage. Furthermore, the source region metal is connected to the second metal layer on the substrate surface via conductive vias, grounding the source region and ensuring normal device operation. Additionally, electrical isolation between the conductive vias and the first region significantly reduces leakage current from the drain region through the first region to the conductive vias. This effectively reduces leakage current and device capacitance in the LDMOS device, improving its operating performance parameters and reliability.

[0023] The above description is merely an overview of the technical solution of the present invention. In order to enable those skilled in the art to better understand the technical means of this application and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described below in conjunction with detailed drawings. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of an LDMOS device provided in a typical embodiment of the present invention;

[0025] Figure 2 This is a partial flowchart illustrating the fabrication method of an LDMOS device provided in a typical embodiment of the present invention;

[0026] Figure 3 This is a partial flowchart illustrating the fabrication method of an LDMOS device provided in a typical embodiment of the present invention;

[0027] Figure 4 This is a partial flowchart illustrating the fabrication method of an LDMOS device provided in a typical embodiment of the present invention;

[0028] Figure 5 This is a partial flowchart illustrating the fabrication method of an LDMOS device provided in a typical embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of the structure of an LDMOS device provided in another typical embodiment of the present invention;

[0030] Explanation of reference numerals in the attached figures: 11, second metal layer; 12, substrate; 13, first region; 14, drain region; 15, third conductive via; 16, second region; 17, body contact region; 18, body region; 19, source region; 110, drift region; 111, leakage protection zone;

[0031] 20. First metal layer; 21. Second conductive via; 22. First conductive via; 23. Fourth conductive via; 24. Drift field plate; 25. Gate; 26. Gate bottom oxide layer. Detailed Implementation

[0032] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0033] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0034] Moreover, relational terms such as “first” and “second” are used merely to distinguish one component or method step from another that has the same name, and do not necessarily require or imply any such actual relationship or order between these components or method steps.

[0035] The English abbreviations, their corresponding meanings, and full names used in this invention are as follows:

[0036] LDMOS: Lateral Double Diffusion Metal Oxide Semiconductor;

[0037] TSV: Through Silicon Via (In this invention, it can refer not only to a through-hole that penetrates silicon, but also to a through-hole that penetrates other materials).

[0038] See Figure 1 The first embodiment of the present invention provides an LDMOS device, including a high-resistivity substrate 12 of a first conductivity type, a semiconductor layer, an insulating layer, a gate 25, a first metal layer 20, and a second metal layer 11.

[0039] The semiconductor layer includes a first semiconductor layer and a second semiconductor layer sequentially disposed on the first surface of the substrate 12.

[0040] The second semiconductor layer includes a body region 18, a drift region 110, a source region 19, and a drain region 14. The source region 19 is disposed within the body region 18 and is in contact with the body contact region 17 therein. The drain region 14 is disposed within the drift region 110.

[0041] The first semiconductor layer includes a first region 13 of a second conductivity type and a second region 16 of a first conductivity type. The first region 13 forms a pn junction with the substrate 12, and the second region 16 is distributed below the source region 19 and is in contact with the substrate 12.

[0042] The gate 25 is disposed within the insulating layer, the first metal layer 20 is disposed on the insulating layer, and the second metal layer 11 is disposed on the second surface of the substrate 12 opposite to the first surface. The first metal layer 20 includes a source metal and a drain metal that are electrically isolated from each other. The source metal is electrically connected to the source region 19 and the body contact region 17 through a first conductive via 22 penetrating the insulating layer. At the same time, the source metal is also electrically connected to the second metal layer 11 through a third conductive via 15 that continuously penetrates the insulating layer, the semiconductor layer, and the substrate 12 along the thickness direction. The drain metal is electrically connected to the drain region 14 through a second conductive via 21 penetrating the insulating layer.

[0043] The third conductive via 15 is electrically isolated from the first region 13.

[0044] In this embodiment, the method for electrically isolating the third conductive via 15 from the first region 13 is as follows:

[0045] The second region 16 and the body region 18 are separated by a local area of ​​the first region 13. The semiconductor layer also includes a leakage protection zone 111 of a first conductivity type. The leakage protection zone 111 is disposed on one side of the semiconductor layer in the radial direction and close to the body region 18. The third conductive via 15 continuously penetrates the insulating layer, the leakage protection zone 111, and the substrate 12 in the thickness direction, and the third conductive via 15 does not contact the circumferential sidewall of the leakage protection zone 111. The leakage protection principle of the leakage protection zone 11 is that it forms a PN junction with the first region 13 in the first semiconductor layer. When the drain region 14 is pressurized, the PN junction is reverse biased and cannot conduct, thereby preventing leakage from the drain region 14 to the third conductive via 15. The specific leakage protection capability (i.e., how much voltage it can prevent) can be adaptively adjusted by adjusting the ion implantation concentration of the leakage protection zone 11.

[0046] Based on the above implementation scheme, the LDMOS device provided in this embodiment uses a semi-insulating high-resistivity substrate 12, which effectively reduces the device capacitance and reduces the high-frequency loss of the device. A first semiconductor layer forming a reverse pn junction with the substrate 12 is provided between the substrate 12 and the second semiconductor layer, which effectively reduces the leakage current in the direction of the substrate 12. At the same time, the second region 16 can help deplete the n-type epitaxy of the first region 13 under high voltage, thereby increasing the breakdown voltage of the device. The source region metal and the second metal layer 11 on the surface of the substrate 12 are connected through conductive vias. Meanwhile, the conductive vias and the first region 13 are electrically isolated, which significantly reduces the leakage current between the drain region 14 and the conductive vias through the first region 13.

[0047] In some embodiments, the first conductivity type is p-type and the second conductivity type is n-type. Furthermore, as a preferred embodiment of the above embodiments, the substrate 12 may include a p-type SiC high-resistivity substrate 12.

[0048] In some embodiments, a drift field plate 24 is further disposed within the insulating layer. A first portion of the drift field plate 24 is adjacent to the drift region 110, and a second portion connected to the first portion extends around the gate 25 to above the gate 25. The second portion is electrically connected to the source region metal through a fourth conductive via 23 disposed within the insulating layer. Thus, the drift field plate 24 is connected to the source region metal through the fourth conductive via 23, ensuring that the drift field plate 24 is grounded and has a zero voltage, preventing the gate 25 from being affected and turned on when a high voltage is applied to the drain region 14. That is, there is a zero-potential field plate on one side of the gate 25, pinning the high potential and preventing voltage from being applied to the gate 25, which would cause the gate 25 to be turned on erroneously.

[0049] In some implementations, the gate 25 may be isolated from the body region 18 via a gate bottom oxide layer 26.

[0050] As a typical application example, this embodiment presents a SiC-based LDMOS device and proposes a specific fabrication method. The invention uses a p-type high-resistivity SiC substrate 12 as the device substrate 12. An n-type SiC epitaxial layer is fabricated on the substrate 12. Within the epitaxial layer, various regions of the device (including the aforementioned first region 13, second region 16, body region 18, drift region 110, source region 19, drain region 14, and the contact region of the body region 18) are further fabricated, ultimately forming the entire device. A reverse pn junction is formed between the substrate 12 and the epitaxial layer (first region 13), which significantly reduces leakage current in the substrate 12 direction. Simultaneously, due to the use of the high-resistivity substrate 12, the device capacitance is reduced, thereby reducing the high-frequency loss of the device.

[0051] Furthermore, a p-well region (i.e., the second region 16, hereinafter the same) is fabricated within the epitaxial layer according to specific process conditions. The p-well region will deplete the auxiliary epitaxial layer under high voltage conditions, thereby improving the breakdown voltage of the device. This p-well region also serves as a lower field plate, which can optimize the internal electric field of the device and improve the device's ability to resist hot carrier injection effects.

[0052] Furthermore, a p-type leakage protection zone 111 is prepared in the epitaxial layer according to the specific process conditions. This zone completely encloses the TSV structure in the epitaxial layer (i.e., the third conductive via 15 mentioned above, the same below), which will block the leakage current from the leakage region 14 through the epitaxial layer to the TSV structure, thereby improving the device performance parameters and reliability.

[0053] See Figures 2-5 The document illustrates a method for fabricating an LDMOS device according to any of the above embodiments of this example, specifically including the following steps:

[0054] The step of fabricating a first semiconductor layer on a first surface of a substrate 12 of a first conductivity type, wherein the first semiconductor layer includes a first region 13 of a second conductivity type and a second region 16 of a first conductivity type, the first region 13 forming a pn junction with the substrate 12, and the second region 16 being distributed below the source region 19 and in contact with the substrate 12.

[0055] The step of fabricating a second semiconductor layer on the first semiconductor layer.

[0056] The step of fabricating gate 25 on the second semiconductor layer.

[0057] The steps of forming a body region 18, a drift region 110, a source region 19, a body contact region 17, and a drain region 14 in the second semiconductor layer.

[0058] The step of forming an insulating layer on the second semiconductor layer.

[0059] The steps of fabricating the first conductive via 22, the second conductive via 21, the third conductive via 15, and the fourth conductive via 23 in the insulating layer.

[0060] The step of forming a first metal layer 20 on the insulating layer.

[0061] The step of forming a second metal layer 11 on the second surface of the substrate 12.

[0062] The method further includes the step of forming a leakage protection zone 111 that is located on one side of the first semiconductor layer and the second semiconductor layer in the radial direction and close to the body region 18, and whose two ends are respectively connected to the insulating layer and the substrate 12 in the thickness direction of the substrate 12. The third conductive via 15 continuously penetrates the insulating layer, the leakage protection zone 111 and the substrate 12 in the thickness direction, and the third conductive via 15 has no contact with the circumferential sidewall of the leakage protection zone 111.

[0063] As a typical application example, the fabrication method of the above-mentioned LDMOS device can be implemented by adopting a fabrication method including the following key steps and processes:

[0064] Step 1: As Figure 3 As shown, an n-type epitaxial layer is prepared on a p-type high-resistivity substrate 12. When preparing the n-type epitaxial layer, the p-well region is selected according to the specific process conditions. A gate bottom oxide layer 26 and a polysilicon gate 25 are further prepared on the epitaxial layer.

[0065] Step Two: As Figure 4 As shown, the main regions of the device, such as source region 19, drain region 14, body region 18, contact region of body region 18, and drift region 110, are fabricated in the epitaxial layer. If the p-well region is not fabricated in step one, the p-well region in the epitaxial layer is fabricated in this step.

[0066] Step 3: As Figure 5 As shown, a field plate is fabricated near the polysilicon gate.

[0067] Step Four: As Figure 6 As shown, a dielectric layer, vias, metal, and TSV structure are fabricated.

[0068] Compared to existing devices, the device structure provided by the first embodiment described above can significantly reduce the capacitance of the device and improve its performance by adjusting the doping concentration of the substrate 12; it can also significantly improve the withstand voltage by adjusting the size and doping concentration of the second region 16.

[0069] Based on the same technical concept, the present invention also provides another embodiment. Figure 1 This is a cross-sectional view of the device according to the first embodiment of the present invention. Figure 6 This is a cross-sectional view of the device according to the second embodiment of the present invention. The difference between the two embodiments lies in the implementation method of the aforementioned leakage protection. In the first embodiment, leakage protection is achieved by using a p-type leakage protection zone 111 that wraps around the TSV structure, while in the second embodiment, leakage protection is achieved by using the second region 16 and the body region 18 to fully wrap around the TSV structure.

[0070] See also Figure 6This illustrates the device structure of a second embodiment of the present invention. In this embodiment, the LDMOS device is essentially the same as that in Embodiment 1, except that:

[0071] Instead of the aforementioned leakage protection zone 111, the second region 16 is in contact with the body region 18; the third conductive via 15 continuously penetrates the insulating layer, body region 18, second region 16 and substrate 12 along the thickness direction, and the third conductive via 15 does not contact the circumferential sidewalls of the body region 18 and the second region 16.

[0072] The fabrication method of the device in this embodiment is basically similar to that in Embodiment 1, with the only difference being:

[0073] The step of creating the leakage protection zone 111 is missing. When forming the epitaxial layer and creating each region, the formed body region 18 is in direct contact with the second region 16. The third conductive via 15 continuously penetrates the insulating layer, body region 18, second region 16 and substrate 12 along the thickness direction, and the third conductive via 15 is not in contact with the circumferential sidewalls of the body region 18 and the second region 16.

[0074] Compared to existing devices, the device structure provided by the second embodiment described above can significantly reduce the capacitance of the device and improve its performance by adjusting the doping concentration of the substrate 12; it can also significantly improve the withstand voltage by adjusting the size and doping concentration of the second region 16.

[0075] Based on the above embodiments, this invention fabricates SiC-based LDMOS devices by growing an n-type epitaxial layer on a p-type high-resistivity SiC substrate 12, which can reduce leakage current and high-frequency substrate 12 losses during device operation. A p-well region is fabricated in the epitaxial layer at the device source end, which can improve the device's breakdown voltage as needed, while also improving the hot carrier injection effect. A p-type leakage protection zone 111 completely enclosing the TSV is fabricated in the epitaxial layer, or a structure is achieved by completely enclosing the source-end TSV together with the p-well region and body region 18, thereby reducing leakage current from the drain region 14 through the epitaxial layer to the TSV. This invention effectively reduces leakage current and device capacitance in SiC LDMOS devices, improving the operating performance parameters and reliability of SiC-based LDMOS devices.

[0076] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. An LDMOS device, characterized in that, It includes a high-resistivity substrate of a first conductivity type, a semiconductor layer, an insulating layer, a gate, a first metal layer, and a second metal layer; The semiconductor layer includes a first semiconductor layer and a second semiconductor layer sequentially disposed on a first surface of the substrate; The second semiconductor layer includes a body region, a drift region, a source region, and a drain region. The source region is disposed within the body region and is in contact with the body contact region therein. The drain region is disposed within the drift region. The first semiconductor layer includes a first region of a second conductivity type and a second region of a first conductivity type. The first region cooperates with the substrate to form a pn junction, and the second region is distributed below the source region and in contact with the substrate. The gate is disposed within the insulating layer, the first metal layer is disposed on the insulating layer, and the second metal layer is disposed on the second surface of the substrate opposite to the first surface. The first metal layer includes a source metal and a drain metal that are electrically isolated from each other. The source metal is electrically connected to both the source region and the body contact region through a first conductive via penetrating the insulating layer. The source metal is also electrically connected to the second metal layer through a third conductive via that continuously penetrates the insulating layer, the semiconductor layer, and the substrate along the thickness direction. The drain metal is electrically connected to the drain region through a second conductive via penetrating the insulating layer. The third conductive via is electrically isolated from the first region.

2. The LDMOS device according to claim 1, characterized in that, The second region and the body region are separated by a local area of ​​the first region; The semiconductor layer further includes a leakage protection zone of a first conductivity type, which is disposed on one side of the semiconductor layer in the radial direction and close to the body region. The third conductive via continuously penetrates the insulating layer, the leakage protection zone and the substrate in the thickness direction, and the third conductive via does not contact the circumferential sidewall of the leakage protection zone.

3. The LDMOS device according to claim 1, characterized in that, The second region is in contact with the body region; The third conductive via continuously penetrates the insulating layer, the body region, the second region, and the substrate along the thickness direction, and the third conductive via does not contact the circumferential sidewalls of the body region and the second region.

4. The LDMOS device according to any one of claims 1-3, characterized in that, The first conductivity type is p-type, and the second conductivity type is n-type.

5. The LDMOS device according to any one of claims 4, characterized in that, The substrate includes a P-type SiC high-resistivity substrate.

6. The LDMOS device according to any one of claims 1-3, characterized in that, A drift field plate is also provided inside the insulating layer; The first portion of the drift field plate is adjacent to the drift region, and the second portion connected to the first portion extends around the gate to above the gate; the second portion is electrically connected to the source region metal through a fourth conductive via disposed in the insulating layer.

7. The LDMOS device according to any one of claims 1-3, characterized in that, The gate and the body region are isolated by a gate bottom oxide layer.

8. A method for fabricating an LDMOS device as described in any one of claims 1-7, characterized in that, include: In the step of fabricating a first semiconductor layer on a first surface of a substrate of a first conductivity type, the first semiconductor layer includes a first region of a second conductivity type and a second region of the same first conductivity type. The first region forms a pn junction with the substrate, and the second region is distributed below the source region and in contact with the substrate. The step of fabricating a second semiconductor layer on the first semiconductor layer. The step of fabricating the gate on the second semiconductor layer The steps of forming a body region, a drift region, a source region, a body contact region, and a drain region in the second semiconductor layer. The step of forming an insulating layer on the second semiconductor layer The steps of fabricating a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via in the insulating layer. The step of forming the first metal layer on the insulating layer, The step of forming a second metal layer on the second surface of the substrate.

9. The manufacturing method according to claim 8, characterized in that, It also includes the step of forming a leakage protection zone that is located on one side of the first semiconductor layer and the second semiconductor layer in the radial direction and close to the body region, and is connected to the insulating layer and the substrate at both ends in the thickness direction of the substrate, respectively. The third conductive via continuously penetrates the insulating layer, the leakage protection zone, and the substrate along the thickness direction, and the third conductive via does not contact the circumferential sidewall of the leakage protection zone.

10. The manufacturing method according to claim 8, characterized in that, The formed body region is in direct contact with the second region; the third conductive via continuously penetrates the insulating layer, the body region, the second region and the substrate along the thickness direction, and the third conductive via is not in contact with the circumferential sidewalls of the body region and the second region.

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