A SENT protocol parsing device and its usage method based on active identifier carrier

Abstract

This invention proposes a SENT protocol parsing device and its usage method based on an active identifier carrier, belonging to the field of SENT protocol parsing technology. It includes a clock source CLK, a reset interface RESET, signal input interfaces SENT0-SENTN, an FPGA module, a serial input interface RXD, a serial output interface TXD, and a serial-to-RJ45 module. The clock source CLK generates an external clock signal and sends it to the FPGA module. The reset interface RESET changes the reset signal state when the device powers on or malfunctions. The signal input interfaces SENT0-SENTN send parallel SENT signals from N channels to the FPGA module. The serial input interface RXD receives control commands sent by the cloud platform through the serial-to-RJ45 module. The serial output interface TXD sends parsed data to the cloud platform through the serial-to-RJ45 module. The serial-to-RJ45 module sends and updates data to the cloud platform and receives control commands, thus realizing remote information sharing, monitoring, and feedback control.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of SENT protocol analysis, and particularly relates to a SENT protocol analysis device based on an active identification carrier and a use method. BACKGROUND

[0002] SENT (Single Edge Nibble Transmission) protocol is a point-to-point single edge nibble transmission protocol, which has the advantages of simple communication mode, fast transmission speed, high precision, no need of transmitter and receiver, etc., and is widely used in sensor signal output of automobiles and their power systems; Chinese patent CN109901628B "SENT protocol E-ACT bit control and speed measurement system and method" discloses a SENT protocol E-ACT bit control and speed measurement system and method using FPGA as a collection operation unit to perform local E-ACT sensor position control and speed measurement, but the method has limited processing capacity for multiple SENT signals, and cannot share remote information; Chinese patent CN113759846B "On-site active identification analysis method and system" discloses that the active identification carrier and the recursive node are connected by HTTP direct communication, and the traditional multi-level and multi-layer structure between the active identification carrier and the recursive node is reduced to a two-layer structure, but the method still uses analog quantity collection, which is not fast enough and has poor anti-interference performance.

[0003] Currently, the analysis of the SENT protocol is based on ECU or MCU, which uses an internal timer to measure the pulse width of the SENT protocol signal sent by the sensor (Tick), and calculates the Nibble according to the Tick, and finally the output data of a group of sensors is composed of the analyzed multiple Nibbles; but the timer of the ECU or MCU is generally in the us level, and the number of timers and external IO ports is limited, which cannot asynchronously poll or synchronously high-speed collect and analyze multiple SENT signals according to different response requirements, the data precision is not enough, and remote control, remote analysis and information remote sharing cannot be realized. SUMMARY

[0004] To solve the technical problems in the above background art, the present application provides a SENT protocol analysis device based on an active identification carrier and a use method, which solves the problems of single-channel analysis, low precision, poor anti-interference ability, inability to remotely control, remotely analyze and share information remotely of the existing SENT protocol.

[0005] The application provides a SENT protocol analysis device based on an active identification carrier, which comprises a clock source CLK, a reset interface RESET, a serial input interface RXD, a serial output interface TXD, a serial port to RJ45 module, signal input interfaces SENT0-SENTN, and an FPGA module.

[0006] The FPGA module is composed of a phase-locked loop unit PLL, an SOPC system, a pulse shaping unit, and a channel selection unit.

[0007] The clock source CLK is electrically connected with the FPGA module, and is used for generating an external clock signal and sending the external clock signal to the FPGA module.

[0008] The reset interface RESET is electrically connected with the FPGA module, and is used for changing a reset signal state when the device is powered on or abnormally.

[0009] The serial input interface RXD is electrically connected with the FPGA module, and is used for receiving a control command sent by a cloud platform through the serial port to RJ45 module.

[0010] The signal input interfaces SENT0-SENTN are electrically connected with the FPGA module, and are used for sending parallel SENT signals of N channels to the FPGA module.

[0011] The serial output interface TXD is electrically connected with the FPGA module, and is used for sending the analyzed data to the cloud platform through the serial port to RJ45 module.

[0012] The serial port to RJ45 module is electrically connected with the FPGA module, and is used for sending and updating data to the cloud platform and receiving a control command.

[0013] The phase-locked loop unit PLL is electrically connected with the clock source CLK and the SOPC system, and is used for receiving a clock source signal, improving the frequency of the clock signal, and sending the clock signal to the SOPC system.

[0014] Preferably, the pulse shaping unit is electrically connected with the signal input interfaces SENT0-SENTN and the channel selection unit, and is used for receiving multiple parallel SENT signals and completing shaping, and sending the multiple parallel SENT signals to the channel selection unit.

[0015] Preferably, the channel selection unit is electrically connected with the pulse shaping unit and the serial input interface RXD, and is used for receiving multiple parallel shaped SENT signals, and selecting one of the multiple parallel shaped SENT signals according to a control command input by the serial input interface RXD and sending the one of the multiple parallel shaped SENT signals to the SOPC system.

[0016] Preferably, the SOPC system is electrically connected with the channel selection unit, the serial output interface TXD and the serial input interface RXD, used for receiving the serial port control command sent by the serial port to RJ45 module, selecting one of the SENT signals according to the command requirement, and outputting the analysis result from the serial output interface TXD to the serial port to RJ45 module.

[0017] Preferably, the SOPC system comprises a NIOSII soft core, an AVALON bus, a UART controller, a TIMER controller, a PIO controller and an EPCS controller.

[0018] The UART controller, the TIMER controller, the PIO controller and the EPCS controller transmit information with the NIOSII soft core through the AVALON bus.

[0019] The UART controller is used for receiving the control command input by the serial input interface RXD, and exchanging, processing, analyzing and parsing the SENT signal with the NIOSII soft core through the AVALON bus, and the UART controller outputs the analysis result to the serial output interface TXD.

[0020] The PIO controller is used for receiving the signal sent by the channel selection unit to the SOPC system.

[0021] The TIMER controller is used for counting the timestamp timestampe when starting, and ending the counting when stopping.

[0022] The NIOSII soft core is used for receiving the counting result of the TIMER controller through the AVALON bus, parsing the Nibble data of the SENT signal, and sending to the UART controller through the AVALON bus, and outputting to the serial output interface TXD.

[0023] The EPCS controller is used for communicating with the FLASH through the SPI protocol, and storing the code to the external chip.

[0024] In another aspect, the application further provides a use method of the SENT protocol analysis device based on the active identification carrier, comprising the following steps:

[0025] S1, when the SENT protocol analysis device is powered on or abnormal, the reset signal state is changed, the FPGA module is reset through the reset interface RESET, the enterprise cloud platform sends the control command, and the serial port to RJ45 module receives and sends to the channel selection unit through the serial input interface RXD.

[0026] S2, the SENT signal is sent into the pulse shaping unit through the SENT0-SENTN interface, and after pulse shaping, it is sent to the channel selection unit, and the channel selection unit selects one of the SENT signals according to the control command of the cloud platform and outputs it to the SOPC system;

[0027] S3, after the SOPC system receives one of the SENT signals, the PIO controller starts the edge trigger, the TIMER controller starts counting, and when the second edge trigger is triggered, the TIMER controller stops counting, and the counting result is sent to the NIOSII soft core through the AVALON bus to calculate a Tick duration, and finally the SENT signal data is output to the serial output interface TXD;

[0028] S4, the serial output interface TXD sends the parsed data to the enterprise cloud platform and the active identification carrier secondary node cloud platform through the serial-to-RJ45 module.

[0029] Preferably, step S1 specifically comprises:

[0030] The FPGA module is connected with N sensors, receives the SENT signal, and parses the sensor according to the control command issued by the enterprise cloud platform.

[0031] Preferably, step S3 specifically comprises:

[0032] The data frame structure of the SENT signal includes a synchronization pulse, a state communication pulse, a data pulse segment, a CRC check segment and a stop pulse segment, a Tick data is parsed through the NIOSII soft core, a Nibble data is obtained through multiple Ticks, and the data is converted into hexadecimal data and output to the serial output interface TXD by the UART controller.

[0033] Preferably, step S4 specifically comprises:

[0034] The parsed data is sent through the serial-to-RJ45 module in the HTTP protocol, the enterprise cloud platform is used for remote sending command, SENT data and standard comparison analysis and feedback control, and the active identification carrier secondary node cloud platform is used for device registration and data updating.

[0035] The SENT protocol parsing device based on the active identification carrier and the use method have the following beneficial effects relative to the prior art:

[0036] The pulse shaping unit, the channel selection unit, the phase-locked loop unit PLL and the SOPC system in the FPGA are used for selecting and frequency converting the multiple SENT signals, so that the processing capacity of the multiple SENT signals and the stability of the SENT input signal are improved;

[0037] Using a serial port to RJ45 module, by enterprise cloud platform remote sending control command, realized the setting of multi-channel SENT signal acquisition, by channel selection unit selects and realizes the multi-channel SENT signal asynchronous polling or single-channel synchronous high-speed acquisition analysis and analysis, improves the analysis efficiency;

[0038] The TIMER controller is arranged with the clock source of the 50MHZ clock selected outside the FPGA module, and is upgraded to 100MHz through a phase-locked loop unit PLL, the clock counting precision of each clock can reach 10ns, the clock stability can reach 1ns level, and the precision of the SENT protocol analysis is ensured at the source.

[0039] The enterprise cloud platform can realize SENT data and standard comparison analysis and feedback control, the active identification carrier secondary node cloud platform can realize device registration POST and data update PUT, and finally realizes information remote control, remote analysis and information remote sharing. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiment or prior art description will be briefly introduced below, and obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creating creative labor.

[0041] Figure 1 It is an internal structure diagram of the SENT protocol analysis device based on the active identification carrier of the present application.

[0042] Figure 2 It is a circuit wiring diagram of the pulse shaping unit of the SENT protocol analysis device based on the active identification carrier of the present application.

[0043] Figure 3 It is a circuit wiring diagram of the channel selection unit of the SENT protocol analysis device based on the active identification carrier of the present application.

[0044] Figure 4 It is a SOPC system structure diagram of the SENT protocol analysis device based on the active identification carrier of the present application.

[0045] Figure 5 It is a flow chart of the use method of the SENT protocol analysis device based on the active identification carrier of the present application.

[0046] Figure 6 It is a working principle diagram of the SENT protocol analysis device based on the active identification carrier of the present application. DETAILED DESCRIPTION

[0047] The technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] Example 1

[0049] Provides a SENT protocol parsing device based on an active identifier carrier, such as... Figure 1 As shown, the SENT protocol parsing device includes a clock source CLK, a reset interface RESET, signal input interfaces SENT0-SENTN, an FPGA module, a serial input interface RXD, a serial output interface TXD, and a serial-to-RJ45 module.

[0050] The FPGA module consists of a phase-locked loop (PLL) unit, an SOPC system, a pulse shaping unit, and a channel selection unit.

[0051] The clock source CLK is electrically connected to the FPGA module and is used to generate an external clock signal to be sent to the FPGA module.

[0052] The RESET interface is electrically connected to the FPGA module and is used to change the state of the reset signal when the device is powered on or malfunctions.

[0053] The signal input interfaces SENT0-SENTN are electrically connected to the FPGA module and are used to send N channels of parallel SENT signals to the FPGA module.

[0054] The serial input interface RXD is electrically connected to the FPGA module and is used to receive control commands sent by the cloud platform through the serial-to-RJ45 module.

[0055] The serial output interface TXD is electrically connected to the FPGA module and is used to send the parsed data to the cloud platform through the serial-to-RJ45 module;

[0056] The serial-to-RJ45 module is electrically connected to the FPGA module and is used to send and update data to the cloud platform and receive control commands.

[0057] The phase-locked loop (PLL) unit is electrically connected to the clock source (CLK) and the SOPC system. It is used to receive the clock source signal, increase the clock signal frequency, and send it to the SOPC system.

[0058] The clock source CLK provides an active clock for the phase-locked loop unit PLL, selects 50MHz, and sends the clock into the phase-locked loop unit PLL circuit inside the FPGA module through the clock source CLK interface; the phase-locked loop unit PLL receives the 50MHz clock provided by the clock source CLK, and outputs the clock frequency to 100MHz through the frequency division factor inside the phase-locked loop unit PLL.

[0059] As shown in Figure 2 As shown in the circuit wiring diagram of the pulse shaping unit of the active identification carrier based SENT protocol analysis equipment, the pulse shaping unit is electrically connected with the signal input interface SENT0-SENTN and the channel selection unit, is used for receiving the multi-channel parallel SENT signals and completing shaping, and is sent into the channel selection unit.

[0060] As shown in Figure 3 As shown in the circuit wiring diagram of the channel selection unit of the active identification carrier based SENT protocol analysis equipment, the channel selection unit is electrically connected with the pulse shaping unit and the serial input interface RXD, is used for receiving the multi-channel parallel shaped SENT signals, and selects one of the signals to be sent to the SOPC system according to the control command input by the serial input interface RXD.

[0061] The SOPC system is electrically connected with the channel selection unit, the serial output interface TXD and the serial input interface RXD, is used for receiving the serial port control command sent by the serial port to RJ45 module, selecting one of the SENT signals to be analyzed according to the requirement of the command, and outputting the analysis result from the serial output interface TXD to the serial port to RJ45 module.

[0062] The serial port to RJ45 module adopts a CH9121 chip, and the hardware composed of peripheral electronic components thereof is used to complete the conversion of communication information between the serial port to RJ45 modules, realize the remote enterprise cloud platform information interaction and the active identification carrier secondary node cloud platform information remote sharing, supervision and feedback control.

[0063] As shown in Figure 4 As shown in the SOPC system structure diagram of the active identification carrier based SENT protocol analysis equipment, the SOPC system comprises a NIOSII soft core, an AVALON bus, a UART controller, a TIMER controller, a PIO controller and an EPCS controller.

[0064] The UART controller, the TIMER controller, the PIO controller and the EPCS controller transmit information with the NIOSII soft core through the AVALON bus.

[0065] The UART controller is used for receiving control commands of the serial input interface RXD input, and exchanging, processing, analyzing and resolving the SENT signal with the NIOSII soft core information through the AVALON bus, and the UART controller outputs the resolution result to the serial output interface TXD;

[0066] The PIO controller is used for receiving a signal sent by the channel selection unit to the SOPC system, starting the TIMER controller when the first SENT pulse edge triggers, and stopping the TIMER controller when the second SENT pulse edge triggers;

[0067] The TIMER controller starts to count at 100MHz when starting, and stops counting when stopping;

[0068] The NIOSII soft core is used for receiving the count result of the TIMER controller through the AVALON bus, and a timer count value represents 10ns, and the count result multiplied by 10ns can calculate a pulse width duration, i.e. a Tick, and continuous repeated analysis of multiple Ticks can resolve the Nibble data of the SENT signal, and the AVALON bus transmits the Nibble data to the UART controller, and finally to the serial output interface TXD for output;

[0069] The EPCS controller is used for communicating with the FLASH through the SPI protocol, and storing the code to the external chip, and the pulse shaping unit and the channel selection unit are realized by the Verilog code on the FPGA hardware, and the SOPC system is realized by the C language code on the FPGA hardware.

[0070] The FPGA module adopts the EP2C8Q208 chip, and uses the Quartus II and Nios II software for compiling.

[0071] The device adopts the FPGA module and the serial port to RJ45 module, and the resolution accuracy can reach the ns level, and can realize the remote control, the remote analysis and the information remote sharing, and through the design, the simulation, the verification, the modular product is formed, the fast transplantation between different platforms can be realized, and the product development process is accelerated.

[0072] Embodiment two

[0073] A use method of a SENT protocol resolution device based on an active identification carrier is provided, as shown in Figure 5 The method comprises the following steps:

[0074] S1, when the SENT protocol analysis device is powered on or abnormal, the reset signal state is changed, the FPGA module is reset through the reset interface RESET, the enterprise cloud platform sends a control command, and the serial-to-RJ45 module receives and sends the channel selection unit through the serial input interface RXD after receiving the control command.

[0075] S2, the SENT signal is sent to the pulse shaping unit through the SENT0-SENTN interface, and is sent to the channel selection unit after pulse shaping, the channel selection unit selects one of the SENT signals according to the control command of the cloud platform, and outputs the selected one to the SOPC system.

[0076] S3, after the SOPC system receives the SENT signal, the PIO controller starts the edge trigger, the TIMER controller starts counting, and when the second edge trigger is triggered, the TIMER controller stops counting, the counting result is sent to the NIOSII soft core through the AVALON bus, a Tick duration is calculated, and finally the SENT signal data is output to the serial output interface TXD.

[0077] S4, the serial output interface TXD sends the parsed data to the enterprise cloud platform and the active identification carrier secondary node cloud platform through the serial-to-RJ45 module.

[0078] Step S1 specifically comprises:

[0079] The FPGA module is connected with N sensors, receives the SENT signal, and analyzes the sensor according to the control command sent by the enterprise cloud platform.

[0080] Step S3 specifically comprises:

[0081] The data frame structure of the SENT signal includes a synchronization pulse, a state communication pulse, a data pulse segment, a CRC check segment and a stop pulse segment, a Tick data is parsed through the NIOSII soft core, a Nibble data is obtained through multiple Ticks, the data is converted into hexadecimal data, and the data is output to the serial output interface TXD by the UART controller.

[0082] The count result is sent to the NIOSII soft core through the AVALON bus for calculation and analysis of a Tick duration, generally 3-90us, and a complete SENT signal data frame structure includes: (1) synchronization pulse: 56 Ticks, (2) state communication pulse: 12-27 Ticks, i.e. 1 Nibble, (3) data pulse section: up to 6 Nibbles, each Nibble can represent 0-15, generally 3 Nibbles represent a complete data, (4) CRC check section: 1-27 Ticks, i.e. 1 Nibble, (5) stop pulse section: selectively inserted 12-728 Ticks, a string of Nibble data is continuously analyzed by this method, and finally converted into hexadecimal data, which is output to the serial output interface TXD by the UART controller.

[0083] The step S4 specifically includes:

[0084] The analyzed data is sent by the serial-to-RJ45 module in the HTTP protocol, the enterprise cloud platform is used for remote sending of commands, SENT data, standard comparison analysis and feedback control, and the active identification carrier secondary node cloud platform is used for device registration and data updating.

[0085] As shown in Figure 6 Fig. 1 is a working principle diagram of a SENT protocol analysis device based on an active identification carrier according to the present application;

[0086] N sensors continuously send signals according to the SENT standard protocol, after the FPGA module receives the sensor signals, the corresponding sensors are analyzed according to the control commands sent by the enterprise cloud platform, and after the analysis is completed, the analysis result is sent to the enterprise cloud platform and the active identification carrier secondary node cloud platform through the serial-to-RJ45 module, and the enterprise cloud platform and the active identification carrier secondary node cloud platform realize information remote sharing, supervision and feedback control.

[0087] The use method of the SENT protocol analysis device in the embodiment is completed by using standard Verilog and C language, and the modular design method is used, the enterprise cloud platform can be received, the FPGA module and the serial-to-RJ45 module are internally realized, the flexibility and expansibility are improved, the analysis of the multi-channel SENT protocol is realized, and the remote control, remote analysis and information remote sharing are realized in the active identification carrier secondary node cloud platform.

[0088] The above only describes the preferred embodiments of the present application and does not limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for parsing a SENT protocol based on an active identification carrier, comprising the following steps: S1, when the SENT protocol parsing device is powered on or abnormal, the state of the reset signal is changed, the FPGA module is reset through the reset interface RESET, the enterprise cloud platform sends a control command, and the serial-to-RJ45 module receives and sends the control command to the channel selection unit through the serial input interface RXD; the FPGA module is connected with N sensors, receives a SENT signal, and parses the sensor according to the control command sent by the enterprise cloud platform; S2, the SENT signal is sent to the pulse shaping unit through the SENT0-SENTN interface, and after pulse shaping, the pulse shaping unit is sent to the channel selection unit, the channel selection unit selects one of the SENT signals according to the control command of the cloud platform, and outputs the selected SENT signal to the SOPC system; S3, after the SOPC system receives the SENT signal, the PIO controller starts the edge trigger, the TIMER controller starts counting, and when the second edge trigger is triggered, the TIMER controller stops counting, the counting result is sent to the NIOSII soft core through the AVALON bus, a Tick duration is calculated, and finally the SENT signal data is output to the serial output interface TXD; The data frame structure of the SENT signal includes a synchronization pulse, a state communication pulse, a data pulse segment, a CRC check segment and a stop pulse segment, a Tick data is parsed by the NIOSII soft core, a Nibble data is obtained by a plurality of Ticks, the Nibble data is converted into hexadecimal data, and the hexadecimal data is output to the serial output interface TXD by the UART controller; the counting result is sent to the NIOSII soft core through the AVALON bus, a Tick duration is calculated, and a Tick duration is calculated; according to a complete data frame structure of the SENT signal, (1) a synchronization pulse: 56 Ticks, (2) a state communication pulse: 12-27 Ticks, that is, 1 Nibble, (3) a data pulse segment: 6 Nibbles, each Nibble can represent 0-15, and 3 Nibbles represent a complete data, (4) a CRC check segment: 1-27 Ticks, that is, 1 Nibble, and (5) a stop pulse segment: 12-728 Ticks are inserted, a string of Nibble data is continuously parsed by the method, and finally the Nibble data is converted into hexadecimal data, which is output to the serial output interface TXD by the UART controller; S4, the serial output interface TXD sends the parsed data to the enterprise cloud platform and the active identification carrier secondary node cloud platform through the serial-to-RJ45 module; the parsed data is sent through the serial-to-RJ45 module in the HTTP protocol, the enterprise cloud platform is used for remote sending of a command, comparison and analysis of SENT data and a standard, and feedback control, and the active identification carrier secondary node cloud platform is used for device registration and data updating.

2. An active identification carrier based SENT protocol parsing device, which adopts the active identification carrier based SENT protocol parsing method as claimed in claim 1, comprising a clock source CLK, a reset interface RESET, a serial input interface RXD, a serial output interface TXD and a serial port to RJ45 module; characterized in that: The signal input interface SENT0-SENTN, the FPGA module; the FPGA module is constituted by the phase-locked loop unit PLL, the SOPC system, the pulse shaping unit and the channel selection unit; The clock source CLK is electrically connected with the FPGA module, and is used for generating an external clock signal and sending to the FPGA module; The reset interface RESET is electrically connected with the FPGA module, and is used for changing the reset signal state when the device is powered on or abnormal; The serial input interface RXD is electrically connected with the FPGA module, and is used for receiving the control command sent by the cloud platform through the serial port to RJ45 module; The signal input interface SENT0-SENTN is electrically connected with the FPGA module, and is used for sending the parallel SENT signal of N channels to the FPGA module; The serial output interface TXD is electrically connected with the FPGA module, and is used for sending the parsed data to the cloud platform through the serial port to RJ45 module; The serial port to RJ45 module is electrically connected with the FPGA module, and is used for sending and updating data to the cloud platform and receiving control commands; The phase-locked loop unit PLL is electrically connected with the clock source CLK and the SOPC system, and is used for receiving the clock source signal and improving the clock signal frequency, and sending to the SOPC system.

3. The active identification carrier based SENT protocol parsing device of claim 2, wherein, The pulse shaping unit is electrically connected with the signal input interface SENT0-SENTN and the channel selection unit, and is used for receiving the multi-channel parallel SENT signal and completing shaping, and sending to the channel selection unit.

4. The active identification carrier based SENT protocol parsing device of claim 3, wherein, The channel selection unit is electrically connected with the pulse shaping unit and the serial input interface RXD, and is used for receiving the multi-channel parallel shaped SENT signal, and selecting one of the signals to send to the SOPC system according to the control command input by the serial input interface RXD.

5. The active identification carrier based SENT protocol parsing device of claim 3, wherein: The SOPC system is electrically connected with the channel selection unit, the serial output interface TXD and the serial input interface RXD, and is used for receiving the serial port control command sent by the serial port to RJ45 module, selecting one of the SENT signals according to the command requirements, and outputting the parsed result from the serial output interface TXD to the serial port to RJ45 module.

6. The active identification carrier based SENT protocol parsing device of claim 3, wherein: The serial port to RJ45 module adopts CH9121 chip.

7. The active identification carrier based SENT protocol parsing device of claim 3, wherein, The SOPC system further includes NIOSII soft core, AVALON bus, UART controller, TIMER controller, PIO controller and EPCS controller; The UART controller, the TIMER controller, the PIO controller and the EPCS controller transmit information with the NIOSII soft core through the AVALON bus; The UART controller is used for receiving the control command input by the serial input interface RXD, and exchanging, processing, analyzing and parsing the SENT signal with the NIOSII soft core through the AVALON bus, and outputting the parsed result to the serial output interface TXD; The PIO controller is used for receiving the signal sent by the channel selection unit to the SOPC system; The TIMER controller is used for counting the timestamp in the starting time and ending the count in the stopping time; The NIOSII soft core is used for receiving the counting result of the TIMER controller through the AVALON bus, analyzing the nibble data of the SENT signal, sending to the UART controller through the AVALON bus, and outputting to the serial output interface TXD. The EPCS controller is used for communicating with the FLASH through the SPI protocol and storing codes to the external chip.

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