A method and device for burst transmission of video data based on FPGA

Abstract

The application provides a kind of based on FPGA's video data burst transmission method and device, comprising: each frame image data in video data is transmitted to the FPGA, and the data amount change value of transmission is obtained;Single frame image data received by the FPGA is carried out data analysis, and the analysis data of single frame image data satisfying condition is obtained;The data amount preprocessing is carried out to the analysis data, and burst data is obtained;The burst interrupt switching processing is carried out to the burst data, and the burst interrupt value is obtained;When the data amount change value is greater than or equal to the burst interrupt value, the single frame image data satisfying condition is cached to memory in the form of burst transmission, and the current burst transmission data is obtained.The application realizes the self-adaptation of video data and guarantees the integrity of burst transmission data.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of data burst transmission, and particularly relates to a video data burst transmission method and device based on FPGA. BACKGROUND

[0002] In recent years, information videoization and video super-high definition have become the development trend of global information industry. Video has developed from traditional standard definition and high definition to 4K and is developing towards 8K and AR / VR, and the technology greatly improves indexes such as resolution, brightness color, frame rate, color depth, sound channel and sampling rate, so that the audio and video data volume is multiplied, and a clearer, more realistic and immersive picture experience is brought, and the effective transmission of data is one of the key indexes. In the FPGA image processing process, external caching operation is needed for data due to reasons such as synchronization and timing conversion, and a DDR series storage chip is generally used to store and read data in a burst transmission mode.

[0003] The resolution of an image is changeable, and can be standard 720P, 1080P or customized non-standard arbitrary resolution according to different requirements. How to adaptively and effectively transmit the changed data volume is a key step in image processing.

[0004] Therefore, it is urgent to provide a video data burst transmission method and device based on FPGA to solve the technical problem that the existing technology cannot adaptively change the dynamic change of the front-end input data volume, resulting in incomplete burst transmission. SUMMARY

[0005] Therefore, it is urgent to provide a video data burst transmission method and device based on FPGA to solve the technical problem that the existing technology cannot adaptively change the dynamic change of the front-end input data volume, resulting in incomplete burst transmission.

[0006] In one aspect, the application provides a video data burst transmission method based on FPGA, comprising:

[0007] transmitting each frame of image data in the video data to the FPGA to obtain a change value of the transmitted data volume;

[0008] performing data analysis on the single frame of image data received by the FPGA to obtain analysis data of the single frame of image data meeting a condition, performing data volume preprocessing on the analysis data to obtain burst data, and performing burst interrupt switching processing on the burst data to obtain a burst interrupt value;

[0009] When the data amount change value is greater than or equal to the burst interrupt value, the single-frame image data meeting the condition is cached to a memory in a burst transmission manner, to obtain current burst transmission data.

[0010] In some possible implementation manners, the data parsing of the single-frame image data received by the FPGA to obtain the parsed data of the single-frame image data meeting the condition comprises:

[0011] The data parsing of all the single-frame image data received by the FPGA is performed to obtain the number of rows and the number of columns of each single-frame image data.

[0012] According to the playing order of the video data, it is judged whether the number of rows and the number of columns of the single-frame image data received by the FPGA within the preset frame number are consistent.

[0013] If yes, the number of rows and the number of columns of the single-frame image data meeting the condition are obtained.

[0014] If no, the step of judging whether the number of rows and the number of columns of the single-frame image data received by the FPGA within the preset frame number are consistent is re-executed after the inconsistent single-frame image data.

[0015] In some possible implementation manners, the number of rows and the number of columns of the single-frame image data meeting the condition are obtained by:

[0016] The number of rows and the number of columns of the single-frame image data received by the FPGA outside the preset frame number are latched, and according to the playing order of the video data, it is judged whether the number of rows and the number of columns outside the preset frame number are consistent.

[0017] If yes, the number of rows and the number of columns of the single-frame image data outside the preset frame number meeting the condition are obtained.

[0018] If no, the number of rows and the number of columns of the single-frame image data outside the preset frame number received by the FPGA are unlatched, and the step of transmitting each frame of image data in the video data to the FPGA to obtain a data amount change value is re-executed from the inconsistent single-frame image data.

[0019] In some possible implementation manners, the data amount preprocessing of the parsed data to obtain burst data comprises:

[0020] The parsed data is calculated to obtain a total amount of transmission data.

[0021] According to a preset burst transmission length, the total amount of transmission data is calculated to obtain a maximum burst number and a residual value.

[0022] According to the maximum burst number, the residual value and the preset burst transmission length, burst data is obtained.

[0023] In some possible implementation manners, the burst data comprises a total burst number, a first burst threshold and a second burst threshold.

[0024] The obtaining of the burst data according to the maximum burst number, the residual value and the preset burst transmission length comprises:

[0025] It is judged whether the residual value is a preset residual value.

[0026] If yes, the maximum burst number is determined as the total burst number, the preset burst transmission length is determined as the first burst threshold, and the preset residual value is determined as the second burst threshold.

[0027] If no, the maximum burst number is calculated, the total burst number is determined, the preset burst transmission length is determined as the first burst threshold, and the residual value is determined as the second burst threshold.

[0028] In some possible implementation manners, the performing of the burst interrupt switching processing on the burst data to obtain a burst interrupt value comprises:

[0029] It is judged whether the second burst threshold is equal to the preset residual value.

[0030] If yes, the first burst threshold is determined as the burst interrupt value.

[0031] If no, the burst interrupt value is obtained according to the total burst number.

[0032] In some possible implementation manners, the obtaining of the burst interrupt value according to the total burst number comprises:

[0033] It is judged whether a difference between the total burst number and a preset burst statistical number is equal to a preset burst number.

[0034] If yes, the second burst threshold is determined as the burst interrupt value.

[0035] If no, the first burst threshold is determined as the burst interrupt value.

[0036] In some possible implementation manners, after the current burst transmission data is obtained by buffering the single-frame image data that meets the condition in the burst transmission manner to the memory when the data amount change value is greater than or equal to the burst interrupt value, the method further comprises:

[0037] updating the preset burst statistics number to obtain an updated preset burst statistics number;

[0038] When the image data still exists image data not transmitted to the FPGA, returning to the step of transmitting each frame of image data in the video data to the FPGA to obtain a data amount change value of transmission according to the image data not transmitted to the FPGA in the image data and the updated preset burst statistics number.

[0039] In some possible implementation manners, the data parsing on the single frame of image data received by the FPGA to obtain the parsed data of the single frame of image data meeting the condition further includes:

[0040] judging whether the video data changes according to the data parsing;

[0041] If yes, canceling the latching of the data parsing of the latched data received by the FPGA, and performing the step of transmitting each frame of image data in the video data to the FPGA to obtain a data amount change value of transmission according to new video data.

[0042] In another aspect, the present application further provides an FPGA-based video data burst transmission device, comprising:

[0043] a data transmission module, configured to transmit each frame of image data in the video data to the FPGA to obtain a data amount change value of transmission;

[0044] a data parsing module, configured to perform data parsing on a single frame of image data received by the FPGA to obtain parsed data of the single frame of image data meeting a condition, perform data amount preprocessing on the parsed data to obtain burst data, and perform burst interrupt switching processing on the burst data to obtain a burst interrupt value;

[0045] a data reading module, configured to, when the data amount change value is greater than or equal to the burst interrupt value, cache the single frame of image data meeting the condition to a storage in a burst transmission manner to obtain current burst transmission data.

[0046] The FPGA-based video data burst transmission method provided by the present application has the beneficial effects of the above embodiments, that is, by performing data parsing on a single frame of image data received by the FPGA, data in the single frame of image data not meeting a condition can be processed to obtain parsed data of the single frame of image data meeting the condition received by the FPGA, so that data self-adaptation is realized. Further, by setting a burst interrupt switching manner, the present application can adapt to changes in image data amount (resolution), guarantee the integrity of data in the burst transmission process, and avoid the risk of data loss. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description only represent some of the embodiments of the present application, and all other drawings obtained by those skilled in the art without creative efforts based on these drawings also belong to the protection scope of the present application.

[0048] Figure 1 An embodiment flow diagram of the FPGA-based video data burst transmission method provided by the present application is shown in FIG. 1.

[0049] Figure 2 An embodiment structure diagram of the data analysis provided by the present application is shown in FIG. 2.

[0050] Figure 3 An embodiment structure diagram of the data volume preprocessing provided by the present application is shown in FIG. 3.

[0051] Figure 4 An embodiment structure diagram of the burst interrupt switching processing provided by the present application is shown in FIG. 4.

[0052] Figure 5 An embodiment structure diagram of the FPGA-based video data burst transmission device provided by the present application is shown in FIG. 5.

[0053] Figure 6 An embodiment structure diagram of the FPGA-based video data burst transmission device provided by the present application is shown in FIG. 6. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0055] Some of the block diagrams shown in the drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different network and / or processor systems and / or microcontroller systems.

[0056] Reference to an "embodiment" in this document means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of other embodiments. It is expressly understood that the embodiments described herein can be combined with other embodiments in any way deemed useful.

[0057] The embodiment of the application provides a video data burst transmission method and device based on FPGA, which are described as follows.

[0058] Figure 1 An embodiment flow diagram of the video data burst transmission method based on FPGA provided by the application is shown in the figure, and the video data burst transmission method based on FPGA comprises the following steps. Figure 1

[0059] S101, transmitting each frame of image data in video data to the FPGA to obtain a data amount change value of transmission;

[0060] S102, performing data analysis on single frame image data received by the FPGA to obtain analysis data of single frame image data meeting a condition; performing data amount preprocessing on the analysis data to obtain burst data; and performing burst interrupt switching processing on the burst data to obtain a burst interrupt value;

[0061] S103, when the data amount change value is greater than or equal to the burst interrupt value, buffering the single frame image data meeting the condition to a storage in a burst transmission mode to obtain current burst transmission data.

[0062] Compared with the prior art, the video data burst transmission method based on FPGA provided by the application can process data in single frame image data not meeting a condition by performing data analysis on single frame image data received by the FPGA, so as to obtain analysis data of single frame image data meeting a condition received by the FPGA, thereby realizing data self-adaptation. Further, the application realizes self-adaptation of image data amount (resolution) by setting a burst interrupt switching mode, guarantees data integrity in the burst transmission process, and avoids the risk of data loss.

[0063] It should be understood that: the manner of obtaining the video data uploaded by the user in step S101 can be that the user uploads on the front end or searches or selects from the front end.

[0064] It should be noted that the data amount change value B is changed in real time according to the data amount received by the FPGA, and when the data amount change value B is greater than the burst interrupt value T, the single frame image data received by the FPGA is read out in a burst transmission mode.​

[0065] The embodiment of the present application can be arranged in a server, and the server can be arranged with an FPGA (Field-Programmable Gate Array), which is a product further developed on the basis of programmable devices such as PAL, GAL and CPLD. The FPGA is a kind of semi-custom circuit in the field of ASIC (Application Specific Integrated Circuit), which solves the shortcomings of custom circuits and overcomes the limitation of the number of gate circuits of the original programmable devices.

[0066] In some embodiments of the present application, step S102 comprises:

[0067] performing data analysis on all the single-frame image data received by the FPGA to obtain the number of rows and the number of columns of each single-frame image data;

[0068] judging whether the number of rows and the number of columns of the single-frame image data received by the FPGA within a preset number of frames are consistent according to the playing order of the video data;

[0069] if yes, obtaining the number of rows and the number of columns of the single-frame image data meeting the condition;

[0070] if no, re-executing the step of judging whether the number of rows and the number of columns of the single-frame image data received by the FPGA within a preset number of frames are consistent according to the playing order of the video data after the inconsistent single-frame image data.

[0071] It should be noted that the number of rows and the number of columns can be used to represent the basic information of an image, for example, the resolution 1920*1080, the number of rows is 1920 and the number of columns is 1080, and the number of rows and the number of columns of the single-frame image data "meet the condition" means that the number of rows and the number of columns of the single-frame image data of the preset number of frames are the same.

[0072] In a specific embodiment of the present application, the preset number of frames is 10, and the number of rows L and the number of columns C of the previous 10 frames of images can be judged according to the playing order of the video data, if they are the same, it means that the condition is met, if they are not the same, it means that the condition is not met, for example, the previous 5 frames are 1920*1080, the 6th frame is 1280*720, the 7th frame is 1920*1080, and the 8th frame is 1920*1080, then starting from the 7th frame, the number of rows L and the number of columns C of the images of 7-16 frames are re-judged to determine whether the condition is met, and the above operation is repeated.

[0073] In some embodiments of the present application, the number of rows and the number of columns of the single-frame image data meeting the condition comprises:

[0074] latch the row number and the column number of the single frame image data received by the FPGA outside the preset frame number, and determine whether the row number and the column number outside the preset frame number are consistent according to the playing order of the video data;

[0075] If yes, the row number and the column number of the single frame image data outside the preset frame number meeting the condition are obtained.

[0076] If no, the row number and the column number of the single frame image data received by the FPGA outside the preset frame number are cancelled from being latched, and the step of transmitting each single frame image data in the video data to the FPGA to obtain the data amount change value of the transmitted data is re-executed starting from the inconsistent single frame image data.

[0077] It should be noted that after the single frame image data within the preset frame number is determined, the single frame image data outside the preset frame number also needs to be determined according to the playing order of the video data, and the latch means that the row number and the column number of the data are latched.

[0078] In the embodiment of the application, when the single frame image data within the first 10 frames is consistent, the single frame image data outside the 10 frames is determined, for example, the single frame image data within the 10 frames is 1920*1080, and the detection is performed according to the video playing order, when all the single frame image data in the video data is 1920*1080, the row number L and the column number C of all the single frame image data of the 11th frame are latched, the burst transmission is started, and all the single frame image data from the 11th frame to the end is obtained; when the 13th frame is 1280*720, the row number L and the column number C of the single frame image data of the 11th frame and the 12th frame are cancelled from being latched, the burst transmission is stopped, and the row number L and the column number C of the single frame image data of the 13th frame to the 22nd frame are determined again, if the 13th frame is 1280*720 and the 14th frame is 1920*1080, the row number L and the column number C of the single frame image data of the 14th frame to the 23rd frame are determined again, if all are 1920*1080, the row number L and the column number C of the single frame image data of the 24th frame are latched, the burst transmission is started again, and then the above steps are re-executed, wherein only the latched single frame image data is stored in the memory, and the single frame image data in the memory is also deleted when the latching is cancelled.

[0079] In the embodiment of the application, Figure 2 An embodiment structure schematic diagram of the data analysis provided by the application is as follows, Figure 2As shown, the single-frame image data is subjected to data analysis to obtain a row periodic monitoring row number L, such as 1920 within 10 frames, and a column periodic monitoring column number C, such as 1080 within 10 frames, and the stability of the single-frame image data is judged according to the row number L and the column number C.

[0080] In some embodiments of the present application, step S102 further comprises:

[0081] The analysis data is calculated to obtain a total amount of transmission data.

[0082] The total amount of transmission data is calculated according to a preset burst transmission length to obtain a maximum burst number and a residual value.

[0083] The burst data is obtained according to the maximum burst number, the residual value and the preset burst transmission length.

[0084] It should be noted that the product of the row number and the column number of the single-frame image data can be calculated to obtain the total amount of transmission data, and the preset burst transmission length can represent the amount of data transmitted each time. The preset burst transmission length can be set according to actual conditions, which is not limited in the embodiments of the present application.

[0085] The total amount of transmission data can be divided by the preset burst transmission length to obtain a calculation result, and the integer in the calculation result is determined as the maximum burst number and the remainder is determined as the residual value. For example, the calculation result is 2.3, the maximum burst number is 2, and the residual value is 3.

[0086] In specific embodiments of the present application, the preset burst transmission length S can be 2048, the row number L is 1920, and the column number C is 1080. Then the total amount of transmission data N is L*N=1920*1080, N / S=1021, the maximum burst number M1 is 1021, and the residual value R is 0.

[0087] In some embodiments of the present application, the burst data includes a total burst number, a first burst threshold and a second burst threshold.

[0088] The burst data is obtained according to the maximum burst number, the residual value and the preset burst transmission length, which includes:

[0089] It is judged whether the residual value is equal to a preset residual value.

[0090] If yes, the maximum burst number is determined as the total burst number, the preset burst transmission length is determined as the first burst threshold, and the preset residual value is determined as the second burst threshold.

[0091] If not, the maximum burst number is calculated, the total burst number is determined, the preset burst transmission length is determined as the first burst threshold, and the residual value is determined as the second burst threshold.

[0092] It should be noted that the preset residual value can be set according to actual needs, and the embodiments of the present application are not limited here.

[0093] In specific embodiments of the present application, the preset residual value can be 0. When the residual value R is 0, the total burst number M is equal to the maximum burst number M1, M=M1=1021, the first burst threshold T1 is equal to the preset burst transmission length S, T1=S=2048, and the second burst threshold T2 is equal to the preset residual value, T2=0. When the residual value R is not 0, the total burst number M is equal to the maximum burst number M1 plus 1, M=M1+1=1021+1=1022, the first burst threshold T1 is equal to the preset burst transmission length S, T1=S=2048, and the second burst threshold T2 is equal to the residual value R, T2=R.

[0094] In specific embodiments of the present application, Figure 3 An embodiment structure diagram of the data preprocessing provided by the present application is shown in FIG. 1. Figure 3 As shown in FIG. 1, according to the preset burst transmission length S and the total transmission data amount N, the maximum burst number M1 and the residual value R can be obtained. According to the judgment result of the residual value R, the residual value R can be processed to obtain the total burst number M, the first burst threshold T1 and the second burst threshold T2.

[0095] In some embodiments of the present application, step S102 further includes:

[0096] determining whether the second burst threshold is equal to the preset residual value;

[0097] If yes, the first burst threshold is determined as the burst interruption value;

[0098] If not, the burst interruption value is obtained according to the total burst number.

[0099] It should be noted that the burst interruption switching processing can be performed according to the processing result of the data preprocessing, and the corresponding burst interruption value can be obtained according to different judgment results in the burst interruption switching processing.

[0100] In specific embodiments of the present application, the preset residual value is 0. When the residual value R is 0, the second burst threshold T2 is 0, and the first burst threshold T1 is equal to the preset burst transmission length S=2048. Therefore, when the second burst threshold is 0, the first burst threshold T1 is equal to the burst interruption value T, S=T=2048.

[0101] In some embodiments of the present application, the obtaining the burst interruption value according to the total number of bursts comprises:

[0102] determining whether the difference between the total number of bursts and the preset burst statistical number is the preset burst number;

[0103] if yes, determining the second burst threshold as the burst interruption value;

[0104] if no, determining the first burst threshold as the burst interruption value.

[0105] It should be noted that the preset burst statistical number and the preset burst number can be set according to actual conditions, and the embodiments of the present application are not limited thereto.

[0106] In specific embodiments of the present application, the preset burst number can be 1, the preset burst statistical number can be 0 when the burst transmission program is executed for the first time, the first burst threshold T1 is equal to the preset burst transmission length S = 2048 when the residual value R is not 0, the second burst threshold T2 is R, the total number of bursts M is 1022, the difference between the total number of bursts M and the preset burst statistical number M2 is M-M2 = 1022-0 = 1022, and the difference is not the preset burst number, so the first burst threshold T1 is determined as the burst interruption value T, T1 = T = 2048. When the preset burst statistical number is 1021, M-M2 = 1022-1021 = 1, the second burst threshold T2 is determined as the burst interruption value T, T2 = T = R.

[0107] In specific embodiments of the present application, Figure 4 An embodiment structure diagram of the burst interruption switching process provided by the present application is shown in FIG. 1, which is Figure 4 In the case that the second burst threshold is not the preset residual value, the total number of bursts M and the preset burst statistical number M2 are compared, the corresponding burst threshold (T1 or T2) is switched according to the comparison result, and the burst interruption value T is determined according to the burst threshold.

[0108] In some embodiments of the present application, the data analysis of the single-frame image data received by the FPGA to obtain the analysis data of the single-frame image data satisfying the condition further comprises:

[0109] determining whether the video data is changed according to the data analysis;

[0110] if yes, canceling the latching of the data analysis of the latched video data received by the FPGA, and performing the step of “transmitting each frame of image data in the video data to the FPGA to obtain the data amount change value” according to the new video data.

[0111] It should be noted that if the analysis data of the previously latched single-frame image data is cancelled latching when it is detected that the video data has been changed, and the embodiment of the application is performed according to the new video data.

[0112] In a specific embodiment of the application, if the previous 15 frames are 1920*1080 and the 16th frame is 1280*720, the analysis data of the previously latched 1920*1080 is cancelled latching, and the embodiment of the application is restarted from the 16th frame.

[0113] In some embodiments of the application, when the data amount change value is greater than or equal to the burst interrupt value, the single-frame image data that meets the condition is cached to the memory in a burst transmission manner to obtain current burst transmission data, and the method further comprises:

[0114] updating the preset burst statistics number to obtain an updated preset burst statistics number;

[0115] When the image data still exists image data that has not been transmitted to the FPGA, the method returns to the step of transmitting each frame of image data in the video data to the FPGA to obtain a data amount change value of the transmitted data according to the image data that has not been transmitted to the FPGA and the updated preset burst statistics number.

[0116] It should be noted that transmitting a complete frame of image data requires multiple burst transmissions, so the current burst transmission data needs to be latched, and then burst transmission is performed, and after the current burst transmission is completed, the above operation is repeated for the next burst transmission.

[0117] In a specific embodiment of the application, in order to control the number of burst transmissions, the preset burst statistics number M2 can be set to 0 at the beginning, M2 can be increased by 1 after one burst transmission, M2=1, and after the data received by the FPGA is read out through burst transmission, the image data is transmitted to the FPGA again according to the playing order of the video data, the data amount change value B is also changed in real time, and then the embodiment of the application is performed again until the burst transmission of the video data uploaded by the user is completed.

[0118] In order to better implement the FPGA-based video data burst transmission method in the embodiment of the application, on the basis of the FPGA-based video data burst transmission method, the embodiment of the application also provides a FPGA-based video data burst transmission device, as shown in Figure 5 The FPGA-based video data burst transmission device comprises:

[0119] The data transmission module 201 is configured to transmit each frame of image data in the video data to the FPGA to obtain a data amount change value of the transmission;

[0120] The data analysis module 202 is configured to perform data analysis on the single frame of image data received by the FPGA to obtain analysis data of the single frame of image data meeting a condition, perform data amount preprocessing on the analysis data to obtain burst data, and perform burst interrupt switching processing on the burst data to obtain a burst interrupt value.

[0121] The data readout module 203 is configured to, when the data amount change value is greater than or equal to the burst interrupt value, cache the single frame of image data meeting the condition to the memory in a burst transmission manner to obtain current burst transmission data.

[0122] The above embodiment provides the FPGA-based video data burst transmission device, which can realize the technical solutions described in the above FPGA-based video data burst transmission method embodiment, and the principles of the implementation of the above modules or units can be referred to the corresponding content in the above FPGA-based video data burst transmission method embodiment, which will not be described here.

[0123] As shown in FIG. 1, Figure 6 The present application also provides a FPGA-based video data burst transmission device 1000. The FPGA-based video data burst transmission device 1000 includes a processor 1001, a memory 1002 and a display 1003. Figure 6 Only part of the components of the FPGA-based video data burst transmission device 1000 are shown, but it should be understood that all the shown components are not required to implement, and more or less components can be alternatively implemented.

[0124] The memory 1002 can be an internal storage unit of the FPGA-based video data burst transmission device 1000 in some embodiments, such as a hard disk or a memory of the FPGA-based video data burst transmission device 1000. The memory 1002 can also be an external storage device of the FPGA-based video data burst transmission device 1000 in other embodiments, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc.

[0125] Further, the memory 1002 can include both an internal storage unit of the FPGA-based video data burst transmission device 1000 and an external storage device. The memory 1002 is used to store application software and various data for installing the FPGA-based video data burst transmission device 1000.

[0126] The processor 1001 can be a central processing unit (CPU), a microprocessor, or other data processing chip in some embodiments, used to run program codes or process data stored in the memory 1002, such as the FPGA-based video data burst transmission method in the present application.

[0127] The display 1003 can be an LED display, a liquid crystal display, a touch liquid crystal display, an OLED (Organic Light-Emitting Diode) touch, etc. in some embodiments. The display 1003 is used to display information of the FPGA-based video data burst transmission device 1000 and to display visualized user interfaces. The components 1001-1003 of the FPGA-based video data burst transmission device 1000 communicate with each other through a system bus.

[0128] In some embodiments of the present application, when the processor 1001 executes the FPGA-based video data burst transmission program in the memory 1002, the following steps can be implemented:

[0129] Transmitting each frame of image data in the video data to the FPGA to obtain a data amount change value of the transmission;

[0130] Performing data analysis on the single frame of image data received by the FPGA to obtain analysis data of the single frame of image data satisfying a condition; performing data amount preprocessing on the analysis data to obtain burst data; performing burst interrupt switching processing on the burst data to obtain a burst interrupt value;

[0131] When the data amount change value is greater than or equal to the burst interrupt value, the single frame of image data satisfying the condition is cached to the memory in a burst transmission manner to obtain current burst transmission data.

[0132] It should be understood that, when the processor 1001 executes the FPGA-based video data burst transmission program in the memory 1002, in addition to the above functions, other functions can also be implemented, which can be referred to the description of the corresponding method embodiments.

[0133] Further, the embodiments of the present application do not make specific limitation on the type of the FPGA-based video data burst transmission device 1000 mentioned above, and the FPGA-based video data burst transmission device 1000 can be a mobile phone, a tablet computer, a personal digital assistant (PDA), a wearable device, a laptop computer, or the like. Exemplary embodiments of the portable FPGA-based video data burst transmission device include, but are not limited to, a portable FPGA-based video data burst transmission device running an IOS, an android, a microsoft, or other operating system. The portable FPGA-based video data burst transmission device can also be other portable FPGA-based video data burst transmission devices, such as a laptop computer having a touch-sensitive surface (e.g., a touch panel), and the like. It should also be understood that in some other embodiments of the present application, the FPGA-based video data burst transmission device 1000 can not be a portable FPGA-based video data burst transmission device, but a desktop computer having a touch-sensitive surface (e.g., a touch panel).

[0134] Correspondingly, the embodiments of the present application also provide a computer readable storage medium for storing computer readable programs or instructions, which, when executed by a processor, can implement the FPGA-based video data burst transmission method steps or functions provided by the above-mentioned method embodiments.

[0135] Those skilled in the art can understand that all or part of the processes of the above-mentioned embodiments can be completed by a computer program instructing relevant hardware (such as a processor, a controller, etc.) to complete, and the computer program can be stored in a computer readable storage medium. The computer readable storage medium is a disk, an optical disk, a read-only memory, or a random access memory, etc.

[0136] The FPGA-based video data burst transmission method and device provided by the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method and its core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range can be changed, and the above description of the present application should not be understood as a limitation.

Claims

1. A method for burst transmission of video data based on FPGA, characterized in that, The method comprises the following steps: transmitting each frame of image data in the video data to the FPGA to obtain a data amount change value of the transmission; the data amount change value is the total data amount of a single frame of image data in the FPGA; performing data analysis on the single frame of image data received by the FPGA to obtain analysis data of the single frame of image data meeting the condition; calculating the analysis data to obtain a total transmission data amount; calculating the total transmission data amount according to a preset burst transmission length to obtain a maximum burst number and a residual value; when the residual value is not a preset residual value, calculating the maximum burst number to determine a total burst number, determining the preset burst transmission length as a first burst threshold, and determining the residual value as a second burst threshold; when the difference between the total burst number and a preset burst statistical number is not equal to a preset burst number, determining the first burst threshold as a burst interruption value; when the data amount to be transmitted in the data amount change value is equal to the burst interruption value, the single frame of image data meeting the condition is cached to a memory in a burst transmission mode; when the difference between the total burst number and a preset burst statistical number is equal to a preset burst number, determining the second burst threshold as the burst interruption value; when the data amount to be transmitted in the data amount change value is equal to the burst interruption value, the single frame of image data meeting the condition is cached to a memory in a burst transmission mode to obtain complete data of the single frame of image data transmitted by the current burst; the data analysis on the single frame of image data received by the FPGA to obtain analysis data of the single frame of image data meeting the condition comprises the following steps: performing data analysis on all the single frames of image data received by the FPGA to obtain the number of rows and the number of columns of each single frame of image data; judging whether the number of rows and the number of columns of the single frame of image data received by the FPGA within a preset frame number are consistent according to the playing order of the video data; if yes, obtaining the number of rows and the number of columns of the single frame of image data meeting the condition; if no, re-executing the step of judging whether the number of rows and the number of columns of the single frame of image data within the preset frame number are consistent according to the playing order of the video data after the inconsistent single frame of image data.

2. The FPGA-based method for video data burst transmission according to claim 1, wherein, the obtaining of the number of rows and the number of columns of the single frame of image data meeting the condition comprises the following steps: latching the number of rows and the number of columns of the single frame of image data outside the preset frame number received by the FPGA, and judging whether the number of rows and the number of columns outside the preset frame number are consistent according to the playing order of the video data; if yes, obtaining the number of rows and the number of columns of the single frame of image data outside the preset frame number meeting the condition; if no, canceling the latching of the number of rows and the number of columns of the single frame of image data outside the preset frame number received by the FPGA, and re-executing the step of transmitting each frame of image data in the video data to the FPGA to obtain a data amount change value of the transmission from the inconsistent single frame of image data.

3. The FPGA-based method for video data burst transmission according to claim 1, wherein, The method further comprises: determining whether the residual value is a preset residual value; if yes, determining the maximum burst number as the total burst number, determining the preset burst transmission length as the first burst threshold, and determining the preset residual value as the second burst threshold.

4. The FPGA-based method for video data burst transmission according to claim 1, wherein, The method further comprises: determining whether the second burst threshold is equal to the preset residual value; if yes, determining the first burst threshold as the burst interruption value; if no, determining the burst interruption value according to a difference between the total burst number and a preset burst statistical number.

5. The FPGA-based method for video data burst transfer of claim 1, wherein, The method further comprises: updating the preset burst statistical number to obtain an updated preset burst statistical number; when a difference between the total burst number and the updated preset burst statistical number is not equal to a preset burst number and the data amount to be transmitted in the data amount change value is equal to the burst interruption value, buffering the single-frame image data meeting the condition to the memory in a burst transmission manner, so as to perform next burst transmission.

6. The FPGA-based method for video data burst transmission according to claim 3, wherein, The method further comprises: determining whether the video data is changed according to the data analysis; if yes, canceling latching of the data analysis of the single-frame image data received by the FPGA according to new video data, and performing the step of transmitting each frame of image data in the video data to the FPGA to obtain a data amount change value of transmission.

7. An FPGA-based apparatus for video data burst transmission, the apparatus comprising: The method comprises: a data transmission module, configured to transmit each frame of image data in the video data to the FPGA to obtain a data amount change value of transmission; the data amount change value is a total data amount of single-frame image data in the FPGA; a data analysis module, configured to perform data analysis on single-frame image data received by the FPGA to obtain analysis data of single-frame image data meeting a condition; performing calculation on the analysis data to obtain a total transmission data amount; performing calculation on the total transmission data amount according to a preset burst transmission length to obtain a maximum burst number and a residual value; when the residual value is not a preset residual value, performing calculation on the maximum burst number to determine a total burst number, determining the preset burst transmission length as a first burst threshold, and determining the residual value as a second burst threshold. The data reading module is configured to determine the first burst threshold as a burst interruption value when a difference between the total burst number and a preset burst statistical number is not equal to a preset burst number; and cache the single-frame image data meeting the condition to a memory in a burst transmission manner when an amount of data to be transmitted in the data amount change value is equal to the burst interruption value. The data reading module is configured to determine the second burst threshold as the burst interruption value when the difference between the total burst number and the preset burst statistical number is equal to the preset burst number; and cache the single-frame image data meeting the condition to the memory in the burst transmission manner when the amount of data to be transmitted in the data amount change value is equal to the burst interruption value, to obtain complete data of the single-frame image data transmitted through a current burst. The data analysis module is further configured to analyze all the single-frame image data received by the FPGA to obtain a row number and a column number of each single-frame image data; determine whether the row number and the column number of the single-frame image data received by the FPGA within a preset frame number are consistent according to a playing order of the video data; if yes, obtain the row number and the column number of the single-frame image data meeting the condition; and if not, re-execute the step of determining whether the row number and the column number of the single-frame image data received by the FPGA within the preset frame number are consistent according to the playing order of the video data after the inconsistent single-frame image data. ​

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