Semiconductor structure and method of fabricating the same

Abstract

This disclosure relates to the semiconductor field, providing a semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate, comprising a bit line on the substrate, and a semiconductor channel on a surface of the bit line away from the substrate. In a direction from the substrate to the bit line, the semiconductor channel includes a first region, a second region, and a third region arranged sequentially. The first region is in contact with the bit line, and the first, second, and third regions are doped with first-type dopant ions. The concentration of the first-type dopant ions in the second region is higher than the concentration in the first and third regions. The first-type dopant ions are N-type or P-type ions. This disclosure at least helps to reduce leakage current at the first and second regions, thereby improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] As the integration density of dynamic memory continues to increase, while researching the arrangement of transistors in dynamic memory array structures and how to reduce the size of individual functional devices in dynamic memory array structures, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] When using a vertical gate-all-around (GAA) transistor structure as a dynamic memory select transistor (access transistor), its area can reach 4F. 2 (F: Minimum pattern size achievable under given process conditions) In principle, higher density efficiency can be achieved. However, due to limitations in the doping process, the concentration distribution of doped elements in each region of the GAA transistor structure is difficult to control precisely, making it difficult to adjust the concentration of majority carriers in each region of the GAA transistor structure, and thus difficult to further improve the electrical performance of the GAA transistor structure and dynamic memory. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and its fabrication method, which at least helps to reduce leakage current in the first and second regions, thereby improving the electrical performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate, the substrate including a base plate, a bit line located on the substrate, and a semiconductor channel located on a surface of the bit line away from the substrate; in a direction along the substrate pointing to the bit line, the semiconductor channel includes a first region, a second region, and a third region arranged sequentially, the first region being in contact with the bit line, and the first region, the second region, and the third region being doped with a first type of dopant ion, and the concentration of the first type of dopant ion in the second region being higher than the concentration in the first region and the third region, wherein the first type of dopant ion is an N-type ion or a P-type ion.

[0006] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a substrate, a semiconductor layer on the substrate, and an initial semiconductor channel on a surface of the semiconductor layer away from the substrate in the substrate; doping the initial semiconductor channel to form a semiconductor channel, wherein the semiconductor channel includes a first region, a second region, and a third region arranged sequentially in a direction along the substrate toward the semiconductor layer, the first region being in contact with the semiconductor layer, and the first region, the second region, and the third region being doped with a first type of dopant ions, wherein the concentration of the first type of dopant ions in the second region is higher than the concentration in the first region and the third region, and the first type of dopant ions are N-type ions or P-type ions.

[0007] The technical solutions provided in this disclosure have at least the following advantages:

[0008] In the above technical solution, the first and third regions constitute the source or drain of the GAA transistor, and the second region constitutes the channel region when the GAA transistor is turned on. The concentration of type I doped ions in the second region is higher than that in the first and third regions. Therefore, when a voltage is applied to the gate surrounding the sidewall of the second region to turn the GAA transistor off, the lower concentration of type I doped ions in the first and third regions helps to reduce the concentration of majority carriers in these regions. This results in fewer majority carriers in the first and third regions being attracted to the gate and migrating to the second region. In other words, the majority carrier concentration in the regions of the first and third regions closest to the second region is lower, which helps to reduce the leakage current in the first and third regions near the second region. This improves the electrical performance of the semiconductor structure. Attached Figure Description

[0009] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0010] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0011] Figure 2 A schematic diagram of a semiconductor channel in a semiconductor structure provided in an embodiment of this disclosure;

[0012] Figure 3 A schematic cross-sectional view of a semiconductor channel, bit line, and substrate in a semiconductor structure provided in an embodiment of the present disclosure;

[0013] Figure 4Concentration distribution curves of various types of doped ions in the semiconductor channel, bit line, and substrate along the Y direction provided in an embodiment of this disclosure;

[0014] Figure 5 This is a distribution curve of the effective concentration of a first type of doped ion in a semiconductor channel along the Y direction, provided for an embodiment of this disclosure;

[0015] Figure 6 Concentration distribution curves of various types of doped ions in local regions of bit lines along directions C1 and C2, provided for an embodiment of this disclosure;

[0016] Figure 7 for Figure 1 A schematic cross-sectional view of the semiconductor structure shown along the first cross-sectional direction AA1;

[0017] Figure 8 for Figure 1 A schematic cross-sectional view of the semiconductor structure shown along the second section direction BB1;

[0018] Figure 9 The current-voltage curves of the GAA transistor in the semiconductor structure when the first region is the drain and the third region is the drain are shown.

[0019] Figure 10 The current-voltage curves of the first region as the drain and the third region as the drain when the GAA transistor in the semiconductor structure is turned on.

[0020] Figures 11 to 25 This is a schematic diagram of the structure corresponding to each step in a method for fabricating a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0021] As can be seen from the background technology, the electrical performance of current semiconductor structures needs to be improved.

[0022] Analysis revealed that in a GAA transistor, the first, second, and third regions are stacked sequentially. The first and third regions serve as the source or drain, while the second region acts as the channel when the transistor is on. To enhance conductivity, the concentrations of dopant ions in the first and third regions are high, sometimes even higher than in the channel region. Consequently, when a voltage is applied to the gate of the GAA transistor to turn off the second region, the high concentrations of dopant ions in the first and third regions (i.e., high majority carrier concentrations) attract more majority carriers to migrate towards the second region. This results in leakage current in the first and third regions near the second region when the transistor is off, reducing the electrical performance of the semiconductor structure and affecting its stability.

[0023] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure and its fabrication method. In the semiconductor structure, the concentration of first-type doped ions in the second region is higher than that in the first and third regions. When a voltage is applied at the location corresponding to the second region to put the GAA transistor in the off state, the lower concentration of first-type doped ions in the first and third regions helps to reduce the concentration of majority carriers in the first and third regions. This results in fewer majority carriers in the first and third regions being attracted to migrate to the second region, meaning that the majority carrier concentration in the regions of the first and third regions near the second region is lower. This, in turn, helps to reduce the leakage current in the regions of the first and third regions near the second region, thereby improving the electrical performance of the semiconductor structure.

[0024] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0025] This disclosure provides a semiconductor structure according to an embodiment. The semiconductor structure provided by this disclosure will be described in detail below with reference to the accompanying drawings.

[0026] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 A schematic diagram of a semiconductor channel in a semiconductor structure provided in an embodiment of this disclosure; Figure 3 A schematic cross-sectional view of a semiconductor channel, bit line, and substrate in a semiconductor structure provided in an embodiment of the present disclosure; Figure 4 Concentration distribution curves of various types of doped ions in the semiconductor channel, bit line, and substrate along the Y direction provided in an embodiment of this disclosure; Figure 5 The distribution curve of the effective concentration of first type doped ions in a semiconductor channel along the Y direction is provided for an embodiment of this disclosure. Figure 6 Concentration distribution curves of various types of doped ions in local regions of bit lines along directions C1 and C2, provided for an embodiment of this disclosure; Figure 7 for Figure 1 A schematic cross-sectional view of the semiconductor structure shown along the first cross-sectional direction AA1; Figure 8 for Figure 1 A schematic cross-sectional view of the semiconductor structure shown along the second section direction BB1; Figure 9 The current-voltage curves of the GAA transistor in the semiconductor structure when the first region is the drain and the third region is the drain are shown. Figure 10This is a current-voltage curve when the first region and the third region of the GAA transistor in the semiconductor structure are turned on, with the first region acting as the drain and the third region acting as the drain.

[0027] refer to Figures 1 to 10 The semiconductor structure includes: a substrate 100, the substrate 100 including a substrate 110, a bit line 101 located on the substrate 110, and a semiconductor channel 102 located on the surface of the bit line 101 away from the substrate 110; in the direction X along the substrate 110 pointing to the bit line 101, the semiconductor channel 102 includes a first region 112, a second region 122 and a third region 132 arranged sequentially, the first region 112 is in contact with the bit line 101, and the first region 112, the second region 122 and the third region 132 are doped with first type doped ions, and the concentration of the first type doped ions in the second region 122 is higher than the concentration in the first region 112 and the third region 132, the first type doped ions are N-type ions or P-type ions.

[0028] In this design, both the first region 112 and the third region 132 can serve as the source or drain of the GAA transistor, while the second region 122 serves as the channel region of the GAA transistor. Since the semiconductor structure includes a vertical GAA transistor, and the bit line 101 is located between the substrate 110 and the GAA transistor, it can form a 3D stacked memory device, which is beneficial for improving the integration density of the semiconductor structure.

[0029] It should be noted that, Figures 1 to 3 , Figure 7 and Figure 8 In the image, the substrate 110, bit line 101, and semiconductor channel 102 are outlined with dashed lines within the substrate 100, and the semiconductor channel 102 is further divided into a first region 112, a second region 122, and a third region 132 using dashed lines. Furthermore, Figure 1 Taking semiconductor channel 102 as an example, that is, in a cross-section perpendicular to direction X, the cross-section of semiconductor channel 102 is rectangular. Figure 2 The semiconductor channel 102 is shown as a cylinder, meaning that in a cross-section perpendicular to the X direction, the cross-section of the semiconductor channel 102 is circular. Figure 3 , Figure 7 and Figure 8 The provided cross-sectional diagram is applicable to Figure 1 The square columnar semiconductor channel 102 is also suitable for Figure 2 In practical applications, the shape of the cross-section of the cylindrical semiconductor channel 102 is not restricted in the cross-section perpendicular to the X direction.

[0030] The following will combine Figures 1 to 10 The semiconductor structure provided in this disclosure will be described in more detail.

[0031] In some embodiments, the material of the substrate 100 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0032] Furthermore, the substrate 100 includes a substrate 110, bit lines 101, and semiconductor channels 102. Since the substrate 110, bit lines 101, and semiconductor channels 102 have the same semiconductor elements, they can be formed using the same film structure. In one example, this film structure is composed of the same semiconductor elements, and the substrate 110, bit lines 101, and semiconductor channels 102 can be formed by etching this film structure. This makes the substrate 110, bit lines 101, and semiconductor channels 102 a single integrated structure, thereby improving interface state defects between the substrate 110 and bit lines 101, and between the semiconductor channels 102 and bit lines 101, thus improving the performance of the semiconductor structure.

[0033] The semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium. In one example, the substrate 110, bit line 101, and semiconductor channel 102 all include silicon. In other examples, the substrate, bit line, and semiconductor channel may all include germanium; or, the substrate, bit line, and semiconductor channel may all include silicon and germanium; or, the substrate, bit line, and semiconductor channel may all include silicon and carbon; or, the substrate, bit line, and semiconductor channel may all include arsenic and gallium; or, the substrate, bit line, and semiconductor channel may all include gallium and indium.

[0034] In some embodiments, in conjunction with reference Figures 3 to 5 In the direction Y from bit line 101 to substrate 110, the concentration of first type doped ions in second region 122 first gradually increases and then gradually decreases.

[0035] Thus, the concentration of the first type of doped ions in the edge regions of the second region 122 near the first region 112 and the third region 132 is relatively low, that is, lower than the concentration of the first type of doped ions in the central region of the second region 122. Because the concentration of type I doped ions in region 122 is higher than that in region 112 and region 132, if the concentration of type I doped ions in region 122 gradually increases and then gradually decreases, while ensuring that the overall concentration of type I doped ions in region 122 is higher than that in region 112 and region 132, it is beneficial to reduce the variation range of the concentration of type I doped ions near region 112 and region 122. This helps to avoid abrupt changes in the potential energy difference between region 112 and region 122, and avoids leakage caused by abrupt changes in the potential energy difference between region 112 and region 122. In addition, it helps to reduce the variation range of the concentration of type I doped ions near region 132 and region 122, and thus helps to avoid abrupt changes in the potential energy difference between region 132 and region 122, and avoids leakage caused by abrupt changes in the potential energy difference between region 132 and region 122.

[0036] It should be noted that, in some embodiments, references Figure 4 The semiconductor channel 102 is also doped with a low concentration of second-type dopant ions. The first-type dopant ions are either N-type or P-type ions, and the second-type dopant ions are either N-type or P-type ions. Here, the low concentration of the second-type dopant ions is relative to the high concentration of the first-type ions in the semiconductor channel 102, and the concentration of the second-type dopant ions in the semiconductor channel 102 differs from the concentration of the first-type dopant ions in the semiconductor channel 102 by at least two orders of magnitude. Thus, even if the semiconductor channel 102 contains both type I and type II doped ions, the combined effect of these two types of doped ions leads to impurity compensation, reducing the effective concentration of type I doped ions in the semiconductor channel 102. However, the concentration of type II doped ions in the semiconductor channel 102 differs from that of type I doped ions by at least two orders of magnitude, having a negligible impact on the concentration of type I doped ions. This means the effective concentration of type I doped ions in the semiconductor channel 102 is equivalent to its actual concentration, meaning the trend of change in the effective concentration of type I doped ions in the semiconductor channel 102 is consistent with the trend of change in the overall concentration of type I doped ions in the semiconductor channel 102. Specifically, the effective concentration of type I doped ions in the semiconductor channel 102 is the difference between the concentration of type I doped ions and the concentration of type II doped ions in the semiconductor channel 102.

[0037] The N-type ion includes at least one of arsenic, phosphorus, or antimony ions; the P-type ion includes at least one of boron, indium, or gallium ions. In one example, the first type of dopant ion is an arsenic ion, and the second type of dopant ion is a boron ion.

[0038] It should be noted that, in conjunction with references Figure 3 and Figure 4 Each semiconductor channel 102 has a central axis D extending in the direction Y along the bit line 101 towards the substrate 110. Figure 4 The concentration distribution of various types of doped ions in the semiconductor channel 102, bit line 101, and substrate 110 along the central axis D is shown. Figure 4 The starting point of the horizontal axis is the top surface of the third region 132 away from the substrate 110. The curve characterized by Arsenic represents the concentration distribution of arsenic ions in the semiconductor channel 102, bit line 101 and substrate 110. The curve characterized by Boron represents the concentration distribution of boron ions in the semiconductor channel 102, bit line 101 and substrate 110. The curve characterized by NetActive represents the concentration distribution of effective dopant ions in the semiconductor channel 102, bit line 101 and substrate 110. The curve characterized by Phosphorus represents the concentration distribution of phosphorus ions in the third region 132.

[0039] Reference Figure 3 and Figure 5 , Figure 5 The effective concentration distribution of the first type of doped ions in the semiconductor channel 102 through which the central axis D is intercepted is shown. The first type of doped ion is arsenic ion.

[0040] Reference Figure 3 and Figure 6 , Figure 6 The curves represent the concentration distribution of various types of doped ions in the local region of bit line 101 along directions C1 and C2. The curve characterized by Arsenic represents the concentration distribution of arsenic ions in the local region of bit line 101, the curve characterized by Boron represents the concentration distribution of boron ions in the local region of bit line 101, and the curve characterized by NetActive represents the concentration distribution of effective doped ions in the local region of bit line 101.

[0041] In some embodiments, in conjunction with reference Figure 4 and Figure 5 The highest concentration of type I doped ions in region 122 is 1.0 × 10⁻⁶. 19 atom / cm 3 ~1.5×10 19 atom / cm3 The concentration of type I doped ions in region 122 is within this range. When the GAA transistor is operating, the on / off ratio of region 122 is relatively high, ensuring that region 122 can be quickly turned on and off. In one example, refer to... Figure 4 The highest concentration of type I doped ions in region 122 can be 1.32 × 10⁻⁶. 19 atom / cm 3 .

[0042] It should be noted that if the semiconductor channel 102 is also doped with a low concentration of type II dopant ions, then the maximum effective concentration of type I dopant ions in the second region 122 can also be 1.0 × 10⁻⁶. 19 atom / cm 3 ~1.5×10 19 atom / cm 3 .

[0043] In some embodiments, in conjunction with reference Figure 5 and Figure 6 Bit line 101 is doped with first-type doped ions, and the concentration of first-type doped ions in bit line 101 is higher than the concentration in first region 112. This increases the conductivity of bit line 101 by increasing the concentration of first-type doped ions in bit line 101, thereby reducing the contact resistance between bit line 101 and first region 112.

[0044] It should be noted that, in some embodiments, in conjunction with reference to the [reference] Figure 4 and Figure 6 Bit line 101 is also doped with a low concentration of type II dopant ions. The concentration of type II dopant ions in bit line 101 differs from that of type I dopant ions by at least one order of magnitude. Even though bit line 101 contains both type I and type II dopant ions, the influence of type II dopant ions on the concentration of type I dopant ions in bit line 101 is very small. This makes the trend of the effective concentration of type I dopant ions in bit line 101 consistent with the trend of the effective concentration of type I dopant ions in bit line 101, that is, the effective concentration of type I dopant ions in bit line 101 is higher than the effective concentration in the first region 112. Specifically, the effective concentration of type I dopant ions in bit line 101 is the difference between the concentration of type I dopant ions and the concentration of type II dopant ions in bit line 101.

[0045] In some embodiments, in conjunction with reference Figure 3 and Figure 4Along the direction Y from the semiconductor channel 102 to the bit line 101, the concentration of the first type of doped ions in the bit line 101 first gradually increases and then gradually decreases. Thus, the concentration of the first type of doped ions in the edge region of the bit line 101 near the first region 112 is lower, i.e., lower than the concentration of the first type of doped ions in the central region of the bit line 101. Therefore, while ensuring a relatively high overall concentration of the first type of doped ions in the bit line 101 to reduce the contact resistance between the bit line 101 and the first region 112, it also helps to reduce the amplitude of the concentration variation of the first type of doped ions near the bit line 101 and the first region 112. This helps to avoid abrupt changes in the potential energy difference between the bit line 101 and the first region 112, and avoids leakage caused by such abrupt changes.

[0046] It should be noted that if the bit line 101 is also doped with a low concentration of second-type doped ions, then in the direction Y along the semiconductor channel 102 pointing to the bit line 101, the effective concentration of the first-type doped ions in the bit line 101 also shows a trend of first gradually increasing and then gradually decreasing.

[0047] In some embodiments, in conjunction with reference Figure 6 and Figure 7 In the direction along the central axis D of semiconductor channel 102 pointing to the gap between adjacent semiconductor channels 102, that is, along the C1 and C2 directions, the concentration of first type doped ions in bit line 101 gradually increases.

[0048] It should be noted that the reference Figure 6 If bit line 101 is also doped with a low concentration of type II dopant ions, then along the C1 and C2 directions, the effective concentration of type I dopant ions in bit line 101 also shows a gradually increasing trend. In some examples, refer to... Figure 6 Along the C1 and C2 directions, the concentration of the second type of doped ions in the bit line 101 shows a trend of first gradually increasing and then gradually decreasing.

[0049] In some embodiments, the highest concentration of the first type of doped ions in the bit line 101 is 2.5 × 10⁻⁶. 20 atom / cm 3 ~3.2×10 20 atom / cm 3 The concentration of type I doped ions in bit line 101 is within this range, which helps to ensure that bit line 101 itself has high conductivity. In one example, refer to Figure 4 and Figure 6 The highest concentration of type I doped ions in bit line 101 can be 2.936 × 10⁻⁶. 20 atom / cm 3 .

[0050] It should be noted that if bit line 101 is also doped with a low concentration of type II dopant ions, then the maximum effective concentration of type I dopant ions in bit line 101 can also be 2.5 × 10⁻⁶. 20 atom / cm 3 ~3.2×10 20 atom / cm 3 .

[0051] In some embodiments, in conjunction with reference Figure 1 and Figure 3 In the direction Z perpendicular to the sidewall of the semiconductor channel 102, the doping depth of the first type of doped ions in the bit line 101 located directly below the semiconductor channel 102 gradually decreases and then gradually increases. That is, the substrate 110 located directly below the semiconductor channel 102 has a protrusion at the contact point with the bit line 101, and the cross-sectional shape of this protrusion is similar to a triangle in the AA1 section. This helps to increase the contact area between the substrate 110 and the bit line 101, thereby reducing the contact resistance between the substrate 110 and the bit line 101 and avoiding leakage between the bit line 101 and the substrate 110.

[0052] Furthermore, in some embodiments, references Figure 7 Each semiconductor channel 102 has a central axis D extending along the direction X from the substrate 110 to the bit line 101. For the bit line 101 located between two adjacent central axes D, the doping depth of the first type of doped ions in the bit line 101 gradually increases. This is beneficial to forming multiple protrusions in the substrate 110, further increasing the contact area between the substrate 110 and the bit line 101, thereby avoiding leakage between the bit line 101 and the substrate 110.

[0053] In some embodiments, in addition to having first-type doped ions in the bit line 101, the bit line 101 is also doped with a metal element. Compared to the unmetallized semiconductor material, the bit line 101 doped with the first-type doped ions and the metal element has a relatively low resistivity. Therefore, it is beneficial to further reduce the conductivity of the bit line 101 itself, thereby further reducing the contact resistance between the bit line 101 and the first region 112, and further improving the electrical performance of the semiconductor structure. The metal element may include at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0054] It should be noted that, in this embodiment of the present disclosure, the substrate 110 may have a plurality of spaced bit lines 101, and each bit line 101 may be in contact with at least one first region 112. Figure 1 , Figure 7 and Figure 8The example uses four spaced-apart bit lines 101, and each bit line 101 in contact with four first regions 112. Figure 2 The example uses two mutually spaced bit lines 101 and each bit line 101 in contact with three first regions 112. In practical applications, the number of bit lines 101 on the substrate 110 and the number of first regions 112 in contact with each bit line 101 can be reasonably set according to actual electrical requirements.

[0055] In some embodiments, reference Figure 4 The substrate 110 is doped with second type doped ions, and the bit line 101 is doped with first type doped ions. Thus, a PN junction is formed between the bit line 101 and the substrate 110. This PN junction helps to prevent leakage current in the bit line 101 and further improves the electrical performance of the semiconductor structure.

[0056] It should be noted that in some embodiments, bit line 101 is doped with first type dopant ions and second type dopant ions, but the effective doping concentration of the dopant ions in bit line 101 is provided by the first type dopant ions.

[0057] In some embodiments, reference Figures 1 to 8 The semiconductor structure may further include a capacitive contact window 103 located on the surface of the third region 132 away from the second region 122, and the capacitive contact window 103 is doped with first-type dopant ions. This facilitates the improvement of the conductivity of the capacitive contact window 103 itself through the first-type dopant ions, thereby reducing the contact resistance between the capacitive contact window 103 and the third region 132, and improving the electrical performance of the semiconductor structure.

[0058] In some embodiments, the third region 132 is doped with a first ion, and the capacitive contact window 103 is doped with a second ion. The first ion and the second ion are different first-type doped ions. (Refer to...) Figure 4 The relative atomic mass of the second ion is smaller than that of the first ion. For example, the first ion is an arsenic ion and the second ion is a phosphorus ion. Therefore, the second ion can easily diffuse from the capacitor contact window 103 into the third region 132, which is conducive to further increasing the concentration of the first type of doped ions in the third region 132. This is beneficial to improving the conductivity of the third region 132 itself, and mainly improves the concentration of the first type of doped ions near the capacitor contact window 103 in the third region 132. This is beneficial to reducing the contact resistance between the third region 132 and the capacitor contact window 103.

[0059] In some embodiments, the height of the semiconductor channel 102 is 100 nm to 150 nm along the direction X from the substrate 110 to the bit line 101, and the heights of the first region 112, the second region 122, and the third region 132 are all 30 nm to 60 nm. In one example, the height of the second region 122 is 60 nm, and the heights of the first region 112 and the third region 132 are both 45 nm.

[0060] In some embodiments, the semiconductor structure may further include: an insulating layer 104 covering the sidewall surface of the second region 122; a word line 105 covering the sidewall surface of the insulating layer 104 away from the second region 122, and the adjacent sidewall of the first region 112, the adjacent sidewall of the word line 105, and the adjacent sidewall of the third region 132 forming a gap; and an isolation layer 106 located in the gap, and the top surface of the isolation layer 106 away from the substrate 110 is not lower than the top surface of the third region 132 away from the substrate 110.

[0061] In some embodiments, reference Figure 3 The orthographic projection of the second region 122 onto the substrate 110 is smaller than that of the first region 112 onto the substrate 110, and also smaller than that of the third region 132 onto the substrate 110. In a cross-section perpendicular to direction X, this facilitates the formation of a second region 122 with a smaller cross-sectional area, which improves the control capability of the word line 105 surrounding the sidewalls of the second region 122, thereby making it easier to control the on / off state of the GAA transistor. In other embodiments, the orthographic projections of the first, second, and third regions onto the substrate may be equal; or, the orthographic projections of the second and third regions onto the substrate may both be smaller than that of the first region onto the substrate.

[0062] In some embodiments, continue to refer to Figure 1 , Figure 7 and Figure 8 The isolation layer 106 may include a second isolation layer 126, a third isolation layer 136, a fourth isolation layer 146, a fifth isolation layer 156, and a sixth isolation layer 166.

[0063] The fourth isolation layer 146 is located in the interval between adjacent bit lines 101 and in the interval between adjacent first regions 112 on adjacent bit lines 101. The fifth isolation layer 156 is located on the sidewall of adjacent first regions 112 on the same bit line 101 and on the sidewall of the fourth isolation layer 146, and there is a first gap between adjacent fifth isolation layers 156. The fourth isolation layer 146 and the fifth isolation layer 156 together constitute the first isolation layer 116 to achieve electrical insulation between adjacent first regions 112 and adjacent bit lines 101. The sixth isolation layer 166 is located between adjacent capacitor contact windows 103 and is used to achieve electrical insulation between adjacent capacitor contact windows 103.

[0064] A second gap exists between adjacent word lines 105. A second isolation layer 126 covers the sidewall surface of the third region 132, and a third gap exists between the second isolation layers 126 located on adjacent sidewalls of the third region 132. A third isolation layer 136 is located within the first gap, the second gap, and the third gap. The first gap, the second gap, and the third gap are interconnected. In some embodiments, the third isolation layer 136 completely fills the first gap, the second gap, and the third gap. In other embodiments, the third isolation layer has a fourth gap, which helps to reduce the capacitance generated between adjacent word lines, thereby improving the electrical characteristics of the semiconductor structure.

[0065] In some embodiments, since the concentration of the first type of doped ions in the second region 122 is higher than that in the first region 112 and the third region 132, when a voltage is applied at the location corresponding to the second region 122 to turn off the GAA transistor, the lower concentration of the first type of doped ions in the first region 112 and the third region 132 is beneficial to reduce the concentration of majority carriers in the first region 112 and the third region 132. This results in fewer majority carriers in the first region 112 and the third region 132 that can be attracted to migrate to the second region 122, i.e., the concentration of majority carriers in the regions of the first region 112 and the third region 132 near the second region 122 is lower, thereby helping to reduce the leakage current in the regions of the first region 112 and the third region 132 near the second region 122.

[0066] For example, refer to Figure 9 Whether the first region 112, which is in contact with bit line 101, serves as the drain of the GAA transistor, corresponding to the curve represented by BL Drain in the figure, or the third region 132, which is in contact with capacitor contact window 103, serves as the drain of the GAA transistor, corresponding to the curve NC represented by NC Drain in the figure, the current generated when the GAA transistor is turned off is very small and less than 0.1fA, which is beneficial to improving the electrical performance of the semiconductor structure.

[0067] In addition, in conjunction with reference Figure 9 and Figure 10 If the first region 112, which is in contact with bit line 101, is used as the drain of the GAA transistor, the on-state current of the GAA transistor can be 19.6uA; if the third region 132, which is in contact with capacitor contact window 103, is used as the drain of the GAA transistor, the on-state current of the GAA transistor can be 16.9uA; the on / off ratio of the GAA transistor can reach 11; the subthreshold swing can be less than 80, that is, the turn-on and turn-off of the GAA transistor are more sensitive; the threshold voltage of the GAA transistor can be 0.49V.

[0068] In summary, in the semiconductor structure, the concentration of the first type of doped ions in the second region 122 is higher than that in the first region 112 and the third region 132. Therefore, when a voltage is applied to the location corresponding to the second region 122 to turn off the GAA transistor, it is beneficial to reduce the majority carrier concentration in the regions of the first region 112 and the third region 132 near the second region 122, thereby reducing the leakage current in the first region 112 and the third region 132 near the second region 122.

[0069] Another embodiment of this disclosure also provides a method for fabricating a semiconductor structure, used to fabricate the semiconductor structure provided in the above embodiments. Figure 1 , Figure 7 , Figure 8 as well as Figures 11 to 25 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to another embodiment of this disclosure. The method for fabricating a semiconductor structure according to another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. Parts that are the same as or corresponding to those in the above embodiments will not be described in detail below.

[0070] in, Figure 14 for Figure 13 The diagram shows a cross-sectional view of the structure along the first section direction AA1. Figure 15 for Figure 13 The diagram shows a cross-sectional view of the structure along the second section direction BB1. It should be noted that subsequent descriptions will include either a cross-sectional view along the first section direction AA1 or a cross-sectional view along the second section direction BB1, or both.

[0071] refer to Figures 11 to 12 The method for fabricating a semiconductor structure includes: providing a substrate 100; forming a substrate 110, a semiconductor layer 120 on the substrate 110, and an initial semiconductor channel 142 on the surface of the semiconductor layer 120 away from the substrate 110 in the substrate 100; doping the initial semiconductor channel 142 to form a semiconductor channel 102, wherein the semiconductor channel 102 includes a first region 112, a second region 122, and a third region 132 arranged sequentially in a direction X along the substrate 110 toward the semiconductor layer 120, the first region 112 being in contact with the semiconductor layer 120, and the first region 112, the second region 122, and the third region 132 being doped with first type doped ions, wherein the concentration of the first type doped ions in the second region 122 is higher than the concentration in the first region 112 and the third region 132, and the first type doped ions are N-type ions or P-type ions.

[0072] In some embodiments, forming a substrate 110, a semiconductor layer 120, and an initial semiconductor channel 142 in a substrate 100 may include the following steps:

[0073] An initial substrate is provided; specifically, the material type of the initial substrate can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. Elemental semiconductor materials can be silicon or germanium; crystalline inorganic compound semiconductor materials can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium dihydrogen phosphate, etc.

[0074] A first mask layer is formed on an initial substrate, the first mask layer having a plurality of mutually discrete first openings. In one example, the length of the first opening is the same as the length of the subsequently formed semiconductor layer along the extension direction Z of the first opening.

[0075] refer to Figure 11 Using a first mask layer as a mask, an initial substrate is etched to form a substrate 110 and an initial semiconductor layer 130. Along direction X, the initial semiconductor layer 130 includes sequentially arranged semiconductor layers 120 and initial semiconductor channels 142, with a plurality of first trenches between adjacent initial semiconductor layers 130. A fourth isolation layer 146 is formed in the first trenches. In some embodiments, the depth of the first trenches along direction X can be 250 nm to 300 nm.

[0076] In some embodiments, the fourth isolation layer 146 may be formed using the following process steps: performing a deposition process to form a fourth dielectric film covering the top surface of the initial semiconductor layer 130 and filling the first trench; performing a chemical mechanical planarization process on the fourth dielectric film until the top surface of the initial semiconductor layer 130 is exposed, with the remaining fourth dielectric film serving as the fourth isolation layer 146. The material of the fourth dielectric film includes silicon oxide.

[0077] In some embodiments, continue to refer to Figure 11 Before doping the initial semiconductor channel 142 to form a semiconductor channel, the method for fabricating the semiconductor structure may include the following steps:

[0078] A first ion implantation process is performed on the substrate 110 and the semiconductor layer 120; a second ion implantation process is then performed on the substrate 110 and the semiconductor layer 120. The ions implanted in both the first and second ion implantation processes are second-type dopant ions. The first-type dopant ion is either an N-type or a P-type ion, and the second-type dopant ion is either an N-type or a P-type ion. Thus, by performing two ion implantations on the substrate 110 and the semiconductor layer 120, it is beneficial to achieve a uniform distribution of the second-type dopant ion concentration in the substrate 110, thereby improving the stability of the semiconductor structure. Furthermore, it is beneficial to achieve a higher concentration of the second-type dopant ions in the substrate 110, which is conducive to forming a PN junction with a large potential energy difference between the substrate 110 and the subsequently formed bit line 101.

[0079] In some embodiments, the second type of doped ion can be boron ions, wherein the energy used in the first ion implantation process can be 110 keV to 140 keV, and the dose can be 2.8 × 10⁻⁶. 13 atom / cm 2 ~3.7×10 13 atom / cm 2 .

[0080] The second ion implantation process uses an energy of 60 keV to 90 keV and a dose of 1.0 × 10⁻⁶. 13 atom / cm 2 ~1.7×10 13 atom / cm 2 This allows the concentration of boron ions in the substrate 110 to reach a maximum of 1.458 × 10⁻⁶. 18 atom / cm 2 .

[0081] Reference Figure 11 and Figure 12 The initial semiconductor channel 142 was doped using a third ion implantation process to form the semiconductor channel 102. The energy used in the third ion implantation process was controlled to be 90 keV to 120 keV, and the dose was 5.0 × 10⁻⁶. 13 atom / cm 2 ~9.5×10 13 atom / cm 2 Thus, by controlling the energy and dosage of the third ion implantation process, it is beneficial to ensure that the concentration of the first type of doped ions in the second region 122 is higher than that in the first region 112 and the third region 132. Furthermore, in the Y direction, the concentration of the first type of doped ions in the second region 122 first gradually increases and then gradually decreases. This helps to reduce the leakage current in the first region 112 and the third region 132 near the second region 122 when the GAA transistor is in the off state, thereby improving the electrical performance of the semiconductor structure.

[0082] It should be noted that after doping the initial semiconductor channel 142, the initial semiconductor channel 142 also needs to be etched to form an array of semiconductor channels 102.

[0083] In some embodiments, reference Figure 12 A second mask layer 107 is formed on the top surface formed by the fourth isolation layer 146 and the initial semiconductor layer 130. The second mask layer 107 has a plurality of mutually discrete second openings. In some embodiments, the length of the second opening is consistent with the length of the subsequently formed word line along the extension direction W of the second opening.

[0084] In some embodiments, in conjunction with reference Figure 11 and Figure 12 The extension direction Z of the first opening is perpendicular to the extension direction W of the second opening, so that the final semiconductor channel 102 exhibits a 4F shape. 2 This arrangement is beneficial for further improving the integration density of the semiconductor structure. In other embodiments, the extension direction of the first opening intersects the extension direction of the second opening, and the included angle between them may not be 90°.

[0085] In some embodiments, the opening width of the first opening along the direction W is equal to the opening width of the second opening along the direction Z, and the spacing between adjacent first openings is equal to the spacing between adjacent second openings. On the one hand, this makes the subsequent formation of multiple semiconductor channels 102 arranged in a regular manner, further improving the integration density of the semiconductor structure; on the other hand, the same mask can be used to form the first mask layer and the second mask layer 107, which is beneficial to reducing the fabrication cost of the semiconductor structure.

[0086] In some embodiments, the methods for forming the first mask layer and the second mask layer 107 both include self-aligned quadruple patterning (SAQP) or self-aligned double patterning (SADP).

[0087] Continue to refer to Figure 12 Using the second mask layer 107 as a mask, the initial semiconductor layer 130 is etched (reference). Figure 11 The second trench 117 and the fourth isolation layer 146 are formed to form a plurality of second trenches 117, a semiconductor layer 120 and a semiconductor channel 102. In the X direction, the depth of the second trench 117 is less than the depth of the first trench, which is beneficial to form a plurality of mutually discrete semiconductor channels 102 on the side of the semiconductor layer 120 away from the substrate 110 while forming the semiconductor layer 120. The semiconductor layer 120 is in contact with the first region 112 of the semiconductor channel 102; the second mask layer 107 is removed.

[0088] In some embodiments, the depth of the second trench 117 can be 100 nm to 150 nm.

[0089] In order to achieve electrical insulation between adjacent semiconductor layers 120 and adjacent semiconductor channels 102, after etching the initial semiconductor layer 130 and the fourth isolation layer 146 with the second mask layer 107 as a mask, the remaining fourth isolation layer 146 is still located in the interval between adjacent semiconductor layers 120 and in the interval between adjacent semiconductor channels 102.

[0090] Since the semiconductor channel 102 is formed perpendicular to the semiconductor layer 120 and away from the top surface of the substrate 110, the GAA transistor can form a 3D stacked semiconductor structure. This is beneficial for designing GAA transistors with smaller size features without adversely affecting the electrical performance of the GAA transistor, thereby improving the integration density of the semiconductor structure.

[0091] Furthermore, by utilizing the first and second mask layers 107, the semiconductor layer 120 and the semiconductor channel 102 are simultaneously formed through two etching processes. On the one hand, this facilitates the control of the size of the semiconductor channel 102 by adjusting the size of the first and second openings, resulting in a semiconductor channel 102 with high dimensional accuracy. On the other hand, the substrate 110, semiconductor layer 120, and semiconductor channel 102 are all formed by etching the initial substrate, meaning that the substrate 110, semiconductor layer 120, and semiconductor channel 102 are formed using the same film structure, making the substrate 110, semiconductor layer 120, and semiconductor channel 102 an integral structure. This improves the interface state defects between the substrate 110, semiconductor layer 120, and semiconductor channel 102, thereby improving the performance of the semiconductor structure.

[0092] It should be noted that in other embodiments, the substrate and semiconductor layer may not be ion implanted with the second type of doped ions, and the initial semiconductor channel may be directly ion implanted with the first type of doped ions.

[0093] In some embodiments, after doping the initial semiconductor channel 142 to form the semiconductor channel 102, the method for fabricating the semiconductor structure may further include the following steps:

[0094] refer to Figures 13 to 15 A protective layer 108 is formed on the sidewalls of the semiconductor channel 102 and on the top surface away from the substrate 110, and the protective layer 108 exposes the semiconductor layer 120 located in the spacing between adjacent semiconductor channels 102 (see reference). Figure 12 The exposed semiconductor layer 120 is doped with a first type of dopant ions and the exposed semiconductor layer 120 is metallized to form a bit line 101, wherein the concentration of the first type of dopant ions in the bit line 101 is higher than the concentration in the first region 112.

[0095] In some embodiments, the material of the protective layer 108 can be silicon oxide or silicon nitride. The thickness of the protective layer 108 along the Z direction can be 20 nm to 40 nm, which helps to avoid interference with the semiconductor channel 102 during the doping of the semiconductor layer 120 with first-type dopant ions and metallization treatment.

[0096] It should be noted that in some embodiments, bit line 101 is also doped with a low concentration of second-type dopant ions, and the concentration of second-type dopant ions in bit line 101 differs from the concentration of first-type dopant ions in bit line 101 by at least one order of magnitude. Thus, even if bit line 101 contains both first-type and second-type dopant ions, the effective concentration of first-type dopant ions in bit line 101 is equivalent to the concentration of first-type dopant ions in bit line 101. Specifically, the effective concentration of first-type dopant ions in bit line 101 is the difference between the concentration of first-type dopant ions and the concentration of second-type dopant ions in bit line 101.

[0097] In some embodiments, a fourth ion implantation process is used to dope the exposed semiconductor layer 120 with first-type dopant ions, and the energy used in the fourth ion implantation process is controlled to be 5 keV to 10 keV, and the dose is 1.0 × 10⁻⁶. 15 atom / cm 2 ~5.0×10 15 atom / cm 2 This is conducive to the formation of... Figure 3 The bit line 101 shown increases the contact area between the substrate 110 and the bit line 101, thereby reducing the contact resistance between the substrate 110 and the bit line 101, preventing leakage between the bit line 101 and the substrate 110, and also helps to achieve a maximum concentration of 2.936 × 10⁻⁶ type I doped ions in the bit line 101. 20 atom / cm 3 .

[0098] It should be noted that after part of the semiconductor layer 120 is converted into bit line 101, the remaining semiconductor layer 120 can be used as part of the substrate 110.

[0099] In some embodiments, before the formation of the capacitive contact window and after the formation of bit line 101, the method for fabricating the semiconductor structure may further include the following steps:

[0100] Reference Figures 13 to 16 A first dielectric layer 109 is formed, filling the gap between adjacent protective layers 108. The material of the first dielectric layer 109 is different from that of the protective layer 108. The material of the first dielectric layer 109 includes silicon nitride. It should be noted that in some embodiments, during the step of forming the protective layer 108, the protective layer 108 located on the top surface of the semiconductor channel 102 is also removed. In other embodiments, during the step of forming the protective layer, the protective layer located on the top surface of the semiconductor channel may be retained.

[0101] Reference Figure 16 and Figure 17 Etch part of the protective layer 108 and part of the fourth isolation layer 146 to expose the sidewall of the third region 132.

[0102] Continue to refer to Figure 17 A second dielectric layer 119 is formed, which surrounds the sidewall of the third region 132. The second dielectric layer 119 located on the sidewall of the third region 132 forms a through hole f, and the bottom of the through hole f exposes the fourth isolation layer 146. The materials of the second dielectric layer 119 and the fourth isolation layer 146 are different.

[0103] It should be noted that while the second dielectric layer 119 surrounds the sidewall of the third region 132, it also covers the top surface of the remaining protective layer 108 and part of the top surface of the fourth isolation layer 146. The through hole f exposes part of the top surface of the fourth isolation layer 146.

[0104] refer to Figures 18 to 20 Remove the protective layer 108 exposed on the sidewall of the second zone 122 through hole f, and the remaining protective layer 108 serves as the fifth isolation layer 156.

[0105] In some embodiments, since the via f exposes part of the top surface of the fourth isolation layer 146, and the material of the fourth isolation layer 146 is the same as that of the protective layer 108, and the material of the fourth isolation layer 146 is different from that of the first dielectric layer 109 and the second dielectric layer 119, an etching solution can be injected into the via f, and the protective layer 108 and the fourth isolation layer 146 located on the sidewall of the second region 122 can be removed by a wet etching process to form the first isolation layer 116.

[0106] Furthermore, the first dielectric layer 109 and the second dielectric layer 119 together form a support framework, which is in contact with and connected to the third region 132, and a portion of the support framework is embedded in the first isolation layer 116. During the wet etching process, on the one hand, the support framework provides support and fixation for the semiconductor channel 102. When the etching solution flows, it generates a squeezing force on the semiconductor channel 102, which helps prevent the semiconductor channel 102 from tilting or shifting due to squeezing, thereby improving the stability of the semiconductor structure. On the other hand, the support framework wraps around the sidewalls of the third region 132, which helps prevent the etching solution from damaging the third region 132.

[0107] After removing the protective layer 108 and the fourth isolation layer 146 located on the side wall of the second zone 122, a first gap g is formed between the second zone 122 and the first medium layer 109. The through hole f and the first gap g together form the cave structure h.

[0108] refer to Figure 21 and Figure 22 An insulating layer 104 is formed on the sidewall surface of the second region 122, and the insulating layer 104 covers the sidewall surface of the second region 122.

[0109] Taking silicon as the material of the semiconductor channel 102 as an example, the exposed sidewall of the second region 122 is thermally oxidized to form an insulating layer 104, which covers the remaining sidewall surface of the second region 122. A second gap i exists between the insulating layer 104 and the first dielectric layer 109. Specifically, the thickness of the insulating layer 104 is 1 nm to 2 nm in the direction perpendicular to the sidewall of the second region 122. In other embodiments, the protective layer can also be formed by a deposition process.

[0110] In some embodiments, if the protective layer 108 on the top surface of the third region 132 has been removed, the top surface of the third region 132 is also exposed during the thermal oxidation process, and the portion of the third region 132 near the top surface and the sidewall of the second region 122 are both transformed into the insulating layer 104. In other embodiments, if the protective layer on the top surface of the third region is not removed, the insulating layer is formed only on the sidewall of the second region.

[0111] refer to Figures 23 to 25 A word line 105 is formed covering the sidewall surface of the insulating layer 104 away from the second region 122, and the word line 105 fills the second gap i (refer to...). Figure 22 ).in, Figure 25 This is a top view of a structure formed by a word line 105 surrounding four semiconductor channels 102 and their sidewall insulating layers 104. It should be noted that... Figure 25 The example shown is a word line 105 surrounding four semiconductor channels. In practical applications, there is no limit to the number of semiconductor channels that a word line 105 can surround.

[0112] The step of forming word line 105 may include: forming an initial word line that fills the second gap i and the via f; removing the initial word line located in the via f, with the remaining initial word line serving as word line 105. The initial word line may be formed by a deposition process, and the material of the initial word line may include at least one of polysilicon, titanium nitride, tantalum nitride, copper, or tungsten.

[0113] The initial word line self-aligns and fills the second gap i and the through hole f. After removing the initial word line located in the through hole f, it is beneficial to form a word line 105 with precise dimensions in a self-aligned manner. There is no need to design the size of the word line 105 through an etching process, which simplifies the formation steps of the word line 105. Furthermore, by adjusting the size of the second gap i, a small-sized word line 105 can be obtained.

[0114] In some embodiments, after forming word line 105, refer to Figure 1 , 6 and Figure 8The method for fabricating the semiconductor structure may further include: forming a capacitor contact window 103 on the surface of the third region 132 away from the second region 122; and doping the capacitor contact window 103 with first-type dopant ions. It should be noted that before forming the capacitor contact window 103, if the top surface of the third region 132 has a protective layer 108, the protective layer 108 on the top surface of the third region 132 is removed; if the top surface of the third region 132 has an insulating layer 104, the insulating layer 104 on the top surface of the third region 132 is removed to expose the top surface of the third region 132.

[0115] In some embodiments, continue to refer to Figure 1 , 6 and Figure 8 After forming the character line 105, the first dielectric layer 109 and the second dielectric layer 119 can be removed. A second isolation layer 126 covering the sidewall surface of the third region 132 is formed in the gaps created by removing the first dielectric layer 109 and the second dielectric layer 119, and a third isolation layer 136 filling the gaps formed by removing the first dielectric layer 109 and the second dielectric layer 119. In other embodiments, the second isolation layer and the third isolation layer can be the same film layer, that is, an isolation layer filling the gaps formed by removing the first dielectric layer and the second dielectric layer is formed.

[0116] Since the first dielectric layer 109 and the second dielectric layer 119 are in contact with the etching liquid phase during the steps of forming the cavity structure h and forming the word line 105, the insulation performance of the first dielectric layer 109 and the second dielectric layer 119 decreases. Therefore, after removing the first dielectric layer 109 and the second dielectric layer 119, the re-formation of the second isolation layer 126 and the third isolation layer 136 to fill the gaps formed by removing the first dielectric layer 109 and the second dielectric layer 119 is beneficial to improving the insulation between adjacent semiconductor channels 102.

[0117] Then, a sixth isolation layer 166 is formed, which fills the gap between adjacent capacitive contact windows 103.

[0118] In summary, by doping the semiconductor channel 102 so that the concentration of the first type of doped ions in the second region 122 is higher than that in the first region 112 and the third region 132, when the semiconductor channel 102 is in the off state, it is beneficial to reduce the concentration of majority carriers in the first region 112 and the third region 132, resulting in a lower concentration of majority carriers in the regions of the first region 112 and the third region 132 near the second region 122. This is beneficial to reduce the leakage current in the regions of the first region 112 and the third region 132 near the second region 122, thereby improving the electrical performance of the semiconductor structure.

[0119] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a substrate, bit lines located on the substrate, and semiconductor channels located on the surface of the bit lines remote from the substrate; In the direction along the substrate toward the bit line, the semiconductor channel includes a first region, a second region, and a third region arranged sequentially. The first region is in contact with the bit line, and the first region, the second region, and the third region are doped with a first type of dopant ions. The concentration of the first type of dopant ions in the second region is higher than the concentration in the first region and the third region. The first type of dopant ions are N-type ions or P-type ions. The substrate is doped with a second type of doped ions, and the bit line forms a PN junction with the substrate. The first type of doped ions and the second type of doped ions have opposite conductivity types.

2. The semiconductor structure as described in claim 1, characterized in that, In the direction from the bit line to the substrate, the concentration of the first type of doped ions in the second region first gradually increases and then gradually decreases.

3. The semiconductor structure as described in claim 2, characterized in that, The highest concentration of the first type of doped ions in the second region is 1.0×10¹⁹ atom / cm³ to 1.5×10¹⁹ atom / cm³.

4. The semiconductor structure as described in claim 1, characterized in that, The bit line is doped with the first type of doped ions, and the concentration of the first type of doped ions in the bit line is higher than the concentration in the first region.

5. The semiconductor structure as described in claim 4, characterized in that, In the direction along the semiconductor channel toward the bit line, the concentration of the first type of doped ions in the bit line first gradually increases and then gradually decreases.

6. The semiconductor structure as described in claim 5, characterized in that, The highest concentration of the first type of doped ions in the bit line is 2.5 × 1020 atom / cm3 to 3.2 × 1020 atom / cm3.

7. The semiconductor structure as described in claim 4, characterized in that, In a direction perpendicular to the sidewall of the semiconductor channel, the doping depth of the first type of dopant ions in the bit line located directly below the semiconductor channel first gradually decreases and then gradually increases.

8. The semiconductor structure as described in claim 1 or 4, characterized in that, The substrate is doped with a second type of dopant ion, wherein the first type of dopant ion is either an N-type ion or a P-type ion, and the second type of dopant ion is either an N-type ion or a P-type ion.

9. The semiconductor structure as described in claim 1, characterized in that, Also includes: A capacitive contact window is located on the surface of the third region away from the second region, and the capacitive contact window is doped with the first type of doped ions.

10. The semiconductor structure as described in claim 9, characterized in that, The third region is doped with a first ion, and the capacitor contact window is doped with a second ion. The first ion and the second ion are different from the first type of doped ion.

11. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A substrate, a semiconductor layer on the substrate, and an initial semiconductor channel on a surface above the semiconductor layer away from the substrate are formed in the substrate; The initial semiconductor channel is doped to form a semiconductor channel. In the direction from the substrate to the semiconductor layer, the semiconductor channel includes a first region, a second region, and a third region arranged sequentially. The first region is in contact with the semiconductor layer, and the first region, the second region, and the third region are doped with a first type of dopant ions. The concentration of the first type of dopant ions in the second region is higher than the concentration in the first region and the third region. The first type of dopant ions are N-type ions or P-type ions. After doping the initial semiconductor channel to form the semiconductor channel, the method further includes: A protective layer is formed on the sidewalls of the semiconductor channel and on the top surface away from the substrate, and the protective layer exposes the semiconductor layer located in the interval between adjacent semiconductor channels; The exposed semiconductor layer is doped with the first type of dopant ions, and the exposed semiconductor layer is metallized to form bit lines, wherein the concentration of the first type of dopant ions in the bit lines is higher than the concentration in the first region. The substrate is doped with a second type of doped ions, and the bit line forms a PN junction with the substrate. The first type of doped ions and the second type of doped ions have opposite conductivity types.

12. The manufacturing method as described in claim 11, characterized in that, Before doping the initial semiconductor channel to form the semiconductor channel, the method further includes: A first ion implantation process is performed on the substrate and the semiconductor layer. A second ion implantation process is performed on the substrate and the semiconductor layer; Wherein, the ions implanted by the first ion implantation process and the second ion implantation process are both second type doped ions, the first type doped ion is either an N-type ion or a P-type ion, and the second type doped ion is either an N-type ion or a P-type ion.

13. The manufacturing method as described in claim 12, characterized in that, The first ion implantation process uses an energy of 110 keV to 140 keV and a dose of 2.8 × 10¹³ atom / cm² to 3.7 × 10¹³ atom / cm².

14. The manufacturing method as described in claim 12 or 13, characterized in that, The second ion implantation process uses an energy of 60 keV to 90 keV and a dose of 1.0 × 10¹³ atom / cm² to 1.7 × 10¹³ atom / cm².

15. The manufacturing method as described in claim 11 or 12, characterized in that, The initial semiconductor channel is doped using a third ion implantation process to form the semiconductor channel, and the energy used in the third ion implantation process is controlled to be 90 keV~120 keV and the dose is 5.0×10¹³ atom / cm²~9.5×10¹³ atom / cm².

16. The manufacturing method as described in claim 11, characterized in that, The exposed semiconductor layer is doped with the first type of dopant ions using a fourth ion implantation process, and the energy used in the fourth ion implantation process is controlled to be 5 keV~10 keV and the dose is 1.0×10¹⁵ atom / cm²~5.0×10¹⁵ atom / cm².

17. The manufacturing method as described in claim 11, characterized in that, Also includes: A capacitive contact window is formed on the surface of the third region away from the second region; the capacitive contact window is doped with the first type of dopant ions.

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