Chip inspection and verification

Abstract

A method includes obtaining a first reference image of a first wafer. The method includes obtaining a first image of the first wafer in a manufacturing state. The first wafer has a first verification structure. The method includes obtaining a first physical measurement while the first wafer is in the manufacturing state. The first physical measurement corresponds to the first verification structure. The method includes determining that the first image matches the first reference image. The method includes obtaining electrical parameter measurements corresponding to the verification structure of a received wafer in a post-manufacturing state. The method includes calculating physical parameter values ​​based on the electrical parameter measurements. The method includes generating a verification response by comparing the physical parameter values ​​with the first physical measurement.

Description

Background Technology

[0001] This disclosure relates to chip manufacturing, and more specifically, to chip inspection and verification.

[0002] Wafer manufacturing can involve forming layers of various materials on a wafer (e.g., a silicon wafer) to create multiple electronic circuits on the wafer. Wafers can be divided into a set of dies, and each die can be integrated into various electronic devices. Summary of the Invention

[0003] According to embodiments of this disclosure, a method may include obtaining a first reference image of a first wafer. The method may include obtaining a first image of the first wafer in a manufacturing state. In the manufacturing state, the first wafer may have a number of manufacturing layers less than a threshold number. The first wafer may have a first verification structure. The method may include obtaining a first physical measurement while the first wafer is in the manufacturing state. The first physical measurement may correspond to the first verification structure. The method may include determining, at a first time, that the first image matches the first reference image by comparing the first image with the first reference image. The method may include obtaining an electrical parameter measurement at a second time after the first time. The electrical parameter measurement may correspond to a verification structure of the wafer received in a post-manufacturing state. In the post-manufacturing state, the received wafer may have a second number of manufacturing layers equal to a threshold number. The method may include calculating physical parameter values ​​based on the electrical parameter measurements. The method may include generating a verification response by comparing the physical parameter values ​​with the first physical measurement.

[0004] This also includes systems and computer program products corresponding to the methods described above.

[0005] According to embodiments of this disclosure, a method may include obtaining a first physical measurement. The first physical measurement may correspond to a first verification structure of a first wafer in a manufacturing state. In the manufacturing state, the first wafer may have a number of manufacturing layers less than a threshold number. The method may include obtaining an electrical parameter measurement. The electrical parameter measurement may correspond to a verification structure of a wafer received in a post-manufacturing state. In the post-manufacturing state, the received wafer may have a second number of manufacturing layers equal to the threshold number. The method may include calculating physical parameter values ​​based on the electrical parameter measurements. The method may include generating a verification response by comparing the physical parameter values ​​with the first physical measurement.

[0006] Embodiments of this disclosure can be illustrated as a device having a wafer. The wafer may have a first verification structure in a first region of the wafer. The first verification structure may include a first target component. The first verification structure may have a first measurable electrical parameter. The first measurable electrical parameter may correspond to a first physical characteristic of the first target component.

[0007] The above description of the invention is not intended to describe every illustrated embodiment or every implementation of this disclosure. Attached Figure Description

[0008] The accompanying drawings included in this application are incorporated in and form a part of this specification. They illustrate embodiments of the present disclosure and, together with the specification, serve to explain the principles of the disclosure. The drawings are merely illustrative of certain embodiments and are not intended to limit the scope of the disclosure.

[0009] Figure 1 An example computing environment with a wafer verification system according to embodiments of the present disclosure is described.

[0010] Figure 2 A flowchart depicts an example method for performing wafer inspection and verification according to embodiments of the present disclosure.

[0011] Figure 3A A top view of an example chip according to an embodiment of the present disclosure is depicted.

[0012] Figure 3B Embodiments according to this disclosure are depicted. Figure 3A The image shows a top view of an example die of a wafer and a corresponding reference image, each having a first fabrication layer.

[0013] Figure 3C Embodiments according to this disclosure are depicted. Figure 3B The example die and the corresponding reference image are top views, each having a first manufacturing layer and a second manufacturing layer.

[0014] Figure 3D Embodiments according to this disclosure are depicted. Figure 3A A cross-sectional view of an example target component in a region of the wafer.

[0015] Figure 3E The embodiments described in this disclosure include... Figure 3D A cross-sectional diagram of an example verification structure for the target component.

[0016] Figure 3F Embodiments according to this disclosure are depicted. Figure 3A A cross-sectional view of an example target component in a region of the wafer.

[0017] Figure 3G The embodiments described in this disclosure include... Figure 3F A top view of the example validation structure for the target component.

[0018] Figure 3H Embodiments according to this disclosure are depicted. Figure 3A A cross-sectional view of an example target component in a region of the wafer.

[0019] Figure 3I The embodiments described in this disclosure include... Figure 3H A top view of the example validation structure for the target component.

[0020] Figure 4 Representative main components of a computer system that can be used according to embodiments of the present disclosure are described.

[0021] Figure 5 A cloud computing environment according to embodiments of the present disclosure is described.

[0022] Figure 6 An abstraction model layer according to embodiments of the present disclosure is described.

[0023] While the invention may have various modifications and substitutions, its details have been shown by way of example in the accompanying drawings and will be described in detail. However, it should be understood that the purpose is not to limit the invention to the specific embodiments described. Rather, the invention covers all modifications, equivalents, and substitutions falling within the spirit and scope of the invention. Detailed Implementation

[0024] This disclosure relates to aspects of chip manufacturing; more specifically, to chip inspection and verification. While this disclosure is not necessarily limited to such applications, various aspects of this disclosure will be understood through discussion of various examples using this context.

[0025] Wafer manufacturing can include forming various material layers on a wafer (e.g., a silicon wafer) to create multiple electronic circuits on the wafer. These layers can be formed according to a design plan that includes detailed specifications (e.g., dimensions, shape, location, and / or material composition) for each layer of the wafer. In some cases, the design entity may submit such a design plan to the manufacturing entity for production. Such submission introduces one or more security risks. In one example, a malicious actor within the manufacturing entity could potentially modify the design plan to omit functionality or add functionality to one or more electronic circuits. Modifications could result in damage, malfunction, and / or destruction of the electronic circuits and / or the devices subsequently including the electronic circuits. Therefore, it is essential for the design entity to have effective means of verifying that each wafer is manufactured according to detailed specifications.

[0026] Obtaining this verification can be challenging. For example, circuit designs can include numerous layers and features, making malicious design modifications difficult to detect during wafer inspection. Additionally, in some cases, malicious actors may attempt to circumvent the inspection process by replacing a verified wafer with a modified or unverified one.

[0027] To address these and other challenges, embodiments of this disclosure include a wafer verification system. In some embodiments, the wafer verification system may perform specific layer inspection of the wafer during manufacturing. In some embodiments, after such specific layer inspection, the wafer verification system may verify that the completed wafer underwent specific layer inspection during manufacturing. More specifically, in some embodiments, to perform specific layer inspection, the wafer verification system may obtain a set of images of the wafer in a manufacturing state. The images may include manufacturing layers formed on the wafer after one or more pattern transfer processes. In these embodiments, the wafer verification system may confirm that one or more layers of the wafer have been formed according to predetermined specifications by comparing the set of images with a set of reference images. In some embodiments, while the wafer is in a manufacturing state, the wafer verification system may obtain physical measurements corresponding to a verification structure of the wafer. In these embodiments, the wafer verification system may verify that the received completed wafer is the same wafer from which the physical measurements were obtained. In some embodiments, the wafer verification system may perform this verification by comparing the physical measurements with calculated physical parameter values ​​corresponding to the verification structure. In some embodiments, the wafer verification system may perform this verification by comparing multiple such physical measurements with multiple calculated physical parameter values ​​corresponding to a respective verification structure of the wafer.

[0028] Therefore, embodiments of this disclosure can perform comprehensive and accurate inspection and / or verification of wafers. By comparing images of multiple manufacturing layers of a wafer, embodiments of this disclosure can identify deviations from predetermined wafer specifications at a specific layer level. Therefore, embodiments of this disclosure can provide the possibility of detecting increased design modifications to a wafer. Embodiments of this disclosure that can inspect / verify wafers based on measurements from one or more verification structures offer several advantages. For example, a verification structure for a first wafer can provide a unique physical measurement for the first wafer. Therefore, embodiments of this disclosure can verify a first wafer and / or distinguish it from different second wafers based on a unique physical measurement. Furthermore, embodiments of this disclosure can include multiple verification structures at multiple wafer locations, and each verification structure can provide such a unique physical measurement. Therefore, the verification structure, its location, and / or the unique physical measurement it provides can effectively act as a fingerprint of the wafer. Embodiments of this disclosure can identify and / or differentiate wafers based on this fingerprint. Therefore, embodiments of this disclosure can help detect when a modified or unverified wafer is presented as a verified wafer.

[0029] Switch to the attached image. Figure 1A computing environment 100 is illustrated, comprising one or more of each of a wafer verification system 105, a patterning apparatus 125, a measurement apparatus 135, an image capture apparatus 140, a computing device 145, and / or a network 150. In some embodiments, at least one wafer verification system 105, patterning apparatus 125, measurement apparatus 135, image capture apparatus 140, and / or computing device 145 may exchange data with at least one other via at least one network 150. One or more of each of the wafer verification system 105, patterning apparatus 125, measurement apparatus 135, image capture apparatus 140, computing device 145, and / or network 150 may include a computer system, such as those described above. Figure 4 The computer system under discussion is 401.

[0030] In some embodiments, the wafer verification system 105 may include software on a computer system installed on at least one of the patterning apparatus 125, the measuring device 135, the image capturing device 140, and / or the computing device 145. For example, in some embodiments, the wafer verification system 105 may include plug-in software components as software installed on the patterning apparatus 125. The wafer verification system 105 may include program instructions implemented by a processor, such as the processor of the computing device 145, to perform operations related to... Figure 2 One or more operations are being discussed.

[0031] In some embodiments, the wafer verification system 105 may include one or more modules, such as a data manager 110, an image analyzer 115, and / or a device manager 120. In some embodiments, the data manager 110, the image analyzer 115, and / or the device manager 120 may be integrated into a single module. In some embodiments, the data manager 110 may acquire, interpret, analyze, store, and / or initiate the storage of data, such as reference data for the wafer 130. In some embodiments, the image analyzer 115 may acquire and analyze an image of the wafer 130. In some embodiments, the image analyzer 115 may include a set of neural networks and / or image analysis software to identify matches between an image of the wafer 130 and a reference image of the wafer 130. In some embodiments, the device manager 120 may transmit commands to one or more pattern forming apparatuses 125, measuring apparatuses 135, image capturing apparatuses 140, and / or computing apparatuses 145. For example, in some embodiments, the device manager 120 may send commands to the measuring apparatus 135 to obtain electrical parameter measurements of the received wafer. In some embodiments, one or more of the data manager 110, image analyzer 115, and / or device manager 120 may include program instructions implemented by a processor (e.g., the processor of computing device 145) to perform operations related to... Figure 2 One or more operations discussed, for example, in some embodiments, data manager 110 may include performing... Figure 2 The program instructions for operations 205 and 240-255. In some embodiments, the image analyzer 115 may include executing... Figure 2 The program instructions for operations 210 and 220-230. In some embodiments, the device manager 120 may include program instructions for performing operations 210 and 220-230. Figure 2 The program instructions for operating 215 and 235.

[0032] In some embodiments, one or more patterning apparatuses 125 may include a set of machines and / or equipment configured to perform processes such as photolithography, etching, deposition, etc., to form a fabrication layer on wafer 130. Wafer 130 may refer to a substrate on which a set of electronic circuits can be formed. In some embodiments, wafer 130 may be made of a semiconductor material such as silicon.

[0033] In some embodiments, one or more measuring devices 135 may include a set of machines and / or equipment configured to obtain physical and / or electrical parameter measurements of the wafer 130. For example, in some embodiments, one or more measuring devices 135 may include a precision ellipsometer configured to measure the thickness of material formed on the wafer 130. In some embodiments, one or more measuring devices 135 may be configured to measure the registration accuracy between shapes printed at different or the same manufacturing level on the wafer 130. In some embodiments, one or more measuring devices 135 may include a scanning electron microscope configured to measure dimensions associated with the wafer 130. In some embodiments, one or more measuring devices may include a precision multimeter configured to obtain electrical parameter measurements of the wafer 130.

[0034] In some embodiments, one or more image capturing devices 140 may include a camera, a scanning electron microscope, etc. One or more image capturing devices may be configured to capture a set of images of the wafer 130. In some embodiments, the set of images may include images of one or more regions and / or fabricated layers of the wafer 130. In some embodiments, the patterning apparatus 125, the measuring device 135, and / or the image capturing device 140 may be integrated into a single device.

[0035] In some embodiments, one or more computing devices 145 may include a computer or server. For example, in some embodiments, one or more computing devices 145 may include a computer operating the entity of pattern forming apparatus 125, such as a manufacturing facility. One or more computing devices 145 may be configured to store and / or process data, such as one or more thresholds of wafer 130, measurement results, and / or images. In some embodiments, network 180 may be a wide area network (WAN), local area network (LAN), Internet, or intranet. In some embodiments, network 180 may be substantially similar to or identical to [the network described above]. Figure 5 The cloud computing environment under discussion is 50.

[0036] Figure 2 A flowchart is shown for an example method 200 for performing wafer inspection and verification according to an embodiment of the present disclosure. Method 200 can be performed by a wafer verification system, for example, regarding... Figure 1 The chip verification system 105 is discussed.

[0037] In operation 205, the wafer verification system may obtain reference data for one or more wafers. The reference data may include information regarding the manufacture of the one or more wafers. For example, in some embodiments, the reference data may include design specifications for manufacturing the one or more wafers. Such specifications may include information such as the dimensions, shapes, patterns, locations, orientations, and / or materials associated with features (such as trenches, leads, conductors, insulators, pillars, and / or layers) used to form electronic circuitry on the one or more wafers. In some embodiments, the reference data may include a set of reference images (e.g., digital photographs, scanning electron microscope images, etc.). In some embodiments, this set of reference images may include images from an electronic model of the wafer (e.g., a set of computer-aided design drawings of the wafer). This set of reference images may illustrate appropriate manufacturing characteristics of the wafer, i.e., the characteristics of a wafer manufactured according to its design specifications. For example, the reference images may show the appropriate dimensions, shapes, patterns, locations, orientations, and / or material characteristics of features such as trenches, leads, conductors, insulators, pillars, and / or layers of the wafer. As discussed in further detail below, the wafer verification system may use such reference images to identify deviations from the design specifications that occur during wafer manufacturing.

[0038] In some embodiments, the set of reference images may include images of the wafer following one or more patterning transfer processes. For example, in some embodiments, the design specification may include multiple patterning transfer processes (e.g., etching, deposition, and / or doping processes) to form a threshold number of fabrication layers on the wafer. In this example, the patterning transfer process may form a total of fifty fabrication layers on the wafer. In this example, the set of reference images may include images of one or more of the fifty fabrication layers formed by the respective patterning transfer processes. In this example, the set of reference images may include images of a first wafer layer formed after etching the wafer and images of a second wafer layer formed after subsequently depositing material onto the wafer. In some embodiments, the set of reference images may include one or more images for each fabrication layer of the wafer. In some embodiments, the set of reference images may include one or more images of a predetermined fabrication layer of the wafer (e.g., images of the first, third, and seventh fabrication layers of a wafer having a total of 10 fabrication layers). In some embodiments, the set of reference images may include images of the entire surface of the wafer and / or images of a predetermined region of the wafer. In some embodiments, such predetermined manufacturing layers and / or predetermined regions may be selected by an entity such as a programmer or operator of the wafer verification system or by the wafer verification system itself (e.g., the wafer verification system may randomly select manufacturing layers and / or regions whose images may be included in the set of reference images).

[0039] In operation 210, the wafer verification system can obtain one or more images of a wafer in a manufacturing state. When a wafer is in a manufacturing state, it may have a number of manufacturing layers less than a threshold number. In some embodiments, the threshold number of layers may be the total number of manufacturing layers associated with a completed wafer (e.g., a wafer for which all patterning transfer processes have been completed). For example, in some embodiments, multiple patterning transfer processes may form a total of 25 manufacturing layers or manufacturing levels on the wafer. In this example, the wafer is in a manufacturing state when it has a first manufacturing layer, a second manufacturing layer, a third manufacturing layer, etc., until all 25 manufacturing layers are formed on the wafer. In some embodiments, the wafer may be in a post-manufacturing state when it has a number of manufacturing layers equal to the threshold number of manufacturing layers associated with a completed wafer. Therefore, in the example above, when the wafer has a total of 25 manufacturing layers, it may be in a post-manufacturing state.

[0040] In some embodiments, operation 210 may include a wafer verification system that acquires a set of images of one or more manufacturing layers of a wafer. This set of images may illustrate the actual manufacturing characteristics of the wafer. For example, the images may show characteristics such as actual size, shape, pattern, location, orientation, and / or material properties of features such as trenches, leads, conductors, insulators, pillars, and / or layers of the wafer. These characteristics may or may not conform to the wafer's design specifications. In some embodiments, the set of images may include images of the entire surface of the wafer and / or images of predetermined regions of the wafer. In some embodiments, such predetermined manufacturing layers and / or predetermined regions may be selected by an entity such as a programmer or operator of the wafer verification system or by the wafer verification system itself (e.g., the wafer verification system may randomly select the manufacturing layers and / or regions whose images may be included in the set of images).

[0041] In some embodiments, operation 210 may include a wafer verification system that receives data from an image capture device (e.g., ...). Figure 1 Image capturing device 140) acquires a set of images. In some embodiments, operation 210 may include a wafer verification system that commands one or more image capturing devices to capture one or more images of the wafer. For example, in some embodiments, the wafer verification system may command a digital camera to capture an image of a first region of the wafer and command a scanning electron microscope to capture 10 images of 10 different regions of the wafer. In some embodiments, the wafer verification system may acquire images from a patterning apparatus (e.g., Figure 1 The pattern forming apparatus 125 obtains a set of images. In some embodiments, the wafer verification system can obtain images stored in a computing device (e.g., Figure 1 A set of images on the computing device 145.

[0042] In operation 215, the wafer verification system can obtain physical measurement data of the wafer in the manufacturing state. The physical measurement data may include measurements of at least one physical characteristic of the wafer. In some embodiments, when the wafer is in the manufacturing state, such physical characteristics may include visually perceptible characteristics, such as distances (e.g., length, width, height, and / or thickness). For example, in some embodiments, the width of a conductor formed on a manufacturing layer may be visually perceptible when the wafer is in the manufacturing state, but the conductor may be obscured by subsequent manufacturing layers, making it less visible (e.g., invisible) in the post-manufacturing state. Therefore, in some embodiments, an optical measurement device may measure the width of the conductor when the wafer is in the manufacturing state, but due to the reduced visibility of the conductor, the optical measurement device may prevent the measurement of such a width when the wafer is in the post-manufacturing state.

[0043] In some embodiments, the measured physical property may correspond to a target component of the verification structure. The verification structure may refer to the structure of a wafer in a post-manufacturing state. Such a verification structure may be configured to provide measurable electrical parameters corresponding to the physical properties of the target component. For example, continuing the example above, the verification structure may include a conductor formed on a fifth manufacturing layer of the wafer, and a pair of conductive probe pads formed on the fiftieth, final manufacturing layer of the wafer. In this example, the conductor may be the target component of the verification structure. As the target component, the conductor may have a physical property (in this example, width) corresponding to a measurable electrical parameter (e.g., resistance). The measurable electrical parameter may be measured across the pair of conductive probe pads formed on the fiftieth manufacturing layer of the wafer (this aspect will be further discussed below with respect to operation 235). Continuing this example, operation 215 may include a wafer verification system that obtains a measurement of the conductor's width after the conductor is formed on the fifth manufacturing layer and before its visibility is obstructed by subsequent manufacturing layers.

[0044] In some embodiments, operational features of the electronic circuitry formed on the wafer (e.g., trenches, leads, conductors, insulators, and / or pillars) can be components of the verification structure (e.g., target components). In these embodiments, the verification structure can be integrated into the design of the electronic circuitry. In some embodiments, the verification structure can be independent of the design of the electronic circuitry and can be used solely for verification as discussed in this disclosure. For example, in some embodiments, the verification structure may not contribute to the operational performance of a computer chip formed on the wafer; instead, it can be used alone to verify that the wafer is genuine when the wafer is in a post-manufacturing state.

[0045] In some embodiments, operation 215 may include the wafer verification system from a measurement device (e.g., Figure 1 The measuring device 135) obtains physical measurement data. In some embodiments, operation 215 may include the wafer verification system commanding one or more measuring devices to obtain physical measurement data from the wafer. In some embodiments, the image capture device (e.g., Figure 1 Image capturing device 140) and / or pattern forming device (e.g., Figure 1 The pattern forming apparatus 135 can be configured to obtain physical measurement data from a wafer. In these embodiments, operation 215 may include the wafer verification system obtaining physical measurement data from an image capturing apparatus and / or a pattern forming apparatus. In some embodiments, operation 215 may include the wafer verification system commanding one or more image capturing apparatuses and / or pattern forming apparatuses to obtain physical measurement data from a wafer.

[0046] By obtaining physical measurement data in operation 215, the wafer verification system can obtain a unique set of physical measurements of the wafer from one or more manufacturing layers of the wafer. For example, in some embodiments, operation 215 may include the wafer verification system obtaining a first physical measurement of a first target component on a second manufacturing layer of the wafer. In this example, the first physical measurement can be measured precisely (e.g., on the order of nanometers). Therefore, the first physical measurement can be unique because the probability that different wafers provide the same physical measurement for their respective corresponding first target components can be low. Continuing with this example, operation 215 may also include the wafer verification system obtaining a second physical measurement of a second target component on a tenth manufacturing layer of the wafer. Therefore, in this example, the set of physical measurements (i.e., the first physical measurement together with the second physical measurement) can be unique because the probability that different wafers provide the same set of physical measurement values ​​for their respective first and second target components can be low. Therefore, in some embodiments, the physical measurement data obtained in operation 215 can effectively serve as a fingerprint that facilitates wafer identification and / or differentiation. This identification and / or differentiation will be discussed further below with reference to operation 245.

[0047] In operation 220, the wafer verification system may compare one or more images of the wafer obtained in operation 210 with one or more corresponding reference images of the wafer obtained in operation 205 and determine whether one or more matches exist. In some embodiments, the wafer verification system may determine that the image of the wafer matches the corresponding reference image of the wafer when the characteristics of the image have a threshold similarity to the characteristics of the corresponding reference image. For example, in some embodiments, the wafer verification system may determine that a match exists when the indicated size, shape, number, pattern, position, orientation, and / or material of features of the wafer, such as trenches, leads, conductors, insulators, pillars, and / or layers, have a threshold similarity between the image of the wafer and the corresponding reference image of the wafer. In a more specific example, the wafer verification system may determine that a first orientation angle of a conductor shown in the image of the wafer matches a second orientation angle of a corresponding conductor shown in the reference image of the wafer when the percentage error between a first orientation angle and a second orientation angle does not exceed a threshold of 1%. In some embodiments, such threshold similarity may be selected by an entity such as a programmer or operator of the wafer verification system, or by the wafer verification system itself. In some embodiments, operation 220 may include the wafer verification system employing image analysis techniques and / or a set of neural networks to identify one or more matches between one or more images of the wafer and one or more reference images of the wafer. If the wafer verification system determines that one or more images of the wafer match one or more corresponding reference images of the wafer, the wafer verification system may proceed to operation 230. Alternatively, if the wafer verification system determines that one or more images of the wafer do not match one or more corresponding reference images of the wafer, the wafer verification system may proceed to operation 225.

[0048] In operation 225, the wafer verification system may initiate a notification indicating that one or more images of the wafer obtained in operation 210 do not match one or more corresponding reference images of the wafer obtained in operation 205. In some embodiments, the mismatched images may indicate that the wafer includes malicious design modifications. In some embodiments, such a notification may indicate that one or more manufacturing layers of the wafer are not formed according to the wafer's predetermined specifications. In some embodiments, operation 225 may include the wafer verification system generating alphanumeric text messages, audible alarms, and / or visual alarms. In some embodiments, operation 225 may include the wafer verification system issuing commands to a device, such as a computing device, to generate and / or issue such text messages and / or alarms.

[0049] In operation 230, the wafer verification system may determine whether a threshold number of manufacturing layers have been formed on the wafer. The threshold number of manufacturing layers may be the total number of manufacturing layers associated with a completed wafer (e.g., a wafer that has completed all patterning transfer processes). In some embodiments, operation 230 may include the wafer verification system analyzing reference data and / or images of the wafer to determine whether the wafer is in a manufacturing state. For example, in some embodiments, the wafer verification system may determine that the wafer is in a manufacturing state by identifying a difference between a reference image of the wafer in a post-manufacturing state and an image of the wafer. In this example, such a difference may indicate that one or more manufacturing layers need to be formed on the wafer before the wafer has a threshold number of manufacturing layers. In some embodiments, operation 230 may include the wafer verification system obtaining data from a patterning apparatus (e.g., a...). Figure 1 Pattern forming apparatus 125) or computing device (e.g., Figure 1 The computing device 145 obtains information about additional layers to be formed on the wafer. Based on this information, the wafer verification system can determine whether a threshold number of manufacturing layers are formed on the wafer. If the wafer verification system determines that a threshold number of manufacturing layers are formed on the wafer, the wafer verification system can proceed to operation 235. Alternatively, if the wafer verification system determines that a threshold number of manufacturing layers are not formed on the wafer, the wafer verification system can proceed to operation 210.

[0050] In operation 235, the wafer verification system can obtain a set of electrical parameter measurements of the received wafer. "Received wafer" can refer to a wafer in a post-manufacturing state to be certified or verified. In some embodiments, the received wafer can be measured by a measuring device (e.g., Figure 1 The measuring device 135 receives the received wafer, which can obtain the set of electrical parameter measurements from the received wafer and transmit these measurements to the wafer verification system. In some embodiments, verifying the received wafer may include identifying the received wafer as the wafer inspected in operation 220. In some embodiments, verifying the received wafer may include distinguishing the received wafer from the wafer inspected in operation 220. The wafer verification system can use the set of electrical parameter measurements to verify the received wafer.

[0051] In the example scenario, at a first moment, the wafer verification system can inspect the first wafer by image comparison, as discussed with respect to operation 220. Additionally, at the first moment, the wafer verification system can obtain physical measurements corresponding to the verification structure, as discussed with respect to operation 215. Continuing this example, at a second moment after the first moment, the measuring device can receive the wafer to be verified. The measuring device can measure the electrical parameters (e.g., capacitance, resistance, current, etc.) of the verification structure on the received wafer. Then, in operation 235, the wafer verification system can obtain the electrical parameter measurements from the measuring device.

[0052] In operation 240, the wafer verification system may calculate a set of physical parameter values ​​based on a set of electrical parameter measurements obtained in operation 235. In some embodiments, the physical parameter values ​​calculated in operation 240 may correspond to physical measurements of the target structure. For example, in some embodiments, operation 235 may include the wafer verification system obtaining capacitance measurements of the verification structure of the received wafer. In this example, the capacitance measurement may correspond to the thickness of the electrical insulator of the verification structure. Therefore, in this example, operation 240 may include the wafer verification system calculating the thickness of the electrical insulator using known scientific principles.

[0053] In operation 245, the wafer verification system may compare one or more physical parameter values ​​calculated in operation 240 with one or more physical measurements obtained in operation 215 to determine whether one or more matches exist. The presence of a match verifies that the received wafer has the physical measurements obtained by the wafer verification system in operation 215. Therefore, the presence of a match indicates that the received wafer was inspected by the wafer verification system in operation 220. The absence of a match indicates that the received wafer does not have the physical measurements obtained by the wafer verification system in operation 215. Therefore, the absence of a match indicates that the received wafer was not inspected by the wafer verification system in operation 220. If the wafer verification system determines that one or more physical parameter values ​​match one or more physical measurements, the wafer verification system may proceed to operation 250. Alternatively, if the wafer verification system determines that one or more physical parameter values ​​do not match one or more physical measurements, the wafer verification system may proceed to operation 255.

[0054] In operation 250, the wafer verification system may generate a match verification response. The match verification response may indicate that the received wafer is the same wafer that was inspected by the wafer verification system in operation 220. In some embodiments, operation 250 may include the wafer verification system generating alphanumeric text messages, audible alarms, and / or visual alarms to indicate a match. In some embodiments, operation 250 may include the wafer verification system issuing commands to a device, such as a computing device, to generate and / or issue such text messages and / or alarms.

[0055] In operation 255, the wafer verification system may generate a mismatch verification response. The mismatch verification response may indicate that the received wafer is not the wafer inspected by the wafer verification system in operation 220. In some embodiments, operation 255 may include the wafer verification system generating alphanumeric text messages, audible alarms, and / or visual alarms to indicate a missing match. In some embodiments, operation 255 may include the wafer verification system issuing commands to a device, such as a computing device, to generate and / or issue such text messages and / or alarms.

[0056] Figure 3A A top view of an example wafer 300 according to an embodiment of the present disclosure is depicted. The wafer 300 includes dies 301, 304, 308, and 312. Die 301 is located in a first region 302 of the wafer 300. Die 312 includes a second region 314, wherein a region is disposed relative to... Figure 3D and 3E The verification structure discussed. Die 308 includes a third region 310, in which a structure is provided relative to... Figure 3F and 3G The verification structure is discussed. Die 304 includes a fourth region 306, in which a structure is provided relative to... Figure 3H and 3I The verification structure is discussed.

[0057] Figure 3B Image 316 depicting die 301 and reference image 318 corresponding to die 301. Figure 2 In operation 210, image 316 can be obtained by the wafer verification system. Figure 2 In operation 205, reference image 318 can be obtained by a wafer verification system. Both image 316 and reference image 318 depict region 302 of wafer 300 in a manufacturing state. Image 316 depicts a set of conductors 320 formed on the wafer 300 as a first manufacturing layer. In some embodiments, conductors 320 may be operational features of an electronic circuit design. Reference image 318 depicts a set of reference conductors 322 of the first reference manufacturing layer of wafer 300. Reference conductors 322 may indicate appropriate characteristics of the set of conductors 320. For example, reference conductors 322 may have dimensions consistent with the design specifications of wafer 300. Therefore, in this example, the wafer verification system can compare image 316 with reference image 318 and determine an image match. In this example, the wafer verification system may determine this match based on a threshold that the percentage error between the dimensions of conductors 320 and the dimensions of reference conductors 322 does not exceed 5%.

[0058] Figure 3C Images 324 and 326, corresponding to image 316 and reference image 318 respectively, are depicted. Image 324 can be derived from... Figure 2 The wafer verification system in operation 210 is used to obtain the reference image 326. Figure 2The image is obtained by the wafer verification system in operation 205. Image 324 depicts region 302 of wafer 300 after a set of conductors 328, 330 are formed on wafer 300 to form a second manufacturing layer. In some embodiments, conductors 328 may be operational features of an electronic circuit design. Reference image 326 depicts a set of reference conductors 332, 334 of the second reference manufacturing layer of wafer 300. Similar to reference conductor 322, reference conductors 332, 334 may exhibit appropriate characteristics of the set of conductors 328, 330. For example, reference conductors 332, 334 may have lengths consistent with the design specifications of wafer 300. Therefore, in this example, the wafer verification system can compare image 324 with reference image 326 and determine that the images do not match. In this example, the wafer verification system may determine a missing match based on a percentage error between the length of conductor 330 and the length of reference conductor 334 exceeding a 2% threshold. In this example, the mismatched image may indicate that wafer 300 has malicious design modifications to the second manufacturing layer of wafer 300.

[0059] Figure 3D A cross-sectional view of an example target component 338 in region 314 of a wafer 300 according to an embodiment of the present disclosure is depicted. The target component 338 may be an insulator formed on a conductive layer 340 of the wafer 300. Figure 3D In this process, wafer 300 is in a manufacturing state; therefore, target component 338 can have a top surface 350 that is not obstructed by subsequent manufacturing layers. Because the top surface 350 of target component 338 is unobstructed, the wafer verification system can obtain physical measurements of target component 338 (e.g., thickness measurements). Figure 2 As described in Operation 215, the wafer verification system can obtain physical measurements. In some embodiments, the wafer verification system can use an ellipsometer to obtain physical measurements.

[0060] Figure 3E A cross-sectional view of an example verification structure 342 including target component 338 according to an embodiment of the present disclosure is depicted. Figure 3E In this configuration, wafer 300 is in a post-manufacturing state. Therefore, verification structure 342 includes a target component 338 formed on conductive layer 340, as well as conductors 344 and probe pads 348 and 346. Probe pads 348 and 346 are included in a manufacturing layer formed above the manufacturing layer including the target component 338. Additionally, when wafer 300 is in a post-manufacturing state, the top surface 350 of the target component 338 may be obstructed; therefore, physical measurements of the target component 338 may not be possible using devices such as ellipsometers. However, verification structure 342 can be configured to provide measurements of electrical parameters (e.g., the capacitance between probe pads 348 and 346). By employing known scientific principles, the wafer verification system can calculate the thickness of the target component 338 based on this capacitance, such as regarding... Figure 2 Operation 240 is described. Using the calculated thickness, the wafer verification system can verify the wafer, as described in section 240. Figure 2 As described in operation 245.

[0061] Figure 3F A cross-sectional view is depicted of an exemplary target component 356 in region 310 of a wafer 300 according to an embodiment of the present disclosure. The target component 356 may be a conductor formed on an insulator 358 of the wafer 300. Figure 3F In this process, wafer 300 is in a manufacturing state; therefore, target component 356 can have a visible top surface 354. Since the top surface 354 is visible, the wafer verification system can obtain physical measurements of target component 356 (e.g., width 363).

[0062] Figure 3G A top view of an example verification structure 360 ​​including target component 356 according to an embodiment of the present disclosure is depicted. Figure 3G In this case, wafer 300 is in a post-manufacturing state. Therefore, target component 356 is covered by a subsequent layer of insulator 358 and is not visible. In this example, verification structure 360 ​​can be configured to provide electrical parameter measurements (e.g., resistance between probe pads 362 and 364). By employing known scientific principles, the wafer verification system can calculate the width 363 of target component 356 based on this resistance, as per [the relevant information]. Figure 2 As described in operation 240. Using the calculated width 363, the wafer verification system can verify the wafer, as per [the relevant information]. Figure 2 As described in operation 245.

[0063] Figure 3H A cross-sectional view depicting an exemplary target component 378 in region 306 of a wafer 300 according to an embodiment of the present invention. The target component 378 may be the width of an insulator 370 between a first conductor 372 and a second conductor 368. Figure 3H In this process, wafer 300 is in a manufacturing state; therefore, target component 378 can be visible during one or more pattern transfer processes. Thus, the wafer verification system can obtain the width of target component 378 as a physical measurement.

[0064] Figure 3I A top view of an example verification structure 374 including a target component 378 according to an embodiment of the present disclosure is depicted. Figure 3IIn this configuration, wafer 300 is in a post-fabrication state; therefore, target component 378 is not visible due to the subsequent layers of insulator 370. In this example, verification structure 374 can be configured to provide electrical parameter measurements (e.g., probing leakage current or capacitance between pads 366 and 376). By employing known scientific principles, the wafer verification system can calculate the width of target component 378 based on this leakage current, such as regarding... Figure 2 Operation 240 describes this. Using the calculated width, the wafer verification system can verify the wafer, as described in section 240. Figure 2 As described in operation 245.

[0065] In some embodiments, the chip 300 may include a reference. Figure 3A and 3D -3I describes at least one of the verification structures. In some embodiments, wafer 300 may include verification structures having components (e.g., target components) in different manufacturing layers of wafer 300. For example, in some embodiments, the target component for a first verification structure may be formed in the tenth manufacturing layer of wafer 300, and the target component for a second verification structure may be formed in the thirtieth manufacturing layer of wafer 300, wherein the thirtieth layer is formed above or on top of the tenth manufacturing layer. In some embodiments, probe pads for one or more verification structures of wafer 300 may be formed in the same layer of wafer 300.

[0066] Figure 4 Representative main components of an exemplary computer system 401 that can be used according to embodiments of the present disclosure are depicted. The specific components described are presented for illustrative purposes only and are not necessarily the only such variations. Computer system 401 may include a processor 410, memory 420, input / output interfaces (also referred to herein as I / O or I / O interfaces) 430, and a main bus 440. Main bus 440 may provide communication paths for other components of computer system 401. In some embodiments, main bus 440 may be connected to other components such as a dedicated digital signal processor (not shown).

[0067] The processor 410 of the computer system 401 may include one or more CPUs 412. The processor 410 may additionally include one or more memory buffers or caches (not shown) that provide temporary storage for instructions and data for the CPU 412. The CPU 412 may execute instructions on input provided from a cache or memory 420 and output results to the cache or memory 420. The CPU 412 may consist of one or more circuits configured to perform one or more methods according to embodiments of the present disclosure. In some embodiments, the computer system 401 may include a relatively large number of processors 410 typical of a system. However, in other embodiments, the computer system 401 may be a single processor with a single CPU 412.

[0068] The memory 420 of computer system 401 may include a memory controller 422 and one or more memory modules (not shown) for temporary or permanent storage of data. In some embodiments, memory 420 may include random access semiconductor memory, storage devices, or storage media (volatile or non-volatile) for storing data and programs. Memory controller 422 may communicate with processor 410 to facilitate the storage and retrieval of information in the memory modules. Memory controller 422 may communicate with I / O interface 430 to facilitate the storage and retrieval of inputs or outputs in the memory modules. In some embodiments, the memory modules may be dual in-line memory modules.

[0069] I / O interface 430 may include I / O bus 450, terminal interface 452, memory interface 454, I / O device interface 456, and network interface 458. I / O interface 430 can connect main bus 440 to I / O bus 450. I / O interface 430 can route instructions and data from processor 410 and memory 420 to various interfaces of I / O bus 450. I / O interface 430 can also route instructions and data from various interfaces of I / O bus 450 to processor 410 and memory 420. The various interfaces may include terminal interface 452, memory interface 454, I / O device interface 456, and network interface 458. In some embodiments, the various interfaces may include a subset of the aforementioned interfaces (e.g., embedded computer systems in industrial applications may not include terminal interface 452 and memory interface 454).

[0070] The logical modules throughout computer system 401—including, but not limited to, memory 420, processor 410, and I / O interface 430—can communicate faults and changes to one or more components to a hypervisor or operating system (not depicted). The hypervisor or operating system can allocate various resources available in computer system 401 and track processes allocated to various CPUs 412 and the location of data in memory 420. In embodiments that combine or rearrange elements, aspects of the capabilities of the logical modules can be combined or redistributed. These variations will be apparent to those skilled in the art.

[0071] It should be understood in advance that although this disclosure includes a detailed description of cloud computing, the implementation of the teachings described herein is not limited to a cloud computing environment. Rather, embodiments of the invention can be implemented in conjunction with any other type of computing environment now known or developed hereafter.

[0072] Cloud computing is a service delivery model that enables convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with the service provider. This cloud model may include at least five features, at least three service models, and at least four deployment models.

[0073] The characteristics are as follows:

[0074] On-demand self-service: Cloud consumers can unilaterally and automatically provide computing power, such as server time and network storage, as needed, without requiring manual interaction with the service provider.

[0075] Wide Area Network (WAN) Access: Gaining capabilities on a network and accessing them through standard mechanisms that facilitate the use of heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

[0076] Resource pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically allocated and reallocated based on demand. Location independence has significance because consumers typically do not control or know the exact location of the resources provided, but can specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0077] Rapid Flexibility: In some cases, the ability to scale outwards and inwards quickly and flexibly can be provided. For consumers, the available capacity often appears unlimited and can be purchased in any quantity at any time.

[0078] Measurement services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at a level of abstraction appropriate to the service type (e.g., storage, processing, bandwidth, and activated user accounts). Resource utilization can be monitored, controlled, and reported, providing transparency for both service providers and consumers.

[0079] The service model is as follows:

[0080] Software as a Service (SaaS): The capability offered to consumers is the ability to use applications from a provider that run on cloud infrastructure. These applications can be accessed from various client devices through thin client interfaces such as web browsers (e.g., web-based email). Consumers do not manage or control the underlying cloud infrastructure, including the network, servers, operating system, storage, or even individual application capabilities, with possible exceptions such as limited user-specific application configuration settings.

[0081] Platform as a Service (PaaS): This provides consumers with the ability to deploy applications created or acquired by the consumer onto cloud infrastructure using programming languages ​​and tools supported by the provider. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but they have control over the deployed applications and the configuration of any application hosting environment.

[0082] Infrastructure as a Service (IaaS): This provides consumers with the capability to offer processing, storage, networking, and other basic computing resources that enable consumers to deploy and run arbitrary software, which may include operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but they have control over the operating system, storage, deployed applications, and possibly limited control over selected networking components (e.g., host firewalls).

[0083] The deployment model is as follows:

[0084] Private cloud: Cloud infrastructure operated solely by an organization. It can be managed by the organization or a third party and can exist inside or outside a building.

[0085] Community cloud: Cloud infrastructure shared by several organizations and supporting a specific community with shared concerns (e.g., tasks, security requirements, policies, and compliance considerations). It can be managed by an organization or a third party and can exist on-site or off-site.

[0086] Public cloud: Cloud infrastructure available to the general public or large industrial groups and owned by organizations that sell cloud services.

[0087] Hybrid cloud: A cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain a single entity but are bound together by standardized or proprietary technologies that enable data and applications to be ported together (e.g., cloud bursting for load balancing between clouds).

[0088] Cloud computing environments are service-oriented, focusing on statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is the infrastructure of a network of interconnected nodes.

[0089] Now for reference Figure 5 The diagram illustrates an illustrative cloud computing environment 50. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 10 with which local computing devices used by cloud consumers can communicate, such as personal digital assistants (PDAs) or cellular phones 54A, desktop computers 54B, laptop computers 54C, and / or automotive computer systems 54N. The nodes 10 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks, such as private clouds, community clouds, public clouds, or hybrid clouds or combinations thereof as described above. This allows the cloud computing environment 50 to provide infrastructure, platform, and / or software as a service, without requiring cloud consumers to maintain resources on their local computing devices. It should be understood that... Figure 5 The types of computing devices 54A-N shown are for illustrative purposes only, and computing node 10 and cloud computing environment 50 can communicate with any type of computerized device on any type of network and / or network-addressable connection (e.g., using a web browser).

[0090] Now for reference Figure 6 This demonstrates a cloud computing environment of 50 ( Figure 5 This provides a set of functional abstraction layers. It should be understood beforehand that... Figure 6 The components, layers, and functions shown are for illustrative purposes only, and embodiments of the invention are not limited thereto. As depicted, the following layers and corresponding functions are provided:

[0091] The hardware and software layer 60 includes hardware and software components. Examples of hardware components include: a host 61; a server 62 based on a RISC (Reduced Instruction Set Computer) architecture; a server 63; a blade server 64; a storage device 65; and a network component 66. In some embodiments, the software components include network application server software 67 and database software 68.

[0092] The virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual server 71; virtual storage 72; virtual network 73, including virtual private network; virtual application and operating system 74; and virtual client 75.

[0093] In one example, management layer 80 may provide the following functionalities: Resource Provisioning 81 provides dynamic procurement of computing resources and other resources used to perform tasks within the cloud computing environment. Metering and Pricing 82 provides cost tracking when utilizing resources in the cloud computing environment, as well as billing or invoicing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides authentication for cloud consumers and tasks, as well as protection for data and other resources. User Portal 83 provides access to the cloud computing environment for consumers and system administrators. Service Level Management 84 provides cloud resource allocation and management to ensure that required service levels are met. Service Level Agreement (SLA) Planning and Fulfillment 85 provides pre-scheduling and procurement of cloud resources, where future needs are anticipated according to the SLA.

[0094] Workload layer 90 provides examples of functionalities that can be leveraged in a cloud computing environment. Examples of workloads and functionalities that can be provided from this layer include: mapping and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analysis and processing 94; transaction processing 95; and inspection / verification logic 96.

[0095] As discussed in more detail herein, it is conceivable that some or all of the operations of some embodiments of the methods described herein may be performed in an alternative order or may not be performed at all; furthermore, multiple operations may occur simultaneously or as part of a larger process.

[0096] Embodiments of the present invention can be systems, methods, and / or computer program products at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or medium) having computer-readable program instructions thereon for causing a processor to perform aspects of the present invention.

[0097] Computer-readable storage media can be tangible devices capable of retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or recessed structures with instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0098] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device, or via a network, such as the Internet, a local area network (LAN), a wide area network (WAN), and / or a wireless network, to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the respective computing / processing device.

[0099] Computer-readable program instructions for performing the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or entirely on a server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing state information from the computer-readable program instructions.

[0100] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0101] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0102] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which are executed on the computer, other programmable apparatus or other device, implement the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0103] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may occur in a different order than indicated in the figures. For example, two blocks shown consecutively may actually be implemented as a single step, executed simultaneously, substantially simultaneously, with partial or complete time overlap, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0104] Various embodiments of this disclosure have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computer-implemented method, comprising: Obtain the first reference image of the first wafer; Obtain a first image of the first wafer in the manufacturing process. In the manufacturing state, the first wafer has a number of manufacturing layers that is less than a threshold number; The first chip has a first verification structure; When the first wafer is in the manufacturing state, a first physical measurement corresponding to the first verification structure is obtained; In the first instance, the matching of the first image and the first reference image is determined by comparing the first image with the first reference image; At a second time following the first time, electrical parameter measurements corresponding to the verification structure of the received wafer in the post-manufacturing state are obtained; In the post-manufacturing state, the received wafer has a second number of manufacturing layers equal to the threshold number; Based on the electrical parameter measurements, calculate the physical parameter values; and A verification response is generated by comparing the physical parameter values ​​with the first physical measurement.

2. The computer-implemented method according to claim 1 further includes: Based on the comparison between the physical parameter value and the first physical measurement, it is determined that the physical parameter value matches the first physical measurement. Specifically, in response to determining that the physical parameter value matches the first physical measurement, generating the verification response includes: indicating that the received wafer is the first wafer in the post-manufacturing state. In the post-manufacturing state, the first wafer has a second number of manufacturing layers equal to the threshold number.

3. The computer-implemented method according to claim 2, wherein, The first verification structure includes a target component; Wherein, the first physical measurement is the measurement of the physical characteristics of the target component; Wherein, when the first wafer is in the manufacturing state, the target component has a first visibility; Wherein, when the first wafer is in the post-manufacturing state, the target component has a second visibility; and The second visibility is less than the first visibility.

4. The computer-implemented method according to claim 1, wherein, The first physical measurement is selected from the group consisting of: the thickness of the insulating material, the width of the conductor, and the distance between the first conductor and the second conductor.

5. The computer-implemented method according to claim 1, further comprising: Based on the comparison between the physical parameter value and the first physical measurement, it is determined that the physical parameter value does not match the first physical measurement. Specifically, in response to determining that the physical parameter value does not match the first physical measurement, generating the verification response includes indicating that the received wafer is not the first wafer.

6. The computer-implemented method according to claim 1, wherein, The first reference image depicts a first reference fabrication layer of the first wafer; Wherein, the first image depicts the first manufacturing layer of the first wafer; and The comparison of the first image with the first reference image includes: comparing the first manufacturing layer with the first reference manufacturing layer.

7. The computer-implemented method according to claim 6, further comprising: Obtain a second image of the first wafer in the manufacturing state. The second image depicts the first manufacturing layer and the second manufacturing layer of the first wafer; Obtain a second reference image of the first wafer; Wherein, the second reference image depicts the first reference fabrication layer and the second reference fabrication layer of the first wafer; and By comparing the second image with the second reference image, it is determined that the second image matches the second reference image.

8. A system comprising: One or more processors; as well as One or more computer-readable storage media storing program instructions, which, when executed by the one or more processors, are configured to cause the one or more processors to perform a method comprising: Obtain the first reference image of the first wafer; Obtain a first image of the first wafer in the manufacturing process. In the manufacturing state, the first wafer has a number of manufacturing layers that is less than a threshold number; The first chip has a first verification structure; When the first wafer is in the manufacturing state, a first physical measurement corresponding to the first verification structure is obtained; In the first instance, the matching of the first image and the first reference image is determined by comparing the first image with the first reference image; At a second time following the first time, electrical parameter measurements corresponding to the verification structure of the received wafer in the post-manufacturing state are obtained; In the post-manufacturing state, the received wafer has a second number of manufacturing layers equal to the threshold number; Based on the electrical parameter measurements, calculate the physical parameter values; and A verification response is generated by comparing the physical parameter values ​​with the first physical measurement.

9. The system according to claim 8, wherein the method further comprises: Based on the comparison between the physical parameter value and the first physical measurement, it is determined that the physical parameter value matches the first physical measurement. Specifically, in response to determining that the physical parameter value matches the first physical measurement, generating the verification response includes: indicating that the received wafer is the first wafer in the post-manufacturing state. In the post-manufacturing state, the first wafer has a second number of manufacturing layers equal to the threshold number.

10. The system according to claim 9, wherein, The first verification structure includes a target component; Wherein, the first physical measurement is the measurement of the physical characteristics of the target component; Wherein, when the first wafer is in the manufacturing state, the target component has a first visibility; Wherein, when the first wafer is in the post-manufacturing state, the target component has a second visibility; and The second visibility is less than the first visibility.

11. The system according to claim 8, wherein, The first physical measurement is selected from the group consisting of: the thickness of the insulating material, the width of the conductor, and the distance between the first conductor and the second conductor.

12. The system according to claim 8, wherein the method further comprises: Based on the comparison between the physical parameter value and the first physical measurement, it is determined that the physical parameter value does not match the first physical measurement. Specifically, in response to determining that the physical parameter value does not match the first physical measurement, generating the verification response includes indicating that the received wafer is not the first wafer.

13. The system according to claim 8, wherein, The first reference image depicts a first reference fabrication layer of the first wafer; Wherein, the first image depicts the first manufacturing layer of the first wafer; and The comparison of the first image with the first reference image includes: comparing the first manufacturing layer with the first reference manufacturing layer.

14. A computer program product comprising one or more computer-readable storage media and program instructions commonly stored on the one or more computer-readable storage media, the program instructions including instructions configured to cause one or more processors to perform a method, the method comprising: Obtain the first reference image of the first wafer; Obtain a first image of the first wafer in the manufacturing process. In the manufacturing state, the first wafer has a number of manufacturing layers that is less than a threshold number; The first chip has a first verification structure; When the first wafer is in the manufacturing state, a first physical measurement corresponding to the first verification structure is obtained; In the first instance, the matching of the first image and the first reference image is determined by comparing the first image with the first reference image; At a second time following the first time, electrical parameter measurements corresponding to the verification structure of the received wafer in the post-manufacturing state are obtained; In the post-manufacturing state, the received wafer has a second number of manufacturing layers equal to the threshold number; Based on the electrical parameter measurements, calculate the physical parameter values; and A verification response is generated by comparing the physical parameter values ​​with the first physical measurement.

15. The computer program product according to claim 14, wherein the method further comprises: Based on the comparison between the physical parameter value and the first physical measurement, it is determined that the physical parameter value matches the first physical measurement. Specifically, in response to determining that the physical parameter value matches the first physical measurement, generating the verification response includes: indicating that the received wafer is the first wafer in the post-manufacturing state. In the post-manufacturing state, the first wafer has a second number of manufacturing layers equal to the threshold number.

16. The computer program product according to claim 15, wherein, The first verification structure includes a target component; Wherein, the first physical measurement is the measurement of the physical characteristics of the target component; Wherein, when the first wafer is in the manufacturing state, the target component has a first visibility; Wherein, when the first wafer is in the post-manufacturing state, the target component has a second visibility; and The second visibility is less than the first visibility.

17. The computer program product according to claim 14, wherein, The first physical measurement is selected from the group consisting of: the thickness of the insulating material, the width of the conductor, and the distance between the first conductor and the second conductor.

18. The computer program product of claim 14, wherein the method further comprises: Based on the comparison between the physical parameter value and the first physical measurement, it is determined that the physical parameter value does not match the first physical measurement. Specifically, in response to determining that the physical parameter value does not match the first physical measurement, generating the verification response includes indicating that the received wafer is not the first wafer.

19. The computer program product according to claim 14, wherein, The first reference image depicts a first reference fabrication layer of the first wafer; Wherein, the first image depicts the first manufacturing layer of the first wafer; and The comparison of the first image with the first reference image includes: comparing the first manufacturing layer with the first reference manufacturing layer.

20. A computer-implemented method, comprising: Obtain the first physical measurement corresponding to the first verification structure of the first wafer in the manufacturing state. In the aforementioned manufacturing state, the first wafer has a number of manufacturing layers less than a threshold number. Obtain electrical parameter measurements corresponding to the verification structure of the received wafer in its post-manufacturing state. In the post-manufacturing state, the received wafer has a second number of manufacturing layers equal to the threshold number. Based on the electrical parameter measurements, calculate the physical parameter values; and A verification response is generated by comparing the physical parameter values ​​with the first physical measurement.

21. An apparatus comprising: A wafer having a first verification structure in a first region of the wafer and a second verification structure in a second region of the wafer. Wherein, the first verification structure includes a first target component, and the second verification structure includes a second target component, and Wherein, the first verification structure has a first measurable electrical parameter corresponding to a first physical characteristic of the first target component, and the second verification structure has a second measurable electrical parameter corresponding to a second physical characteristic of the second target component, and The first physical characteristic of the first target component corresponding to the first measurable electrical parameter and the second physical characteristic of the second target component corresponding to the second measurable electrical parameter together form the unique identifier of the wafer.

22. The apparatus according to claim 21, wherein, The wafer includes a first manufacturing layer and a second manufacturing layer, wherein the second manufacturing layer is formed on top of the first manufacturing layer. The first target component is included in the first manufacturing layer. The first verification structure further includes a first pair of pads, which are included in the second manufacturing layer. The first measurable electrical parameter can be measured through the first pair of pads.

23. The apparatus according to claim 22, wherein, The wafer further includes a third manufacturing layer formed on top of the first manufacturing layer, and the second manufacturing layer formed on top of the third manufacturing layer. The second target component is included in the third manufacturing layer. The second verification structure further includes a second pair of pads, which are incorporated within the second manufacturing layer. The second measurable electrical parameter can be measured via the second pair of pads.

24. The apparatus according to claim 21, wherein, The first target component is an insulator. The first measurable electrical parameter is capacitance. The first physical characteristic is thickness. The second target component is a conductor. Wherein, the second measurable electrical parameter is resistance, and The second physical characteristic is width.

Images