Systems and methods for providing leakage reduction for power gated domains

Abstract

A system includes: a first power supply; a second power supply; a head switch disposed between the first power supply and a logic circuit device; an enable driver coupling the second power supply to a control terminal of the head switch; and a voltage generator operable to: in response to a first voltage level of the first power supply exceeding a reference voltage level, adjust a control voltage from the second power supply to the control terminal of the head switch.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Patent Application No. 17 / 015,466, filed on September 9, 2020, the entire contents of which are fully set forth below and are incorporated herein by reference for all applicable purposes. Technical Field

[0003] The present application relates generally to power gated domains and, more particularly, to reducing leakage in power gated switches. Background Art

[0004] Conventional computing devices (e.g., smartphones, tablet computers, etc.) may include a system on a chip (SOC) having a processor and other operating circuits. The SOC may receive its power from a battery, so conventional designs may balance SOC performance and power usage to provide the user with a desired experience while requiring as little battery charging as possible.

[0005] Power gating is a technique that can be used to save power in some cases. One way some systems can use power gating to save power is to implement a power collapse of some parts of the processing core (using a first power multiplexer and a first power domain) while providing power to other parts of the processing core (using a second power multiplexer and a second power domain). Another way some conventional systems can use power gating is to switch from a first power supply to a second power supply to power the central processing unit (CPU) memory, and then adjust the second power supply to overdrive the CPU memory. This technique can save power by allowing the SOC to selectively increase the voltage at some components without increasing the voltage at other components. Of course, power gating can also include simply causing the power to collapse at one or more components that are not in use, and then restoring the power later.

[0006] Some power gating circuits may use a head switch or a foot switch, each with a transistor. The transistor may be turned off to power down the corresponding portion of the processing core or other processing logic. However, even if the transistor is turned off, it may still allow some leakage current. For example, for a P-channel metal oxide semiconductor (PMOS) head switch, it is turned off when its gate-source voltage is greater than or equal to zero. The real-world PMOS head switch is not an ideal switch, and there may be leakage current even in the off state. Leakage may be converted into power drawn from a power supply that is always on, resulting in a shortened battery life. Therefore, circuits and techniques to reduce leakage are needed. Summary of the invention

[0007] Various embodiments provide circuits and techniques for reducing leakage in a power gating switch. In an example embodiment, a PMOS head switch is maintained in a super cutoff state when it is turned off. The super cutoff state can include providing a positive gate-source voltage to the transistor in at least some voltage ranges. In addition, in this example, when the source voltage exceeds a threshold, the system can adjust the gate-source voltage to approximately zero so that the transistor remains in an off state, but not in a super cutoff state.

[0008] According to one embodiment, a system includes: a first power supply; a second power supply; a head switch disposed between the first power supply and a logic circuit device; an enable driver coupling the second power supply to a control terminal of the head switch; and a voltage generator operable to: in response to a first voltage level of the first power supply exceeding a reference voltage level, adjust a control voltage from the second power supply to the control terminal of the head switch.

[0009] According to another embodiment, a method includes: enabling a head switch to conduct current from a first power supply to a logic circuit device; and shutting off the current by disabling the head switch, including: selecting a first voltage level from a first voltage level and a second voltage level in response to comparing the first voltage level and the second voltage level; and applying the first voltage level from a second power supply to a gate of the head switch.

[0010] According to another embodiment, a circuit includes: a first power rail coupled to a first power supply; a second power rail coupled to a second power supply; a power gating switch coupled between the first power rail and a portion of a logic circuit device of a central processing unit (CPU); and means for selecting a control voltage from the second power rail to a control terminal of the gating switch in response to a first voltage level of the first power supply being lower than a reference voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a simplified diagram illustrating an example system for power gating logic circuitry according to one implementation.

[0012] Figure 2 It is shown that according to one embodiment Figure 1 FIG. 1 is a graph of an example relationship between a drain current of a head switch and a gate voltage of the head switch.

[0013] Figure 3 It shows that according to Figure 2 Graph of an example relationship between gate voltage and source voltage for an embodiment of the present invention.

[0014] Figure 4 is used for Figure 1 0048] Figure 2 is a diagram of various voltage levels in an embodiment of the present invention.

[0015] Figure 5 is a diagram of an example voltage generator adapted in accordance with one implementation.

[0016] Figure 6 It is shown that according to one embodiment Figure 1 A simplified diagram of a system that can be repeated to power down multiple sections of logic.

[0017] Figure 7 is a diagram of a reference voltage circuit for generating a reference voltage according to one embodiment.

[0018] Figure 8 is an illustration of a method of multiplexing between multiple power supplies according to one embodiment. DETAILED DESCRIPTION

[0019] Various embodiments provided herein include systems and methods for providing power gating for a logic circuit, the systems and methods having reduced leakage compared to other embodiments. An example includes a first power supply, the first power supply is coupled to the source of a transistor. A second power supply is coupled to a control terminal (e.g., a gate) of the transistor. The transistor itself, which may include a head switch, is disposed between the first power supply and a logic circuit device (e.g., the drain of the transistor may be coupled to the logic circuit device). An enabling driver such as a buffer with an inverter may couple the second power supply to the gate of the transistor.

[0020] Continuing with this example, the system may also include a voltage generator for adjusting a control voltage from the second power supply to the control terminal of the transistor. The voltage generator adjusts the control voltage in response to the voltage level of the first power supply exceeding a reference voltage level. The reference voltage level may be set at any suitable value, which may be selected by trial and error, simulation, etc. In this example embodiment, the reference voltage level is set so that the level of the control voltage reduces or avoids gate induced drain leakage (GIDL).

[0021] Thus, in this example, during the off-state of the transistor, the transistor can be maintained in a super-cutoff state where the gate voltage is higher than the source voltage. However, the transistor may have an operating region in which a positive gate-source voltage reaching above a certain gate voltage level may actually increase leakage rather than reduce leakage. This increased leakage is referred to as GIDL. Maintaining a positive gate-source voltage during the off-state of the transistor may not be effective if the source voltage varies and may reach a level that determines the gate voltage to cause GIDL.

[0022] In one example, the proposed system and method reduces or eliminates GIDL by providing a voltage generator that adjusts a control voltage from a second power supply to a gate of a transistor. When a source voltage from a first power supply exceeds a reference voltage level, the voltage generator can adjust the control voltage from the second power supply so that it is approximately equal to the source voltage.

[0023] In other words, when the source voltage from the first power supply exceeds the reference voltage level, the voltage generator may then adjust the control voltage so that the gate-source voltage is zero or approximately zero. As described above, a zero gate-source voltage may still result in leakage, but the system may be designed so that the leakage caused by the zero gate-source voltage is less than the leakage experienced due to the GIDL.

[0024] In one example, the voltage generator includes a comparator having a first input coupled to a first power supply and a second input coupled to a reference voltage. The voltage generator may also include a circuit device operable to adjust a control voltage between a first voltage level (of the first power supply) and a second voltage level (reference voltage level) in response to an output of the comparator. For example, if the voltage level of the first power supply exceeds the reference voltage level, the voltage generator may output the voltage level of the first power supply as the control voltage. On the other hand, if the voltage level of the first power supply is lower than the reference voltage level, the voltage generator may output the reference voltage level as the control voltage.

[0025] Various embodiments may also include methods. An example method includes enabling a head switch to conduct current from a first power source to a logic circuit device. When the head switch is in an on state and conducts current to the logic circuit device, the logic circuit device is not power-collapsed. The method may also include shutting off the current by disabling the head switch, thereby power-collapse the logic circuit device. Shutting off the current may include selecting a first voltage level from a first voltage level and a second voltage level in response to comparing the first voltage level and the second voltage level. For example, the first voltage level may include a source voltage, and the second voltage level may include a reference voltage, so the method includes selecting the source voltage or the reference voltage to be applied to the gate of the transistor as a control voltage.

[0026] Various embodiments may include advantages over other systems. One advantage includes reducing leakage by applying a super cutoff state to the power gating switch. The super cutoff state can reduce leakage, and the reduction of the leakage exceeds the leakage achieved by simply turning off the power gating switch. In addition, the circuits described herein can use less silicon area than other alternatives to achieve the super cutoff state. Specifically, some embodiments described herein can provide the use of an operational amplifier (op amp) and a plurality of transistors to provide voltage selection, which has less overhead than previously considered for other leakage reduction alternatives.

[0027] Figure 1 1 is a simplified diagram illustrating an example system 100 for power-gating a logic circuit device 120 according to one embodiment. The example system 100 includes an enable driver 102 that provides a control voltage to a control terminal (gate) of a head switch 108. The head switch 108 in this example includes a P-channel metal oxide semiconductor (PMOS) transistor that is disposed between a first power supply (Vdd_ext) and the logic circuit device 120. Specifically, a source of the head switch 108 is coupled to a power supply 106 that provides power to the logic circuit device 120 when the head switch 108 is turned on. A drain of the head switch 108 is coupled to a power-gated power rail 110 that provides power to the logic circuit device 120.

[0028] The behavior of head switch 108 is such that when its gate-source voltage is greater than or equal to zero, head switch 108 turns off, thereby powering down logic circuit device 120. Similarly, when its gate-source voltage is negative, head switch 108 turns on, thereby powering logic circuit device 120 from power rail 106.

[0029] The enable driver 102 is coupled to the second power supply 104 (Vdd_Drvr). The enable driver 102 is also coupled to a level shifter 112 and an enable control circuit device 114. When the enable signal (Sw_enable) is high, the enable driver 102 drives a zero to the gate of the head switch 108, thereby turning on the head switch 108. When the enable signal is low, the enable driver drives a logic one to the gate of the head switch 108, thereby turning off the head switch 108. The level shifter 112 outputs an enable signal at the same voltage (Vdd_Drvr) as the second power supply 104. The enable control circuit device 114 determines whether the enable signal is high or low and can communicate with other components, such as an adaptive power program running in an operating system kernel (kernel) of a central processing unit (CPU) core, which may or may not include the logic circuit device 120.

[0030] As described above, the enable signal is at the same voltage as the second power supply 104, and the enable driver 102 outputs the same voltage as the voltage received on the power rail coupled to the power supply 104. Therefore, when the head switch 108 is turned off, the enable signal becomes zero, which passes Vdd_Drvr (digital 1) to the gate of the head switch 108. Now, the voltage difference between the gate and the source (gate-source voltage) is Vdd_Drvr minus Vdd_ext. As described below, various embodiments can change Vdd_Drvr so that it can be higher than Vdd_ext to put the PMOS transistor of the head switch 108 into a super cut-off state.

[0031] Reference now Figure 2 , Figure 2 is a graph illustrating an example relationship between the drain current of the headswitch 108 (on the Y-axis) and the gate voltage of the headswitch 108 (on the x-axis).

[0032] Figure 2 The graph of assumes that the voltage Vdd_ext at the first power supply 106 is equal to 0.6 V. It should be noted that the various voltages discussed herein are merely examples, and other applications may use different voltages for the gate or source of the head switch 108, as appropriate for the particular transistor used for the head switch 108.

[0033] The drain current is mostly high and positive until the gate voltage equals the source voltage, or in other words, the gate-source voltage equals zero. This is shown at 201. However, when the gate-source voltage equals zero, the current at the drain is not completely zero. Instead, the drain current can be further reduced as shown at point 204, where the gate voltage is 0.7V. The portion of graph 200 where the gate-source voltage is positive is referred to as the super-cutoff state of the transistor. The current at point 201 is approximately seven times the current at point 204, thereby showing that the super-cutoff state can be further reduced. Figure 1 . In addition, it should be noted that as the gate voltage increases beyond point 205 (the gate voltage is approximately 0.8V), the GIDL increases, thereby offsetting some or all of the gain from placing the transistor in the super-cut state. Therefore, various embodiments described herein can adjust the control voltage from the second power supply 104 to the control terminal of the head switch 108 to achieve the super-cut state of the transistor while also avoiding GIDL. This is described in more detail below.

[0034] exist Figure 3 The concepts of super cutoff state and GIDL are further illustrated in FIG. Figure 3 It shows that according to Figure 2 A graph of an exemplary relationship between gate voltage and source voltage of an embodiment of the invention. In addition, Figure 3 shows that in transistors (such as Figure 1 108 of the head switch 108). Three different levels of leakage current are shown: low and acceptable, higher but acceptable, and high and unacceptable. Of course, these markings are only examples, as are the specific gate and source voltages. Other embodiments may use different voltages and have different tolerances for leakage current, so that the difference between acceptable and unacceptable may be moved up or down for other embodiments.

[0035] exist Figure 3 In this example, a gate voltage above about 0.9 V provides an unacceptable amount of leakage current, and the leakage current increases as the gate voltage increases. In contrast, a gate voltage below about 0.9 V is within an acceptable range, and the amount of leakage current decreases as the gate voltage decreases. Figure 3 The bottom boundary of the graph of is when the gate-source voltage is zero, which in this example is indicated as high but acceptable.

[0036] See also Figure 1 and Figure 3, various embodiments can prevent leakage by maintaining the head switch 108 in a super cut-off state. However, if the first power supply (Vdd_ext) changes, the level of Vdd_ext may rise to a point where the gate voltage (Vdd_Drvr) will cause an unacceptable level of leakage current, which is high enough to maintain the head switch 108 in a super cut-off state. Therefore, Figure 1 Some embodiments of the system may adjust the control voltage Vdd_Drvr so that it maintains the head switch 108 in a super cutoff state for some Vdd_ext levels, but if Vdd_ext exceeds a threshold, the system may cause the control voltage Vdd_Drvr to be equal to Vdd_ext so that the gate-source voltage is zero and the leakage current is still within an acceptable range.

[0037] Thus, example implementations include selecting a reference voltage, e.g. Figure 4 The reference voltage Vdd1 is chosen to be at a level above which the gate voltage is expected to experience unacceptable GIDL. Of course, this will be different for each application as some applications are generally more tolerant to GIDL or leakage. Figure 4 Examples for Figure 3 The relationship shown in , shows some acceptable leakage levels among other unacceptable leakage levels. Specifically, the level of the reference voltage Vdd1 is set between 0.7V and 0.8V, which corresponds to Figure 3 In some embodiments, the specific level of Vdd1 is not set with a high level of precision, but is set based on experiments or simulations, and can be set within a range of gate voltages that result in acceptable leakage levels. Figure 3 The example can also be served by a reference voltage level Vdd1 up to 0.85V.

[0038] Curve 401 shows the Figure 1 Curve 402 shows the time varying level of Vdd_ext associated with the first power supply 106. Curve 402 shows the reference voltage level Vdd1, which is set to a level between 0.7 V and 0.8 V. Curve 403 shows the level of Vdd_Drvr associated with the second power supply 104 as it varies over time in response to changes in the level of Vdd_ext. Figure 4 Curve 403 is shown vertically shifted downward relative to curve 401 for ease of illustration and is not intended to illustrate the absolute voltage level of Vdd_Drvr.

[0039] Before time T1, Vdd_ext is lower than the voltage level of Vdd1. Figure 1In the event of a power collapse of the logic circuit device 120, Figure 1 The system maintains the head switch 108 in the super cutoff state by applying a control voltage Vdd_Drvr equal to Vdd1. This is represented by the ellipse around Vdd1 and Vdd_Drvr on the left. Again, Vdd_ext is associated with the first power supply 106 and is the source voltage. Therefore, before time T1, the gate-source voltage is positive.

[0040] At time T1, Vdd_ext is equal to the reference voltage Vdd1. As described above, Vdd_ext can be a time-varying voltage, so the system uses a dynamic setting for Vdd_Drvr. After time T1, if the control voltage Vdd_Drvr remains at the value of Vdd1, the gate-source voltage will be negative, turning on the head switch 108. Therefore, in order to maintain the head switch 108 in the off state, the system makes Vdd_Drvr equal to Vdd_ext, so that the gate-source voltage is zero and the head switch 108 is kept in the off state.

[0041] Furthermore, it is expected that maintaining the super-off state of the head switch 108 after time T1 will cause unacceptable leakage due to GIDL because the gate voltage will be higher than 0.7V-0.8V, as described above with respect to Figure 3 Therefore, after time T1, the system uses zero gate-source voltage to keep the head switch 108 in the off state with an acceptable amount of leakage.

[0042] Figure 5 is a diagram of an example voltage generator 500 adapted according to one embodiment. The voltage generator 500 is operable to: adjust a control voltage Vdd_Drvr from the second power supply 104 to the control terminal of the head switch 108 in response to the voltage level of Vdd_ext exceeding the reference voltage level Vdd1. In short, when Vdd1 is higher than Vdd_ext, then the voltage generator 500 selects Vdd1 and passes it to Vdd_Drvr. When Vdd1 is lower than Vdd_ext, then the voltage generator selects Vdd_ext and passes it to Vdd_Drvr. According to one embodiment, the output of the voltage generator 500 can be coupled to a power rail associated with the power supply 104.

[0043] The voltage generator 500 includes a comparator 501 (e.g., an operational amplifier or op amp) that receives a reference voltage Vdd1 at its + input and a voltage Vdd_ext from the first power supply 106 at its inverting input. The output of the comparator 501 is a digital 1 or a digital 0, which is converted by a voltage level converter 502 into a voltage domain compatible with transistors 510 and 512. When Vdd1 is higher than Vdd_ext, the comparator outputs a digital 1, and the digital 1 turns off the PMOS transistor 510 and turns on the PMOS transistor 512, so that Vdd1 appears at Vdd_Drvr.

[0044] When Vdd_ext is higher than Vdd1, this causes a digital zero to appear at the output of comparator 501. This turns on PMOS 510 and turns off PMOS 512, causing Vdd_ext to appear at Vdd_Drvr. This causes the selection of one voltage level (Vdd_ext) and another voltage level (Vdd1) to be output as Vdd_Drvr. As described above, during system design, Vdd1 is selected to be set at or below a potential at which experiments or simulations indicate that GIDL will occur. Therefore, voltage generator 500 causes Vdd_Drvr to follow Figure 4 , thereby reducing the amount of leakage during the off-state of the head switch 108 by keeping the transistor of the head switch 108 in a super-cut state or a state where the gate-source voltage is zero (at least when the head switch 108 is turned off).

[0045] continue Figure 5, which also includes an override mechanism 503 in series between the voltage level shifter 502 and the transistors 510, 512. In this example, the override mechanism 503 is operable to force the voltage generator 500 to output Vdd_Drvr at a voltage equal to Vdd_ext. In some examples, when the override mechanism 503 overrides the output of the comparator 501, the comparator 501 and the voltage level converter 502 can be turned off. In some cases, it is more desirable for the gate-source voltage to be zero than to change the gate-source voltage. For example, there may be a sleep mode in which Vdd_ext can be zero, and it will generally be more desirable to make the gate voltage Vdd_Drvr zero to put the chip into deep sleep. In some examples, the override mechanism 503 can be implemented in software. Of course, the scope of implementation is not limited to using software override in any particular scenario. The override mechanism 503 may include a logic circuit device having a programmed software control register, or may include a logic block that combines multiple inputs indicating the state of the system 100 at a particular point in time. In one implementation, override mechanism 503 may include logic circuitry to generate enable signals for transistors 510, 512 based on the output from comparator 501 and the state of an override signal (not shown) from another source within system 100. Such logic circuitry may be referred to as override circuitry.

[0046] Figure 6 is a diagram of an example system 600 according to one implementation. Figure 6 It is shown Figure 1 The system 600 may be repeated to power down multiple portions of logic. For example, the system 600 includes enabling drivers 102a to 102N, where N is an integer greater than 1. In practice, N may be any appropriate integer. Each enabling driver in the enabling driver 102 is coupled to a second power supply 104.

[0047] The example system 600 also includes a plurality of head switches 108a through 108N, where again N is an integer greater than 1. In this example, there are N enable drivers 102 and N head switches 108, but in other embodiments, each enable driver 102 may drive multiple head switches 108, depending on the size of the enable driver 102 and the size of the head switches 108. In addition, the head switches 108 may be drain coupled, as shown in the diagram 600, although in other embodiments the drain may be uncoupled.

[0048] Power collapse domain 602 may include multiple portions of logic circuitry (e.g., multiple instances of logic circuitry 120). The portions of logic circuitry may be homogeneous or heterogeneous, and the number of portions of logic circuitry may be any suitable number. For example, system 600 may be used to power collapse an entire domain or a portion of a domain as appropriate.

[0049] It should be understood that for ease of explanation, Figure 6 Some features are omitted. For example, although Figure 1 The level shifter 112 and the enable control 114 are shown, but it should be understood that by level shifting the software enable signal to be equal to Vdd_Drvr, Figure 6 The same or similar features are implemented in the system 600, and the enable signal can be controlled to be high or low by the software enable control circuit device 114.

[0050] Figure 6 The circuit in operates according to the above principle. For example, Vdd_Drvr can be provided by, for example Figure 5 The generator shown is provided. Therefore, the Vdd_Drvr voltage can be selected based on the voltage at the source of the head switch 108 (Vdd_ext). Therefore, when the head switch 108 is placed in the off state, it can be maintained in a super cut-off state or a zero gate-source voltage state, depending on the level of Vdd_ext relative to the reference voltage. When the domain 602 is not power collapsed, the head switch 108 is turned on, thereby supplying power to the domain 602 from the first power supply 106 via its corresponding drain. For example, the logic using the control 114 can cause the domain 602 to power collapse or provide power to the domain 602 based on any standard and any power algorithm.

[0051] Figure 7 is a diagram of a reference voltage circuit 700 for generating a reference voltage Vdd1 according to one embodiment. Figure 7 The example assumes that the appropriate level for Vdd1 is 0.7V to 0.8V, and as described above, various embodiments may use different voltage levels for the gate or source of the head switch. Therefore, other embodiments may use different levels for reference voltage Vdd1, and it should be understood that Figure 7 The specific architecture shown in can be adapted to generate any appropriate reference voltage level. In addition, the voltage levels of power supplies VddA and VddB are exemplary only, and it should be understood that other embodiments can have different available voltage levels and can be adapted to use these voltage levels to output appropriate reference voltage levels.

[0052] Switches S1 and S2 can be implemented as PMOS switches, N-channel metal oxide semiconductor (NMOS) switches or any other transistor technology. VddA in this example is a high voltage rail, such as 1.8V. Low dropout (LDO) voltage regulator 701 can include a resistor drop that reduces the voltage to 0.7V-0.8V. When switch S1 is closed, it applies the voltage from LDO 701 to rail 708 to generate Vdd1. VddB represents another power supply pole voltage available at 0.7-0.8V. However, it may not be available all the time, so circuit 700 uses VddA and VddB to provide reliable Vdd1 at various times and operating modes. For example, VddB may be intermittently available, such as if it is a variable voltage that may be lower than the expected range or exceed the expected range, it may not be available. When VddB is available, circuit 700 can turn on switch S2 to place VddB on power rail 708 to generate Vdd1.

[0053] In this example, switches S1 and S2 are complementary so that at least when circuit 700 is powered on, only one switch is always open at a time and only one switch is always closed at a time. Current direction control boxes 702, 703 ensure that current does not flow backwards from VddB to VddA (or vice versa) when switching from one power rail to the other. Switches S1 and S2 are not ideal in practice, so even if switches S1, S2 are complementary, it is possible that current may flow from one rail to the other, which is generally undesirable.

[0054] The current direction control boxes 702, 703 can be as simple as diodes (or more complex), and they reduce or prevent reverse current from flowing from one rail to the other. The current direction controller 707 switches the current direction control boxes 702, 703 on or off to save power when not in use.

[0055] The power controller 706 is a master controller that understands the levels of VddA and VddB and controls switches S1 and S2 based on the states of the different voltage levels. For example, if VddB is not available, the power controller 706 can send a signal to the switch controller 704 to turn S1 on and turn S2 off. On the other hand, if VddB is available at the desired level of Vdd_Drvr, the power controller 706 can send a signal to the switch controller 704 to turn S2 on and turn S1 off.

[0056] Various embodiments may include one or more advantages over other systems. For example, some systems may use a zero gate-source voltage to place the head switch in the off state for the entire duration of the off state. However, as described above, the system may still experience undesirable leakage because the zero gate-source voltage state may not be as effective as the super-off state. In contrast, the embodiments described herein may use the super-off state when appropriate, thereby experiencing less leakage at least at certain voltages.

[0057] In addition, when it is desired that the zero voltage state causes less leakage than the super cutoff state, the embodiments described herein can be changed from the super cutoff state to the zero gate-source voltage state. Therefore, various embodiments can experience less total leakage than other systems, thereby increasing battery life. In addition, various embodiments described herein can provide reduced leakage with relatively small increased silicon area.

[0058] Various embodiments described herein may be applicable to a system on a chip (SOC). Examples of SOCs include semiconductor chips having multiple processing devices therein, including a graphics processing unit (GPU), a central processing unit (CPU), a modem unit, a camera unit, etc. In some examples, the SOC may be included in a chip package, mounted on a printed circuit board, and disposed in a portable device (e.g., a smart phone or a tablet computer). However, the scope of the embodiments is not limited to chips implemented in a tablet computer or a smart phone, as other applications are possible.

[0059] The SOC may include a CPU having multiple cores, and one or more of these cores may execute computer readable code that provides the functionality of an operating system kernel. In addition, the example operating system kernel may include power management software that may power down those portions of logic on the SOC when they are not being used, and may power up those portions of logic on the SOC when they are expected to be used. Figure 1-Figure 7 The described principles can be implemented in a SOC, and more specifically, Figure 1 and Figure 5-Figure 7 The circuit shown in can be implemented in a SOC to provide power collapse functionality.

[0060] For example, in a multi-core CPU, some of the cores may not be used at a given time, and the power management software may power down those unused cores. Continuing with the example herein, a given core may be served by one or more head switches, such as described above with respect to Figure 1 and Figure 6 Power management software can turn the head switch off to provide power collapse and turn the head switch on when use is expected.

[0061] A given core can be served by a single head switch (e.g. Figure 1 ), or may have multiple head switches serving the Figure 6 Of course, the scope of the embodiments is not limited to power-crashing the core of a CPU, as other logic circuits in a SOC may also be power-crashed, such as a camera, modem, GPU, etc.

[0062] Figure 8 A flow chart of an example method 800 for multiplexing between multiple power supplies is shown. In one example, the method 800 comprises: Figure 1 and Figure 5-Figure 7 The circuit can be operated under the control of a power management unit, which may include a Figure 1 and Figure 5-Figure 7 The circuitry provides hardware and / or software functions at a processor (e.g., CPU) of a computing device that provides services. In some examples, the power management unit includes a processing circuit that executes computer-readable instructions to power up a logic circuit device or a power collapse logic circuit device.

[0063] At step 810 , a head switch is enabled to conduct current from a first power source to the logic circuit device. Figure 1 , where the head switch 108 can provide current from the first power supply 106 through its drain to the logic circuit device 120. Continuing with this example, the current is provided at a voltage of Vdd_ext. The head switch 108 in this example is enabled by applying a logical 0 to its control terminal (its gate), which may include a negative gate-source voltage.

[0064] Steps 820 and 830 illustrate shutting off the current by disabling the head switch. For example, step 820 includes selecting a first voltage level from a first voltage level and a second voltage level. Figure 5 An example is given in which the voltage generator of Vdd_Drvr selects between the reference voltage Vdd1 and the source voltage Vdd_ext.

[0065] exist Figure 5 In the example of , the comparator 501 compares Vdd1 and Vdd_ext. If Vdd1 is at a level higher than Vdd_ext, the voltage generator 500 selects Vdd1 as Vdd_Drvr and outputs it. On the other hand, if Vdd_ext is higher than Vdd1, the voltage generator 500 selects Vdd_ext (source voltage) as Vdd_Drvr and outputs it.

[0066] Furthermore, in this example, Vdd1 is a reference voltage set at a level above which the gate voltage is expected to experience an undesirable GIDL. Therefore, the voltage generator 500 makes Vdd_Drvr equal to Vdd_ext so that if GIDL occurs, the gate-source voltage is zero, which would otherwise cause leakage. On the other hand, in the case where the gate voltage is lower than GIDL is undesirable, the voltage generator 500 uses Vdd1 as Vdd_Drvr, thereby maintaining the head switch in a super cut-off state, which is expected to cause less leakage than a state where the gate-source voltage is zero.

[0067] At step 530, the circuit applies a first voltage level from a second power supply to the gate of the head switch. Continuing with this example, Figure 5 The circuit enables Vdd1 or Vdd_ext to be applied to the gate of the head switch by the second power supply (Vdd_Drvr).

[0068] The scope of the embodiments is not limited to Figure 8 80. In contrast, other implementations may add, omit, rearrange, or modify one or more steps. In one example, during normal operation of the computing device, an implementation may switch multiple times between powering up the logic circuitry as in step 810 and powering down the logic as in steps 820, 830. For example, when the logic circuitry is being used to execute code, the logic circuitry may be powered up, and when the logic circuitry would otherwise be idle, it may be powered down.

[0069] As those skilled in the art will now appreciate and depending on the particular application at hand, many modifications, substitutions and changes may be made in the materials, devices, configurations and methods of use of the apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the scope of the particular embodiments shown and described herein, as they are merely by way of some examples thereof, but should be fully commensurate with the scope of the claims appended hereto and their functional equivalents.

Claims

1. An electronic system comprising: First power source; Second power supply; A head switch, arranged between the first power supply and the logic circuit device; an enable driver coupling the second power supply to a control terminal of the head switch, wherein the enable driver is operable to apply a control voltage of the second power supply to the control terminal of the head switch; as well as a voltage generator operable to: adjust the control voltage of the second power supply in response to a first voltage level of the first power supply exceeding a reference voltage level; The voltage generator comprises: a comparator having a first input coupled to the first power supply and a second input coupled to a reference voltage circuit that generates the reference voltage level; a first transistor coupled to the reference voltage level, the first transistor having a gate coupled to an output of the comparator via an inverter; and a second transistor coupled to the first power supply, the second transistor having a gate coupled to an output of the comparator; and The reference voltage circuit comprises: a first switch coupled to a first reference voltage source; a second switch coupled to a second reference voltage source; and A switch controller is operable to select between the first reference voltage source and the second reference voltage source.

2. The electronic system according to claim 1, further comprising: An override circuit device is coupled to the voltage generator and is operable to force the voltage generator to the first voltage level. The electronic system of claim 1 , wherein the first power supply comprises a power rail. 4 . The electronic system of claim 1 , wherein a source terminal of the head switch is coupled to the first power supply.

5. The electronic system of claim 1 , wherein the head switch comprises a positive channel metal oxide semiconductor transistor having a drain coupled to the logic circuit device, and wherein the control terminal comprises a gate of the positive channel metal oxide semiconductor transistor.

6. A method of operating an electronic system, the electronic system comprising: First power source; Second power supply; A head switch, arranged between the first power supply and the logic circuit device; an enable driver coupling the second power supply to a control terminal of the head switch, wherein the enable driver is operable to apply a control voltage of the second power supply to the control terminal of the head switch; as well as a voltage generator operable to: adjust the control voltage of the second power supply in response to a first voltage level of the first power supply exceeding a reference voltage level; The voltage generator comprises: a comparator having a first input coupled to the first power supply and a second input coupled to a reference voltage circuit that generates the reference voltage level; a first transistor coupled to the reference voltage level, the first transistor having a gate coupled to an output of the comparator via an inverter; and a second transistor coupled to the first power supply, the second transistor having a gate coupled to an output of the comparator; and The reference voltage circuit comprises: a first switch coupled to a first reference voltage source; a second switch coupled to a second reference voltage source; and a switch controller operable to select between the first reference voltage source and the second reference voltage source; The method further comprises: enabling the head switch to conduct current from the first power supply to the logic circuit device; and Turning off the current by disabling the head switch comprises: selecting the control voltage from among a first voltage level and a second voltage level in response to comparing the first voltage level and the second voltage level; and The control voltage from the second power supply is applied to a gate of the head switch. The method of claim 6 , wherein applying the control voltage comprises maintaining the headswitch in a super cutoff state. 8 . The method of claim 6 , wherein applying the control voltage comprises maintaining the head switch in an off state with a zero gate-source voltage.

9. The method of claim 6, wherein the control voltage is selected in response to the first voltage level being higher than the second voltage level, wherein the first voltage level corresponds to a reference voltage.

10. The method of claim 6, wherein the control voltage is selected in response to the first voltage level being higher than the second voltage level, and further wherein the first voltage level corresponds to a time-varying power rail voltage and the second voltage level corresponds to a reference voltage.

11. The method of claim 6, wherein shutting off the current comprises receiving an enable signal at a buffer, wherein the enable signal is at the same voltage level as the control voltage.

12. An electronic circuit comprising: a first power rail coupled to a first power supply; a second power rail coupled to a second power supply; a power gating switch coupled between the first power rail and a portion of a logic circuit device of a central processing unit CPU; as well as means for selecting a control voltage from the second power rail to a control terminal of the power gating switch in response to a first voltage level of the first power supply being lower than a reference voltage level; The components available for selection include: a comparator having a first input coupled to the first power rail and a second input coupled to means for generating the reference voltage level; and means for adjusting the control voltage between the first voltage level and the reference voltage level in response to an output of the comparator; and The component for generating the reference voltage level comprises: a first switch coupled to a first reference voltage source; a second switch coupled to a second reference voltage source; and Means for selecting between the first reference voltage source and the second reference voltage source for application to the second input.

13. The electronic circuit of claim 12, further comprising means for applying the control voltage to the control terminal in response to an enable signal.

14. The electronic circuit of claim 13, wherein the means for applying the control voltage comprises an inverting buffer configured to receive the enable signal, wherein the enable signal is at the same voltage level as the reference voltage level.

15. The electronic circuit of claim 12, wherein the power gating switch comprises a positive channel metal oxide semiconductor (PMOS) transistor head switch.

16. The electronic circuit of claim 12, further comprising: An override circuit device is coupled to the means for selecting and is operable to force the means for selecting to the first voltage level.

17. The electronic circuit of claim 12, wherein means for selecting comprises means for applying the control voltage at the reference voltage level from the second power supply rail.

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