FPGA-based image diffusion wave spectrum technology detection system and method

Abstract

The application discloses a system and method of image diffuse wave spectrum technology based on FPGA, which can realize the logic circuit design of the image diffuse wave spectrum algorithm with high parallelism, real-time and stability by using FPGA, simplify the experimental operation and greatly improve the acquisition speed of the experimental results. Compared with the prior art, the application realizes the operation of the diffuse wave spectrum algorithm in high speed and real time by using the design of the parallelism of the CMOS camera, the FPGA chip and the peripheral storage circuit, reduces the cost of the system, and makes sufficient preparation for the miniaturization of the system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of high-concentration nanoparticle dynamic property measurement, and particularly relates to a detection system and method based on FPGA (Field Programmable Gate Array) image diffusion wave spectrum technology. BACKGROUND

[0002] With the increasing progress and development of nanotechnology, high-concentration nanoparticle systems are increasingly widely used in many fields such as pharmaceuticals, petroleum, chemical industry, food, etc. The flowability and stability of particles and other dynamic properties are important parameters for characterizing the performance of nanoparticles, and improving the measurement accuracy is of great significance for improving the quality and research and development speed of related products. In the measurement of low-concentration nanoparticles, dynamic light scattering method is mainly used, but in the measurement of high-concentration nanoparticles, the dynamic light scattering method needs to be diluted for sampling when measuring particle size distribution and dynamic properties, which may cause the measurement results to deviate from the standard particle size, making it difficult to accurately measure. The image diffusion wave spectrum method based on high-concentration nanoparticles is proposed, which has the advantages of non-contact, convenient operation, repeatability, etc. The image diffusion wave spectrum method obtains the speckle pattern generated by multiple light scattering in the high-concentration nanoparticle system through a camera, and then performs decorrelation analysis to obtain the light intensity decorrelation function, and further analyzes to obtain the dynamic properties of the particles.

[0003] The image diffusion wave spectrum method has the characteristics of large image data volume, high processing speed requirement, high flexibility, and real-time by processing the speckle image collected by the camera. The current CPU-based image processing platform has the problems of large volume, high cost, and slow operation. The GPU-based image processing platform has the problem of high power consumption. The ASIC-based image processing platform has the problems of long development cycle, high cost, and poor flexibility. The DSP-based image processing platform has poor processing capability for complex algorithms. The FPGA-based image processing platform has the characteristics of circuit parallelism, programmability, real-time, and small volume, which can be well applied to the design of image diffusion wave spectrum algorithm. At the same time, how to apply FPGA to design high-parallel, stable, and real-time image diffusion wave spectrum algorithm logic circuit with high bandwidth and large-capacity storage resources is also an important technical problem (Brunel, L. et al_2007_Adaptive Speckle Imaging Interferometry;Method and device for the analysis of movement in a scattering medium (US7782458B2)). SUMMARY

[0004] In view of the problems in the prior art, the present application provides a system and method for image diffusion wave spectrum technology based on FPGA, which can realize the logic circuit design of the image diffusion wave spectrum algorithm with high parallelism, real-time performance and stability by using FPGA, simplify the experimental operation and greatly improve the acquisition speed of experimental results.

[0005] The object of the present application is achieved at least by one of the following technical solutions.

[0006] The detection method for image diffusion wave spectrum technology based on FPGA comprises the following steps:

[0007] S1, acquiring speckle images: applying a CMOS camera to collect the scattered light information generated by laser scattering through a high-concentration nanoparticle system, and outputting the collected speckle image video data stream into FPGA through photoelectric conversion;

[0008] S2, video format gray scale conversion: the speckle image video data input into FPGA is converted into RGB565 format data through serial-parallel conversion, and YCbCr format data through format conversion, and the Y channel pixel point gray scale value is output;

[0009] S3, image normalization processing: after waiting for the stable data of the input video stream, the average value of a gray scale image frame is obtained by synchronously accumulating and averaging the first frame of stable data input, and the first frame of data is stored in SDRAM at the same time, then the first frame of image data is taken out after obtaining the average value of the first frame of image data, and the normalized image is obtained by subtracting the first frame of image data, and the normalization operation is performed on each frame of image;

[0010] S4, multi-frame difference processing: the normalized image data of the first frame is stored in SDRAM, and when the decorrelation function is not saturated, the pixel points of the subsequent input normalized image corresponding to the position are subtracted from the stored normalized image data of the first frame, to obtain the difference image of the second to nth frame minus the first frame;

[0011] S5, correlation analysis: the difference result is further squared, divided, summed, accumulated and averaged to obtain the decorrelation coefficient, and the value is stored under the condition that the decorrelation function is saturated, and step S4 is repeated to obtain the decorrelation coefficient and transmit it into the upper computer through the serial port, and the decorrelation curve can be further obtained.

[0012] Further, in step S1, the collected scattered light information is photoelectrically converted and analog-digital converted to output 8-bit data, and the data signal line of the camera interface is used to write data from FPGA to the register related to the camera image information, and the output is configured as 640*480, 30fps speckle image data stream into FPGA.

[0013] Further, in step S2, the 8-bit data output by the CMOS camera is converted into a 16-bit RGB565 data through serial-parallel conversion and splicing, and then a gray scale conversion is realized according to the RGB to YCbCr formula and the floating-point to fixed-point operation to obtain an 8-bit Y channel gray scale value, an 8-bit Cb channel blue chroma value and an 8-bit Cr channel red chroma value, and the Y channel gray scale value is taken as the input data of the image normalization module.

[0014] Further, in step S3, the function of subtracting the average value of the pixel gray scale value of the image itself from the incoming 8-bit 640*480 size image gray scale data is realized to reduce the influence of the conversion of the ambient light.

[0015] When the first frame of image data after the data is stable is written, the image gray scale data of a frame is accumulated and stored, and at the same time, the data is input to the write FIFO1 buffer, the first piece of address space of the SDRAM is set, and when the burst read-write length of the SDRAM is reached, the first piece of address space is written again, when the second frame of image data arrives, the first frame of image data stored in the first piece of address space of the SDRAM is read out to the read FIFO1 buffer, and then the read-out data is subtracted from the stored average value to complete the normalization processing of each frame of image, and the normalized image data is transmitted to the multi-frame difference module.

[0016] Further, in step S3, the normalization operation is performed on each frame of image, and the calculation formula is shown in (1):

[0017]

[0018] wherein I0(x, y, t) represents the pixel value of the normalized image at coordinate (x, y) at time t, I(x, y, t) represents the pixel value at coordinate (x, y) at time t, represents the average value of the pixel points of a frame of image at time t.

[0019] Further, in step S4, the simultaneous read-write of the two pieces of address space in the SDRAM is completed through the control, command interface and data bit width control module of the four FIFOs and the SDRAM, the incoming normalized first frame of image data is written into the write FIFO2 buffer, when the burst read-write length 256 is reached, the data is written into the second piece of address space of the SDRAM again, and when the third frame and subsequent image data arrives, the data is read out to the read FIFO2, and then the data is taken out from the read FIFO2 and subtracted from the second frame and subsequent normalized image data newly transmitted to the module to obtain the difference image of the second to nth frame minus the first frame, and the calculation formula is shown in (2):

[0020] I D (x, y, t) = I0(x, y, t) - I0(x, y, 0) (2)

[0021] wherein, I D (x,y,t) represents the pixel value of the coordinate (x,y) after the difference processing of multiple frames at time t, and I0(x,y,0) represents the pixel value of the normalized image of the coordinate (x,y) at time 0.

[0022] Further, in step S5, when the decorrelation function is not saturated, the difference image and the normalized image data are subjected to time sequence synchronization processing, and division, summation, accumulation and averaging operations are performed to obtain the decorrelation coefficient; after the decorrelation function is saturated, a new frame of normalized image data is written into the second piece of storage space of the SDRAM, and the difference between multiple frames and the image decorrelation operation are repeatedly calculated, and the obtained decorrelation coefficient is transmitted to the host computer through the serial port, and a corresponding decorrelation curve is further drawn.

[0023] Further, the decorrelation coefficient calculation formula is shown in (3):

[0024]

[0025] wherein, dim x and dim y represent the number of horizontal and vertical pixels respectively, D(τ) is the decorrelation coefficient, and τ is the time interval between two frames of images.

[0026] The detection system of the image diffusion wave spectrum technology based on the FPGA includes a speckle image signal generation unit, an optoelectronic conversion unit, an FPGA image processing unit and an upper computer unit.

[0027] The speckle signal generation unit is composed of a laser, a collimating mirror, a reflecting mirror and a high-concentration nanoparticle system, the laser irradiates the high-concentration nanoparticle system to generate light information after multiple scattering; the optoelectronic conversion unit is a CMOS camera, which applies a sensing array to detect the scattered light signal and convert it into an electrical signal to input the speckle image information into the FPGA image processing unit; the FPGA image processing unit includes an FPGA chip, an SDRAM chip and a lookup table corresponding to the digital circuit programmed in the FPGA chip, and the upper computer unit is a general-purpose computer which receives the decorrelation coefficient data transmitted by the FPGA through the serial port and further draws a decorrelation curve.

[0028] Further, the lookup table corresponding to the digital circuit programmed in the FPGA chip includes a speckle SCCB interface protocol module simulated by the lookup table, an image acquisition module, a video format gray scale conversion module, an image normalization module, a multiple frame difference module and a correlation analysis module.

[0029] Compared with the prior art, the advantages of the present application are that:

[0030] Compared with the prior art, the application provides an implementation method of image diffusion wave technology based on FPGA, and the design of CMOS camera, FPGA chip and peripheral storage circuit is combined with parallelism, so that the operation of diffusion wave spectrum algorithm is realized in high speed and real time, the cost of the system is reduced, and the miniaturization of the system is prepared. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 The figure is a system block diagram of the image diffusion wave spectrometer in the embodiment of the application.

[0032] Figure 2 The figure is a system block diagram of the image diffusion wave spectrum technology based on FPGA in the embodiment of the application.

[0033] Figure 3 The figure is a flow chart of the image diffusion wave spectrum algorithm in the embodiment of the application.

[0034] Figure 4 The figure is a structure diagram of the double read-write port SDRAM controller realized by combining the image normalization and multi-frame difference modules in the embodiment of the application.

[0035] Figure 5 The figure is a read-write operation timing diagram of the four FIFOs in the SDRAM in the embodiment of the application.

[0036] Figure 6 The figure is a circuit design schematic diagram of the correlation analysis module in the embodiment of the application.

[0037] Figure 7 The figure is a data sending state machine schematic diagram of the serial communication module in the embodiment of the application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical scheme and advantages of the application more clear, specific embodiments of the application are described in detail below with reference to the drawings and examples.

[0039] Embodiment:

[0040] The application combines FPGA with CMOS camera to collect the scattered light information formed by multiple scattering of laser through high-concentration nanoparticle system, and designs a digital circuit of image diffusion wave spectrum algorithm to obtain the light intensity decorrelation function in high speed and real time, so as to obtain the dynamic characteristics of the high-concentration nanoparticle system.

[0041] For example, Figure 1As shown, in one embodiment, a photoelectric detection system based on FPGA image diffusion wave spectrum technology is studied, which includes a laser 5V power supply R1; a laser diode of THORLABS company, model CPS635F, the laser power is 4.8mW, the wavelength is 636.2nm, and the volume is 11mm*54mm; a collimating mirror R3 for converging the laser beam; a 45-degree cage mirror frame and a mirror R4 of GCT-090604 of Hengyang optics, the frame can adjust the pitch angle of the mirror, the single-axis adjustment range is ±3 degrees; an OV7725 CMOS camera R5 of Haoweitech; a high-concentration nanoparticle system R6, such as toothpaste; a DE2-115 FPGA board R7 of Youjinchuang, on-board EP4CE115F29C7 FPGA chip of Altera company and 2 pieces of 64MB SDRAM, a general-purpose computer R8;

[0042] The working framework of the system is as shown in Figure 2 The system is composed of speckle image signal generation unit, photoelectric conversion unit, FPGA image processing unit and host computer unit, and the internal algorithm design process is as shown in Figure 3 The system is composed of speckle image signal generation unit, photoelectric conversion unit, FPGA image processing unit and host computer unit, and the internal algorithm design process is as shown in

[0043] S1, speckle image acquisition: the CMOS camera is used to collect the scattered light information of the laser passing through the high-concentration nanoparticle system, and the collected speckle image is transmitted into the FPGA through photoelectric conversion output video data stream; as shown in Figure 1 The laser passes through the collimating mirror to converge the beam, is reflected by the mirror to the high-concentration nanoparticle system placed below, the OV7725 CMOS camera is placed in the space with the strongest scattered light to collect the light information after multiple scattering, and the light is transmitted into the FPGA through the photoelectric conversion of the sensing array, the corresponding pixel clock signal, image line field signal and pixel data are output through the serial camera control bus SCCB interface protocol circuit design and corresponding register configuration, the image pixel is 640*480, and the frame rate is 30fps.

[0044] S2, video format gray scale conversion: the speckle image video data input into the FPGA is converted into RGB565 format data through serial-parallel conversion, YCbCr format data is output through format conversion, and Y channel pixel gray scale value is output;

[0045] The 8bit data output by the CMOS camera is output in VGA frame output mode via the SCCB interface protocol module of the FPGA image processing unit, is converted into 16bit RGB565 data, and is subjected to gray scale conversion according to the RGB to YCbCr formula and floating point to fixed point operation to obtain 8bit Y channel gray scale value, 8bit Cb channel blue chrominance value and 8bit Cr red chrominance value, and the Y channel gray scale value is taken as the input data of the image normalization module.

[0046] In one embodiment, when the pixel clock is enabled, the front and rear two clocks splice the 8bit pixel into 16bit RGB565 format. In order to facilitate the design of digital circuit to realize the video format conversion of RGB to YCbCr, prevent the occurrence of floating point and negative number, the gray scale conversion formula is expanded by 256 times, then right shifted by 8bit and adjusted position, as shown in (1)

[0047] Y = (77 * R + 150 * G + 29 * B) >> 8

[0048] Cb = (-43 * R + 85 * G + 128 * B + 32768) >> 8

[0049] Cr = (128 * R - 107 * G - 21 * B + 32768) >> 8 (1)

[0050] Through the formula, Y gray scale data, Cb blue chrominance data and Cr red chrominance data are obtained, and the bit width is 8bit. A corresponding pixel clock signal with half frequency is generated, and the Y gray scale data is input into the image normalization module.

[0051] S3, image normalization processing: after waiting for the input video stream data to be stable, the first frame of stable data is input, and the accumulation and average processing are synchronized to obtain the average value of a frame of gray scale image. Meanwhile, the first frame data is stored in SDRAM. After obtaining the average value of the first frame image data, the stored first frame image is taken out and the difference is obtained to obtain the normalized image. The normalization operation is performed on each frame of image;

[0052] The image normalization module of the FPGA image processing unit is completed, and the function of subtracting the average value of the pixel gray scale from the input 8bit 640*480 size image gray scale data is realized, so as to reduce the influence of the change of environmental light;

[0053] In one embodiment, when the first frame of image data after stabilization is written, the image gray data of one frame is accumulated and stored while the data is input to the write FIFO 1 buffer, the first piece of address space of the SDRAM is set, and when the burst read / write length of the SDRAM is reached, the data is written into the space. When the second frame of image data arrives, the first frame of image data stored in the first piece of address space of the SDRAM is read out to the read FIFO 1 buffer, and then the read data is subtracted from the stored average value to complete the normalization of each frame of image. The normalized image data is transmitted to the multi-frame difference module.

[0054] Normalization is performed on each frame of image, and the calculation formula is shown in equation (2):

[0055]

[0056] where I0(x, y, t) represents the normalized pixel value of the coordinate (x, y) image at time t, I(x, y, t) represents the pixel value of the coordinate (x, y) at time t, and represents the average value of the pixel points of one frame of image at time t.

[0057] In order to complete the image normalization and subsequent multi-frame difference processing, and to realize the simultaneous read / write of the storage space of two pieces of SDRAM, a double read / write port SDRAM controller is designed in combination with two algorithm modules, as shown in Figure 4 The module is composed of a command interface, a control interface, four FIFOs, and an SDRAM controller module. The command interface mainly controls the burst read / write operation, pre-charge, pre-refresh, and other commands. The control interface is used to realize the operation of the SDRAM timing and initialize the SDRAM. The four FIFO modules realize simultaneous data buffering through time division multiplexing. When the burst read / write length of the SDRAM is set to 256, the FIFOs are sequentially arranged in the priority order of read FIFO 1, read FIFO 2, write FIFO 1, and write FIFO 2 to determine whether the buffer address reaches 256, so as to control the corresponding SDRAM read / write enable signals, determine whether the SDRAM responds to read / write data to the SDRAM or the FIFO. The timing diagram of the FIFO read / write is shown in Figure 5

[0058] ​In one embodiment, the image normalization module under the pixel clock enablement, accumulates the input pixel gray data through the accumulator, at the end of a frame field signal, instantiates the divider to obtain the average value of the frame and registers it, and at the same time writes the pixel gray data into the write FIFO1 for caching, and then writes into the first piece of address space opened in the SDRAM. When the second frame field signal arrives, i.e. the pixel gray data of the second frame is input, the read FIFO1 is enabled, and the cached image data of a frame is read out from the first piece of address space of the SDRAM, and each pixel gray data is subtracted from the average value registered by the subtractor, thereby reducing the influence of ambient light. The enablement signal of the read-write FIFO1 is designed to enable the pipeline access strategy of caching each frame and reading out the next frame to make a difference. The normalized image data is input into the multi-frame difference module.

[0059] S4, multi-frame difference processing: the normalized image data of the first frame is stored in the SDRAM, and when the decorrelation function is not saturated, the pixel points of the corresponding positions of the normalized images input subsequently are subtracted from the normalized image data of the first frame stored, to obtain the difference images of the second to nth frames minus the first frame;

[0060] After the multi-frame difference module of the FPGA image processing unit is completed, the simultaneous reading and writing of the two pieces of address space in the SDRAM is completed through the control, command interface and data bit width control module of the SDRAM, and the first frame of image data transmitted and normalized is written into the write FIFO2 for caching. When the burst read-write length of 256 is reached, it is written into the second piece of address space of the SDRAM, and when the third frame and subsequent image data arrive, it is read out to the read FIFO2, and then the second frame and subsequent normalized image data newly transmitted into the module are subtracted from the read FIFO2, to obtain the difference images of the second to nth frames minus the first frame, and the calculation formula is shown in equation (3):

[0061] I D (x,y,t)=I0(x,y,t)-I0(x,y,0)(3)

[0062] Wherein, I D (x,y,t) represents the pixel value of the multi-frame difference processing at the coordinate (x,y) at time t, and I0(x,y,0) represents the pixel value of the image normalization at the coordinate (x,y) at time 0. The difference result is transmitted into the decorrelation processing module.

[0063] In one embodiment, after the first frame of normalized image data is obtained, it is written into the write FIFO2 module for caching at the beginning of the second field signal, which is the next clock registered by the register, and is written into the second piece of address space opened in the SDRAM, whose first address is offset from the first address of the first piece of address space by 640*480 addresses. After the end of the second field signal, the first frame of normalized image data is stored in the second piece of address space in the SDRAM by enabling the write FIFO2 signal. The read enable signal of the read FIFO2 is designed to enable the read enable signal of the FIFO2 at the third field signal and subsequent field signals, so as to read the cached first frame of normalized image data from the SDRAM to the read FIFO2, and then read it out from the read FIFO2 and transmit it into the multi-frame difference module, and subtract it from the newly transmitted frame of normalized image data by the subtracter, and then register the result by the register and write it into the correlation analysis module.

[0064] S5, correlation analysis: the result of the difference is further squared, divided, summed, accumulated and averaged to obtain a decorrelation coefficient, and the value is stored in the case of judging the saturation of the decorrelation function, and the step S4 is repeated to obtain the decorrelation coefficient and transmit it into the upper computer through the serial port, so as to further draw a decorrelation curve;

[0065] When the correlation analysis module of the FPGA image processing unit is completed, the difference image and the normalized image data are processed in time sequence synchronization when the decorrelation function is not saturated, and the decorrelation coefficient is calculated by division, summation, accumulation and averaging operation. After the decorrelation function is saturated, a new frame of normalized image data is written into the second piece of storage space in the SDRAM, and the multi-frame difference and image decorrelation operation are repeatedly calculated, and the obtained decorrelation coefficient is transmitted into the upper computer through the serial port, so as to further draw a corresponding decorrelation curve;

[0066] The calculation formula is shown in equation (4):

[0067]

[0068] Wherein, dim x and dim y represent the number of horizontal and vertical pixels respectively, D(τ) is the decorrelation coefficient, and τ is the time interval between two frames of images.

[0069] In one embodiment, the circuit pipeline design of the correlation analysis module is as follows Figure 6As shown, after obtaining the differential image data, the corresponding row field signals and clock enable signals are time-synchronized, when it is judged that the decorrelation function is not saturated, the multiplier is instantiated to complete the corresponding square, the two frames of normalized image data after square are added by the adder, and then the result is stored by the divider, all the pixels are operated and accumulated by the accumulator, and finally the decorrelation coefficient is obtained by the divider, since the correlation analysis operation adopts a large bit width multiplier and divider, a register is inserted between each operation for pipeline processing. After it is judged that the decorrelation function is saturated, the read-write FIFO2 enable signal of the SDRAM is designed to enable a new frame of normalized image data to be cached to the second address space of the SDRAM, a new decorrelation function is calculated, the obtained decorrelation coefficient is stored by the register, and a serial communication module is designed to send 16bit data to the upper computer at a time, and the corresponding state machine is as shown in Figure 7 As shown, the high 8 bits and low 8 bits of 16bit data are sent by the state jump of send1 and send2 each time, so that the continuous sending of 16bit data is realized, and the decorrelation curve can be further made on the upper computer.

[0070] In summary, the application provides an implementation method of image diffusion wave spectrum technology based on FPGA. The system is composed of a photoelectric system including a speckle image signal generation unit, an optoelectronic conversion unit, an FPGA image processing unit and an upper computer unit. The speckle image signal generation unit is used for collecting speckle patterns formed by laser scattering after passing through a high-concentration nanoparticle system; the optoelectronic conversion unit collects scattering light information, and obtains speckle image data transmitted to the FPGA through photoelectric conversion and analog-digital conversion; the FPGA image processing unit designs an image diffusion wave spectrum algorithm circuit to process the speckle image data and obtain a decorrelation coefficient; and the upper computer unit receives the decorrelation coefficient transmitted by the FPGA, and can further make a decorrelation curve. The application adopts FPGA to realize the circuit design of the image diffusion wave spectrum algorithm, applies a CMOS camera combined with the parallelism of the FPGA chip and the peripheral storage circuit, and realizes the operation of the diffusion wave spectrum algorithm in a high speed and real-time manner, reduces the cost of the system, and makes sufficient preparation for the miniaturization of the system.

Claims

1. A detection method based on FPGA-based image diffusion wave spectroscopy technology, characterized in that, It comprises the following steps: S1, obtaining speckle image: applying CMOS camera to collect laser scattering light information scattered by high concentration nanoparticle system, and collecting speckle image and outputting video data stream into FPGA through photoelectric conversion; S2, video format gray scale conversion: speckle image video data input into FPGA is converted into RGB565 format data through serial-parallel conversion, and YCbCr format data is output through format conversion, and Y channel pixel gray scale value is output; S3, image normalization processing: after waiting for stable data input video stream, synchronization accumulation and average processing are performed on the first frame of stable data input to obtain the average value of a frame of gray scale image, and the first frame of data is stored in SDRAM at the same time, then the first frame of image data is taken out after obtaining the average value of the first frame of image data, and the normalized image is obtained by subtracting the first frame of image data, and normalization operation is performed on each frame of image; When the first frame of image after data stabilization is written, the image gray scale data of a frame is accumulated and stored, and the data is input to write FIFO1 buffer at the same time, the first piece of address space of SDRAM is set, and when the burst read-write length of SDRAM is reached, the piece of space is written again, when the second frame of image arrives, the first frame of image stored in the first piece of address space of SDRAM is read out to read FIFO1 buffer, and then the read-out is subtracted from the stored average value, and the image normalization processing of each frame is completed, and the normalized image data is transmitted into the multi-frame difference module; Normalization operation is performed on each frame of image, and the calculation formula is shown in formula (1): (1) wherein, represents the pixel value of the coordinate (x, y) at time t, represents the pixel value of the coordinate (x, y) at time t, represents the average value of the pixel points of a frame of image at time t; S4, multi-frame difference processing: the first frame of normalized image data is stored in SDRAM, and when the decorrelation function is not saturated, the pixel points corresponding to the normalized image of subsequent input are subtracted from the first frame of normalized image data, and the difference image of the second to the n-th frame minus the first frame is obtained; S5, correlation analysis: the difference result is further squared, divided, summed, accumulated and averaged to obtain the decorrelation coefficient, and the value is stored under the condition that the decorrelation function is saturated, and step S4 is repeated to obtain the decorrelation coefficient and transmit it into the upper computer through the serial port to further draw the decorrelation curve; The decorrelation coefficient calculation formula is shown in formula (3): （3） where dim x and dim y represent the number of horizontal and vertical pixels, respectively, is the decorrelation coefficient, is the time interval between two frames of images.

2. The FPGA-based detection method of image diffusing wave spectroscopy technology according to claim 1, characterized in that, In step S1, the collected scattering light information is converted into 8bit data through CMOS camera photoelectric conversion and analog-digital conversion, and the data is written from FPGA to the register related to camera image information through the data signal line of camera interface, and the output is set as 640*480, 30fps speckle image data stream into FPGA.

3. The method according to claim 2, wherein the method is based on FPGA. In step S2, the 8bit data output by the CMOS camera is converted into a 16bit RGB565 data through serial-parallel conversion, and the gray scale conversion is realized according to the RGB to YCbCr formula and floating point to fixed point operation to obtain 8bit Y channel gray scale value, 8bit Cb channel blue chroma value and 8bit Cr red chroma value, and the Y channel gray scale value is taken as the input data of the image normalization module.

4. The FPGA-based detection method of image diffusing wave spectroscopy technology according to claim 1, characterized in that, In step S4, the simultaneous reading and writing of two address spaces in SDRAM is completed by four FIFOs and the control, command interface, data bit width control module of SDRAM, and the incoming normalized first frame image data is written into the write FIFO2 buffer, and when the burst read-write length of 256 is reached, the second address space in SDRAM is written again, and the third frame and subsequent image data are read out to the read FIFO2, and the difference between the second frame and subsequent normalized image data newly input into the module is obtained by taking out the difference between the second frame and the first frame, and the difference image is calculated as shown in formula (2): （2） wherein, represents the pixel value of the coordinate (x, y) after the multi-frame difference processing at time t, represents the pixel value of the coordinate (x, y) after the image normalization at time 0, and the difference result is transmitted to the decorrelation processing module.

5. The FPGA-based detection method of image diffusing wave spectroscopy technology according to claim 1, characterized in that, In step S5, when the decorrelation function is not saturated, the difference image and the normalized image data are processed in time sequence synchronization, and the decorrelation coefficient is calculated by division, summation, accumulation and averaging operation, and after the decorrelation function is saturated, a new frame of normalized image data is written into the second storage space of SDRAM, and the difference between multiple frames and the image decorrelation operation are repeated to obtain the decorrelation coefficient, which is transmitted to the host computer through the serial port, and the corresponding decorrelation curve is further made.

6. A detection system based on the image diffusion wave spectroscopy technology of the detection method of claim 1, characterized in that, The system comprises a speckle image signal generation unit, an optical-electric conversion unit, an FPGA image processing unit and a host computer unit. The speckle signal generation unit is composed of a laser, a collimating mirror, a reflecting mirror and a high-concentration nanoparticle system, the laser irradiates the high-concentration nanoparticle system to generate multiple scattered light information; the optical-electric conversion unit is a CMOS camera, which applies a sensing array to detect scattered light signals and convert them into electrical signals to input speckle image information into the FPGA image processing unit; the FPGA image processing unit comprises an FPGA chip, an SDRAM chip and a digital circuit corresponding lookup table programmed in the FPGA chip, and the host computer unit is a general-purpose computer which receives the decorrelation coefficient data transmitted by the FPGA through a serial port and further makes a decorrelation curve.

7. The FPGA-based detection system for image diffusing wave spectroscopy according to claim 6, wherein, The lookup table programmed in the FPGA chip includes a speckle SCCB interface protocol module simulated by the lookup table, an image acquisition module, a video format grayscale conversion module, an image normalization module, a multi-frame difference module and a correlation analysis module.

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