High-speed true random number generator based on memristor and method for generating true random number thereof

Abstract

The application provides a high-speed true random number generator based on a memristor and a method for generating a true random number. The true random number generator comprises a memristor random source module, a feedback shift register module and a single-chip microcomputer data acquisition module. The memristor random source module generates a random seed according to a delay time, so that the feedback shift register module further outputs a random number according to the seed. The single-chip microcomputer data acquisition module acquires data of the random number. The application can realize high speed and unpredictability of the whole random number generator, and has great contribution to a high-speed encryption security system.

Description

Technical Field

[0001] This invention relates to the field of information security, specifically to a high-speed true random number generator based on memristors and a method for generating true random numbers. Background Technology

[0002] The Internet of Things (IoT) is a vast network that connects the internet with other objects through information sensing devices, enabling information exchange between people, machines, and things anytime, anywhere. With the rapid growth in the number of IoT objects and the excessive use of cyberspace by global users, existing hardware infrastructure is becoming increasingly vulnerable to security threats. Random numbers, as a modern cryptographic technique, play a crucial role in solving information security problems, and are used in digital signatures, key management, and other areas. Therefore, the security of an information security system through the use of random numbers depends to a certain extent on the randomness and security of the random numbers themselves.

[0003] Currently, random number generators are divided into two types: pseudo-random number generators and true random number generators. Pseudo-random number generators, as a traditional software-based data protection method, generate pseudo-random sequences. These sequences are produced using a known initial value sequence called a "seed" and a fixed algorithm. If the "seed" and algorithm are public, it is highly likely that identical random numbers can be obtained, significantly reducing the reliability of information security. True random number generators, on the other hand, are hardware components that can generate unpredictable true random number sequences based on inherent random physical processes such as noise and vibration. These sequences are used to generate keys and encrypt data, thus solving the periodicity problem of pseudo-random numbers and are of great significance for encryption in high-security systems.

[0004] Physically unclonable functions (PUFs) are a hardware security technique commonly used in cryptography, characterized by uniqueness, randomness, and unclonability. True random number generators (TRNGs) are an important component of PUFs. Unlike pseudo random number generators (PRNGs), which use random sources, TRNGs utilize uncontrollable factors such as noise and vibration as random source sources, generating truly random numbers.

[0005] Memristors possess advantages such as simple structure, ease of integration, fast erase / write speed, low power consumption, large on / off ratio, and compatibility with complementary metal-oxide-semiconductor (CMOS) processes, and have been applied in fields such as non-volatile memory and neuromorphic devices. Early TRNGs used the switching voltage or current fluctuations of non-volatile memristors as a random source; while these schemes were feasible, they lacked true randomness. Subsequently, researchers shifted their focus to volatile memristors, using their delay and relaxation times as random sources to construct true random number generators.

[0006] Volatile memristors spontaneously return from a low-resistivity state (LRS) to a high-resistivity state (HRS) after a period of time following the removal of external excitation. This dynamic change in conductance is related to ion migration, thermal effects, and electronic effects, and can be modulated by external voltage amplitude, pulse width, ambient temperature, and other factors. The unique delay and relaxation time response of the volatile resistance switching phenomenon make volatile memristors suitable for a wide range of electronic applications, including memory access devices, neural / synaptic components for neuromorphic computing, and random sources for hardware security.

[0007] Traditional memristor-based true random number generators in integrated circuits mostly use two threshold switching devices connected in parallel. After applying a pulse stimulus, the voltage across their resistors is read and compared. However, this method depends on the accuracy of the reference voltage. If the reference voltage is not accurate enough, it will affect the probability of generating random binary numbers. The reference voltage is easily affected by factors such as integrated circuit process, voltage, and temperature. If a high-precision reference voltage is generated using a bandgap reference circuit, it will consume a lot of circuit overhead.

[0008] In addition, although traditional true random number generators scramble the output, there is still a certain relationship between the numbers, making it difficult to achieve true randomness. To achieve different random sequences, traditional true random number generators need to increase circuit complexity by modifying the tap positions. For circuits with fixed random number bits and a fixed number of variable tap positions, the number of random number sequences generated is also fixed. Therefore, the ability to increase the number of random sequences using this method is also limited. Summary of the Invention

[0009] The purpose of this invention is to provide a high-speed true random number generator based on memristors and a method for generating true random numbers. This true random number generator can generate random binary numbers of arbitrary length, and its circuit structure consists only of logic gates and shift registers, making it simple in structure and significantly faster in generating random number sequences.

[0010] The present invention is implemented as follows: a high-speed true random number generator based on memristors, the true random number generator comprising a random source module composed of memristors and resistors in series, a feedback shift register module, and a microcontroller data acquisition module; the random source module provides a random seed to the feedback shift register module; since the delay time of the memristors in the random source module is random, the random sequence generated after the delay time is used as input and further generated into a sequence with higher randomness through the feedback shift register module.

[0011] In the random source module, the memristor in the series structure is connected to the pulse generator, and the feedback shift register module receives the clock signal.

[0012] The memristor structure in this invention is Ag / SiN x The / n-Si memristor exhibits typical threshold characteristics with a delay time of approximately 47ns. A sequence of pulses from a pulse generator is applied to the memristor, causing it to flip its resistance state. The delay time before this flip serves as a random seed for the feedback shift register module. After the delay, the logic levels represented by the high and low resistance states of the memristor are introduced into the feedback shift register module.

[0013] The feedback shift register module includes a feedback module composed of XOR gates and NOT gates, and a shift register composed of multiple flip-flops connected in sequence. The output of the flip-flop of the previous stage is connected to the input of the flip-flop of the next stage, and the output of the feedback module is connected to the input of the leftmost flip-flop (i.e., the input of the shift register).

[0014] The feedback module includes an XOR gate and a NOT gate. The XOR gate has a first input terminal and a second input terminal. The first input terminal is connected to the input signal of a memristor or the output terminal of a flip-flop. The second input terminal is connected to the output terminal of a flip-flop or the output terminal of an XOR gate. The input terminal of the NOT gate is connected to the output terminal of the XOR gate, and its output terminal is connected to the input terminal of a shift register, which can effectively prevent the shift register from latching.

[0015] The feedback module is configured to receive a random seed generated by the random source module, use the random seed and the output of the trigger as inputs to the feedback module for linear operation, connect to a shift register for final output, and the participation of the random seed transforms the original linear feedback function composed of XOR gates and NOT gates into a nonlinear function, increasing the randomness of the data.

[0016] If the memristor is in a high-impedance state, the voltage drop across the corresponding resistor connected in series is very small, resulting in a low-level logic output; if the memristor is in a low-impedance state, the voltage drop across the corresponding resistor is very large, resulting in a high-level logic output.

[0017] The microcontroller data acquisition module is configured to acquire the level signals at the output terminals using a microcontroller. By performing edge detection on the clock signal, the output level of the first output terminal OUT1 of the overall circuit is acquired at the rising edge, and the output level of the second output terminal OUT2 of the overall circuit is acquired at the falling edge, and saved to a text file for later use.

[0018] The circuit structure of this invention is described in detail below.

[0019] Specifically, the true random number generator provided by this invention includes a memristor M1 and a resistor in a series structure. The memristor M1 is connected to a voltage signal source; the resistor is connected to ground; the connection between the resistor and the memristor M1 is connected to the first input of an XOR gate XOR1; the second input of XOR1 is connected to the output of XOR2; the output of XOR1 is connected to NOT1; NOT1 inverts the signal and inputs it into a first shift register composed of four D flip-flops. The third output of the first shift register is connected to the first input of XOR2; the fourth output of the first shift register is connected to the first input of XOR3; and the fourth output of the first shift register is also the first output OUT1 of the overall circuit.

[0020] To increase the randomness of the output random sequence, this invention adds a random number generator circuit consisting of a memristor M2, logic gates, and a second shift register. The first output terminal OUT1, i.e., the fourth output terminal of the first shift register, is connected to the first input terminal of the XOR gate XOR4 as an input to the feedback function of the newly added circuit. The output terminal of the XOR gate XOR4 is connected to the NOT gate NOT2, which inverts the signal and inputs it into a new second shift register consisting of four D flip-flops. The third output terminal of the second shift register is connected to the first input terminal of the XOR gate XOR6, and the fourth output terminal is connected to the second input terminal of the XOR gate XOR6. Furthermore, the fourth output terminal of the second shift register serves as the second output terminal OUT2 of the overall circuit. Then, the output of XOR gate XOR6 is connected to the second input of XOR gate XOR5, the first input of XOR gate XOR5 is connected to the newly added memristor M2 random source, and the first input of XOR gate XOR5 is connected to the connection point of memristor M2 and the second resistor. Finally, the output of XOR gate XOR5 is connected to the second input of XOR gate XOR4, and the nonlinear output data with the participation of the new random source is fed back to XOR gate XOR4. After logical operation between XOR gate XOR4 and the first output OUT1, the data is passed to the second shift register to continue the loop.

[0021] It is worth noting that the second output terminal OUT2 of the overall circuit is connected to the second input terminal of the XOR gate XOR3, and the output terminal of the XOR gate XOR3 is connected to the second input terminal of the XOR gate XOR2. The XOR gate XOR3 performs an XOR operation between the signal at the second output terminal OUT2 and the signal at the first output terminal OUT1, and then feeds the signal into the first part of the circuit by connecting to the second input terminal of the XOR gate XOR2. This complex operation mode greatly improves the randomness of the data sequence generated by the circuit.

[0022] Furthermore, this invention inverts the CLK clock signal used by the first shift register and uses it as the clock source for the second shift register. This allows two random data to be output in one clock cycle, which greatly improves the efficiency of the random number generator in outputting random sequences.

[0023] Furthermore, in the circuit structures of the two random number generators, the non-series terminals of the resistors are both grounded.

[0024] Secondly, the present invention also provides a method for generating a true random number generator, which uses the aforementioned true random number generator and specifically includes the following steps:

[0025] Step 1): The process of generating a high-resistance state and then a low-resistance state by applying a pulse generator to the memristor, and then the low-resistance state and then the high-resistance state.

[0026] Step 2): The voltage divider across the resistor generates a logic level and inputs it to the feedback shift register module;

[0027] Step 3): The feedback shift register module further increases the randomness of the data through logic function operations;

[0028] Step 4): The feedback shift register module ultimately generates a highly random number at the output.

[0029] Step 5): Finally, the microcontroller data acquisition module acquires the random number data.

[0030] Compared with existing technical solutions, the present invention has at least the following beneficial effects:

[0031] 1) The true random number generator containing memristors proposed in this invention has high encryption security: by using the random delay time generated by the memristor device in response to the pulse, the unpredictability and non-replicability of the overall circuit output are achieved, which makes a significant contribution to encryption security systems with high requirements.

[0032] 2) The true random number generator containing memristors proposed in this invention has stable output random signals and long service life: Memristor devices have good data retention characteristics and cycle tolerance, and can continuously and stably provide a physical random signal source for the system, ensuring the stable output random signal characteristics and long service life of the random number generator.

[0033] 3) The true random number generator containing memristors proposed in this invention greatly improves the speed of physical generation of true random numbers through stable memristor devices and reasonable circuit design, and its bit production rate can reach 112kb / s.

[0034] 4) The true random number generator containing memristors proposed in this invention can output two sets of random sequences in one clock cycle by effectively utilizing clock signals and related circuit designs, which greatly improves the efficiency of random number generation.

[0035] 5) The true random number generator containing memristors proposed in this invention has a simple circuit system structure and high integration. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the delay time of the memristor under a single pulse in this invention.

[0037] Figure 2 This is a schematic diagram showing the delay time distribution of the memristor under the same pulse in this invention.

[0038] Figure 3 The diagram shows the circuit structure of four types of NFSR.

[0039] Figure 4 This is a schematic diagram of a true random number generator circuit structure provided in an embodiment of the present invention.

[0040] Figure 5 This is a schematic diagram of the test conditions of each test node marked in the circuit structure diagram of an embodiment of the present invention.

[0041] Figure 6 A flowchart illustrating the operation of a true random number generator circuit provided in an embodiment of the present invention.

[0042] Figure 7 This is a schematic diagram of the feedback shift register module circuit structure in an embodiment of the present invention.

[0043] Figure 8 This is a schematic diagram of the circuit structure of the microcontroller data acquisition module in an embodiment of the present invention. Detailed Implementation

[0044] The true random number generator provided by this invention uses a memristor as the random source and a random number generation circuit composed of a shift register, an XOR gate, and a NOT gate. This circuit includes a feedback module composed of logic gates (with logic operation functions) and a shift register composed of D flip-flops. The output of the D flip-flops serves as the input of the feedback module, and the output of the feedback module is connected to the input of the D flip-flops. Thus, two random numbers are output at the outputs of the two shift registers in each pulse cycle. Because the memristor itself has a random delay time characteristic of transitioning from a high-resistance state to a low-resistance state, the random number generator can have different feedback forms, thereby increasing the random sequence generated by the random number circuit without changing the tap positions, and thus improving the randomness of the random numbers.

[0045] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments of the invention will now be described in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention.

[0046] Example 1:

[0047] For a memristor, under pulse stimulation, it transitions from an initial high-resistivity state to a low-resistivity state. The voltage across the resistor connected in series with the memristor also changes rapidly. However, the memristor does not immediately change its state after being stimulated by a pulse; instead, it experiences a delay, typically on the order of nanoseconds. Figure 1 As shown.

[0048] Figure 2 This shows the distribution of delay time for the same device under the same pulse.

[0049] refer to Figure 2 Under the same pulse stimulus, the delay time of the device will also be different. This invention uses this random delay time interval as a random source, operates a shift register by inputting a high-speed clock signal, and performs a nonlinear function operation between the output signal and the random source to finally generate a random sequence.

[0050] In common random number circuits, linear feedback shift registers (LFSRs) are a method to increase bit generation rate while consuming less power.

[0051] The feedback function of an LFSR simply performs logical operations on certain bits in the shift register and fills the leftmost end of the LFSR with the result. Each bit of data in the LFSR may or may not participate in the operation. However, the output of the LFSR largely depends on the construction of the feedback function. Even if logic gates are added to complicate the feedback function, the output is not random but predictable. Furthermore, when using XOR gates for logical operations, if all initial states are "0", all D flip-flops will remain in the "0" state, and all their outputs will always be locked to "0".

[0052] To address the above issues, this invention employs a nonlinear feedback shift register (NFSR), which differs from an LFSR.

[0053] Furthermore, a logic structure consisting of XOR and NOT gates is used as the linear function, and the random logic level generated by the memristor participates in the operation of the feedback function. The function output is then fed back to a shift register consisting of four D flip-flops. In this case, the input bits are a linear function of their previous state, but due to the participation of the memristor as a random source, this linear function becomes non-linear. This effectively solves the aforementioned latching problem, making it more resistant to attacks and providing higher security.

[0054] Figure 3 Four types of NFSR are shown.

[0055] See Figure 3 , Figure 3 (a) shows the Fibonacci NFSR method, accompanied by a clock signal, where the new input of (n-1) bits is the result of taking the state of all the output bits from the previous operation and calculating it using a nonlinear function. This output signal is strongly dependent on the nonlinear function during transmission. Figure 3 (b) The Geffe generator shown consists of three LFSRs and a multiplexer composed of AND and NOT gates. Bits generated by one LFSR select any one of the other two sub-LFSRs, and the corresponding bits from the selected LFSR are used for the final output sequence. This method enhances linear complexity by incorporating the outputs of multiple LFSRs into a nonlinear function for computation and outputting the result. Besides nonlinear feedback transformation, another solution is to use irregular clocks in the LFSRs, such as... Figure 3 As shown in (c), the Massey-Rueppel multispeed generator uses LFSRs timed at different speeds, with one clock signal being n times the speed of the other, to enhance the complexity of the feedback by setting two different clocks. Irregular clocks are also used to increase linear complexity in other methods. Figure 3(d) shows the Beth-Pipergenerator, in which LFSR1 controls the clock of LFSR2 via an AND gate.

[0056] In designing the circuit, this invention takes into account the operating characteristics of the Fibonacci NFSR, introduces multiple output bits from the shift register into the feedback function, and then combines the working principle of the Geffe generator. Different states of the memristor will lead to different outputs of the same feedback function. This random behavior destroys the circuit's dependence on the XOR gate and avoids the predictability of the linear function generated by the pure XOR gate.

[0057] Furthermore, it incorporates the working principle of the Massey-Rueppel multispeed generator, separating the same clock signal into rising and falling edges, and inverting the rising edge to serve as the right-side circuit. Figure 4 The clock of the shift register in the middle (right side) can be used to output two sets of random sequences in one clock cycle, which greatly improves the efficiency of random number generation.

[0058] Figure 4 The structural design of the random number generation circuit of the present invention is shown.

[0059] Specifically, the random number generation circuit provided by this invention includes two parts, the first part of which has a circuit structure (corresponding to) Figure 4 The circuit on the left side includes the following components: a first memristor M1, a first resistor, a first shift register, a first XOR gate XOR1, a second XOR gate XOR2, a third XOR gate XOR3, and a first NOT gate NOT1; the second part of the circuit structure (corresponding to Figure 4 The circuit on the right side includes the following components: a second memristor M2, a second resistor, a second shift register, a fourth XOR gate XOR4, a fifth XOR gate XOR5, a sixth XOR gate XOR6, and a second NOT gate NOT2.

[0060] Both the first and second shift registers consist of four D flip-flops. Specifically, in each shift register, the four D flip-flops are arranged sequentially, with the output (Q) of the preceding D flip-flop connected to the data signal input (D) of the adjacent following D flip-flop. The clock signal inputs (CLK) of the four D flip-flops are all connected together. In the first shift register, the clock signal inputs of the four D flip-flops are all connected to the CLK clock signal. The CLK clock signal is then connected to the clock signal inputs of the four D flip-flops in the second shift register after passing through the third NOT gate (NOT3).

[0061] In the first part of the circuit structure, one end of the first memristor M1 is connected to a voltage signal source, and the other end of the first memristor M1 is connected to one end of a first resistor, the other end of which is grounded; the first memristor M1 and the first resistor form a series structure. The connection end between the first resistor and the first memristor M1 is connected to the first input terminal of the first XOR gate XOR1, the second input terminal of the first XOR gate XOR1 is connected to the output terminal of the second XOR gate XOR2, the output terminal of the first XOR gate XOR1 is connected to the input terminal of the first NOT gate NOT1, and the output terminal of the first NOT gate NOT1 is connected to the data signal input terminal (D terminal) of the first D flip-flop in the first shift register, that is, the first NOT gate NOT1 inverts the signal and inputs it into the first shift register. The output terminal (Q terminal) of the third D flip-flop in the first shift register is connected to the first input terminal of the second XOR gate XOR2, and the output terminal of the fourth D flip-flop in the first shift register is connected to the first input terminal of the third XOR gate XOR3. At the same time, the output terminal of the fourth D flip-flop in the first shift register is also the output terminal of the first part of the circuit structure, or the first output terminal OUT1 of the overall circuit of the present invention.

[0062] In the second part of the circuit structure, the second memristor M2 is connected in series with the second resistor. One end of the second memristor M2 is connected to a voltage signal source, and the other end of the second memristor M2 is connected to one end of the second resistor, which is grounded. The output terminal OUT1 of the first part of the circuit structure, i.e., the output terminal of the fourth D flip-flop in the first shift register, is connected to the first input terminal of the fourth XOR gate XOR4 in the second part of the circuit structure. The output terminal of the fourth XOR gate XOR4 is connected to the input terminal of the second NOT gate NOT2. The output terminal of the second NOT gate NOT2 is connected to the data signal input terminal of the first D flip-flop in the second shift register, i.e., the second NOT gate NOT2 inverts the signal and inputs it into the second shift register. The output terminal of the third D flip-flop in the second shift register is connected to the first input terminal of the sixth XOR gate XOR6, and the output terminal of the fourth D flip-flop in the second shift register is connected to the second input terminal of the sixth XOR gate XOR6. Furthermore, the output terminal of the fourth D flip-flop in the second shift register is the output terminal of the second part of the circuit structure, which is also the second output terminal OUT2 of the overall circuit of this invention. Then, the output of the sixth XOR gate XOR6 is connected to the second input of the fifth XOR gate XOR5. The first input of the fifth XOR gate XOR5 is connected to the connection point of the second memristor M2 and the second resistor. The output of the fifth XOR gate XOR5 is connected to the second input of the fourth XOR gate XOR4. The second memristor M2 serves as the random source in the second part of the circuit structure. It feeds back the output data to the fourth XOR gate XOR4 through the fifth XOR gate XOR5. Then, it performs a logical operation with the first output OUT1 of the overall circuit of the present invention through the fourth XOR gate XOR4 and is then passed to the second shift register to continue the loop.

[0063] The second output terminal OUT2 of the overall circuit of the present invention is connected to the second input terminal of the third XOR gate XOR3. The output terminal of the third XOR gate XOR3 is connected to the second input terminal of the second XOR gate XOR2. The third XOR gate XOR3 performs an XOR operation between the signal of the second output terminal OUT2 and the signal of the first output terminal OUT1 of the overall circuit of the present invention, and then feeds the signal into the first part of the circuit structure through the second XOR gate XOR2. This complex operation mode greatly improves the randomness of the data sequence generated by the circuit.

[0064] Furthermore, this invention inverts the CLK clock signal used by the first shift register and uses it as the clock source for the second shift register. This allows two random data to be output in one clock cycle, which greatly improves the efficiency of the random number generator in outputting random sequences.

[0065] This invention introduces two memristors as random sources, which generate corresponding random seeds at the rising and falling edges of the clock respectively to participate in the calculation of the feedback function. The random signal generated by the rising edge of the left circuit is input to the right circuit as the input of the feedback function of the right circuit.

[0066] This circuit structure not only makes full use of the edge triggering of the clock signal and improves the efficiency of the output, but also increases the complexity of the logic operation, enabling it to generate more random data output.

[0067] Regarding the circuit structure in the first part Figure 5 The nodes for each test are marked in the text.

[0068] When the input pulse ( Figure 5 When V1 in (a) is applied to the first memristor M1, the voltage value obtained by the voltage divider obtained by the resistor connected in series with it is shown as follows. Figure 5 V in (a) 2.1 V 2.1 A sustained high level appears after a certain delay, which is related to the feedback signal from the second XOR gate (XOR2). Figure 5 V in (a) 3.1 The inputs are combined and fed into the first XOR gate (XOR1) for XOR operation. The output is then passed through the first NOT gate (NOT1), and the inverted signal after passing through NOT1 is... Figure 5 V in (b) 4.1 Finally, V 4.1 Enter the first shift register. The first shift register transmits V on each rising edge of the clock signal. 4.1 The numerical value is then output as a random sequence. Figure 5 V in (c) out1The output signal OUT1 will also be used as an input to the right-side circuit in its feedback function, and the output signal OUT2 of the right-side circuit will also be used as an input to the left-side feedback function as an input to the left-side third XOR gate XOR3. Figure 5 (d) is V 5.1 With V OUT1 The timing correspondence. This invention, through this novel circuit design combined with a stable memristor random source, significantly improves the generation efficiency of random sequences while ensuring their randomness.

[0069] Figure 7 This is a schematic diagram of the feedback shift register module circuit structure in an embodiment of the present invention.

[0070] See Figure 7 The circuit includes a NOT gate (CD4069, Texas Instruments), an XOR gate (SN74HC86, Renesas), and a D flip-flop (MC14015B, ON Semiconductor). Two memristors and their corresponding resistors are introduced through terminals P1 and P2, and the two output terminals OUT1 and OUT2 correspond to pins PB8 and PB9 of the circuit, respectively.

[0071] Figure 8 This is a schematic diagram of the circuit structure of the microcontroller data acquisition module in an embodiment of the present invention.

[0072] By building upon the STM32 microcontroller minimum system Figure 7 The output signal PB8 and PB8 pin shown are related to Figure 8 The circuit is connected to the microcontroller's I / O pins, and output data is acquired through code. Furthermore, a small-capacity lithium battery charging chip, MCP73831, is added, allowing the circuit to be powered by an external lithium battery, increasing its portability and facilitating data acquisition.

[0073] Example 2:

[0074] Figure 6 This is a flowchart of a method for generating truly random numbers provided in an embodiment of the present invention, combined with... Figure 4 The specific steps are as follows:

[0075] 1) In the left-hand circuit, the logic level generated by the first memristor M1 under pulse stimulation will enter the first logic operation function. Similarly, in the right-hand circuit, the logic level generated by the second memristor M2 under pulse stimulation will enter the second logic operation function. These logic operation functions are mainly implemented using XOR gates and NOT gates connected to the inputs of the shift register.

[0076] 2) When the clock signal is rising, the first shift register in the left circuit will pass the results of the above logic operation sequentially through its D flip-flop.

[0077] 3) The outputs of the third and fourth D flip-flops of the first shift register are respectively input into the logic function formed by the second XOR gate XOR2 and the third XOR gate XOR3 for operation. The output of the fourth D flip-flop is also input into the logic function in the right circuit with the second memristor M2 as the random source for operation. At the same time, the output of the fourth D flip-flop is also the first output OUT1 of the entire circuit.

[0078] 4) When the clock signal is a falling edge, the second shift register in the circuit on the right will pass the results of the above logic operation in sequence through its four D flip-flops.

[0079] 5) The outputs of the third and fourth D flip-flops of the second shift register on the right are respectively input to the two inputs of the sixth XOR gate XOR6 for logic function operation. The output of the fourth D flip-flop of the second shift register is also input to the logic function in the left circuit with the first memristor M1 as the random source for operation. At the same time, the output of the fourth D flip-flop is also the second output OUT2 of the entire circuit.

[0080] Example 3:

[0081] The performance of TRNGs was evaluated using the NIST Statistical Test Suite. This suite consists of 15 tests to assess the randomness and unpredictability of TRNGs. Each test was considered to pass if the p-value was greater than 0.0001, representing the minimum pass rate. A larger p-value indicates stronger evidence supporting the null hypothesis. 85 tests of 10-10 were collected here. 6 The bit sequences, which passed all 15 NIST tests without any post-processing steps, verify the randomness of the invention.

[0082] The test results are shown in Table 1.

[0083] Table 1

[0084] Test number Test metrics P-VALUE PROPOTION Test Results 1 Frequency test 0.676097 0.952941 pass 2 Intra-block frequency test 0.701879 0.988235 pass 3 Cumulative and test 0.126842 0.952941 pass 4 Trip test 0.340461 0.988235 pass 5 Longest run test 0.126842 0.988235 pass 6 Binary matrix order test 0.947557 1 pass 7 Discrete Fourier Transform Spectrum Test 0.284375 0.976470 pass 8 Non-overlapping module matching test 0.701879 0.989427 pass 9 Overlapping module matching test 0.823278 0.988235 pass 10 General Statistical Test 0.999091 1 pass 11 Approximate Entropy Test 0.624107 0.976470 pass 12 Random deviation test 0.419021 0.992788 pass 13 Random deviation variable test 0.455937 0.991452 pass 14 Serial test 0.448892 0.976470 pass 15 Linear complexity test 0.598138 0.976470 pass

[0085] This invention proposes a memristor-based true random number generator and a method for generating true random numbers. Utilizing the uncertainty of the memristor's delay time, combined with circuitry, it can generate binary true random numbers of arbitrary bits. Compared to traditional memristor-based true random number generators, this invention has a simpler structure, consisting only of logic gates and shift registers, eliminating the need for voltage comparators, thus significantly reducing circuit overhead. Furthermore, it generates highly efficient random numbers and has excellent application prospects.

Claims

1. A high-speed true random number generator based on memristors, characterized in that, It includes a first memristor, a first feedback module, and a first shift register; one end of the first memristor is connected to a pulse generator, the other end of the first memristor is connected to one end of a first resistor, and the other end of the first resistor is grounded; the connection between the first memristor and the first resistor is connected to the first shift register through the first feedback module, the first shift register is composed of several sequentially connected flip-flops, and the output of the first shift register is connected to the input of the first feedback module, the first feedback module is a feedback circuit composed of XOR gates and NOT gates; The method for generating true random numbers using a high-speed true random number generator based on memristors includes the following steps: 1) The logic level generated by the first memristor under pulse stimulation enters the first logic operation function, and the logic level generated by the second memristor under pulse stimulation enters the second logic operation function; the first logic operation function and the second logic operation function are implemented by the first feedback module and the second feedback module, respectively; 2) When the clock signal is on the rising edge, the first shift register will pass the results of the above logic operation sequentially through its D flip-flops; 3) The outputs of the third and fourth D flip-flops of the first shift register are respectively input into the logic function formed by the second and third XOR gates for operation. The output of the fourth D flip-flop is also input into the logic function with the second memristor as the random source for operation. At the same time, the output of the fourth D flip-flop is also the first output terminal OUT1. 4) When the clock signal is a falling edge, the second shift register will pass the results of the above logic operation sequentially through its four D flip-flops; 5) The outputs of the third and fourth D flip-flops of the second shift register are respectively input to the two inputs of the sixth XOR gate for logic function operation. The output of the fourth D flip-flop of the second shift register is also input to the logic function with the first memristor as the random source for operation. At the same time, the output of the fourth D flip-flop is also the second output terminal OUT2.

2. The high-speed true random number generator based on memristors according to claim 1, characterized in that, The first shift register includes four D flip-flops connected in sequence, and the output of the previous D flip-flop is connected to the data signal input of the next adjacent D flip-flop. The clock signal inputs of the four D flip-flops are all connected to the CLK clock signal.

3. The high-speed true random number generator based on memristors according to claim 2, characterized in that, The first feedback module includes a first XOR gate, a second XOR gate, a third XOR gate, and a first NOT gate; the connection terminal of the first memristor and the first resistor is connected to the first input terminal of the first XOR gate, the second input terminal of the first XOR gate is connected to the output terminal of the second XOR gate, the output terminal of the first XOR gate is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is connected to the data signal input terminal of the first D flip-flop in the first shift register; the output terminal of the third D flip-flop in the first shift register is connected to the first input terminal of the second XOR gate, the output terminal of the fourth D flip-flop in the first shift register is connected to the first input terminal of the third XOR gate, and the output terminal of the fourth D flip-flop in the first shift register also serves as the first output terminal OUT1.

4. The high-speed true random number generator based on memristors according to claim 3, characterized in that, It also includes a second memristor, a second feedback module, and a second shift register; the second memristor is connected in series with a second resistor, and after being divided by the second resistor, the second memristor is connected to the second shift register through the second feedback module. The second shift register is composed of several flip-flops connected in sequence, and the output of the second shift register is connected to the input of the second feedback module. At the same time, the output of the second shift register is also connected to the second input of the third XOR gate; the first output terminal OUT1 is connected to the second feedback module, which is a feedback circuit composed of XOR gates and NOT gates.

5. The high-speed true random number generator based on memristors according to claim 4, characterized in that, The second shift register includes four D flip-flops connected in sequence, and the output of the previous D flip-flop is connected to the data signal input of the next adjacent D flip-flop; the CLK clock signal is connected to the clock signal input of the four D flip-flops in the second shift register after passing through the third NOT gate.

6. The high-speed true random number generator based on memristors according to claim 5, characterized in that, The second feedback module includes a fourth XOR gate, a fifth XOR gate, a sixth XOR gate, and a second NOT gate; the first output terminal OUT1 is connected to the first input terminal of the fourth XOR gate, the output terminal of the fourth XOR gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is connected to the data signal input terminal of the first D flip-flop in the second shift register; the output terminals of the third and fourth D flip-flops in the second shift register are respectively connected to the first and second input terminals of the sixth XOR gate, the output terminal of the sixth XOR gate is connected to the second input terminal of the fifth XOR gate, the first input terminal of the fifth XOR gate is connected to the connection terminal of the second memristor and the second resistor, and the output terminal of the fifth XOR gate is connected to the second input terminal of the fourth XOR gate.

7. The high-speed true random number generator based on memristors according to claim 6, characterized in that, The output of the fourth D flip-flop in the second shift register is used as the second output OUT2 and is connected to the second input of the third XOR gate; the output of the third XOR gate is connected to the second input of the second XOR gate.

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