Display substrate, driving method thereof, and display device

Abstract

The display substrate, the driving method thereof and the display device provided by the present disclosure comprise a substrate, a display area and a frame area located at least one side of the display area; a plurality of pixel islands arranged in an array in the display area; each pixel island has a plurality of sub-pixels arranged in an array; a plurality of data lines extending along the column direction in the display area and arranged along the row direction, the data lines being electrically connected with the sub-pixels; a plurality of operational amplifiers located in the frame area; each operational amplifier is electrically connected with a column of sub-pixels through the data lines; a plurality of multiplexing circuits located in the frame area; each multiplexing circuit connects at least two operational amplifiers, and the sub-pixels electrically connected by each multiplexing circuit are located in at least two columns.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, its driving method, and a display device. Background Technology

[0002] Glasses-free 3D technology refers to 3D display technology that allows users to perceive space and depth without the aid of any auxiliary equipment. As users' demands for viewing experience increase, glasses-free 3D display technology is gradually being applied to display screens. Summary of the Invention

[0003] The display substrate, its driving method, and the display device provided in this disclosure are specifically as follows:

[0004] On one hand, an embodiment of this disclosure provides a display substrate, comprising:

[0005] The substrate includes a display area and a border area located on at least one side of the display area;

[0006] Multiple pixel islands are arranged in an array in the display area; each pixel island has multiple sub-pixels arranged in an array.

[0007] Multiple data lines extend along the column direction and are arranged along the row direction in the display area, and the data lines are electrically connected to the sub-pixels;

[0008] Multiple operational amplifiers are located in the border area; each operational amplifier is electrically connected to a column of sub-pixels via the data line.

[0009] Multiple multiplexed circuits are located in the border area; each multiplexed circuit is connected to at least two operational amplifiers, and the sub-pixels electrically connected to each multiplexed circuit via the data lines are located in at least two columns.

[0010] In some embodiments, in the display substrate provided in the present disclosure, each pair of at least two adjacent columns of pixel islands in the row direction constitutes a partition;

[0011] The multiplexing circuit includes a first sub-multiplexing circuit, and each of the sub-pixels electrically connected to the first sub-multiplexing circuit is located within at least two of the partitions.

[0012] In some embodiments, in the display substrate provided in the present disclosure, each of the first sub-multiplexing circuits is connected between the two operational amplifiers and the data lines electrically connected to the two operational amplifiers, and the sub-pixels electrically connected to each of the first sub-multiplexing circuits are located within the two partitions.

[0013] In some embodiments, the display substrate provided in the present disclosure has 2n partitions in the row direction, where n is a positive integer;

[0014] The first to nth consecutive partitions are considered fixation areas, and the (n+1)th to 2nth consecutive partitions are considered non-fixation areas.

[0015] Each of the sub-pixels electrically connected to the first sub-multiplexing circuit is located in the m-th and (m+n)-th partitions, where m is an integer greater than or equal to 1 and less than or equal to n.

[0016] In some embodiments, in the display substrate provided in the present disclosure, each partition includes i columns of pixel islands, where i is an integer greater than or equal to 2;

[0017] Each of the sub-pixels electrically connected to the first sub-multiplexing circuit is located in the pixel island in the j-th column of the m-th partition and in the pixel island in the j-th column of the (m+n)-th partition, where j is an integer greater than or equal to 1 and less than or equal to i.

[0018] In some embodiments, in the display substrate provided in the present disclosure, each pixel island has k sub-pixels arranged in a single row, where k is an even number;

[0019] Each of the first sub-multiplexing circuits is electrically connected to at least a portion of the sub-pixels in the h-th column of the j-th pixel island within the m-th partition, and at least a portion of the sub-pixels in the h-th column of the j-th pixel island within the (m+n)-th partition, where h is an integer greater than or equal to 1 and less than or equal to k.

[0020] In some embodiments, in the display substrate provided in the present disclosure, a data line is connected between one of the operational amplifiers and a column of the sub-pixels.

[0021] In some embodiments, in the display substrate provided in the present disclosure, each of the first sub-multiplexing circuits is electrically connected to the sub-pixel in the h-th column of the pixel island in the j-th column of the m-th partition, and the sub-pixel in the h-th column of the pixel island in the j-th column of the (m+n)-th partition.

[0022] In some embodiments, in the display substrate provided in the present disclosure, the multiplexing circuit further includes a second sub-multiplexing circuit;

[0023] Each of the second sub-multiplexing circuits is connected between two columns of sub-pixels in the same column of the pixel island, and between the two first sub-multiplexing circuits corresponding to the two columns of sub-pixels.

[0024] In some embodiments, in the display substrate provided in the present disclosure, k is a multiple of 4, h is an integer greater than or equal to 1 and less than or equal to k / 4, and an integer greater than or equal to (1+k / 4) and less than or equal to (k-4);

[0025] Each of the second sub-multiplexing circuits is electrically connected to the sub-pixel in the h-th column and the sub-pixel in the (h+k / 4)-th column of the pixel island in the same column.

[0026] In some embodiments, in the display substrate provided in the present disclosure, the first sub-multiplexing circuit connecting the sub-pixel in the h-th column of the pixel island in the j-th column of the m-th partition and the sub-pixel in the h-th column of the pixel island in the j-th (m+n)-th partition includes a first transistor, a second transistor and a third transistor;

[0027] The first sub-multiplexing circuit connecting the sub-pixel in the (h+k / 4)th column of the pixel island in the m-th partition and the sub-pixel in the (h+k / 4)th column of the pixel island in the (m+n)-th partition includes a fourth transistor, a fifth transistor, and a sixth transistor;

[0028] The second sub-multiplexing circuit connecting the sub-pixel in the h-th column of the pixel island in the j-th column of the m-th partition and the sub-pixel in the (h+k / 4)-th column includes a seventh transistor, an eighth transistor, and a ninth transistor;

[0029] The second sub-multiplexing circuit connecting the sub-pixel in column h and the sub-pixel in column (h+k / 4) of the pixel island in column j of the (m+n)th partition includes a tenth transistor, an eleventh transistor, and a twelfth transistor; wherein,

[0030] The gate of the first transistor is electrically connected to the first control signal terminal, the first terminal of the first transistor is electrically connected to the operational amplifier corresponding to the sub-pixel of the h-th column of the pixel island in the (m+n)th partition, and the second terminal of the first transistor is electrically connected to the operational amplifier corresponding to the sub-pixel of the h-th column of the pixel island in the j-th partition.

[0031] The gate of the second transistor is electrically connected to the second control signal terminal, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the second transistor is electrically connected to the first terminal of the seventh transistor.

[0032] The gate of the third transistor is electrically connected to the third control signal terminal, the first terminal of the third transistor is electrically connected to the first terminal of the first transistor, and the second terminal of the third transistor is electrically connected to the first terminal of the tenth transistor.

[0033] The gate of the fourth transistor is electrically connected to the fourth control signal terminal, the first terminal of the first transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the (m+n)th partition, and the second terminal of the first transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the (m)th partition.

[0034] The gate of the fifth transistor is electrically connected to the fifth control signal terminal, the first terminal of the fifth transistor is electrically connected to the second terminal of the fourth transistor, and the second terminal of the fifth transistor is electrically connected to the first terminal of the eighth transistor.

[0035] The gate of the sixth transistor is electrically connected to the sixth control signal terminal, the first terminal of the sixth transistor is electrically connected to the second terminal of the eleventh transistor, and the second terminal of the sixth transistor is electrically connected to the first terminal of the fourth transistor.

[0036] The gate of the seventh transistor is electrically connected to the seventh control signal terminal, and the second terminal of the seventh transistor is electrically connected to the data line corresponding to the sub-pixel in the h-th column of the pixel island in the m-th partition;

[0037] The gate of the eighth transistor is electrically connected to the eighth control signal terminal, and the second terminal of the eighth transistor is electrically connected to the data line corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the mth partition.

[0038] The gate of the ninth transistor is electrically connected to the ninth control signal terminal, the first terminal of the ninth transistor is electrically connected to the second terminal of the fourth transistor, and the second terminal of the ninth transistor is electrically connected to the second terminal of the second transistor.

[0039] The gate of the tenth transistor is electrically connected to the tenth control signal terminal, and the second terminal of the tenth transistor is electrically connected to the data line corresponding to the sub-pixel in the h-th column of the j-th pixel island in the (m+n)-th partition.

[0040] The gate of the eleventh transistor is electrically connected to the eleventh control signal terminal, and the second terminal of the eleventh transistor is electrically connected to the data line corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the (m+n)th partition.

[0041] The gate of the twelfth transistor is electrically connected to the twelfth control signal terminal, the first terminal of the twelfth transistor is electrically connected to the second terminal of the sixth transistor, and the second terminal of the twelfth transistor is electrically connected to the second terminal of the third transistor.

[0042] In some embodiments, in the display substrate provided in the present disclosure, two data lines are connected between one of the operational amplifiers and a column of sub-pixels, one of the two data lines being connected to the sub-pixels in the odd-numbered rows of the column, and the other being connected to the sub-pixels in the even-numbered rows of the column.

[0043] In some embodiments, in the display substrate provided in the present disclosure, each of the first sub-multiplexing circuits is electrically connected to the sub-pixel in the even-numbered row of the h-th column of the pixel island in the j-th column of the m-th partition, and the sub-pixel in the even-numbered row of the h-th column of the pixel island in the j-th column of the (m+n)-th partition.

[0044] In some embodiments, in the display substrate provided in the present disclosure, the first sub-multiplexing circuit includes: a thirteenth transistor and a fourteenth transistor; wherein,

[0045] The gate of the thirteenth transistor is electrically connected to the thirteenth control signal terminal, the first terminal of the thirteenth transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the h-th column of the pixel island in the m-th partition, and the second terminal of the thirteenth transistor is electrically connected to the data line corresponding to the sub-pixel in the even-numbered row of the h-th column of the pixel island in the (m+n)-th partition.

[0046] The gate of the fourteenth transistor is electrically connected to the fourteenth control signal terminal. The first terminal of the fourteenth transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the h-th column of the j-th pixel island in the (m+n)-th partition. The second terminal of the fourteenth transistor is electrically connected to the data line corresponding to the sub-pixel in the even-numbered row of the h-th column of the j-th pixel island in the m-th partition.

[0047] In some embodiments, the display substrate provided in this disclosure further includes a plurality of gating circuits located in the frame area;

[0048] Each of the gating circuits is connected between one of the operational amplifiers and the two data lines corresponding to that operational amplifier.

[0049] In some embodiments, in the display substrate provided in this disclosure, the gating circuit includes a fifteenth transistor and a sixteenth transistor; wherein,

[0050] The gate of the fifteenth transistor is electrically connected to the fifteenth control signal terminal, the first terminal of the fifteenth transistor is electrically connected to one of the operational amplifiers, and the second terminal of the fifteenth transistor is electrically connected to one of the two data lines.

[0051] The gate of the sixteenth transistor is electrically connected to the sixteenth control signal terminal, the first terminal of the sixteenth transistor is electrically connected to one of the operational amplifiers, and the second terminal of the sixteenth transistor is electrically connected to the other of the two data lines.

[0052] In some embodiments, the display substrate provided in the present disclosure further includes a source driver chip located in the border area, the source driver chip including the plurality of gating circuits, the plurality of multiplexing circuits, and the plurality of operational amplifiers.

[0053] In some embodiments, in the display substrate provided in the present disclosure, each pixel island has k sub-pixels arranged in a single row, where k is a multiple of 4;

[0054] The multiplexing circuit includes a third sub-multiplexing circuit, wherein the sub-pixel electrically connected to the third sub-multiplexing circuit is the sub-pixel in the h-th column of the pixel island in the same column, and the sub-pixel in the (h+k / 4)-th column, where h is an integer greater than or equal to 1 and less than or equal to k / 4, and an integer greater than or equal to (1+k / 4) and less than or equal to (k-4).

[0055] In some embodiments, in the display substrate provided in the present disclosure, each adjacent i columns of pixel islands in the row direction constitute a partition, and there are 2n partitions in the row direction, where i is an integer greater than or equal to 2 and n is a positive integer;

[0056] The multiplexing circuit further includes a fourth sub-multiplexing circuit, which connects the m-th partition and the sub-pixels of the same sequence of pixel islands in the (m+n)-th partition, where m is an integer greater than or equal to 1 and less than or equal to n.

[0057] In some embodiments, in the display substrate provided in the present disclosure, the third sub-multiplexing circuit connecting the sub-pixel in the h-th column of the pixel island in the j-th column of the m-th partition and the sub-pixel in the (h+k / 4)-th column includes the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, and the twenty-first transistor, where j is an integer greater than or equal to 1 and less than or equal to i.

[0058] The third sub-multiplexing circuit connecting the sub-pixel in column h of the pixel island in column j within the (m+n)th partition and the sub-pixel in column (h+k / 4) includes a 22nd transistor, a 23rd transistor, a 24th transistor, a 25th transistor, and a 26th transistor;

[0059] The fourth sub-multiplexing circuit connecting the sub-pixel in the h-th column of the pixel island in the j-th column of the m-th partition and the sub-pixel in the h-th column of the pixel island in the j-th (m+n)-th partition includes a twenty-seventh transistor;

[0060] The fourth sub-multiplexing circuit connecting the sub-pixel in the (h+k / 4)th column of the pixel island in the m-th partition and the sub-pixel in the (h+k / 4)th column of the pixel island in the (m+n)-th partition includes a twenty-eighth transistor; wherein,

[0061] The gate of the seventeenth transistor is electrically connected to the seventeenth control signal terminal, the first terminal of the seventeenth transistor is electrically connected to the second terminal of the eighteenth transistor, and the second terminal of the seventeenth transistor is electrically connected to the data line corresponding to the sub-pixel in the h-th column of the pixel island in the m-th partition;

[0062] The gate of the eighteenth transistor is electrically connected to the eighteenth control signal terminal, and the first terminal of the eighteenth transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the h-th column of the pixel island in the m-th partition;

[0063] The gate of the nineteenth transistor is electrically connected to the nineteenth control signal terminal, the first terminal of the nineteenth transistor is electrically connected to the second terminal of the twentieth transistor, and the second terminal of the nineteenth transistor is electrically connected to the data line corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the mth partition.

[0064] The gate of the twentieth transistor is electrically connected to the twentieth control signal terminal, and the first terminal of the twentieth transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the mth partition;

[0065] The gate of the 21st transistor is electrically connected to the 21st control signal terminal, the first terminal of the 21st transistor is electrically connected to the second terminal of the 20th transistor, and the second terminal of the 21st transistor is electrically connected to the second terminal of the 18th transistor.

[0066] The gate of the 22nd transistor is electrically connected to the 22nd control signal terminal, the first terminal of the 22nd transistor is electrically connected to the second terminal of the 23rd transistor, and the second terminal of the 22nd transistor is electrically connected to the data line corresponding to the sub-pixel in the h-th column of the pixel island in the (m+n)th partition;

[0067] The gate of the 23rd transistor is electrically connected to the 23rd control signal terminal, and the first terminal of the 23rd transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the h-th column of the pixel island in the m-th partition;

[0068] The gate of the 24th transistor is electrically connected to the 24th control signal terminal, the first terminal of the 24th transistor is electrically connected to the second terminal of the 25th transistor, and the second terminal of the 24th transistor is electrically connected to the data line corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the mth partition.

[0069] The gate of the 25th transistor is electrically connected to the 25th control signal terminal, and the first terminal of the 25th transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the mth partition;

[0070] The gate of the 26th transistor is electrically connected to the 26th control signal terminal, the first terminal of the 26th transistor is electrically connected to the second terminal of the 25th transistor, and the second terminal of the 26th transistor is electrically connected to the second terminal of the 23rd transistor.

[0071] The gate of the 27th transistor is electrically connected to the 27th control signal terminal, the first terminal of the 27th transistor is electrically connected to the operational amplifier corresponding to the sub-pixel of the h-th column of the pixel island in the (m+n)th partition, and the second terminal of the 27th transistor is electrically connected to the operational amplifier corresponding to the sub-pixel of the h-th column of the pixel island in the j-th partition;

[0072] The gate of the 28th transistor is electrically connected to the 28th control signal terminal, the first terminal of the 28th transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the (m+n)th partition, and the second terminal of the 28th transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the (m)th partition.

[0073] On the other hand, embodiments of this disclosure provide a driving method for the above-mentioned display substrate, including:

[0074] In multiplexing mode, the control multiplexing circuit turns on one data line electrically connected to it and disconnects the other data lines electrically connected to it, so that the data signals output by at least two operational amplifiers can be provided to the sub-pixels in the same column electrically connected to the data lines through the turned-on multiplexing circuit and the data lines.

[0075] In non-multiplexing mode, all data lines electrically connected to the control multiplexing circuit are disconnected to provide the data signals output by each operational amplifier to each column of sub-pixels electrically connected to each operational amplifier.

[0076] On the other hand, this disclosure provides a display device including the display substrate described above. Attached Figure Description

[0077] Figure 1 This is a schematic diagram of the structure of a display substrate in related technologies;

[0078] Figure 2 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure;

[0079] Figure 3 This is a schematic diagram of the structure of a partition;

[0080] Figure 4 A schematic diagram illustrating the multiplexing of operational amplifiers corresponding to different partitions;

[0081] Figure 5 To ensure compatibility between the multiplexing of operational amplifiers corresponding to different partitions and the multiplexing of operational amplifiers corresponding to different sub-pixels within the same pixel island;

[0082] Figure 6 This is a schematic diagram illustrating the multiplexing of operational amplifiers corresponding to different sub-pixels within the same pixel island;

[0083] Figure 7 for Figure 4 A schematic diagram of the structure of the first sub-multiplexing circuit;

[0084] Figure 8 for Figure 5 A schematic diagram of the structure of the first and second multiplexing circuits;

[0085] Figure 9 A charging simulation diagram showing the use of an operational amplifier to provide data signals to sub-pixels in the same column;

[0086] Figure 10 A charging simulation diagram showing the use of two operational amplifiers to provide data signals to sub-pixels in the same column;

[0087] Figure 11 This is another schematic diagram of operational amplifiers used in different partitions;

[0088] Figure 12 for Figure 11 A schematic diagram of the structure of the first sub-multiplexing circuit and the gating circuit;

[0089] Figure 13 for Figure 6A schematic diagram of the multiplexing of operational amplifiers corresponding to local sub-pixels;

[0090] Figure 14 This diagram illustrates the multiplexing of operational amplifiers corresponding to different sub-pixels within the same pixel island, and the multiplexing of operational amplifiers corresponding to different partitions.

[0091] Figure 15 for Figure 13 A schematic diagram of the structure of the third sub-multiplexing circuit;

[0092] Figure 16 for Figure 14 Schematic diagram of the structure of the third and fourth multiplexing circuits;

[0093] Figure 17 This is a flowchart of a driving method for a display substrate provided in an embodiment of this disclosure. Detailed Implementation

[0094] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout the drawings.

[0095] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0096] Figure 1 The diagram illustrates the structure of a display substrate in related technologies. Each operational amplifier (OP) is electrically connected to a row of sub-pixels (P), and the number of OPs matches the number of sub-pixels in a row. The OPs amplify the data signals output by the source driver chip (Source IC) and provide them to the corresponding connected sub-pixels (P). However, in 3D displays, the refresh rate of the area the human eye is focused on is higher than that of the non-focused area, or not all sub-pixels (P) are illuminated. This results in the OPs corresponding to non-focused areas or unilluminated sub-pixels (P) remaining idle, leading to resource waste.

[0097] To address the aforementioned technical problems in related technologies, this disclosure provides a display substrate, such as... Figures 2 to 4 As shown, it includes:

[0098] The substrate 101 includes a display area AA and a border area BB located on at least one side of the display area AA;

[0099] Multiple pixel islands 102 are arranged in an array in the display area AA; each pixel island 102 has multiple sub-pixels P arranged in an array;

[0100] Multiple data lines 103 extend along the column direction Y and are arranged along the row direction X in the display area AA. The data lines 103 are electrically connected to the sub-pixel P.

[0101] Multiple operational amplifiers (OPs) 104 are located in the border area BB; each operational amplifier 104 is electrically connected to a column of sub-pixels P via a data line 103.

[0102] Multiple multiplexed circuits 105 are located in the border area BB; each multiplexed circuit 105 is connected to at least two operational amplifiers 104, and each multiplexed circuit 105 is electrically connected to sub-pixels P via data lines 103 located in at least two columns.

[0103] In the display substrate provided in this embodiment, by controlling the multiplexing circuit 105 to turn on one data line 103 electrically connected to it and disconnecting the other data lines 103 electrically connected to it, the data signals output by at least two operational amplifiers OP can be provided to the sub-pixels P in the same column electrically connected to the data lines 103 through the turned-on multiplexing circuit 105 and data lines 103. Thus, by dynamically selecting idle operational amplifiers OP in related technologies through the multiplexing circuit 105, the resource utilization rate of operational amplifiers 104 is improved.

[0104] In addition, in this disclosure, the multiplexing circuit 105 can be controlled to disconnect all data lines 103 electrically connected to it, so as to provide the data signals output by each operational amplifier 104 to each column sub-pixel P that is electrically connected to each operational amplifier 104. At this time, each operational amplifier 104 works independently and is not multiplexed with each other.

[0105] In some embodiments, all sub-pixels P of each pixel island 102 are located in three rows and at least two columns, and within each pixel island 102, sub-pixels P in the same row have the same display color, while sub-pixels P in different rows have different display colors. For example, in Figure 3In this array, each pixel island 102 may include a red sub-pixel r, a green sub-pixel g, and a blue sub-pixel b. The number of red sub-pixels r, green sub-pixels g, and blue sub-pixels b are equal. The red sub-pixels r are arranged in a row along the X-axis, the green sub-pixels g are arranged in a row along the X-axis, and the blue sub-pixels b are arranged in a row along the X-axis. The rows of red, green, and blue sub-pixels are arranged along the Y-axis, thus arranging the pixel island 102 and the sub-pixels P within it in an array.

[0106] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 2 to 4 As shown, at least two adjacent columns of pixel islands 102 in the row direction X constitute a partition Z; the multiplexing circuit 105 includes a first sub-multiplexing circuit 1051, and each sub-pixel P electrically connected to the first sub-multiplexing circuit 1051 is located in at least two partitions Z, so as to realize the multiplexing of the operational amplifier 104 corresponding to the sub-pixel P in different partitions Z through the first sub-multiplexing circuit 1051.

[0107] To better understand the technical solution of this disclosure, the following will be described with the example that each first sub-multiplexing circuit 1051 is connected between two operational amplifiers 104 and the data line 103 electrically connected to the two operational amplifiers 104, and the sub-pixel P electrically connected to each first sub-multiplexing circuit 1051 is located in two partitions Z.

[0108] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 2 to 4 As shown, there are 2n (e.g., 16) partitions Z in the row direction X, where n is a positive integer;

[0109] The first to nth consecutive partitions are the viewing area W, and the (n+1)th to 2nth consecutive partitions are the non-viewing area NW; since the viewing area W is a continuous range, it can support 1 / 2 continuous area of ​​the display substrate;

[0110] Each sub-pixel P electrically connected to the first sub-multiplexing circuit 1051 is located in the m-th and (m+n)-th partitions Z, where m is an integer greater than or equal to 1 and less than or equal to n.

[0111] Since the m-th partition Z is located within the gaze area W and the (m+n)-th partition Z is located within the non-gaze area NW, when the non-gaze area NW is not refreshed but the gaze area W is refreshed, the operational amplifier 104 corresponding to the (m+n)-th partition Z in the non-gaze area NW can be multiplexed to the m-th partition Z in the gaze area W through the first sub-multiplexing circuit 1051. This allows the operational amplifier 104 corresponding to the (m+n)-th partition Z and the operational amplifier 104 corresponding to the m-th partition Z to simultaneously provide data signals to the sub-pixels P within the m-th partition Z, thereby reducing charging time and increasing the charging rate of the gaze area W. Furthermore, when both the gaze area W and the non-gaze area NW are refreshed, each uses its own operational amplifier 104, meaning they are not multiplexed.

[0112] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 2 to 4 As shown, each partition Z includes i columns of pixel islands 102, where i is an integer greater than or equal to 2; each sub-pixel P electrically connected to the first sub-multiplexing circuit 1051 is located in the j-th column of pixel island 102 of the m-th partition and the j-th column of pixel island 102 of the (m+n)-th partition, where j is an integer greater than or equal to 1 and less than or equal to i. This configuration not only enables the mutual multiplexing of the operational amplifier 104 corresponding to the j-th column of pixel island 102 of the m-th partition and the operational amplifier 104 corresponding to the j-th column of pixel island 102 of the (m+n)-th partition, but also simplifies the wiring method.

[0113] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 2 to 4 As shown, each pixel island 102 has k sub-pixels P arranged in a single row, where k is an even number; each first sub-multiplexing circuit 1051 is electrically connected to at least a portion of the sub-pixels P in the h-th column of the j-th pixel island in the m-th partition Z, and at least a portion of the sub-pixels P in the h-th column of the j-th pixel island in the (m+n)-th partition Z, where h is an integer greater than or equal to 1 and less than or equal to k / 4, and an integer greater than or equal to (1+k / 4) and less than or equal to (k-4). This configuration not only enables the mutual multiplexing of the operational amplifier 104 corresponding to the h-th column sub-pixel P of the j-th pixel island 102 in the m-th partition Z and the operational amplifier 104 corresponding to the h-th column sub-pixel P of the j-th pixel island 102 in the (m+n)-th partition Z, but also simplifies the wiring method.

[0114] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 2 to 4As shown, an operational amplifier 104 is connected to a column of sub-pixels P by a data line 103. At this time, each sub-multiplexing circuit 1051 is electrically connected to the sub-pixel P in the h-th column of the j-th pixel island in the m-th partition, and the sub-pixel P in the h-th column of the j-th pixel island in the (m+n)-th partition.

[0115] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 5 As shown, the multiplexing circuit 105 may further include a second sub-multiplexing circuit 1052; each second sub-multiplexing circuit 1052 is connected between two columns of sub-pixels P in the same column pixel island 102 and between two first sub-multiplexing circuits 1051 corresponding to the two columns of sub-pixels P.

[0116] The second sub-multiplexing circuit 1052 can be used to multiplex the operational amplifiers 104 corresponding to two columns of sub-pixels P in the same column of pixel island 102. Furthermore, when the multiplexing circuit 105 simultaneously has the first sub-multiplexing circuit 1051 and the second sub-multiplexing circuit 1052, it can achieve multiplexing of operational amplifiers 104 corresponding to different partitions Z through the first sub-multiplexing circuit 1051, and is also compatible with multiplexing of operational amplifiers 104 corresponding to two columns of sub-pixels P within the same column of pixel island 102 in the same partition Z.

[0117] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 5 and Figure 6 As shown, k is a multiple of 4, h is an integer greater than or equal to 1 and less than or equal to k / 4, and an integer greater than or equal to (1+k / 4) and less than or equal to (k-4); the outgoing light rays from the 1st to the k / 2nd sub-pixel P can converge to the left eye L to form the left eye viewpoint, and the outgoing light rays from the 1+k / 2nd to the kth sub-pixel P can converge to the right eye R to form the right eye viewpoint, thereby achieving naked-eye 3D display. Optionally, each second sub-multiplexing circuit 1052 is electrically connected to the hth column sub-pixel P and the (h+k / 4)th column sub-pixel P of the same column pixel island 102, respectively, so that the operational amplifier 104 corresponding to the hth column sub-pixel P and the operational amplifier 104 corresponding to the (h+k / 4)th column sub-pixel P of the same column pixel island 102 can be reused, which is beneficial to simplifying the wiring design.

[0118] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 7 and Figure 8 As shown, the first sub-multiplexing circuit 1051, which connects the h-th sub-pixel P of the j-th column pixel island 102 in the m-th partition Z and the h-th sub-pixel P of the j-th column pixel island 102 in the (m+n)-th partition Z, includes a first transistor M1, a second transistor M2 and a third transistor M3.

[0119] The first sub-multiplexing circuit 1051, which connects the (h+k / 4)th column sub-pixel P of the j-th column pixel island 102 in the m-th partition Z and the (h+k / 4)th column sub-pixel P of the j-th column pixel island 102 in the (m+n)-th partition Z, includes a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6;

[0120] The second sub-multiplexing circuit 1052 connecting the h-th sub-pixel P and the (h+k / 4)-th sub-pixel P of the j-th column pixel island 102 in the m-th partition Z includes a seventh transistor M7, an eighth transistor M8 and a ninth transistor M9;

[0121] The second sub-multiplexing circuit 1052 connecting the h-th column sub-pixel P and the (h+k / 4)-th column sub-pixel P of the j-th column pixel island 102 within the (m+n)-th partition Z includes a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12; wherein,

[0122] The gate of the first transistor M1 is electrically connected to the first control signal terminal G1. The first terminal of the first transistor M1 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the h-th column of the pixel island 102 in the (m+n)th partition Z. The second terminal of the first transistor M2 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the h-th column of the pixel island 102 in the m-th partition Z.

[0123] The gate of the second transistor M2 is electrically connected to the second control signal terminal G2, the first terminal of the second transistor M2 is electrically connected to the second terminal of the first transistor M1, and the second terminal of the second transistor M2 is electrically connected to the first terminal of the seventh transistor M7.

[0124] The gate of the third transistor M3 is electrically connected to the third control signal terminal G3, the first terminal of the third transistor M3 is electrically connected to the first terminal of the first transistor M1, and the second terminal of the third transistor M3 is electrically connected to the first terminal of the tenth transistor M10.

[0125] The gate of the fourth transistor M4 is electrically connected to the fourth control signal terminal G4. The first terminal of the first transistor M1 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the (h+k / 4)th column of the pixel island 102 in the (m+n)th partition Z. The second terminal of the first transistor M1 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the (h+k / 4)th column of the pixel island 102 in the mth partition Z.

[0126] The gate of the fifth transistor M5 is electrically connected to the fifth control signal terminal G5, the first terminal of the fifth transistor M5 is electrically connected to the second terminal of the fourth transistor M4, and the second terminal of the fifth transistor M5 is electrically connected to the first terminal of the eighth transistor M8.

[0127] The gate of the sixth transistor M6 is electrically connected to the sixth control signal terminal G6, the first terminal of the sixth transistor M6 is electrically connected to the second terminal of the eleventh transistor M11, and the second terminal of the sixth transistor M6 is electrically connected to the first terminal of the fourth transistor M4.

[0128] The gate of the seventh transistor M7 is electrically connected to the seventh control signal terminal G7, and the second terminal of the seventh transistor M7 is electrically connected to the data line 103 corresponding to the sub-pixel P in the h-th column of the pixel island 102 in the m-th partition Z.

[0129] The gate of the eighth transistor M8 is electrically connected to the eighth control signal terminal G8, and the second terminal of the eighth transistor M8 is electrically connected to the data line 103 corresponding to the (h+k / 4)th column sub-pixel P of the pixel island 102 in the m-th partition Z.

[0130] The gate of the ninth transistor M9 is electrically connected to the ninth control signal terminal G9, the first terminal of the ninth transistor M9 is electrically connected to the second terminal of the fourth transistor M4, and the second terminal of the ninth transistor M9 is electrically connected to the second terminal of the second transistor M2.

[0131] The gate of the tenth transistor M10 is electrically connected to the tenth control signal terminal G10, and the second terminal of the tenth transistor M10 is electrically connected to the data line 103 corresponding to the h-th sub-pixel P of the j-th column pixel island 102 in the (m+n)-th partition Z.

[0132] The gate of the eleventh transistor M11 is electrically connected to the eleventh control signal terminal G11, and the second terminal of the eleventh transistor M11 is electrically connected to the data line 103 corresponding to the (h+k / 4)th sub-pixel P of the j-th column pixel island 102 in the (m+n)-th partition Z.

[0133] The gate of the twelfth transistor M12 is electrically connected to the twelfth control signal terminal G12, the first terminal of the twelfth transistor M12 is electrically connected to the second terminal of the sixth transistor M6, and the second terminal of the twelfth transistor M12 is electrically connected to the second terminal of the third transistor M3.

[0134] Taking the display substrate provided in this disclosure as an example, it has 16 partitions Z, each partition Z has 30 columns of pixel islands 102, and each pixel island 102 has 16 sub-pixels P. Figure 4 and Figure 7The total number of transistors in all the first sub-multiplexing circuits 1051 in the display substrate shown is "3 (the number of transistors in each first sub-multiplexing circuit 1051) × 8 (8 groups of zones) × 30 (30 pixel islands in one zone) × 16 (16 sub-pixels in one pixel island) = 11520". If the display state of sub-pixels P in each zone Z is the same, "3 (the number of transistors in each first sub-multiplexing circuit 1051) × 8 (8 groups of zones) × 16 (16 sub-pixels in one pixel island) = 384" control signal terminals are needed to determine the switching state of the transistors. Figure 5 and Figure 8 The total number of transistors contained in all the first sub-multiplexing circuits 1051 and 1052 in the display substrate shown is "12 (the number of transistors contained in the two first sub-multiplexing circuits 1051 and the two second sub-multiplexing circuits 1052) × 8 (8 groups in each pixel island) × 30 (30 pixel islands in one partition) × 8 (8 partitions) = 23040". If the display state of sub-pixels P in each partition Z is the same, "12 (the number of transistors contained in the two first sub-multiplexing circuits 1051 and the two second sub-multiplexing circuits 1052) × 8 (8 groups in each pixel island) × 8 (8 partitions) = 768" control signal terminals are needed to determine the switching state of the transistors.

[0135] Specifically, in Figure 7 and Figure 8 The diagram shows that the first column sub-pixel P of the first column pixel island 102 in the first partition Z and the first column sub-pixel P of the first column pixel island 102 in the ninth partition Z are electrically connected to the same first sub-multiplexing circuit 1051, and the fifth column sub-pixel P of the first column pixel island 102 in the first partition Z and the fifth column sub-pixel P of the first column pixel island 102 in the ninth partition Z are electrically connected to another first sub-multiplexing circuit 1051; additionally, in Figure 8 The diagram also shows that the first column sub-pixel P and the fifth column sub-pixel P of the first column pixel island 102 in the first partition Z are electrically connected to the same second sub-multiplexing circuit 1052, and the first column sub-pixel P and the fifth column sub-pixel P of the first column pixel island 102 in the ninth partition Z are electrically connected to another second sub-multiplexing circuit 1052.

[0136] In some embodiments, 1 represents a high-level signal and 0 represents a low-level signal. Each transistor is turned on under a high-level signal and turned off under a low-level signal. It should be noted that 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of this disclosure, and are not the voltages applied to the gates of each transistor in actual implementation.

[0137] Table 1 shows the specific details. Figure 7The operational amplifier 104 (OP1 in Table 1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z and the operational amplifier 104 (OP1' in Table 1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z, when different logic levels are applied to each transistor, and the operational amplifier 104 (OP5 in Table 1) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the first partition Z and the operational amplifier 104 (OP5' in Table 1) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the ninth partition Z.

[0138] From Table 1 and Figure 7 As can be seen, when the first transistor M1 and the third transistor M3 are turned on, and the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned off, the operational amplifier 104 (i.e., OP1' in Table 1) corresponding to the first sub-pixel P of the first column of the pixel island 102 in the 9th partition Z reuses the operational amplifier 104 (i.e., OP1 in Table 1) corresponding to the first sub-pixel P of the first column of the pixel island 102 in the 1st partition Z; when the first transistor M1 and the second transistor M2 are turned on, and the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned off, the operational amplifier 104 (i.e., OP1 in Table 1) corresponding to the first sub-pixel P of the first column of the pixel island 102 in the 1st partition Z reuses the operational amplifier 104 (i.e., OP1' in Table 1) corresponding to the first sub-pixel P of the first column of the pixel island 102 in the 9th partition Z.

[0139] When the fourth transistor M4 and the sixth transistor M6 are turned on, and the first transistor M1, the second transistor M2, the third transistor M3, and the fifth transistor M5 are turned off, the operational amplifier 104 (i.e., OP5' in Table 1) corresponding to the fifth sub-pixel P of the first column pixel island 102 in the 9th partition Z is reused; when the fourth transistor M4 and the fifth transistor M5 are turned on, and the first transistor M1, the second transistor M2, the third transistor M3, and the sixth transistor M6 are turned off, the operational amplifier 104 (i.e., OP5 in Table 1) corresponding to the fifth sub-pixel P of the first column pixel island 102 in the 1st partition Z is reused.

[0140] With the first transistor M1, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 turned on, and the second transistor M2 and the fifth transistor M5 turned off, the operational amplifier 104 (OP1' in Table 1) corresponding to the first sub-pixel P of the first column of the first column of the pixel island 102 in the 9th partition Z reuses the operational amplifier 104 (OP1 in Table 1) corresponding to the first sub-pixel P of the first column of the pixel island 102 in the 1st partition Z, and the operational amplifier 104 (OP5' in Table 1) corresponding to the fifth sub-pixel P of the first column of the pixel island 102 in the 9th partition Z reuses the operational amplifier 104 (OP5 in Table 1) corresponding to the fifth sub-pixel P of the first column of the pixel island 102 in the 1st partition Z. With the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 turned on, and the third transistor M3 and the sixth transistor M6 turned off, the operational amplifier 104 (OP1 in Table 1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP1' in Table 1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z, and the operational amplifier 104 (OP5 in Table 1) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP5' in Table 1) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the ninth partition Z.

[0141] When the second transistor M2, the third transistor M3, the fifth transistor M5, and the sixth transistor M6 are turned on, and the first transistor M1 and the fourth transistor M4 are turned off, the operational amplifier 104 (i.e., OP1' in Table 1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the 9th partition Z is not reused with the operational amplifier 104 (i.e., OP1 in Table 1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the 1st partition Z, and the operational amplifier 104 (i.e., OP5' in Table 1) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the 9th partition Z is not reused with the operational amplifier 104 (i.e., OP5 in Table 1) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the 1st partition Z.

[0142] Table 1

[0143]

[0144] Tables 2-1 and 2-2 show in detail... Figure 8The operating states of the operational amplifier 104 (OP1) corresponding to the first column sub-pixel P of the first column pixel island 102 in the first partition Z and the operational amplifier 104 (OP1') corresponding to the first column sub-pixel P of the first column pixel island 102 in the ninth partition Z when different logic levels are applied to each transistor; the operating states of the operational amplifier 104 (OP5) corresponding to the fifth column sub-pixel P of the first column pixel island 102 in the first partition Z and the operational amplifier 104 (OP5') corresponding to the fifth column sub-pixel P of the first column pixel island 102 in the ninth partition Z; the operating states of the operational amplifier 104 (OP1 and OP5) corresponding to the first and fifth column sub-pixels P of the first column pixel island 102 in the first partition Z and the operational amplifier 104 (OP1' and OP5') corresponding to the first and fifth column sub-pixels P of the first column pixel island 102 in the ninth partition Z.

[0145] From Table 2-1 and Figure 8 As can be seen, when transistors M1 to M12 are in the first to twelfth positions, with transistors M2, M5, M7, and M9 turned on and the remaining transistors off, the operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP5) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the first partition Z; when transistors M2, M5, M8, and M9 are turned on and the remaining transistors off, the operational amplifier 104 (OP5) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP5) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the first partition Z. The operational amplifier 104 (OP5) corresponding to the first column sub-pixel P of the first column pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP1) corresponding to the first column sub-pixel P of the first column pixel island 102 in the first partition Z. When the second transistor M2, the fifth transistor M5, the seventh transistor M7 and the eighth transistor M8 are turned on and the remaining transistors are turned off, the operational amplifier 104 (OP1) corresponding to the first column sub-pixel P of the first column pixel island 102 in the first partition Z is not reused with the operational amplifier 104 (OP5) corresponding to the first column sub-pixel P of the first column pixel island 102 in the first partition Z.

[0146] When transistors M1 through M12 are all turned on (i.e., transistors M3, M6, M10, and M12 are on, and the remaining transistors are off), the operational amplifier 104 (OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the 9th partition Z reuses the operational amplifier 104 (OP5') corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the 9th partition Z; when transistors M1 through M12 are all turned on (i.e., transistors M3, M6, M11, and M12 are on, and the remaining transistors are off), the operational amplifier 104 (OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the 9th partition Z reuses the operational amplifier 104 (OP5') corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the 9th partition Z. The operational amplifier 104 (OP5') corresponding to the 5th column sub-pixel P of pixel island 102 is multiplexed with the operational amplifier 104 (OP1') corresponding to the 1st column sub-pixel P of pixel island 102 in the 9th partition Z. When the third transistor M3, the sixth transistor M6, the tenth transistor M10 and the eleventh transistor M11 are turned on and the remaining transistors are turned off, the operational amplifier 104 (OP1') corresponding to the 1st column sub-pixel P of pixel island 102 in the 9th partition Z is not multiplexed with the operational amplifier 104 (OP5') corresponding to the 1st column sub-pixel P of pixel island 102 in the 9th partition Z.

[0147] From Table 2-2 and Figure 8 As can be seen, when the first transistor M1, the second transistor M2, and the seventh transistor M7 are turned on, and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z is multiplexed with the operational amplifier 104 (i.e., OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z; when the first transistor M1, the third transistor M3, and the tenth transistor M10 are turned on, and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z is multiplexed with the operational amplifier 104 (i.e., OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z.

[0148] When the fourth transistor M4, the fifth transistor M5, and the eighth transistor M8 are turned on and the remaining transistors are turned off among the first transistors M1 to the twelfth transistors M12, the operational amplifier 104 (i.e., OP5) corresponding to the fifth sub-pixel P of the first column pixel island 102 in the first partition Z is reused as the operational amplifier 104 (i.e., OP5') corresponding to the fifth sub-pixel P of the first column pixel island 102 in the ninth partition Z; when the fourth transistor M4, the sixth transistor M6, and the eleventh transistor M11 are turned on and the remaining transistors are turned off among the first transistors M1 to the twelfth transistors M12, the operational amplifier 104 (i.e., OP5') corresponding to the fifth sub-pixel P of the first column pixel island 102 in the ninth partition Z is reused as the operational amplifier 104 (i.e., OP5) corresponding to the fifth sub-pixel P of the first column pixel island 102 in the first partition Z.

[0149] When transistors M1 to M12 are turned on (first transistor M1, second transistor M2, fourth transistor M4, fifth transistor M5, seventh transistor M7, and eighth transistor M8), and the remaining transistors are turned off, the operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z, and the operational amplifier 104 (OP5) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP5') corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the ninth partition Z; in When transistors M1 to M12 are turned on (first transistor M1, third transistor M3, fourth transistor M4, sixth transistor M6, tenth transistor M10, and eleventh transistor M11, and the remaining transistors are turned off), the operational amplifier 104 (OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the 9th partition Z reuses the operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the 1st partition Z, and the operational amplifier 104 (OP5') corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the 9th partition Z reuses the operational amplifier 104 (OP5) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the 1st partition Z.

[0150] When the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, and the eleventh transistor M11 are turned on, and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP1) corresponding to the first column sub-pixel P of the first column pixel island 102 in the first partition Z, the operational amplifier 104 (i.e., OP5) corresponding to the fifth column sub-pixel P of the first column pixel island 102 in the first partition Z, the operational amplifier 104 (i.e., OP1') corresponding to the first column sub-pixel P of the first column pixel island 102 in the ninth partition Z, and the operational amplifier 104 (i.e., OP5') corresponding to the fifth column sub-pixel P of the first column pixel island 102 in the ninth partition Z are all not reused.

[0151] Table 2-1

[0152]

[0153]

[0154] Table 2-2

[0155]

[0156] Figure 9 The image shown is a charging simulation diagram using an operational amplifier 104 to provide data signals to sub-pixel P. Figure 10 The diagram shows a charging simulation using two operational amplifiers 104 (i.e., in the multiplexed case) to provide data signals to sub-pixel P. A comparison shows that charging to 90% with one operational amplifier 104 takes 243.846 ns, while charging to 90% with two operational amplifiers 104 reduces the time to 136.755 ns. Therefore, this disclosure can reduce charging time, thereby improving the charging rate.

[0157] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 11 and Figure 12As shown, an operational amplifier 104 can be connected to a column of sub-pixels P via two data lines 103. One of the data lines 103 is connected to the sub-pixels P in the odd-numbered rows of a column, and the other is connected to the sub-pixels P in the even-numbered rows of a column. In this case, each first sub-multiplexing circuit 1051 is electrically connected to the sub-pixels P in the even-numbered rows of the h-th column of the pixel island 102 in the m-th partition Z, and the sub-pixels P in the even-numbered rows of the h-th column of the pixel island 102 in the (m+n)-th partition Z. Therefore, the data signal provided by the operational amplifier 104 corresponding to the sub-pixel P in the h-th column of the pixel island 102 in the m-th partition Z can be written into the even-numbered row sub-pixel P in the h-th column of the pixel island 102 in the (m+n)-th partition Z through the first sub-multiplexing circuit 1051. Alternatively, the data signal provided by the operational amplifier 104 corresponding to the sub-pixel P in the h-th column of the pixel island 102 in the (m+n)-th partition Z can be written into the even-numbered row sub-pixel P in the h-th column of the pixel island 102 in the m-th partition Z through the first sub-multiplexing circuit 1051. This can reduce the charging time of one frame, thereby increasing the frame rate. Figure 11 and Figure 12 In the first partition Z, P1 represents the first sub-pixel P of the first column of pixel island 102, and P1' represents the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z.

[0158] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 12 As shown, the first sub-multiplexing circuit 1051 includes: a thirteenth transistor M13 and a fourteenth transistor M14; wherein,

[0159] The gate of the thirteenth transistor M13 is electrically connected to the thirteenth control signal terminal G13. The first terminal of the thirteenth transistor M13 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the h-th column of the pixel island 102 in the m-th partition Z. The second terminal of the thirteenth transistor M13 is electrically connected to the data line 103 corresponding to the even-numbered row sub-pixel P in the h-th column of the pixel island 102 in the (m+n)-th partition Z.

[0160] The gate of the fourteenth transistor M14 is electrically connected to the fourteenth control signal terminal G14. The first terminal of the fourteenth transistor M14 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the h-th column of the pixel island 102 in the (m+n)th partition Z. The second terminal of the fourteenth transistor M14 is electrically connected to the data line 103 corresponding to the even-numbered row sub-pixel P in the h-th column of the pixel island 102 in the m-th partition Z.

[0161] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 11As shown in Figure 12, it may also include multiple gating circuits 106 located in the border area BB; each gating circuit 106 is connected between an operational amplifier 104 and the two data lines 103 corresponding to the operational amplifier 104. The gating circuit 106 can cooperate with the first sub-multiplexing circuit 105 to realize different row multiplexing of the operational amplifiers 104 in different partitions Z.

[0162] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 12 As shown, the gating circuit 106 may include a fifteenth transistor M15 and a sixteenth transistor M16; wherein,

[0163] The gate of the fifteenth transistor M15 is electrically connected to the fifteenth control signal terminal G15, the first terminal of the fifteenth transistor M15 is electrically connected to an operational amplifier 104, and the second terminal of the fifteenth transistor M15 is electrically connected to one of the two data lines 103.

[0164] The gate of the sixteenth transistor M16 is electrically connected to the sixteenth control signal terminal G16, the first terminal of the sixteenth transistor M16 is electrically connected to an operational amplifier 104, and the second terminal of the sixteenth transistor M16 is electrically connected to the other of the two data lines 106.

[0165] Taking the display substrate provided in this disclosure as an example, it has 16 partitions Z, each partition Z has 30 columns of pixel islands 102, and each pixel island 102 has 16 sub-pixels P. Figure 11 and Figure 12 The total number of transistors in all the first sub-multiplexing circuits 1051 and gating circuits 106 in the display substrate shown is "6 (number of transistors corresponding to every two columns of sub-pixels) × 16 (16 zones) × 30 (30 pixel islands in one zone) × 8 (8 groups of sub-pixels in one pixel island) = 23040". If the display state of sub-pixels P in each zone Z is the same, "6 (number of transistors corresponding to every two columns of sub-pixels) × 16 (16 zones) × 8 (8 groups of sub-pixels in one pixel island) = 768" control signal terminals are needed to determine the switching state of the transistors.

[0166] Specifically, in Figure 12 The diagram shows that the first sub-pixel P of the first column of pixel island 102 in the first partition Z is electrically connected to the first sub-multiplexing circuit 1051 via two data lines 103 and a gating circuit 106. The first sub-pixel P of the first column of pixel island 102 in the ninth partition Z is electrically connected to the same first sub-multiplexing circuit 1051 via two data lines 103 and another gating circuit 106.

[0167] In some embodiments, 1 represents a high-level signal and 0 represents a low-level signal. Each transistor is turned on under a high-level signal and turned off under a low-level signal. It should be noted that 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of this disclosure, and are not the voltages applied to the gates of each transistor in actual implementation.

[0168] Table 3 shows the specific details. Figure 12 The operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of the first column of the pixel island 102 in the first partition Z and the operational amplifier 104 (OP1') corresponding to the first sub-pixel P of the first column of the pixel island 102 in the ninth partition Z are in operation when different logic levels are applied to each transistor.

[0169] From Table 3 and Figure 12 As can be seen, when the fourteenth transistor M14 and the fifteenth transistor M15 in the gating circuit 106 corresponding to the first column sub-pixel P of the first column pixel island 102 in the first partition Z are turned on, and the sixteenth transistor M16 in the gating circuit 106 corresponding to the first column sub-pixel P of the first column pixel island 102 in the first partition Z, and the fifteenth transistor M15 (i.e., M15' in Table 3) and the sixteenth transistor M16 (i.e., M16' in Table 3) in the gating circuit 106 corresponding to the first column sub-pixel P of the first column pixel island 102 in the ninth partition Z are turned off, the operational amplifier 104 (i.e., OP1) corresponding to the even-numbered row sub-pixel P of the first column pixel island 102 in the first partition Z reuses the operational amplifier 104 (i.e., OP1') corresponding to the first column sub-pixel P of the first column pixel island 102 in the ninth partition Z.

[0170] When the thirteenth transistor M13 and the fifteenth transistor M15 (i.e., M15') in the gating circuit 106 corresponding to the first column sub-pixel P of the first column pixel island 102 in the 9th partition Z are turned on, and the fifteenth transistor M15 and the sixteenth transistor M16 in the gating circuit 106 corresponding to the first column sub-pixel P of the first column pixel island 102 in the 1st partition Z, and the sixteenth transistor M16 (i.e., M16') in the gating circuit 106 corresponding to the first column sub-pixel P of the first column pixel island 102 in the 9th partition Z are turned off, the operational amplifier 104 (i.e., OP1') corresponding to the even-numbered row sub-pixel P of the first column pixel island 102 in the 1st column of the 9th partition Z reuses the operational amplifier 104 (i.e., OP1) corresponding to the first column sub-pixel P of the first column pixel island 102 in the 1st partition Z.

[0171] It should be noted that when the operational amplifiers 104 (OP1 and OP1') are multiplexed, the gate scan signal needs to be applied to the odd-numbered row sub-pixels P and the adjacent even-numbered row sub-pixels P simultaneously to reduce the charging time of one frame, thereby increasing the frame rate.

[0172] When the fifteenth transistor M15 and the sixteenth transistor M16 in the gating circuit 106 corresponding to the first column sub-pixel P of the first column pixel island 102 in the first partition Z, and the fifteenth transistor M15 (i.e., M15') and the sixteenth transistor M16 (i.e., M16') in the gating circuit 106 corresponding to the first column sub-pixel P of the first column pixel island 102 in the ninth partition Z, are turned on, and the thirteenth transistor M13 and the fourteenth transistor M14 are turned off, the operational amplifier 104 (i.e., OP1) corresponding to the even-numbered row sub-pixel P of the first column pixel island 102 in the first partition Z, and the operational amplifier 104 (i.e., OP1') corresponding to the even-numbered row sub-pixel P of the first column pixel island 102 in the ninth partition Z are not reused. Furthermore, the fifteenth transistor M15 in the gating circuit 106 corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z, and the fifteenth transistor M15 (i.e., M15') in the gating circuit 106 corresponding to the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z are simultaneously turned on, so that the data signals of the operational amplifier 104 (i.e., OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z, and the operational amplifier 104 (i.e., OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z are given to the sub-pixels in the odd-numbered rows. P; The sixteenth transistor M16 in the gating circuit 106 corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z, and the sixteenth transistor M16 (i.e., M16') in the gating circuit 106 corresponding to the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z are simultaneously turned on, so that the data signal of the operational amplifier 104 (i.e., OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z, and the operational amplifier 104 (i.e., OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z are given to the sub-pixel P in the even row.

[0173] Table 3

[0174]

[0175] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 13As shown, each pixel island 102 has k sub-pixels P arranged in a single row, where k is a multiple of 4; the multiplexing circuit 105 includes a third sub-multiplexing circuit 1053, which electrically connects the sub-pixels P in the h-th column and the (h+k / 4)-th column of the same pixel island 102, where h is an integer greater than or equal to 1 and less than or equal to k / 4, and an integer greater than or equal to (1+k / 4) and less than or equal to (k-4); this allows the operational amplifier 104 corresponding to the sub-pixel P in the h-th column and the operational amplifier 104 corresponding to the sub-pixel P in the (h+k / 4)-th column of the same pixel island 102 to be reused, which is beneficial for simplifying the wiring design.

[0176] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 2 , Figure 3 and Figure 14 As shown, each adjacent i-column pixel island 102 in the row direction X constitutes a partition Z, and there are 2n partitions Z in the row direction X, where i is an integer greater than or equal to 2 and n is a positive integer. The multiplexing circuit 105 may also include a fourth sub-multiplexing circuit 1054, which connects the m-th partition Z and the sub-pixels P of the same sequence (e.g., column j, where j is an integer greater than or equal to 1 and less than or equal to i) of the pixel island 102 in the (m+n)-th partition Z to the same sequence (e.g., column h), where m is an integer greater than or equal to 1 and less than or equal to n. This configuration not only enables the mutual multiplexing of the operational amplifiers 104 corresponding to the sub-pixels P of the same sequence of pixel islands 102 in the m-th partition Z and the (m+n)-th partition Z, but also simplifies the wiring.

[0177] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 15 and Figure 16 As shown, the third sub-multiplexing circuit 1053 connecting the h-th sub-pixel P and the (h+k / 4)-th sub-pixel P in the j-th column of the pixel island 102 in the m-th partition Z includes the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, the twentieth transistor M20, and the twenty-first transistor M21, where j is an integer greater than or equal to 1 and less than or equal to i.

[0178] The third sub-multiplexing circuit 1053 connecting the h-th sub-pixel P and the (h+k / 4)-th sub-pixel P of the j-th column pixel island 102 in the (m+n)-th partition Z includes a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25, and a twenty-sixth transistor M26.

[0179] The fourth sub-multiplexing circuit 1054, which connects the h-th sub-pixel P of the j-th column pixel island 102 in the m-th partition Z and the h-th sub-pixel P of the j-th column pixel island 102 in the (m+n)-th partition Z, includes a twenty-seventh transistor M27.

[0180] The fourth sub-multiplexing circuit 1054, connecting the (h+k / 4)th column sub-pixel P of the j-th column pixel island 102 within the m-th partition Z and the (h+k / 4)th column sub-pixel P of the j-th column pixel island 102 within the (m+n)-th partition Z, includes a twenty-eighth transistor M28; wherein,

[0181] The gate of the seventeenth transistor M17 is electrically connected to the seventeenth control signal terminal G17, the first terminal of the seventeenth transistor M17 is electrically connected to the second terminal of the eighteenth transistor M18, and the second terminal of the seventeenth transistor M17 is electrically connected to the data line 103 corresponding to the sub-pixel P of the j-th column pixel island 102 in the m-th partition Z.

[0182] The gate of the eighteenth transistor M18 is electrically connected to the eighteenth control signal terminal G18, and the first terminal of the eighteenth transistor M18 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P of the j-th column pixel island 102 in the m-th partition Z.

[0183] The gate of the nineteenth transistor M19 is electrically connected to the nineteenth control signal terminal G19, the first terminal of the nineteenth transistor M19 is electrically connected to the second terminal of the twentieth transistor M20, and the second terminal of the nineteenth transistor M19 is electrically connected to the data line 103 corresponding to the (h+k / 4)th column sub-pixel P of the j-th column pixel island 102 in the m-th partition Z.

[0184] The gate of the twentieth transistor M20 is electrically connected to the twentieth control signal terminal G20, and the first terminal of the twentieth transistor M20 is electrically connected to the operational amplifier 104 corresponding to the (h+k / 4)th column sub-pixel P of the j-th column pixel island 102 in the m-th partition Z.

[0185] The gate of the twenty-first transistor M21 is electrically connected to the twenty-first control signal terminal G21, the first terminal of the twenty-first transistor M21 is electrically connected to the second terminal of the twentieth transistor M20, and the second terminal of the twenty-first transistor M21 is electrically connected to the second terminal of the eighteenth transistor M18.

[0186] The gate of the 22nd transistor M22 is electrically connected to the 22nd control signal terminal G22, the first terminal of the 22nd transistor M22 is electrically connected to the second terminal of the 23rd transistor M23, and the second terminal of the 22nd transistor M22 is electrically connected to the data line 103 corresponding to the sub-pixel P of the j-th column pixel island 102 in the (m+n)-th partition Z.

[0187] The gate of the 23rd transistor M23 is electrically connected to the 23rd control signal terminal G23, and the first terminal of the 23rd transistor M23 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P of the j-th column pixel island 102 in the m-th partition Z.

[0188] The gate of the 24th transistor M24 is electrically connected to the 24th control signal terminal G24, the first terminal of the 24th transistor M24 is electrically connected to the second terminal of the 25th transistor M25, and the second terminal of the 24th transistor M24 is electrically connected to the data line 103 corresponding to the (h+k / 4)th column sub-pixel P of the j-th column pixel island 102 in the m-th partition Z.

[0189] The gate of the 25th transistor M25 is electrically connected to the 25th control signal terminal G25, and the first terminal of the 25th transistor M25 is electrically connected to the operational amplifier 104 corresponding to the (h+k / 4)th column sub-pixel P of the j-th column pixel island 102 in the m-th partition Z.

[0190] The gate of the 26th transistor M26 is electrically connected to the 26th control signal terminal G26, the first terminal of the 26th transistor M26 is electrically connected to the second terminal of the 25th transistor M25, and the second terminal of the 26th transistor M26 is electrically connected to the second terminal of the 23rd transistor M23.

[0191] The gate of the 27th transistor M27 is electrically connected to the 27th control signal terminal G27. The first terminal of the 27th transistor M27 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the h-th column of the pixel island 102 in the (m+n)th partition Z. The second terminal of the 27th transistor M27 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the h-th column of the pixel island 102 in the m-th partition Z.

[0192] The gate of the twenty-eighth transistor M28 is electrically connected to the twenty-eighth control signal terminal G28. The first terminal of the twenty-eighth transistor M28 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the (h+k / 4)th column of the pixel island 102 in the (m+n)th partition Z. The second terminal of the twenty-eighth transistor M28 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the (h+k / 4)th column of the pixel island 102 in the mth partition Z.

[0193] Taking the display substrate provided in this disclosure as an example, it has 16 partitions Z, each partition Z has 30 columns of pixel islands 102, and each pixel island 102 has 16 sub-pixels P. Figure 13 and Figure 15The total number of transistors in all the third sub-multiplexing circuits 1053 in the display substrate shown is "5 (the number of transistors in each third sub-multiplexing circuit 1051) × 8 (one pixel island with 8 groups of sub-pixel columns) × 30 (one partition with 30 pixel islands) × 16 (16 partitions) = 19200". If the display state of sub-pixels P in each partition Z is the same, "5 (the number of transistors in each third sub-multiplexing circuit 1051) × 8 (one pixel island with 8 groups of sub-pixel columns) × 16 (16 partitions) = 640" control signal terminals are needed to determine the switching state of the transistors. Figure 14 and Figure 16 The total number of transistors in all the third and fourth sub-multiplexing circuits 1054 in the display substrate shown is "12 (the number of transistors in the two third sub-multiplexing circuits 1053 and the two fourth sub-multiplexing circuits 1054) × 8 (8 groups in each pixel island) × 30 (30 pixel islands in one partition) × 8 (8 partitions) = 23040". If the display state of sub-pixels P in each partition Z is the same, "12 (the number of transistors in the two first sub-multiplexing circuits 1051 and the two second sub-multiplexing circuits 1052) × 8 (8 groups in each pixel island) × 8 (8 partitions) = 768" control signal terminals are needed to determine the switching state of the transistors.

[0194] Specifically, in Figure 15 The diagram shows that the first column sub-pixel P and the fifth column sub-pixel P of the first column pixel island 102 in the first partition Z are electrically connected to the same third sub-multiplexing circuit 1053.

[0195] In some embodiments, 1 represents a high-level signal and 0 represents a low-level signal. Each transistor is turned on under a high-level signal and turned off under a low-level signal. It should be noted that 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of this disclosure, and are not the voltages applied to the gates of each transistor in actual implementation.

[0196] Table 4 shows the specific details. Figure 15 The operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of the first column of the pixel island 102 in the first partition Z and the operational amplifier 104 (OP5) corresponding to the fifth sub-pixel P of the first column of the pixel island 102 in the first partition Z are in operation when different logic levels are applied to each transistor.

[0197] From Table 4 and Figure 15As can be seen, when transistors 17 (M17), 18 (M18), 20 (M20), and 21 (M21) are turned on, and transistor 19 (M19) is turned off, the operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP5) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the first partition Z. When transistors 18 (M18), 19 (M19), 20 (M20), and 21 (M21) are turned on, and transistor 17 (M17) is turned off, the operational amplifier 104 (OP5) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z. With the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, and the twentieth transistor M20 turned on, and the twenty-first transistor M21 turned off, the operational amplifier 104 (i.e., OP1) corresponding to the first sub-pixel P of the first column of the first pixel island 102 in the first partition Z, and the operational amplifier 104 (i.e., OP5) corresponding to the fifth sub-pixel P of the first column of the first pixel island 102 in the first partition Z are not reused.

[0198] Table 4

[0199]

[0200] Tables 5-1 and 5-2 show in detail... Figure 16 The operating states of the operational amplifier 104 (OP1) corresponding to the first column sub-pixel P of the first column pixel island 102 in the first partition Z and the operational amplifier 104 (OP1') corresponding to the first column sub-pixel P of the first column pixel island 102 in the ninth partition Z when different logic levels are applied to each transistor; the operating states of the operational amplifier 104 (OP5) corresponding to the fifth column sub-pixel P of the first column pixel island 102 in the first partition Z and the operational amplifier 104 (OP5') corresponding to the fifth column sub-pixel P of the first column pixel island 102 in the ninth partition Z; the operating states of the operational amplifier 104 (OP1 and OP5) corresponding to the first and fifth column sub-pixels P of the first column pixel island 102 in the first partition Z and the operational amplifier 104 (OP1' and OP5') corresponding to the first and fifth column sub-pixels P of the first column pixel island 102 in the ninth partition Z.

[0201] From Table 5-1 and Figure 16As can be seen, when transistors M17, M18, M20, and M21 are turned on and the remaining transistors are turned off, the operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP5) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the first partition Z; when transistors M18, M19, M20, and M21 are turned on and the remaining transistors are turned off, the first The operational amplifier 104 (OP5) corresponding to the first sub-pixel P of the first column of pixel island 102 in partition Z is reused as the operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in partition Z. When the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, and the twentieth transistor M20 are turned on and the other transistors are turned off, the operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in partition Z, and the operational amplifier 104 (OP5) corresponding to the first sub-pixel P of the first column of pixel island 102 in partition Z are not reused.

[0202] When transistors M17 to M28 are active, transistors M22, M23, M25, and M26 are active, and the remaining transistors are off, the operational amplifier 104 (OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the 9th partition Z reuses the operational amplifier 104 (OP5') corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the 9th partition Z; when transistors M17 to M28 are active, transistors M23, M24, M25, and M26 are active, and the remaining transistors are off, the 9th partition... The operational amplifier 104 (OP5') corresponding to the 5th sub-pixel P of the 1st column pixel island 102 in the 9th partition Z is reused. When the 22nd transistor M22, the 23rd transistor M23, the 24th transistor M24 and the 25th transistor M25 are turned on and the remaining transistors are turned off, the operational amplifier 104 (OP1') corresponding to the 1st column sub-pixel P of the 1st column pixel island 102 in the 9th partition Z and the operational amplifier 104 (OP5') corresponding to the 1st column sub-pixel P of the 1st column pixel island 102 in the 9th partition Z are not reused.

[0203] From Table 5-2 and Figure 16 As can be seen, when transistors M17, M18, and M27 are turned on and the remaining transistors are turned off, the operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z; when transistors M22, M23, and M27 are turned on and the remaining transistors are turned off, the operational amplifier 104 (OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z reuses the operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z.

[0204] When transistors M17 to M28 are in the 17th to 28th segments, with transistors M19, M20, and M28 turned on and the remaining transistors turned off, the operational amplifier 104 (OP5) corresponding to the 5th sub-pixel P of the 1st column pixel island 102 in the 1st segment Z reuses the operational amplifier 104 (OP5') corresponding to the 5th sub-pixel P of the 1st column pixel island 102 in the 9th segment Z. When transistors M24, M25, and M28 are in the 17th to 28th segments, with transistors M24, M25, and M28 turned on and the remaining transistors turned off, the operational amplifier 104 (OP5') corresponding to the 5th sub-pixel P of the 1st column pixel island 102 in the 9th segment Z reuses the operational amplifier 104 (OP5) corresponding to the 5th sub-pixel P of the 1st column pixel island 102 in the 1st segment Z.

[0205] When transistors M17 to M28 are turned on (M17, M18, M19, M20, M27, and M28, respectively) and the remaining transistors are turned off, the operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the ninth partition Z, and the operational amplifier 104 (OP5) corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the first partition Z reuses the operational amplifier 104 (OP5') corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the ninth partition Z; in the... Among transistors M17 to M28, transistors M22, M23, M24, M25, M27, and M28 are turned on, while the remaining transistors are turned off. When the operational amplifier 104 (OP1') corresponding to the first sub-pixel P of the first column of pixel island 102 in the 9th partition Z is multiplexed, the operational amplifier 104 (OP1) corresponding to the first sub-pixel P of the first column of pixel island 102 in the 1st partition Z is multiplexed, and the operational amplifier 104 (OP5') corresponding to the fifth sub-pixel P of the first column of pixel island 102 in the 9th partition Z is multiplexed.

[0206] Among transistors M17 to M28, when transistors M17, M18, M19, M20, M22, M23, M24, and M25 are turned on and the remaining transistors are turned off, the operational amplifiers 104 (OP1), OP5, OP1', and OP5' corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z, OP1' and OP5' corresponding to the first sub-pixel P of the first column of pixel island 102 in the first partition Z are not reused.

[0207] Table 5-1

[0208]

[0209] Table 5-2

[0210]

[0211] It should be noted that in the embodiments of this disclosure, each transistor can be a top-gate transistor or a bottom-gate transistor, and there is no limitation herein. Optionally, each transistor can be a field-effect transistor, a low-temperature polycrystalline silicon transistor, an amorphous silicon transistor, an oxide transistor, etc. In addition, the first and second terminals of each transistor are the drain and the source, respectively, and no specific distinction is made here.

[0212] In some embodiments, the display substrate provided in this disclosure may further include a source driver chip located in the bezel area BB. Multiple gating circuits 106, multiple multiplexing circuits 105, and multiple operational amplifiers 104 can be integrated within the source driver chip to reduce data signal loss (RC loading) along the transmission path from the source driver chip to the sub-pixel P. It should be understood that when operational amplifiers 104 are multiplexed between partitions Z, the trace distance between the two operational amplifiers 104 between partitions Z is greater than that when operational amplifiers 104 are multiplexed within the pixel island 102. Therefore, it is suitable to integrate the gating circuits 106, multiplexing circuits 105, and operational amplifiers 104 within the source driver chip. When the operational amplifier 104 is multiplexed within the pixel island 102, the traces between the two operational amplifiers 104 are relatively close. In this case, the gating circuit 106, the multiplexing circuit 105, and the operational amplifier 104 can be integrated into the source driver chip, or the gating circuit 106, the multiplexing circuit 105, and the operational amplifier 104 can be fabricated on the display substrate. No specific limitation is made here.

[0213] Based on the same inventive concept, this disclosure provides a driving method for the above-mentioned display substrate. Since the principle of this driving method in solving the problem is similar to that of the above-mentioned display substrate in solving the problem, the implementation of the driving method provided in this disclosure can refer to the implementation of the above-mentioned display substrate provided in this disclosure, and repeated details will not be described again.

[0214] Specifically, the present disclosure provides a driving method for the above-mentioned display substrate, such as... Figure 17 As shown, it includes the following steps:

[0215] S1701. In multiplexing mode, control the multiplexing circuit to turn on one data line electrically connected to it and disconnect the other data lines electrically connected to it, so as to provide the data signals output by at least two operational amplifiers to the sub-pixels in the same column electrically connected to the data lines through the turned-on multiplexing circuit and data lines.

[0216] S1702. In non-multiplexing mode, all data lines electrically connected to the control multiplexing circuit are disconnected so that the data signals output by each operational amplifier can be provided to each column of sub-pixels that are electrically connected to each operational amplifier.

[0217] Based on the same inventive concept, this disclosure provides a display device including the display substrate described above. Since the principle by which this display device solves the problem is similar to that of the display substrate, the implementation of the display device provided in this disclosure can refer to the implementation of the display substrate described above, and repeated details will not be described again.

[0218] In some embodiments, the display device provided in this disclosure can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. This display device includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, memory, processor, and power supply. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in this disclosure. In other words, the display device provided in this disclosure may include more or fewer of the aforementioned components, or combine certain components, or have different component arrangements.

[0219] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display substrate, wherein, include: The substrate includes a display area and a border area located on at least one side of the display area; Multiple pixel islands are arranged in an array in the display area; each pixel island has multiple sub-pixels arranged in an array. Multiple data lines extend along the column direction and are arranged along the row direction in the display area, and the data lines are electrically connected to the sub-pixels; Multiple operational amplifiers are located in the border area; each operational amplifier is electrically connected to a column of sub-pixels via the data line. Multiple multiplexed circuits are located in the border area; each multiplexed circuit is connected to at least two operational amplifiers, and the sub-pixels electrically connected to each multiplexed circuit via the data lines are located in at least two columns; In the row direction, at least two adjacent columns of the pixel islands constitute a partition; the multiplexing circuit includes a first sub-multiplexing circuit, and each sub-pixel electrically connected to the first sub-multiplexing circuit is located within at least two of the partitions; Each of the first sub-multiplexing circuits is connected between the two operational amplifiers and the data lines electrically connected to the two operational amplifiers, and the sub-pixels electrically connected to each of the first sub-multiplexing circuits are located within the two partitions; There are 2n partitions in the row direction, where n is a positive integer; the 1st to nth consecutive partitions are gaze regions, and the (n+1)th to 2nth consecutive partitions are non-gaze regions; each sub-pixel electrically connected to the first sub-multiplexing circuit is located in the mth and (m+n)th partitions, where m is an integer greater than or equal to 1 and less than or equal to n; Each partition includes i columns of pixel islands, where i is an integer greater than or equal to 2; each sub-pixel electrically connected to the first sub-multiplexing circuit is located in the j-th column of the pixel island in the m-th partition and in the j-th column of the pixel island in the (m+n)-th partition, where j is an integer greater than or equal to 1 and less than or equal to i; Each pixel island has k sub-pixels arranged in a single row, where k is an even number; each of the sub-pixels electrically connected to the first sub-multiplexing circuit is at least a portion of the sub-pixels in the h-th column of the j-th column of the pixel island in the m-th partition, and at least a portion of the sub-pixels in the h-th column of the j-th column of the pixel island in the (m+n)-th partition, where h is an integer greater than or equal to 1 and less than or equal to k.

2. The display substrate as claimed in claim 1, wherein, A data line is connected between one of the operational amplifiers and a column of the sub-pixels.

3. The display substrate as described in claim 2, wherein, Each of the first sub-multiplexing circuits is electrically connected to the sub-pixel in the h-th column of the pixel island in the j-th column of the m-th partition, and the sub-pixel in the h-th column of the pixel island in the j-th column of the (m+n)-th partition.

4. The display substrate as described in claim 3, wherein, The multiplexing circuit also includes a second sub-multiplexing circuit; Each of the second sub-multiplexing circuits is connected between two columns of sub-pixels in the same column of the pixel island, and between the two first sub-multiplexing circuits corresponding to the two columns of sub-pixels.

5. The display substrate as claimed in claim 4, wherein, k is a multiple of 4, h is an integer greater than or equal to 1 and less than or equal to k / 4, and an integer greater than or equal to (1+k / 4) and less than or equal to (k-4); Each of the second sub-multiplexing circuits is electrically connected to the sub-pixel in the h-th column and the sub-pixel in the (h+k / 4)-th column of the pixel island in the same column.

6. The display substrate as claimed in claim 5, wherein, The first sub-multiplexing circuit connecting the sub-pixel in the h-th column of the pixel island in the j-th column of the m-th partition and the sub-pixel in the h-th column of the pixel island in the j-th (m+n)-th partition includes a first transistor, a second transistor, and a third transistor; The first sub-multiplexing circuit connecting the sub-pixel in the (h+k / 4)th column of the pixel island in the m-th partition and the sub-pixel in the (h+k / 4)th column of the pixel island in the (m+n)-th partition includes a fourth transistor, a fifth transistor, and a sixth transistor; The second sub-multiplexing circuit connecting the sub-pixel in the h-th column of the pixel island in the j-th column of the m-th partition and the sub-pixel in the (h+k / 4)-th column includes a seventh transistor, an eighth transistor, and a ninth transistor; The second sub-multiplexing circuit connecting the sub-pixel in column h and the sub-pixel in column (h+k / 4) of the pixel island in column j of the (m+n)th partition includes a tenth transistor, an eleventh transistor, and a twelfth transistor; wherein, The gate of the first transistor is electrically connected to the first control signal terminal, the first terminal of the first transistor is electrically connected to the operational amplifier corresponding to the sub-pixel of the h-th column of the pixel island in the (m+n)th partition, and the second terminal of the first transistor is electrically connected to the operational amplifier corresponding to the sub-pixel of the h-th column of the pixel island in the j-th partition. The gate of the second transistor is electrically connected to the second control signal terminal, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the second transistor is electrically connected to the first terminal of the seventh transistor. The gate of the third transistor is electrically connected to the third control signal terminal, the first terminal of the third transistor is electrically connected to the first terminal of the first transistor, and the second terminal of the third transistor is electrically connected to the first terminal of the tenth transistor. The gate of the fourth transistor is electrically connected to the fourth control signal terminal, the first terminal of the first transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the (m+n)th partition, and the second terminal of the first transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the (m)th partition. The gate of the fifth transistor is electrically connected to the fifth control signal terminal, the first terminal of the fifth transistor is electrically connected to the second terminal of the fourth transistor, and the second terminal of the fifth transistor is electrically connected to the first terminal of the eighth transistor. The gate of the sixth transistor is electrically connected to the sixth control signal terminal, the first terminal of the sixth transistor is electrically connected to the second terminal of the eleventh transistor, and the second terminal of the sixth transistor is electrically connected to the first terminal of the fourth transistor. The gate of the seventh transistor is electrically connected to the seventh control signal terminal, and the second terminal of the seventh transistor is electrically connected to the data line corresponding to the sub-pixel in the h-th column of the pixel island in the m-th partition; The gate of the eighth transistor is electrically connected to the eighth control signal terminal, and the second terminal of the eighth transistor is electrically connected to the data line corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the mth partition. The gate of the ninth transistor is electrically connected to the ninth control signal terminal, the first terminal of the ninth transistor is electrically connected to the second terminal of the fourth transistor, and the second terminal of the ninth transistor is electrically connected to the second terminal of the second transistor. The gate of the tenth transistor is electrically connected to the tenth control signal terminal, and the second terminal of the tenth transistor is electrically connected to the data line corresponding to the sub-pixel in the h-th column of the j-th pixel island in the (m+n)-th partition. The gate of the eleventh transistor is electrically connected to the eleventh control signal terminal, and the second terminal of the eleventh transistor is electrically connected to the data line corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the (m+n)th partition. The gate of the twelfth transistor is electrically connected to the twelfth control signal terminal, the first terminal of the twelfth transistor is electrically connected to the second terminal of the sixth transistor, and the second terminal of the twelfth transistor is electrically connected to the second terminal of the third transistor.

7. The display substrate as claimed in claim 1, wherein, Two data lines are connected between one of the operational amplifiers and a column of the sub-pixels, one of the two data lines connecting to the sub-pixels in the odd-numbered rows of the column and the other connecting to the sub-pixels in the even-numbered rows of the column.

8. The display substrate as claimed in claim 7, wherein, Each of the first sub-multiplexing circuits is electrically connected to the sub-pixel in the even-numbered row of the h-th column of the pixel island in the j-th column of the m-th partition, and the sub-pixel in the even-numbered row of the h-th column of the pixel island in the j-th column of the (m+n)-th partition.

9. The display substrate as claimed in claim 8, wherein, The first sub-multiplexing circuit includes: a thirteenth transistor and a fourteenth transistor; wherein, The gate of the thirteenth transistor is electrically connected to the thirteenth control signal terminal, the first terminal of the thirteenth transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the h-th column of the pixel island in the m-th partition, and the second terminal of the thirteenth transistor is electrically connected to the data line corresponding to the sub-pixel in the even-numbered row of the h-th column of the pixel island in the (m+n)-th partition. The gate of the fourteenth transistor is electrically connected to the fourteenth control signal terminal. The first terminal of the fourteenth transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the h-th column of the j-th pixel island in the (m+n)-th partition. The second terminal of the fourteenth transistor is electrically connected to the data line corresponding to the sub-pixel in the even-numbered row of the h-th column of the j-th pixel island in the m-th partition.

10. The display substrate according to any one of claims 7 to 9, wherein, It also includes multiple gating circuits located in the border area; Each of the gating circuits is connected between one of the operational amplifiers and the two data lines corresponding to that operational amplifier.

11. The display substrate as claimed in claim 10, wherein, The gating circuit includes a fifteenth transistor and a sixteenth transistor; wherein, The gate of the fifteenth transistor is electrically connected to the fifteenth control signal terminal, the first terminal of the fifteenth transistor is electrically connected to one of the operational amplifiers, and the second terminal of the fifteenth transistor is electrically connected to one of the two data lines. The gate of the sixteenth transistor is electrically connected to the sixteenth control signal terminal, the first terminal of the sixteenth transistor is electrically connected to one of the operational amplifiers, and the second terminal of the sixteenth transistor is electrically connected to the other of the two data lines.

12. The display substrate as claimed in claim 10, wherein, It also includes a source driver chip located in the border area, the source driver chip including the plurality of gating circuits, the plurality of multiplexing circuits, and the plurality of operational amplifiers.

13. The display substrate as claimed in claim 1, wherein, Each pixel island has k sub-pixels arranged in a single row, where k is a multiple of 4; The multiplexing circuit includes a third sub-multiplexing circuit, wherein the sub-pixel electrically connected to the third sub-multiplexing circuit is the sub-pixel in the h-th column of the pixel island in the same column, and the sub-pixel in the (h+k / 4)-th column, where h is an integer greater than or equal to 1 and less than or equal to k / 4, and an integer greater than or equal to (1+k / 4) and less than or equal to (k-4).

14. The display substrate as claimed in claim 13, wherein, Each adjacent i columns of pixel islands in the row direction constitute a partition, and there are 2n partitions in the row direction, where i is an integer greater than or equal to 2 and n is a positive integer; The multiplexing circuit further includes a fourth sub-multiplexing circuit, which connects the m-th partition and the sub-pixels of the same sequence of pixel islands in the (m+n)-th partition, where m is an integer greater than or equal to 1 and less than or equal to n.

15. The display substrate as claimed in claim 14, wherein, The third sub-multiplexing circuit connecting the sub-pixel in column h and the sub-pixel in column (h+k / 4) of the pixel island in column j of the m-th partition includes the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, and the twenty-first transistor, where j is an integer greater than or equal to 1 and less than or equal to i; The third sub-multiplexing circuit connecting the sub-pixel in column h of the pixel island in column j within the (m+n)th partition and the sub-pixel in column (h+k / 4) includes a 22nd transistor, a 23rd transistor, a 24th transistor, a 25th transistor, and a 26th transistor; The fourth sub-multiplexing circuit connecting the sub-pixel in the h-th column of the pixel island in the j-th column of the m-th partition and the sub-pixel in the h-th column of the pixel island in the j-th (m+n)-th partition includes a twenty-seventh transistor; The fourth sub-multiplexing circuit connecting the sub-pixel in the (h+k / 4)th column of the pixel island in the m-th partition and the sub-pixel in the (h+k / 4)th column of the pixel island in the (m+n)-th partition includes a twenty-eighth transistor; wherein, The gate of the seventeenth transistor is electrically connected to the seventeenth control signal terminal, the first terminal of the seventeenth transistor is electrically connected to the second terminal of the eighteenth transistor, and the second terminal of the seventeenth transistor is electrically connected to the data line corresponding to the sub-pixel in the h-th column of the pixel island in the m-th partition; The gate of the eighteenth transistor is electrically connected to the eighteenth control signal terminal, and the first terminal of the eighteenth transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the h-th column of the pixel island in the m-th partition; The gate of the nineteenth transistor is electrically connected to the nineteenth control signal terminal, the first terminal of the nineteenth transistor is electrically connected to the second terminal of the twentieth transistor, and the second terminal of the nineteenth transistor is electrically connected to the data line corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the mth partition. The gate of the twentieth transistor is electrically connected to the twentieth control signal terminal, and the first terminal of the twentieth transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the mth partition; The gate of the 21st transistor is electrically connected to the 21st control signal terminal, the first terminal of the 21st transistor is electrically connected to the second terminal of the 20th transistor, and the second terminal of the 21st transistor is electrically connected to the second terminal of the 18th transistor. The gate of the 22nd transistor is electrically connected to the 22nd control signal terminal, the first terminal of the 22nd transistor is electrically connected to the second terminal of the 23rd transistor, and the second terminal of the 22nd transistor is electrically connected to the data line corresponding to the sub-pixel in the h-th column of the pixel island in the (m+n)th partition; The gate of the 23rd transistor is electrically connected to the 23rd control signal terminal, and the first terminal of the 23rd transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the h-th column of the pixel island in the m-th partition; The gate of the 24th transistor is electrically connected to the 24th control signal terminal, the first terminal of the 24th transistor is electrically connected to the second terminal of the 25th transistor, and the second terminal of the 24th transistor is electrically connected to the data line corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the mth partition. The gate of the 25th transistor is electrically connected to the 25th control signal terminal, and the first terminal of the 25th transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the mth partition; The gate of the 26th transistor is electrically connected to the 26th control signal terminal, the first terminal of the 26th transistor is electrically connected to the second terminal of the 25th transistor, and the second terminal of the 26th transistor is electrically connected to the second terminal of the 23rd transistor. The gate of the 27th transistor is electrically connected to the 27th control signal terminal, the first terminal of the 27th transistor is electrically connected to the operational amplifier corresponding to the sub-pixel of the h-th column of the pixel island in the (m+n)th partition, and the second terminal of the 27th transistor is electrically connected to the operational amplifier corresponding to the sub-pixel of the h-th column of the pixel island in the j-th partition; The gate of the 28th transistor is electrically connected to the 28th control signal terminal, the first terminal of the 28th transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the (m+n)th partition, and the second terminal of the 28th transistor is electrically connected to the operational amplifier corresponding to the sub-pixel in the (h+k / 4)th column of the pixel island in the (m)th partition.

16. A driving method for a display substrate as described in any one of claims 1 to 15, wherein, include: In multiplexing mode, the control multiplexing circuit turns on one data line electrically connected to it and disconnects the other data lines electrically connected to it, so that the data signals output by at least two operational amplifiers can be provided to the sub-pixels in the same column electrically connected to the data lines through the turned-on multiplexing circuit and the data lines. In non-multiplexing mode, all data lines electrically connected to the control multiplexing circuit are disconnected to provide the data signals output by each operational amplifier to each column of sub-pixels electrically connected to each operational amplifier.

17. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 15.

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