Uncooled infrared detector imaging and thermal time constant testing system and method

Abstract

The application provides a non-refrigeration type infrared detector imaging and thermal time constant testing system and method, and the system comprises: a case, an FPGA board, a power supply board module, a non-refrigeration type infrared detector, a chopper and a surface source radiation blackbody; the FPGA board and the power supply module are arranged in the case; the chopper is arranged between the detector and the surface source radiation blackbody, and the surface source radiation blackbody, the chopper and the detector are located on the same horizontal line; the chopper is used for generating signals with different frequencies, and the surface source radiation blackbody is used for providing a light source for the detector; the FPGA board is connected with the non-refrigeration type infrared detector, and is used for generating a detector driving signal and receiving image data collected by the detector; and an upper computer processes the collected image data to obtain a thermal time constant. When collecting images, two independent fifos are used to buffer odd rows and even rows, and the images can be directly output by rows, so that additional on-board buffering is not needed, and resources are saved.

Description

Technical Field

[0001] This invention belongs to detector imaging testing technology, specifically a system and method for imaging and thermal time constant testing of an uncooled infrared detector. Background Technology

[0002] With the rapid development of science and technology, especially in microelectronics and optoelectronics, a wide variety of infrared devices have emerged and found extensive applications in both civilian and military fields. Since different objects emit specific infrared radiation bands, this characteristic allows people to identify and detect objects by determining specific infrared radiation bands. Infrared detection technology is the technique of detecting invisible infrared radiation and converting it into a measurable signal.

[0003] In recent years, the rapid development of semiconductor manufacturing technology has led to a continuous increase in demand, which in turn has driven the rapid development of uncooled infrared focal plane detector technology. Although its sensitivity is still somewhat lacking compared to cooled infrared detectors, its advantages over cooled infrared detectors lie in its lower cost, lower power consumption, lighter weight, smaller size, and faster start-up and stabilization speed. Therefore, it has a wider range of applications and development space. Precisely because of its better development prospects and space, the future development of this technology is more likely to be promoted. At the same time, because uncooled infrared focal plane detector technology has low cost, its price is relatively cheap, which can also meet the urgent needs of civilian infrared systems and some large-scale military infrared systems.

[0004] Uncooled infrared focal plane array (FLAS) detector technology has sparked a new revolution in infrared technology, with broad applications and promising prospects in both military and civilian fields. For any technology, testing and verification techniques are often an indispensable component of the design and manufacturing process. Therefore, the corresponding testing and verification technologies for uncooled infrared FLAS detectors have extremely important implications and practical value for future design improvements and application development research of focal plane arrays.

[0005] Foreign manufacturers of infrared detector testing systems have widely applied their infrared detector testing methods in military and civilian fields, and have gained widespread recognition from users. However, due to the sensitivity of infrared detection technology and the importance of testing systems for the development of infrared detectors, and because most manufacturers impose export restrictions on China, the few testing systems or equipment that can be exported to China also suffer from problems such as high prices and inconvenient maintenance.

[0006] Several domestic infrared detector manufacturers and related research institutes have also successively carried out research on infrared detector testing systems. They have designed and developed practical testing systems adapted to their own products and have promoted their application to some extent. However, compared with foreign products, there are still some gaps in terms of the degree of automation, stability, and accuracy of the testing systems. Summary of the Invention

[0007] To address the aforementioned technical deficiencies in the prior art, this invention proposes an uncooled infrared detector imaging and testing system.

[0008] The technical solution to achieve the purpose of this invention is: an imaging and thermal time constant testing system for an uncooled infrared detector, comprising: a chassis, an FPGA board, a power board module, an uncooled infrared detector, a chopper, and a surface source blackbody.

[0009] The FPGA board and power module are housed inside the chassis.

[0010] The chopper is positioned between the detector and the surface source blackbody, and the surface source blackbody, the chopper, and the center of the detector are located on the same horizontal line. The chopper is used to generate signals at different frequencies, and the surface source blackbody is used to provide a light source for the detector.

[0011] The FPGA board is connected to the uncooled infrared detector and is used to generate detector drive signals and receive image data acquired by the detector.

[0012] The host computer processes the acquired image data to obtain the thermal time constant.

[0013] Preferably, the uncooled infrared detector is mounted on the detector interface board, and is connected to the FPGA board via a differential signal connector mounted on the detector interface board and a connector on the FPGA board, thereby realizing the connection between the FPGA board and the uncooled infrared detector.

[0014] Preferably, the detector interface board has a detector clamp in the middle for fixing the detector and connecting the detector to the interface board, two 68-pin differential signal interfaces on the left and right sides for connecting to the connector and then transmitting data with the FPGA board, and power connectors at the top and bottom of the interface board.

[0015] Preferably, the uncooled infrared detector operates at a frame rate of 25Hz and a resolution of 1280*1024. The main clock of the uncooled infrared detector is 162MHz. The pixel data is converted into digital signals by the on-chip A / D conversion module and output in a serial manner in four-channel LVDS differential form, accompanied by one differential clock signal.

[0016] Preferably, the FPGA board has a built-in Kintex-7 FPGA chip.

[0017] Preferably, the power supply board is a programmable power supply board that provides the detector with a 3.6V analog power supply, a 1.8V digital power supply, and a 3.6V to 10V bias power supply.

[0018] Preferably, image data is acquired at different chopping frequencies, namely 0Hz, 2Hz, 4Hz, 6Hz, 8Hz, 10Hz, and 12Hz.

[0019] This invention also proposes a method for imaging and thermal time constant testing of an uncooled infrared detector, the specific steps of which are as follows:

[0020] Step 1: Turn on the blackbody radiation source and tune the chopper to a specific frequency;

[0021] Step 2: Write I using Verilog code 2 The C detector is configured with a driver program, and an EDF netlist file is generated. The host computer on the chassis calls the EDF netlist file through the LabVIEW platform to generate the detector configuration driver IP core. This function program is written into the FPGA board. The FPGA board uses the detector configuration driver IP core to drive the detector and transmits the drive signal to the detector through the detector interface board.

[0022] Step 3: The infrared detector receives the drive signal, acquires infrared images, and generates digital image data, which is then sent to the FPGA board through the interface board.

[0023] Step 4: The FPGA board restores the collected data according to odd and even rows;

[0024] Step 5: The FPGA board buffers the odd and even rows of image data in two FIFOs respectively, and outputs them row by row in odd and even order.

[0025] Step 6: The host computer acquires and saves 100 consecutive frames of image data output by the FPGA board;

[0026] Step 7: The host computer reads the saved image through the thermal time constant test program, takes the pixel values ​​of 100 frames of images at a certain point and stores them in an array, and performs Fourier transform on the 100 sets of data to restore the response value at the corresponding chopping frequency.

[0027] Step 8: Change the modulation frequency of the chopper to 0Hz, 2Hz, 4Hz, 6Hz, 8Hz, 10Hz, and 12Hz, and repeat the above steps to obtain 7 sets of response values ​​corresponding to different response frequencies. Fit the obtained 7 sets of data to obtain the frequency response curve, and extract it. The cutoff frequency corresponding to the location is used to calculate the thermal time constant according to the formula, and then displayed on the front panel of the host computer.

[0028] Compared with the prior art, the present invention has the following significant advantages: (1) The present invention uses an FPGA board to drive the detector and acquire data, and the NI system host computer saves the image data and performs tests, realizing the integration of detector imaging and testing. It can measure the thermal time constant in real time after the detector acquires the image. The operation interface written in LabVIEW is simple to operate and highly automated. (2) When acquiring images, the present invention uses two independent FIFOs to buffer the odd and even rows and outputs them directly row by row, which eliminates the need for additional onboard buffers and saves resources.

[0029] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0030] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0031] Figure 1 This is a structural block diagram of the uncooled infrared detector imaging and testing system of the present invention.

[0032] Figure 2 This is a diagram showing the connection of the imaging and testing system equipment for the uncooled infrared detector imaging and testing system of the present invention.

[0033] Figure 3 This is a flowchart of the image acquisition process for the uncooled infrared detector imaging and testing system of the present invention.

[0034] Figure 4 This is an image data reconstruction and analysis diagram of the uncooled infrared detector imaging and testing system of the present invention.

[0035] Figure 5 This is a structural diagram of the detector interface board of the uncooled infrared detector imaging and testing system of the present invention.

[0036] Figure 6 This is a structural diagram of the detector fixture for the uncooled infrared detector imaging and testing system of the present invention.

[0037] Figure 7 This is the front panel of the host computer test software for the uncooled infrared detector camera test system of the present invention. Detailed Implementation

[0038] It is readily understood that, based on the technical solution of this invention, various embodiments of the invention can be conceived by those skilled in the art without altering the essential spirit of the invention. Therefore, the following detailed embodiments and accompanying drawings are merely illustrative examples of the technical solution of this invention and should not be considered as the entirety of the invention or as limitations or restrictions on the technical solution of this invention. Rather, these embodiments are provided to enable those skilled in the art to gain a more thorough understanding of the invention. Preferred embodiments of the invention are described below in conjunction with the accompanying drawings, which form part of this application and, together with the embodiments of the invention, serve to illustrate the innovative concept of the invention.

[0039] The present invention is conceived as an imaging and thermal time constant testing system for an uncooled infrared detector, comprising: a chassis, an FPGA board, a power supply board module, an uncooled infrared detector, a chopper, and a surface source blackbody.

[0040] The FPGA board and power module are housed inside the chassis.

[0041] The chopper is positioned between the detector and the surface source blackbody, and the surface source blackbody, the chopper, and the center of the detector are located on the same horizontal line. The chopper is used to generate signals at different frequencies, and the surface source blackbody is used to provide a light source for the detector.

[0042] The FPGA board is connected to the uncooled infrared detector and is used to generate detector drive signals and receive image data acquired by the detector.

[0043] The host computer processes the acquired image data to obtain the thermal time constant.

[0044] Combination Figure 2 and Figure 3 An uncooled infrared detector imaging and thermal time constant testing method, the specific steps of which are as follows:

[0045] Step 1: The host computer controls the power supply module to provide the detector interface board with a 3.6V analog power supply, a 1.8V digital power supply, and a 3.6V~10V bias power supply.

[0046] The blackbody radiation source is activated, and the chopper is adjusted to a specific frequency. The blackbody radiation source used in this invention is a surface source blackbody.

[0047] Step 2: Write I using Verilog code 2 C detector configuration driver, implementing I through state machine 2The steps of starting the C signal, writing the device address, writing the register address, and writing the data are performed sequentially, and the configuration information is written into a self-built lookup table. This function is then coded into an EDF netlist file using RTL code. The host computer in the chassis calls the EDF netlist file to generate the detector configuration driver IP core. This function program is written to the FPGA board, which uses the detector configuration driver IP core to drive the detector. Drive signals are transmitted to the detector through the detector interface board. The FPGA board used in this invention has a built-in Kintex-7 FPGA chip, and its interface requires a differential signal connector to achieve data input and output. Through the written I... 2 The C register configures the IP core, outputs the corresponding initialization configuration information to the detector, and completes the driving of the detector container;

[0048] Step 3: The infrared detector receives the drive signal, acquires infrared images, and generates digital image data. The differential data connectors at both ends of the interface board are connected via differential data lines, thereby sending the image data from four channels, the clock data from one channel, and the frame synchronization data from one channel to the FPGA board. The uncooled infrared detector used in this invention operates at a frame rate of 25Hz and a resolution of 1280*1024. The sensor's main clock is 162MHz. Pixel data is converted into digital signals by the on-chip A / D conversion module and output serially in four-channel LVDS differential format, accompanied by one differential clock signal and one differential frame synchronization signal. The detector outputs 16-bit wide pixel values ​​at a clock speed of 50MHz.

[0049] After receiving the drive signal and completing parameter configuration, the infrared detector generates a 16-bit random number 'a' and stores it in a register. The FPGA board reads the data at that register address and calculates a key value 'key'. The calculation formula is as follows:

[0050] b = a × 2 16 +a×2 10 +a×2 4 +1

[0051] key = b / 4

[0052] The calculated 32-bit configuration key is written into the corresponding register address of the detector via the FPGA board. After waiting for 100ms, the data in the register address of the decryption result is read. If the read data bit is 1, it means that the key verification is complete, and image data and frame synchronization signals are collected.

[0053] Step 4: The FPGA board processes the received image data from the four channels according to... Figure 3The data is restored using the following method: for channels A and B, the first eight bits of each 16-bit data are interleaved to obtain the first 16-bit data for odd-numbered rows, and the last eight bits are interleaved to obtain the second 16-bit data for odd-numbered rows. For channels C and D, the first eight bits of each 16-bit data are interleaved to obtain the first 16-bit data for even-numbered rows, and the last eight bits are interleaved to obtain the second 16-bit data for even-numbered rows, and so on, to restore the image data for even-numbered rows. At the beginning of each row, the data transmission channel outputs a specific identifier 1010_0000, which, after interleaving, is displayed as a hexadecimal flag of 0xcc00.

[0054] Step 5: The FPGA board buffers the odd and even rows of the reconstructed image data using two FIFOs respectively, and sets up a counter to count the number of rows. The read / write validity time of the FIFOs is determined based on the row synchronization signal and the frame synchronization signal. The last bit of the counter's binary value indicates whether it's an odd or even row. When the frame synchronization limit signal is high, row synchronization is valid, and the last bit of the counter is 0, a row of data is written to the odd-row FIFO; when the frame synchronization limit signal is high, row synchronization is valid, and the last bit of the counter is 0, a row of data is written to the even-row FIFO. The read enable of the odd-row and even-row FIFOs is sequentially pulled high according to the odd / even row flag. When the buffer in the FIFO is greater than one row of data, data transmission to the host computer begins. The host computer saves the 100 consecutive frames of images acquired.

[0055] Step 6: The host computer acquires and saves 100 consecutive frames of image data output by the FPGA board;

[0056] Step 7: The host computer reads the saved image through the thermal time constant test program, takes the pixel values ​​of 100 frames of images at a certain point and stores them in an array, and performs Fourier transform on the 100 sets of data to restore the response value at the corresponding chopping frequency.

[0057] Step 8: Change the chopper modulation frequency to 0Hz, 2Hz, 4Hz, 6Hz, 8Hz, 10Hz, and 12Hz, and repeat the steps 1-5 above. Save the 100 frames of image data obtained under each of the 7 chopper modulation frequencies.

[0058] A LabVIEW-based host computer test program processes 100 frames of images in a loop. It sets the extraction range, extracts a 3×3 pixel region at the center of each image, and stores it sequentially into an array. The average value of the extracted pixel values ​​is calculated by iteratively summing and then dividing by the total number of pixels. A shift register is used to store the average pixel value of each frame into another array, resulting in a pixel average sampling array containing 100 pixel values. An FFT transformation is performed on the 100 pixel data in the array to reconstruct the detector response value at the given chopping frequency. This process is repeated for seven groups of images modulated at different frequencies, reconstructing the response values ​​at different chopping frequencies, and storing the response values ​​and their corresponding frequency values ​​in two separate arrays. Curve fitting is then performed on the obtained detector response frequencies and values ​​to generate a frequency response curve. The maximum value of the response curve is then selected. The frequency corresponding to the location is taken as the cutoff frequency f.

[0059] The thermal time constant can be calculated from the cutoff frequency f, as shown in the following formula:

[0060] τ=1 / 2πf

[0061] The thermal time constant is calculated on the host computer according to the formula and displayed on the front panel to complete the test.

[0062] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

[0063] It should be understood that, in order to simplify the present invention and help those skilled in the art understand its various aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes described in a single embodiment or with reference to a single figure. However, the present invention should not be construed as including all features in the exemplary embodiments as essential technical features of the claims of this patent.

[0064] It should be understood that the modules, units, components, etc., included in the device of one embodiment of the present invention can be adaptively changed to be placed in a device different from that embodiment. Different modules, units, or components included in the device of the embodiment can be combined into a single module, unit, or component, or they can be divided into multiple sub-modules, sub-units, or sub-components.

Claims

1. A thermal time constant testing system based on imaging of uncooled infrared detectors, characterized in that, The application relates to a non-cooled infrared detector test system. The system comprises a case, an FPGA board, a power supply board module, a non-cooled infrared detector, a chopper and a surface source radiation blackbody. The FPGA board and the power supply module are arranged in the case. The chopper is arranged between the detector and the surface source radiation blackbody, and the surface source radiation blackbody, the chopper and the detector are located on the same horizontal line. The FPGA board is connected with the non-cooled infrared detector and is used for generating a detector driving signal and receiving image data collected by the detector. The infrared detector receives the driving signal, collects infrared images and generates digital image data. The differential data connectors at two ends of the interface board are connected with the connectors through differential data lines, so that four-channel image data, one-channel clock data and one-channel frame synchronization data are sent into the FPGA board. An upper computer processes the collected image data to obtain a thermal time constant. The upper computer collects and saves 100 continuous frames of image data output by the FPGA board. The upper computer reads the saved pictures through a thermal time constant test program, stores pixel values of 100 frames of images at a certain point in an array, carries out Fourier transform on the 100 groups of data, restores response values corresponding to different chopping frequencies, changes the modulation frequency of the chopper to 0Hz, 2Hz, 4Hz, 6Hz, 8Hz, 10Hz and 12Hz, repeats the above steps, obtains response values corresponding to seven groups of different response frequencies, carries out fitting on the obtained seven groups of data, obtains a frequency response curve, takes a corresponding cut-off frequency f at 1 / 2, calculates the thermal time constant according to the formula tau=1 / 2pi f, and displays the thermal time constant on a front panel of the upper computer. The non-cooled infrared detector works in a working state with a frame frequency of 25Hz and a resolution of 1280*1024. The main clock of the non-cooled infrared detector is 162MHz. Pixel data is converted into digital signals by an A / D conversion module on the chip and is output in a four-way LVDS differential form in a serial mode. A differential clock signal is accompanied.

2. The thermal time constant test system based on non-cooled infrared detector imaging of claim 1, wherein, The non-cooled infrared detector is arranged on the detector interface board and is connected with the connector on the FPGA board card through the differential signal connector arranged on the detector interface board, so that the FPGA board card is connected with the non-cooled infrared detector.

3. The thermal time constant test system based on non-cooled infrared detector imaging of claim 2, wherein, The middle of the detector interface board is a detector clamp for fixing the detector and connecting the detector with the interface board, the left and right sides are two 68-pin differential signal interfaces for being connected with the connector and then transmitting data with the FPGA board card, and the upper and lower ends of the interface board are power connectors.

4. The thermal time constant test system based on non-cooled infrared detector imaging of claim 1, wherein, The FPGA board card is built-in Kintex-7 FPGA chip.

5. The thermal time constant test system based on non-cooled infrared detector imaging of claim 1, wherein, The power board card is a programmable power board card, which provides 3.6V analog power, 1.8V digital power and 3.6V-10V bias power for the detector.

6. A method for testing thermal time constant based on imaging of uncooled infrared detectors, characterized in that, The steps are as follows: Step 1, start the blackbody radiation source, and adjust the chopper arranged between the detector and the surface source radiation blackbody to the set frequency; Step 2, use Verilog code to write I 2 The C detector configuration driver generates an edf netlist file, the host computer on the chassis calls the edf netlist file through the Labview platform to generate a detector configuration driving IP core, writes a function program into the FPGA board card, and the FPGA board card drives the detector using the detector configuration driving IP core to transmit a driving signal to the detector through the detector interface board. Step 3, the infrared detector receives the driving signal, collects the infrared image, and generates digital image data, which is sent to the FPGA board card through the interface board; four channel image data, one channel clock data and one channel frame synchronization data are sent to the FPGA board card through the differential signal connector arranged on the detector interface board and the connector on the FPGA board card; Step 4, the FPGA board card restores the collected data according to odd and even rows, specifically: the detector outputs four channels of data, the first 16 bits of data of each 16 bits of channel 1 and channel 2 are cross-arranged to obtain the first 16bit data of the odd row, and the second 16bit data of the odd row is cross-arranged, the first 16bit data of each 16 bits of channel 3 and channel 4 is cross-arranged to obtain the first 16bit data of the even row, and the second 16bit data of the even row is cross-arranged, and so on, the image data of the even row and the even row is restored, and a set identifier 1010_0000 is output at the beginning of each row, and the hexadecimal mark displayed after cross-arrangement is 0xcc00, indicating the beginning of a row of data; Step 5, the FPGA board card buffers the odd and even row image data in two FIFOs respectively, and outputs them in turn according to the odd-even order; Step 6, the host computer collects and saves 100 frames of image data output by the FPGA board card; Step 7, the host computer reads the saved pictures through the thermal time constant test program, stores the pixel values of 100 frames of images at a certain point in an array, and performs Fourier transform on the 100 groups of data to restore the response value under the corresponding chopping frequency; Step 8, change the modulation frequency of the chopper to 0Hz, 2Hz, 4Hz, 6Hz, 8Hz, 10Hz, 12Hz, repeat the contents in the above steps, obtain 7 groups of response values corresponding to different response frequencies, fit the 7 groups of data obtained, obtain the frequency response curve, take out the corresponding cut-off frequency f at 1 / 2, and calculate the thermal time constant according to the formula τ=1 / 2πf, and display it on the front panel of the host computer.

7. The thermal time constant test method based on non-cooled infrared detector imaging according to claim 6, characterized in that, The specific process of obtaining the thermal time constant is as follows: Image reading: Through the Labview loop structure cycle 100 times, read the saved 100 frames of images collected at each frequency in sequence, and through the addition of image conversion array function module, set the extraction range, extract the pixel value of the 3*3 region of the image and store it in the array; Solving the pixel mean: the pixel value array of the extracted pixel points is averaged, define an initial empty array, add a loop structure, and add a register in the loop structure, the elements in the array enter the loop body one by one, and are added up one by one. After the loop ends, the output cumulative sum is output with the number of elements in the array, and the pixel mean value is obtained. For each frame of picture, a pixel mean value is solved and stored in an empty array. After 100 times of loop, a sampling array containing the pixel mean values of 100 frames of images is obtained; Fourier transform: the acquisition frequency is set to 25Hz, the data length is 100, the pixel mean value sampling array obtained in the last step is subjected to fast Fourier transform by FFT conversion function, the maximum value max_data is extracted from the restored function, and the horizontal coordinate is scanned by loop. When the corresponding vertical coordinate value is equal to max_data, the horizontal coordinate corresponds to the response frequency, and the vertical coordinate corresponds to the response value. The horizontal coordinate and the vertical coordinate are stored in two empty arrays respectively, the chopper frequency is changed to obtain the response frequency and response value under different modulation frequencies, and they are stored in the array in turn to obtain two groups of data. Thermal time constant test solving: the response frequency and response value are fitted to obtain the frequency response curve of the detector. Through the loop body, the numerical value is compared to obtain the horizontal coordinate corresponding to 1 / 2 of the maximum value of the curve, which is the cut-off frequency f. According to the relationship between cut-off frequency f and time constant: τ = 1 / (2πf), the time constant is calculated and displayed on the front panel.

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