Detection circuit and its driving method, ultrasonic detection array panel

Abstract

This disclosure provides a detection circuit and its driving method, as well as an ultrasonic detection array panel, belonging to the field of ultrasonic testing technology. The detection circuit includes a voltage sensing module, a current conversion module, and an energy storage capacitor. The voltage sensing module is configured to write the sensing voltage generated by the transducer element in response to the ultrasonic echo signal into a first terminal of the energy storage capacitor. The current conversion module has a driving transistor and is capable of writing the threshold voltage of the driving transistor into a second terminal of the energy storage capacitor. The driving transistor is configured to output a sensing current based on the voltage at the second terminal of the energy storage capacitor. This detection circuit can improve testing accuracy and image quality.

Description

Technical Field

[0001] This disclosure relates to the field of ultrasonic testing technology, and more specifically, to a detection circuit and its driving method, and an ultrasonic testing array panel. Background Technology

[0002] Currently, due to manufacturing process issues, the threshold voltage of the driving transistors in ultrasonic imaging pixel arrays is not uniform, resulting in significant differences in the output signals between different pixels under the same excitation. This leads to differences in the receiving sensitivity between different pixels, which seriously affects the test accuracy and image quality.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a detection circuit and its driving method, an ultrasonic detection array panel, to improve testing accuracy and image quality.

[0005] According to a first aspect of this disclosure, a detection circuit is provided, including a voltage sensing module, a current conversion module, and an energy storage capacitor;

[0006] The voltage sensing module is configured to write the sensing voltage generated by the transducer element in response to the ultrasonic echo signal into the first terminal of the energy storage capacitor.

[0007] The current conversion module has a driving transistor and is capable of writing the threshold voltage of the driving transistor to the second terminal of the energy storage capacitor; the driving transistor is configured to output a sensing current based on the voltage at the second terminal of the energy storage capacitor.

[0008] According to one embodiment of this disclosure, the voltage sensing module includes:

[0009] A biasing unit is configured to apply a bias voltage to a first node in response to a bias control signal; the first node is electrically connected to one end of the transducer element.

[0010] The write unit is configured to electrically connect the first node and the first terminal of the energy storage capacitor in response to a write control signal.

[0011] According to one embodiment of the present disclosure, the bias unit includes a bias transistor, the gate of the bias transistor is used to load the bias control signal, the source of the bias transistor is used to load the bias voltage, and the drain of the bias transistor is electrically connected to the first node.

[0012] The writing unit includes a writing transistor, the gate of which is used to load the writing control signal, the source of which is electrically connected to the first node, and the drain of which is electrically connected to the first terminal of the energy storage capacitor.

[0013] According to one embodiment of this disclosure, the current conversion module further includes a scanning control unit, a threshold compensation unit, and a path control unit;

[0014] The gate of the driving transistor is electrically connected to the second terminal of the energy storage capacitor, the source of the driving transistor is electrically connected to the second node, and the drain of the driving transistor is electrically connected to the third node.

[0015] The scanning control unit is configured to electrically connect the third node and the output terminal of the detection circuit in response to a scanning signal;

[0016] The threshold compensation unit is configured to electrically connect the second node and the second terminal of the energy storage capacitor in response to a path control signal.

[0017] The path control unit is configured to apply a drive power supply voltage to the second node in response to a compensation control signal.

[0018] According to one embodiment of this disclosure, the scanning control unit includes a scanning transistor, the gate of which is used to load the scanning signal, the source of which is electrically connected to the third node, and the drain of which is electrically connected to the output terminal of the detection circuit.

[0019] The threshold compensation unit includes a threshold compensation transistor, the gate of which is used to load the path control signal, the source of which is electrically connected to the second node, and the drain of which is electrically connected to the second terminal of the energy storage capacitor.

[0020] The path control unit includes a path control transistor, the gate of which is used to load the compensation control signal, the source of which is used to load the drive power supply voltage, and the drain of which is electrically connected to the second node.

[0021] According to one embodiment of this disclosure, the current conversion module further includes a scanning control unit, a threshold compensation unit, and a path control unit;

[0022] The gate of the driving transistor is electrically connected to the second terminal of the energy storage capacitor, the source of the driving transistor is electrically connected to the second node, and the drain of the driving transistor is electrically connected to the third node.

[0023] The scanning control unit is configured to apply a drive power supply voltage to the second node in response to a scanning signal;

[0024] The threshold compensation unit is configured to electrically connect the second node and the second terminal of the energy storage capacitor in response to a path control signal.

[0025] The pathway control unit is configured to electrically connect the third node and the output of the detection circuit in response to a compensation control signal.

[0026] According to one embodiment of this disclosure, the scan control unit includes a scan transistor, the gate of the scan transistor is used to load the scan signal, the source of the scan transistor is used to load the driving power supply voltage, and the drain of the scan transistor is electrically connected to the second node.

[0027] The threshold compensation unit includes a threshold compensation transistor, the gate of which is used to load the path control signal, the source of which is electrically connected to the second node, and the drain of which is electrically connected to the second terminal of the energy storage capacitor.

[0028] The path control unit includes a path control transistor, the gate of which is used to load the compensation control signal, the source of which is electrically connected to the third node, and the drain of which is electrically connected to the output of the detection circuit.

[0029] According to one embodiment of this disclosure, the current conversion module further includes a scanning control unit and a threshold compensation unit; the gate of the driving transistor is electrically connected to the second terminal of the energy storage capacitor, the source of the driving transistor is electrically connected to the second node, and the drain of the driving transistor is electrically connected to the output terminal of the detection circuit.

[0030] The scanning control unit is configured to apply a drive power supply voltage to the second node in response to a scanning signal;

[0031] The threshold compensation unit is configured to electrically connect the second node and the second terminal of the energy storage capacitor in response to a path control signal.

[0032] According to one embodiment of this disclosure, the scan control unit includes a scan transistor, the gate of the scan transistor is used to load the scan signal, the source of the scan transistor is used to load the driving power supply voltage, and the drain of the scan transistor is electrically connected to the second node.

[0033] The threshold compensation unit includes a threshold compensation transistor, the gate of which is used to load the path control signal, the source of which is electrically connected to the second node, and the drain of which is electrically connected to the second terminal of the energy storage capacitor.

[0034] According to a second aspect of this disclosure, a driving method for a detection circuit is provided, applied to the aforementioned detection circuit; the driving method includes:

[0035] During the transmission phase, the current conversion module is driven so that the threshold voltage of the driving transistor is written to the second terminal of the energy storage capacitor; the voltage sensing module is driven so that the first terminal of the energy storage capacitor remains in a reset state.

[0036] During the sampling phase, the voltage sensing module is driven so that the sensing voltage generated by the transducer element is written to the first terminal of the energy storage capacitor, thereby allowing the sensing voltage to be written to the second terminal of the energy storage capacitor through a coupling effect.

[0037] During the readout phase, the current conversion module is driven so that the driving transistor outputs a sense current based on the voltage at the second terminal of the energy storage capacitor.

[0038] According to one embodiment of this disclosure, the voltage sensing module includes a bias unit and a write unit; the bias unit is configured to apply a bias voltage to a first node in response to a bias control signal; the first node is electrically connected to one end of the transducer element; the write unit is configured to make electrical conduction between the first node and a first end of the energy storage capacitor in response to a write control signal.

[0039] The step of driving the voltage sensing module during the sampling phase so that the sensing voltage generated by the transducer element is written into the first terminal of the energy storage capacitor includes:

[0040] During the sampling phase, a bias voltage is applied to the bias unit, and the bias control signal and the write control signal are also applied to the bias unit.

[0041] At the end of the sampling phase, the bias control signal and the write control signal are no longer loaded into the bias unit.

[0042] According to one embodiment of this disclosure, the current conversion module includes a driving transistor, a scan control unit, a threshold compensation unit, and a path control unit; the gate of the driving transistor is electrically connected to the second terminal of the energy storage capacitor, the source of the driving transistor is electrically connected to a second node, and the drain of the driving transistor is electrically connected to a third node; the scan control unit is configured to, in response to a scan signal, electrically connect the third node to the output terminal of the detection circuit; the threshold compensation unit is configured to, in response to a path control signal, electrically connect the second node to the second terminal of the energy storage capacitor; the path control unit is configured to, in response to a compensation control signal, apply a driving power supply voltage to the second node;

[0043] The step of driving the current conversion module during the emission phase to write the threshold voltage of the driving transistor to the second terminal of the energy storage capacitor includes:

[0044] In the first sub-phase of the launch phase, the path control signal is loaded to the threshold compensation unit and the compensation control signal is loaded to the path control unit so that the drive power supply voltage is applied to the second terminal of the energy storage capacitor.

[0045] In the second sub-phase of the launch phase, the path control signal is loaded to the threshold compensation unit and the scan signal is loaded to the scan control unit, so that the second terminal of the energy storage capacitor discharges to the turn-off of the drive transistor.

[0046] The step of driving the current conversion module during the readout phase so that the driving transistor outputs a sense current based on the voltage at the second terminal of the energy storage capacitor includes:

[0047] During the readout phase, the compensation control signal is loaded to the path control unit and the scan signal is loaded to the scan control unit.

[0048] According to one embodiment of this disclosure, the current conversion module includes a driving transistor, a scan control unit, a threshold compensation unit, and a path control unit; the gate of the driving transistor is electrically connected to the second terminal of the energy storage capacitor, the source of the driving transistor is electrically connected to a second node, and the drain of the driving transistor is electrically connected to a third node; the scan control unit is configured to apply a driving power supply voltage to the second node in response to a scan signal; the threshold compensation unit is configured to conduct electricity between the second node and the second terminal of the energy storage capacitor in response to a path control signal; the path control unit is configured to conduct electricity between the third node and the output terminal of the detection circuit in response to a compensation control signal.

[0049] The step of driving the current conversion module during the emission phase to write the threshold voltage of the driving transistor to the second terminal of the energy storage capacitor includes:

[0050] In the first sub-phase of the launch phase, the path control signal is loaded to the threshold compensation unit and the scan signal is loaded to the scan control unit, so that the drive power supply voltage is applied to the second terminal of the energy storage capacitor;

[0051] In the second sub-phase of the launch phase, the path control signal is loaded to the threshold compensation unit and the compensation control signal is loaded to the path control unit, so that the second terminal of the energy storage capacitor discharges to the point where the driving transistor is turned off.

[0052] The step of driving the current conversion module during the readout phase so that the driving transistor outputs a sense current based on the voltage at the second terminal of the energy storage capacitor includes:

[0053] During the readout phase, the compensation control signal is loaded to the path control unit and the scan signal is loaded to the scan control unit.

[0054] According to one embodiment of this disclosure, the current conversion module includes a driving transistor, a scan control unit, and a threshold compensation unit; the gate of the driving transistor is electrically connected to the second terminal of the energy storage capacitor, the source of the driving transistor is electrically connected to the second node, and the drain of the driving transistor is electrically connected to the output terminal of the detection circuit; the scan control unit is configured to apply a driving power supply voltage to the second node in response to a scan signal; the threshold compensation unit is configured to conduct electricity between the second node and the second terminal of the energy storage capacitor in response to a path control signal.

[0055] The step of driving the current conversion module during the emission phase to write the threshold voltage of the driving transistor to the second terminal of the energy storage capacitor includes:

[0056] In the first sub-phase of the launch phase, the path control signal is loaded to the threshold compensation unit and the scan signal is loaded to the scan control unit, so that the drive power supply voltage is applied to the second terminal of the energy storage capacitor;

[0057] In the second sub-phase of the launch phase, the path control signal is loaded onto the threshold compensation unit to cause the second terminal of the energy storage capacitor to discharge until the driving transistor is turned off.

[0058] The step of driving the current conversion module during the readout phase so that the driving transistor outputs a sense current based on the voltage at the second terminal of the energy storage capacitor includes:

[0059] During the readout phase, the scan signal is loaded into the scan control unit.

[0060] According to a third aspect of this disclosure, an ultrasonic detection array panel is provided, including the detection circuit described above and a transducer element electrically connected to the detection circuit.

[0061] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0062] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0063] Figure 1 This is a schematic diagram of the structure of an ultrasonic testing module in one embodiment of the present disclosure.

[0064] Figure 2-1 This is a schematic diagram of the detection unit in one embodiment of the present disclosure.

[0065] Figure 2-2 This is a flowchart illustrating the driving method of the detection circuit in one embodiment of the present disclosure.

[0066] Figure 3 This is a schematic diagram of the detection unit in the first embodiment of this disclosure.

[0067] Figure 4 This is a schematic diagram of the equivalent circuit of the detection unit in the first embodiment of this disclosure.

[0068] Figure 5 This is a schematic diagram of the driving timing of the detection unit in the first embodiment of this disclosure.

[0069] Figure 6 This is a schematic diagram of the detection unit in the first embodiment of this disclosure.

[0070] Figure 7 This is a schematic diagram of the equivalent circuit of the detection unit in the first embodiment of this disclosure.

[0071] Figure 8 This is a schematic diagram of the driving timing of the detection unit in the first embodiment of this disclosure.

[0072] Figure 9 This is a schematic diagram of the detection unit in the first embodiment of this disclosure.

[0073] Figure 10 This is a schematic diagram of the equivalent circuit of the detection unit in the first embodiment of this disclosure.

[0074] Figure 11 This is a schematic diagram of the driving timing of the detection unit in the first embodiment of this disclosure. Detailed Implementation

[0075] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0076] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0077] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0078] A transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), through which current can flow. The channel region is the area where current primarily flows. In cases where transistors with opposite polarities are used or where the direction of current changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" are interchangeable.

[0079] See Figure 1This disclosure provides an ultrasonic testing module, which includes an ultrasonic testing array panel and a driving chip connected to the ultrasonic testing array panel. The ultrasonic testing array panel includes arrayed testing units UU, each testing unit UU including a transducer element EE and a detection circuit PDC electrically connected to the transducer element EE. The transducer element EE can generate a sensing voltage Vx in response to an ultrasonic signal; the detection circuit PDC can output a sensing current Iout based on the sensing voltage Vx. The driving chip includes a data acquisition circuit CC, which can acquire the sensing current Iout. Based on the sensing current Iout output by each testing unit UU, the driving chip can determine the intensity of the ultrasonic signal on each testing unit UU, thereby achieving ultrasonic imaging.

[0080] In one embodiment of this disclosure, see Figure 1 The ultrasonic testing array panel is equipped with data lines DL extending along the column direction and scan lines GL extending along the row direction. The detection circuits PDC of detection units UU arranged in the same row are electrically connected to the same scan line GL. The output of the detection circuits PDC of detection units UU arranged in the same column can be connected to the same data line DL. Each data line DL can be electrically connected to an acquisition circuit CC; for example, multiple data lines DL can be electrically connected to multiple acquisition circuits CC in a one-to-one correspondence. During the readout phase, a scan signal Gate can be sequentially applied to each scan line GL, causing each row of detection circuits PDC to sequentially output a sensing current Iout. The acquisition circuit CC can receive the sensing current Iout from the connected data lines DL. Thus, the ultrasonic testing array panel can make each detection unit UU output a sensing current Iout by scanning row by row.

[0081] Understandably, other wiring or conductive structures can be set in the ultrasonic testing array panel as needed, so that the various signals or voltages required by the testing unit UU can be applied to the testing unit UU.

[0082] In one embodiment of this disclosure, see Figure 2-1 The detection circuit PDC includes a voltage sensing module PA, a current conversion module PB, and an energy storage capacitor CST. The voltage sensing module PA is configured to write the sensing voltage Vx generated by the transducer EE in response to the ultrasonic echo signal into the first terminal of the energy storage capacitor CST. The current conversion module PB has a driving transistor T3 and is capable of writing the threshold voltage of the driving transistor T3 into the second terminal of the energy storage capacitor CST; the driving transistor T3 is configured to output a sensing current Iout based on the voltage at the second terminal of the energy storage capacitor CST.

[0083] In this embodiment, see Figure 2-2 , Figure 5 , Figure 8 and Figure 11 The detection circuit PDC can be driven using the following driving method:

[0084] Step S110: During the transmission phase t1, drive the current conversion module PB so that the threshold voltage of the driving transistor T3 is written to the second terminal of the energy storage capacitor CST; drive the voltage sensing module PA so that the first terminal of the energy storage capacitor CST remains in a reset state.

[0085] In step S120, during the sampling phase t2 after the transmission phase t1, the voltage sensing module PA is driven so that the sensing voltage Vx generated by the transducer element EE is written into the first terminal of the energy storage capacitor CST, thereby allowing the sensing voltage Vx to be written into the second terminal of the energy storage capacitor CST through the coupling effect.

[0086] In step S130, during the readout stage t4 following the sampling stage t2, the current conversion module PB is driven so that the driving transistor T3 outputs the sensing current Iout based on the voltage at the second terminal of the energy storage capacitor CST.

[0087] In the transmission phase, the ultrasonic generator emits an ultrasonic signal Tx. During this phase, the detection circuit PDC can initially perform threshold voltage compensation on the driving transistor T3 of the current conversion module PB, without sampling, so that the threshold voltage of the driving transistor T3 is written to the second terminal of the energy storage capacitor CST. In the sampling phase t2, the detection unit UU samples the echo signal of the ultrasonic signal, and the transducer EE generates a sensing voltage Vx in response to the echo signal. In this sampling phase t2, the transducer EE is electrically connected to the first terminal of the energy storage capacitor CST, allowing the sensing voltage Vx to be written into the first terminal of the energy storage capacitor CST. Under capacitive coupling, the voltage at the second terminal of the energy storage capacitor CST changes synchronously with the voltage at the first terminal, thus also writing the sensing voltage Vx into the second terminal of the energy storage capacitor CST. Afterwards, the ultrasonic detection array panel can enter the holding phase t3, keeping the voltage at the second terminal of the energy storage capacitor CST essentially constant, awaiting readout. During the readout phase t4, the driving transistor T3 outputs a sensing current Iout based on the voltage at the second terminal of the energy storage capacitor CST, thereby amplifying and converting the sensed signal. The voltage at the second terminal of the energy storage capacitor CST is related to the threshold voltage of the driving transistor T3 and the sensed voltage Vx. This ensures that the sensing current Iout output when the driving transistor T3 is turned on is independent of its threshold voltage. This overcomes the problem of poor image quality caused by the non-uniform threshold voltage of the driving transistor T3.

[0088] It is understandable that writing the sensed voltage Vx to the first terminal of the energy storage capacitor CST means that the voltage at the first terminal of the energy storage capacitor CST is positively correlated with the sensed voltage Vx, such as synchronously rising or falling, rather than meaning that the voltage at the first terminal of the energy storage capacitor CST is equal to the sensed voltage Vx. Similarly, writing the threshold voltage of the driving transistor T3 to the second terminal of the energy storage capacitor CST means that the voltage at the second terminal of the energy storage capacitor CST is positively correlated with the threshold voltage of the driving transistor T3, such as synchronously rising or falling, rather than meaning that the voltage at the second terminal of the energy storage capacitor CST is equal to the threshold voltage of the driving transistor T3. In one example, when the threshold voltage Vth of the driving transistor T3 is written to the second terminal of the energy storage capacitor CST, the gate-source voltage of the driving transistor T3 is equal to the threshold voltage Vth of the driving transistor T3.

[0089] In one embodiment of this disclosure, see Figures 3-5 The voltage sensing module PA includes a bias unit U1 and a write unit U2. The bias unit U1 is configured to apply a bias voltage Vbias to a first node N1 in response to a bias control signal Vrst; the first node N1 is electrically connected to one end of the transducer element EE. The write unit U2 is configured to electrically connect the first node N1 and a first end of the energy storage capacitor CST in response to a write control signal Vclose.

[0090] During sampling phase t2, the voltage sensing module PA can be driven to write the sensed voltage Vx generated by the transducer EE to the first terminal of the energy storage capacitor CST, thereby allowing the sensed voltage Vx to be written to the second terminal of the energy storage capacitor CST through a coupling effect. Specifically, during sampling phase t2, the transducer EE and the first terminal of the energy storage capacitor CST are electrically connected for half a cycle of the ultrasonic echo signal. After sampling phase t2 ends, the electrical circuit between the transducer EE and the first terminal of the energy storage capacitor CST is broken.

[0091] Optionally, during the sampling phase t2, a bias voltage Vbias is applied to the bias unit U1, along with the bias control signal Vrst and the write control signal Vclose. Starting at the end of the sampling phase t2, the bias control signal Vrst and the write control signal Vclose are no longer applied to the bias unit U1. Thus, the voltage at the first terminal of the energy storage capacitor CST is the superposition of the bias voltage Vbias and the sensing voltage Vx.

[0092] Optionally, during the transmit phase t1, a bias control signal Vrst is applied to the bias unit U1 and a write control signal Vclose is applied to the write unit U2, while no bias voltage Vbias is applied to the bias unit U1 (i.e., a low-level signal is applied, especially the ground voltage GND). This allows for the reset of the first node N1 and the first terminal of the energy storage capacitor CST; additionally, it maintains the stability of the first terminal of the energy storage capacitor CST, facilitating the writing of the threshold voltage of the driving transistor T3 to the second terminal of the energy storage capacitor CST during the transmit phase t1.

[0093] As an example, the bias unit U1 includes a bias transistor T1, the gate of which is used to load the bias control signal Vrst, the source of which is used to load the bias voltage Vbias, and the drain of which is electrically connected to the first node N1; the write unit U2 includes a write transistor T2, the gate of which is used to load the write control signal Vclose, the source of which is electrically connected to the first node N1, and the drain of which is electrically connected to the first terminal of the energy storage capacitor CST.

[0094] As an exemplary driving method, during the transmit phase t1, the gate of bias transistor T1 is loaded with a bias control signal Vrst to turn on bias transistor T1, while the source of bias transistor T1 is not loaded with a bias voltage Vbias (the source of bias transistor T1 is loaded with a low-level signal instead of a high-level bias voltage Vbias) to reduce power consumption. The gate of write transistor T2 is loaded with a write control signal Vclose to turn on write transistor T2, which makes the first node N1 electrically connected to the first terminal of the energy storage capacitor CST. The first node N1 is electrically connected to one end of the transducer element EE, and the other end of the transducer element EE is used to load the ground voltage GND. At this time, since bias transistor T1 and write transistor T2 remain on, the sensed voltage Vx generated by the transducer element EE is not latched into the first terminal of the energy storage capacitor CST.

[0095] During sampling phase t2, the bias control signal Vrst is applied to the gate of bias transistor T1 to turn it on, and the write control signal Vclose is applied to the gate of write transistor T2 to turn it on. A bias voltage Vbias (high-level signal) is applied to the source of bias transistor T1 to raise the voltage at the first terminal of energy storage capacitor CST. At the cutoff point of sampling phase t2, the voltage at the first terminal of energy storage capacitor CST is approximately equal to Vbias + Vx. Starting at the cutoff point of sampling phase t2, the gate of bias transistor T1 is applied with the inverted voltage of the bias control signal Vrst, and the gate of write transistor T2 is applied with the inverted voltage of the write control signal Vclose, causing bias transistor T1 and write transistor T2 to turn off. At this time, the voltage at the first terminal of energy storage capacitor CST is locked and no longer changes. Correspondingly, the voltage at the second terminal of energy storage capacitor CST is locked along with the first terminal of energy storage capacitor CST, and is approximately Vbias + Vx + Vth.

[0096] During the hold phase t3 following the sampling phase t2, the write transistor T2 remains off, thereby maintaining the voltage at the second terminal of the energy storage capacitor CST. In this example, at the cutoff point of the sampling phase, the source of the bias transistor T1 is not loaded with a high-level bias voltage Vbias, and the bias transistor T1 is also turned off, which helps reduce power consumption.

[0097] It is understood that the above description of the voltage sensing module PA is merely an exemplary embodiment of the voltage sensing module PA, and the driving method of the voltage sensing module PA is also merely an exemplary driving method. In other embodiments of this disclosure, the voltage sensing module PA may employ other structures or other driving methods.

[0098] In one embodiment of this disclosure, the transducer EE is a piezoelectric device, which may include a first electrode, a piezoelectric material layer, and a second electrode stacked sequentially. The first electrode is used to apply a ground voltage GND, and the second electrode is electrically connected to a first node N1. Optionally, the piezoelectric material layer may be a PVDF (polyvinylidene fluoride) layer.

[0099] In one embodiment of this disclosure, see Figures 3-5The current conversion module PB includes a driving transistor T3, a scan control unit U4, a threshold compensation unit U5, and a path control unit U6. The gate of the driving transistor T3 is electrically connected to the second terminal of the energy storage capacitor CST, the source of the driving transistor T3 is electrically connected to the second node N2, and the drain of the driving transistor T3 is electrically connected to the third node N3. The scan control unit U4 is configured to conduct the third node N3 and the output terminal of the detection circuit PDC in response to the scan signal Gate. The threshold compensation unit U5 is configured to conduct the second node N2 and the second terminal of the energy storage capacitor CST in response to the path control signal Rn. The path control unit U6 is configured to apply the driving power supply voltage Vdd to the second node N2 in response to the compensation control signal Sn.

[0100] During the sampling phase t2, the current conversion module PB can be driven as follows:

[0101] In the first sub-stage t11 of the transmission phase t1, the path control signal Rn is loaded to the threshold compensation unit U5 and the compensation control signal Sn is loaded to the path control unit U6, so that the driving power supply voltage Vdd is loaded to the second terminal of the energy storage capacitor CST; thus, the voltage at the second terminal of the energy storage capacitor CST is the driving power supply voltage Vdd.

[0102] In the second sub-stage t12 of the transmission phase t1, the path control signal Rn is loaded into the threshold compensation unit U5 and the scan signal Gate is loaded into the scan control unit U4, so that the second terminal of the energy storage capacitor CST is discharged until the driving transistor T3 is turned off. At this time, the voltage at the second terminal of the energy storage capacitor CST is the threshold voltage of the driving transistor T3.

[0103] During the readout stage t4, the current conversion module PB can be driven as follows: During the readout stage t4, the compensation control signal Sn is loaded onto the path control unit U6, and the scan signal Gate is loaded onto the scan control unit U4. At this time, the scan transistor T4 and the path control transistor T6 are turned on, and the driving transistor T3 can generate a sensing current Iout under the control of the voltage at the second terminal of the energy storage capacitor CST. At this time, the voltage on the driving transistor T3 is Vbias+Vth+Vx, and the gate-source voltage Vgs of the driving transistor T3 is Vbias+Vth+Vx-Vdd; therefore, the sensing current Iout output by the driving transistor T3 is:

[0104] Iout = β*(Vgs - Vth) 2 =β*(Vbias+Vx-Vdd) 2 ,

[0105] β is a constant, which is related to the structure and material properties of the driving transistor T3. Therefore, the sensing current Iout is related to the sensing voltage Vx, but not to Vth.

[0106] In one example, the scan control unit U4 includes a scan transistor T4, the gate of which is used to load the scan signal Gate, the source of which is electrically connected to the third node N3, and the drain of which is electrically connected to the output of the detection circuit PDC.

[0107] In one example, the threshold compensation unit U5 includes a threshold compensation transistor T5, the gate of which is used to load the path control signal Rn, the source of which is electrically connected to the second node N2, and the drain of which is electrically connected to the second terminal of the energy storage capacitor CST.

[0108] In one example, the path control unit U6 includes a path control transistor T6, the gate of which is used to load the compensation control signal Sn, the source of which is used to load the drive power supply voltage Vdd, and the drain of which is electrically connected to the second node N2.

[0109] Simulation verification of this implementation scheme revealed that the timing and level changes at each stage met expectations and fully achieved the purpose of pre-compensating the threshold voltage of the driving transistor T3.

[0110] In one example, the compensation control signal Sn and the path control signal Rn are global signals acting on each row of detection units across the entire ultrasound detection array panel, and the scan signal Gate is a line-by-line scan signal.

[0111] For example, in the first sub-stage t11 of the transmission phase t1, a compensation control signal Sn and a path control signal Rn are loaded. These signals are simultaneously applied to the detection circuit PDC of each detection unit UU. This causes the second terminal of the energy storage capacitor CST of each detection circuit PDC on the ultrasonic detection array panel to be filled with the driving power supply voltage Vdd. In the second sub-stage t12 of the transmission phase t1, a path control signal Rn is loaded onto the ultrasonic detection array panel, applied to each detection circuit PDC. Simultaneously, a scan signal Gate is loaded row by row. When a scan signal Gate is loaded onto a row, the driving transistor T3 of that row's detection circuit PDC begins to discharge until it is turned off. Thus, in the transmission phase t1, the ultrasonic detection array panel can employ a strategy of synchronously loading the driving power supply voltage Vdd and discharging row by row to achieve threshold compensation for each driving transistor T3.

[0112] In this embodiment, the acquisition circuit CC can be directly electrically connected to the output terminal of the detection circuit PDC. For example, the acquisition circuit CC can be directly electrically connected to the data line DL connected to the detection circuit PDC.

[0113] In another embodiment of this disclosure, see [link to relevant documentation]. Figures 6-8 The current conversion module PB includes a driving transistor T3, a scan control unit U4, a threshold compensation unit U5, and a path control unit U6. The gate of the driving transistor T3 is electrically connected to the second terminal of the energy storage capacitor CST, the source of the driving transistor T3 is electrically connected to the second node N2, and the drain of the driving transistor T3 is electrically connected to the third node N3. The scan control unit U4 is configured to apply the driving power supply voltage Vdd to the second node N2 in response to the scan signal Gate. The threshold compensation unit U5 is configured to conduct electricity between the second node N2 and the second terminal of the energy storage capacitor CST in response to the path control signal Rn. The path control unit U6 is configured to conduct electricity between the third node N3 and the output terminal of the detection circuit PDC in response to the compensation control signal Sn.

[0114] During the sampling phase t2, the current conversion module PB can be driven using the following method:

[0115] In the first sub-stage t11 of the transmission phase t1, the path control signal Rn is loaded to the threshold compensation unit U5 and the scan signal Gate is loaded to the scan control unit U4, so that the drive power supply voltage Vdd is loaded to the second terminal of the energy storage capacitor CST; thus, the voltage at the second terminal of the energy storage capacitor CST is the drive power supply voltage Vdd.

[0116] In the second sub-stage t12 of the transmission phase t1, the path control signal Rn is loaded into the threshold compensation unit U5 and the compensation control signal Sn is loaded into the path control unit U6, so that the second terminal of the energy storage capacitor CST discharges until the driving transistor T3 is turned off. At this time, the voltage at the second terminal of the energy storage capacitor CST is the threshold voltage of the driving transistor T3.

[0117] In one example, the scan control unit U4 includes a scan transistor T4, the gate of which is used to load the scan signal Gate, and the source of which is used to load the drive power supply voltage Vdd; the drain of the scan transistor T4 is electrically connected to the second node N2.

[0118] In one example, the threshold compensation unit U5 includes a threshold compensation transistor T5, the gate of which is used to load the path control signal Rn, the source of which is electrically connected to the second node N2, and the drain of which is electrically connected to the second terminal of the energy storage capacitor CST.

[0119] In one example, the path control unit U6 includes a path control transistor T6, the gate of which is used to load the compensation control signal Sn, the source of which is electrically connected to the third node N3, and the drain of which is electrically connected to the output of the detection circuit PDC.

[0120] In one example, the compensation control signal Sn and the path control signal Rn are global signals acting on each row of detection units across the entire ultrasound detection array panel, and the scan signal Gate is a line-by-line scan signal.

[0121] For example, in the first sub-stage t11 of the transmission phase t1, a path control signal Rn is applied to the detection circuit PDC of each detection unit UU; this turns on the threshold compensation transistor T5 of each detection circuit PDC on the ultrasonic detection array panel. In this first sub-stage t11, a scan signal Gate is sequentially applied to each row of detection circuit PDCs in a row-by-row scanning manner; when a scan signal Gate is applied to a certain row of detection circuit PDCs, the scan transistor T4 of that row of detection circuit PDCs turns on, thereby causing the drive power supply voltage Vdd to be written to the second terminal of the energy storage capacitor CST of that row of detection circuit PDCs. In the second sub-stage t12 of the transmission phase t1, a path control signal Rn and a compensation control signal Sn are applied to the ultrasonic detection array panel, and these signals are applied to each detection circuit PDC on the ultrasonic detection array panel. At this time, the threshold compensation transistor T5 and the path control transistor T6 of each detection circuit PDC turn on, thereby causing the drive transistor T3 of each detection circuit PDC to discharge until the drive transistor T3 turns off. When the gate voltage of the driving transistor T3 drops to its threshold voltage, the driving transistor T3 is turned off, thus achieving threshold compensation for the driving transistor T3. In this way, during the emission phase t1, the ultrasonic detection array panel can employ a strategy of sequentially scanning and loading the driving power supply voltage Vdd, and synchronously discharging, to achieve threshold compensation for each driving transistor T3.

[0122] In this embodiment, the acquisition circuit CC can be directly electrically connected to the output terminal of the detection circuit PDC. For example, the acquisition circuit CC can be directly electrically connected to the data line DL connected to the detection circuit PDC.

[0123] In one example, the scanning transistor T4 can be made a low-impedance transistor, for example, with a resistance of no more than 500 ohms, to reduce the influence of the voltage division of the scanning transistor T4 in the second sub-stage t12. For example, in the second sub-stage t12, it can be assumed that the drain of the scanning transistor T4 is grounded and its voltage is 0, and the voltage division of the scanning transistor T4 is Vds(T4); then the voltage of the second node N2 is Vds(4). When the driving transistor T3 is discharged and cut off, Vg(3)-Vd(T3)=Vth; therefore, Vg(T3)=Vds(T4)+Vth. It can be seen that the smaller the voltage division of the scanning transistor T4, the closer Vg(T3) is to Vth, and the more accurate the threshold compensation of the driving transistor T3. Optionally, the on-resistance of the scanning transistor T4 can be reduced by increasing the width-to-length ratio of the channel region of the scanning transistor T4. Taking the on-resistance of scanning transistor T4 as 500 ohms as an example, assuming the current of driving transistor T3 when it discharges is 20μA and Vth is 1V, then the voltage division of scanning transistor T4 is 10mV. The voltage division of scanning transistor T4 has only 1% effect on the compensation accuracy of threshold voltage, and has little effect on the ultrasonic detection results.

[0124] In another embodiment of this disclosure, see [link to relevant documentation]. Figures 9-11 The current conversion module PB includes a driving transistor T3, a scanning control unit U4, and a threshold compensation unit U5;

[0125] The gate of the driving transistor T3 is electrically connected to the second terminal of the energy storage capacitor CST, the source of the driving transistor T3 is electrically connected to the second node N2, and the drain of the driving transistor T3 is electrically connected to the output terminal of the detection circuit PDC.

[0126] The scanning control unit U4 is configured to apply the drive power supply voltage Vdd to the second node N2 in response to the scanning signal Gate;

[0127] The threshold compensation unit U5 is configured to, in response to the path control signal Rn, make the second node N2 electrically connected to the second terminal of the energy storage capacitor CST.

[0128] In the ultrasonic testing module, the data line DL is electrically connected to the acquisition circuit CC via a switching element SW. In other words, the output terminal of the detection circuit PDC is electrically connected to the acquisition circuit CC via the switching element SW. This switching element SW is configured to electrically connect the output terminal of the detection circuit PDC and the acquisition circuit CC in response to a compensation control signal Sn. Furthermore, the switching element SW and the acquisition circuit CC can be integrated into the same chip or placed on the same circuit board.

[0129] In this embodiment, the current conversion module PB can be driven using the following driving method:

[0130] In the first sub-stage t11 of the transmission stage t1, the path control signal Rn is loaded to the threshold compensation unit U5 and the scan signal Gate is loaded to the scan control unit U4, so that the drive power supply voltage Vdd is loaded to the second terminal of the energy storage capacitor CST.

[0131] In the second sub-stage t12 of the transmission phase t1, the path control signal Rn is applied to the threshold compensation unit U5 to discharge the second terminal of the energy storage capacitor CST to a voltage equal to the threshold voltage of the driving transistor T3. It is understood that in this second sub-stage t12, a compensation control signal Sn also needs to be applied to the switching element SW to turn on the switching element SW, thereby allowing the discharge current from the acquisition circuit CC to flow out when the driving transistor T3 discharges.

[0132] During the readout phase t4, a compensation control signal Sn can be applied to the switching element SW, and a scan signal Gate can be applied to the scan control unit U4. Thus, the sensing current Iout generated by the driving transistor T3 under the control of the voltage at the second terminal of the energy storage capacitor CST can be output to the acquisition circuit CC.

[0133] In one example, the scan control unit U4 includes a scan transistor T4, the gate of which is used to load the scan signal Gate, the source of which is used to load the drive power supply voltage Vdd, and the drain of which is electrically connected to the second node N2.

[0134] The threshold compensation unit U5 includes a threshold compensation transistor T5. The gate of the threshold compensation transistor T5 is used to load the path control signal Rn. The source of the threshold compensation transistor T5 is electrically connected to the second node N2, and the drain of the threshold compensation transistor T5 is electrically connected to the second terminal of the energy storage capacitor CST.

[0135] In one example, the pathway control signal Rn is a global signal acting on each row of detection units across the entire ultrasound detection array panel, and the scan signal Gate is a line-by-line scan signal.

[0136] For example, in the first sub-stage t11 of the transmission phase t1, a path control signal Rn can be loaded, which is applied to the detection circuit PDC of each detection unit UU. This turns on the threshold compensation transistor T5 of each detection circuit PDC on the ultrasonic detection array panel. In this first sub-stage t11, a scan signal Gate is sequentially applied to each row of detection circuit PDCs in a row-by-row scanning manner. When a scan signal Gate is applied to a row of detection circuit PDCs, the scan transistor T4 of that row of detection circuit PDCs turns on, thereby causing the drive power supply voltage Vdd to be written to the second terminal of the energy storage capacitor CST of that row of detection circuit PDCs. In the second sub-stage t12 of the transmission phase t1, a path control signal Rn is applied to the ultrasonic detection array panel, which is applied to each detection circuit PDC on the ultrasonic detection array panel. At this time, the threshold compensation transistor T5 of each detection circuit PDC turns on. Simultaneously, a compensation control signal Sn is applied to the switching element SW, causing the switching element SW to turn on. This allows the driving transistor T3 of each detection circuit PDC to discharge until it is turned off; when the gate voltage of the driving transistor T3 drops to its threshold voltage, the driving transistor T3 is turned off, thus achieving threshold compensation for the driving transistor T3. In this way, during the transmission phase t1, the ultrasonic detection array panel can adopt a strategy of sequentially scanning and loading the driving power supply voltage Vdd and synchronously discharging to achieve threshold compensation for each driving transistor T3.

[0137] In this embodiment, the acquisition circuit CC can be directly electrically connected to the output terminal of the detection circuit PDC. For example, the acquisition circuit CC can be directly electrically connected to the data line DL connected to the detection circuit PDC.

[0138] In one example, the switching element SW is an analog switch, such as the ADG841. The on-resistance of this analog switch is very small, for example, no more than 1 ohm, and has a very small impact on the accuracy of threshold voltage compensation.

[0139] Optionally, the semiconductor material of any transistor can be amorphous silicon, low-temperature polycrystalline silicon, or metal-oxide-semiconductor (MODS). In one example, each transistor can be MODS to improve the voltage holding capability of the detection circuit PDC. In another example, the write transistor T2 and the threshold compensation transistor T5 can be MODS transistors, while the remaining transistors can be MODS transistors. Thus, the write transistor T2 and the threshold compensation transistor T5 have lower leakage current, which enhances the voltage holding capability of the first and second terminals of the energy storage capacitor CST, thereby improving detection accuracy.

[0140] It should be noted that although the steps of the driving method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0141] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A detection circuit, comprising a voltage sensing module, a current conversion module, and an energy storage capacitor; The voltage sensing module is configured to write the sensing voltage generated by the transducer element in response to the ultrasonic echo signal into the first terminal of the energy storage capacitor. The current conversion module has a driving transistor and is capable of writing the threshold voltage of the driving transistor into the second terminal of the energy storage capacitor. The driving transistor is configured to output a sensing current based on the voltage at the second terminal of the energy storage capacitor; The voltage sensing module includes: A biasing unit is configured to apply a bias voltage to a first node in response to a bias control signal during the sampling phase; the first node is electrically connected to one end of the transducer element. The writing unit is configured to respond to a write control signal during the sampling phase to make electrical conduction between the first node and the first terminal of the energy storage capacitor. The bias unit includes a bias transistor, the gate of which is used to load the bias control signal, the source of which is used to load the bias voltage, and the drain of which is electrically connected to the first node. The writing unit includes a writing transistor, the gate of which is used to load the writing control signal, the source of which is electrically connected to the first node, and the drain of which is electrically connected to the first terminal of the energy storage capacitor. The current conversion module also includes a scanning control unit, a threshold compensation unit, and a path control unit; The gate of the driving transistor is electrically connected to the second terminal of the energy storage capacitor, the source of the driving transistor is electrically connected to the second node, and the drain of the driving transistor is electrically connected to the third node. The scanning control unit is configured to electrically connect the third node and the output terminal of the detection circuit in response to a scanning signal; The threshold compensation unit is configured to electrically connect the second node and the second terminal of the energy storage capacitor in response to a path control signal. The path control unit is configured to apply a drive power supply voltage to the second node in response to a compensation control signal.

2. The detection circuit according to claim 1, wherein, The scanning control unit includes a scanning transistor, the gate of which is used to load the scanning signal, the source of which is electrically connected to the third node, and the drain of which is electrically connected to the output terminal of the detection circuit. The threshold compensation unit includes a threshold compensation transistor, the gate of which is used to load the path control signal, the source of which is electrically connected to the second node, and the drain of which is electrically connected to the second terminal of the energy storage capacitor. The path control unit includes a path control transistor, the gate of which is used to load the compensation control signal, the source of which is used to load the drive power supply voltage, and the drain of which is electrically connected to the second node.

3. A detection circuit, comprising a voltage sensing module, a current conversion module, and an energy storage capacitor; The voltage sensing module is configured to write the sensing voltage generated by the transducer element in response to the ultrasonic echo signal into the first terminal of the energy storage capacitor. The current conversion module has a driving transistor and is capable of writing the threshold voltage of the driving transistor into the second terminal of the energy storage capacitor. The driving transistor is configured to output a sensing current based on the voltage at the second terminal of the energy storage capacitor; The voltage sensing module includes: A biasing unit is configured to apply a bias voltage to a first node in response to a bias control signal during the sampling phase; the first node is electrically connected to one end of the transducer element. The writing unit is configured to respond to a write control signal during the sampling phase to make electrical conduction between the first node and the first terminal of the energy storage capacitor. The bias unit includes a bias transistor, the gate of which is used to load the bias control signal, the source of which is used to load the bias voltage, and the drain of which is electrically connected to the first node. The writing unit includes a writing transistor, the gate of which is used to load the writing control signal, the source of which is electrically connected to the first node, and the drain of which is electrically connected to the first terminal of the energy storage capacitor. The current conversion module also includes a scanning control unit, a threshold compensation unit, and a path control unit; The gate of the driving transistor is electrically connected to the second terminal of the energy storage capacitor, the source of the driving transistor is electrically connected to the second node, and the drain of the driving transistor is electrically connected to the third node. The scanning control unit is configured to apply a drive power supply voltage to the second node in response to a scanning signal; The threshold compensation unit is configured to electrically connect the second node and the second terminal of the energy storage capacitor in response to a path control signal. The pathway control unit is configured to electrically connect the third node and the output of the detection circuit in response to a compensation control signal.

4. The detection circuit according to claim 3, wherein, The scanning control unit includes a scanning transistor, the gate of which is used to load the scanning signal, the source of which is used to load the driving power supply voltage, and the drain of which is electrically connected to the second node. The threshold compensation unit includes a threshold compensation transistor, the gate of which is used to load the path control signal, the source of which is electrically connected to the second node, and the drain of which is electrically connected to the second terminal of the energy storage capacitor. The path control unit includes a path control transistor, the gate of which is used to load the compensation control signal, the source of which is electrically connected to the third node, and the drain of which is electrically connected to the output of the detection circuit.

5. A detection circuit, comprising a voltage sensing module, a current conversion module, and an energy storage capacitor; The voltage sensing module is configured to write the sensing voltage generated by the transducer element in response to the ultrasonic echo signal into the first terminal of the energy storage capacitor. The current conversion module has a driving transistor and is capable of writing the threshold voltage of the driving transistor into the second terminal of the energy storage capacitor. The driving transistor is configured to output a sensing current based on the voltage at the second terminal of the energy storage capacitor; The voltage sensing module includes: A biasing unit is configured to apply a bias voltage to a first node in response to a bias control signal during the sampling phase; the first node is electrically connected to one end of the transducer element. The writing unit is configured to respond to a write control signal during the sampling phase to make electrical conduction between the first node and the first terminal of the energy storage capacitor. The bias unit includes a bias transistor, the gate of which is used to load the bias control signal, the source of which is used to load the bias voltage, and the drain of which is electrically connected to the first node. The writing unit includes a writing transistor, the gate of which is used to load the writing control signal, the source of which is electrically connected to the first node, and the drain of which is electrically connected to the first terminal of the energy storage capacitor. The current conversion module further includes a scanning control unit and a threshold compensation unit; the gate of the driving transistor is electrically connected to the second terminal of the energy storage capacitor, the source of the driving transistor is electrically connected to the second node, and the drain of the driving transistor is electrically connected to the output terminal of the detection circuit. The scanning control unit is configured to apply a drive power supply voltage to the second node in response to a scanning signal; The threshold compensation unit is configured to electrically connect the second node and the second terminal of the energy storage capacitor in response to a path control signal.

6. The detection circuit according to claim 5, wherein, The scanning control unit includes a scanning transistor, the gate of which is used to load the scanning signal, the source of which is used to load the driving power supply voltage, and the drain of which is electrically connected to the second node. The threshold compensation unit includes a threshold compensation transistor, the gate of which is used to load the path control signal, the source of which is electrically connected to the second node, and the drain of which is electrically connected to the second terminal of the energy storage capacitor.

7. A driving method for a detection circuit, applied to the detection circuit according to any one of claims 1 to 6; the driving method comprising: During the transmission phase, the current conversion module is driven so that the threshold voltage of the driving transistor is written to the second terminal of the energy storage capacitor; Drive the voltage sensing module to keep the first end of the energy storage capacitor in a reset state; During the sampling phase, the voltage sensing module is driven so that the sensing voltage generated by the transducer element is written to the first terminal of the energy storage capacitor, thereby allowing the sensing voltage to be written to the second terminal of the energy storage capacitor through a coupling effect. During the readout phase, the current conversion module is driven so that the driving transistor outputs a sense current based on the voltage at the second terminal of the energy storage capacitor.

8. The driving method according to claim 7, wherein, The voltage sensing module includes a bias unit and a write unit; the bias unit is configured to apply a bias voltage to a first node in response to a bias control signal; the first node is electrically connected to one end of the transducer element; the write unit is configured to make electrical conduction between the first node and a first end of the energy storage capacitor in response to a write control signal. The step of driving the voltage sensing module during the sampling phase so that the sensing voltage generated by the transducer element is written into the first terminal of the energy storage capacitor includes: During the sampling phase, a bias voltage is applied to the bias unit, and the bias control signal and the write control signal are also applied to the bias unit. At the end of the sampling phase, the bias control signal and the write control signal are no longer loaded into the bias unit.

9. The driving method according to claim 7, wherein, The current conversion module includes a driving transistor, a scan control unit, a threshold compensation unit, and a path control unit. The gate of the driving transistor is electrically connected to the second terminal of the energy storage capacitor, the source of the driving transistor is electrically connected to the second node, and the drain of the driving transistor is electrically connected to the third node. The scan control unit is configured to electrically connect the third node and the output terminal of the detection circuit in response to a scan signal. The threshold compensation unit is configured to electrically connect the second node and the second terminal of the energy storage capacitor in response to a path control signal. The path control unit is configured to apply a driving power supply voltage to the second node in response to a compensation control signal. The step of driving the current conversion module during the emission phase to write the threshold voltage of the driving transistor to the second terminal of the energy storage capacitor includes: In the first sub-phase of the launch phase, the path control signal is loaded to the threshold compensation unit and the compensation control signal is loaded to the path control unit so that the drive power supply voltage is applied to the second terminal of the energy storage capacitor. In the second sub-phase of the launch phase, the path control signal is loaded to the threshold compensation unit and the scan signal is loaded to the scan control unit, so that the second terminal of the energy storage capacitor discharges to the turn-off of the drive transistor. The step of driving the current conversion module during the readout phase so that the driving transistor outputs a sense current based on the voltage at the second terminal of the energy storage capacitor includes: During the readout phase, the compensation control signal is loaded to the path control unit and the scan signal is loaded to the scan control unit.

10. The driving method according to claim 7, wherein, The current conversion module includes a driving transistor, a scan control unit, a threshold compensation unit, and a path control unit. The gate of the driving transistor is electrically connected to the second terminal of the energy storage capacitor, the source of the driving transistor is electrically connected to the second node, and the drain of the driving transistor is electrically connected to the third node. The scan control unit is configured to apply a driving power supply voltage to the second node in response to a scan signal. The threshold compensation unit is configured to conduct electricity between the second node and the second terminal of the energy storage capacitor in response to a path control signal. The path control unit is configured to conduct electricity between the third node and the output terminal of the detection circuit in response to a compensation control signal. The step of driving the current conversion module during the emission phase to write the threshold voltage of the driving transistor to the second terminal of the energy storage capacitor includes: In the first sub-phase of the launch phase, the path control signal is loaded to the threshold compensation unit and the scan signal is loaded to the scan control unit, so that the drive power supply voltage is applied to the second terminal of the energy storage capacitor; In the second sub-phase of the launch phase, the path control signal is loaded to the threshold compensation unit and the compensation control signal is loaded to the path control unit, so that the second terminal of the energy storage capacitor discharges to the point where the driving transistor is turned off. The step of driving the current conversion module during the readout phase so that the driving transistor outputs a sense current based on the voltage at the second terminal of the energy storage capacitor includes: During the readout phase, the compensation control signal is loaded to the path control unit and the scan signal is loaded to the scan control unit.

11. The driving method according to claim 7, wherein, The current conversion module includes a driving transistor, a scan control unit, and a threshold compensation unit; the gate of the driving transistor is electrically connected to the second terminal of the energy storage capacitor, the source of the driving transistor is electrically connected to the second node, and the drain of the driving transistor is electrically connected to the output terminal of the detection circuit; the scan control unit is configured to apply a driving power supply voltage to the second node in response to a scan signal; the threshold compensation unit is configured to conduct electricity between the second node and the second terminal of the energy storage capacitor in response to a path control signal. The step of driving the current conversion module during the emission phase to write the threshold voltage of the driving transistor to the second terminal of the energy storage capacitor includes: In the first sub-phase of the launch phase, the path control signal is loaded to the threshold compensation unit and the scan signal is loaded to the scan control unit, so that the drive power supply voltage is applied to the second terminal of the energy storage capacitor; In the second sub-phase of the launch phase, the path control signal is loaded onto the threshold compensation unit to cause the second terminal of the energy storage capacitor to discharge until the driving transistor is turned off. The step of driving the current conversion module during the readout phase so that the driving transistor outputs a sense current based on the voltage at the second terminal of the energy storage capacitor includes: During the readout phase, the scan signal is loaded into the scan control unit.

12. An ultrasonic detection array panel, comprising the detection circuit as described in any one of claims 1 to 6 and a transducer element electrically connected to the detection circuit.

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