Reference voltage adjustment for word line groups

Abstract

The present application relates to reference voltage adjustment for word line groups. In some examples, one or more components of a memory system may determine a duration for which data has been stored to one or more memory cells. Based on the duration, the voltage value of one or more reference voltages may be adjusted accordingly. For example, the voltage value of one or more reference voltages may be adjusted based on the duration. In addition, the reference voltage value may be adjusted differently in response to a memory cell having stored data for a relatively long duration relative to a memory cell having stored data for a relatively short duration. The adjusted reference voltage may be used during a subsequent read operation. For example, the voltage value of the one or more reference voltages may be adjusted on a word line group by word line group.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 649,885 filed by Jiang et al. on February 3, 2022, entitled “REFERENCE VOLTAGE ADJUSTMENT FOR WORD LINE GROUPS,” which is assigned to the present assignee and is expressly incorporated herein by reference.

[0003] The technical field relates to reference voltage adjustment for groups of word lines. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. In order to access information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. In order to store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross point memory (3D cross point), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Unless periodically refreshed by an external power source, volatile memory cells (e.g., DRAM cells) may lose their programmed state over time. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of external power. Summary of the invention

[0006] An apparatus is described. The apparatus may include: a controller associated with a memory device, wherein the controller is configured to cause the apparatus to: write data to at least one memory cell of a first plurality of memory cells at a first time, wherein the first plurality of memory cells are coupled to a first word line associated with a block of memory cells; initiate a read operation to read the data at a second time after the first time based at least in part on writing the data; determine a duration between the first time and the second time based at least in part on initiating the read operation; adjust first multiple reference voltage values ​​of a first multiple reference voltage associated with a first word line associated with a block storing data and second multiple reference voltage values ​​of a second multiple reference voltage associated with a second word line associated with a block storing data based at least in part on determining the duration between the first time and the second time, wherein the first multiple reference voltage values ​​are different from the second multiple reference voltage values; and read data from at least one memory cell associated with the first word line based at least in part on adjusting the first multiple reference voltage values ​​and the second multiple reference voltage values.

[0007] A non-transitory computer-readable medium storing code is described, the non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: write data to at least one memory cell of a first plurality of memory cells at a first time, wherein the first plurality of memory cells are coupled to a first word line associated with a block of memory cells; initiate a read operation at a second time after the first time to read the data based at least in part on the write data; determine a duration between the first time and the second time based at least in part on the initiation of the read operation; adjust first multiple reference voltage values ​​of a first multiple reference voltage associated with a first word line associated with a block storing data, and second multiple reference voltage values ​​of a second multiple reference voltage associated with a second word line associated with a block storing data, based at least in part on the determination of the duration between the first time and the second time, wherein the first multiple reference voltage values ​​are different from the second multiple reference voltage values; and read data from at least one memory cell associated with the first word line based at least in part on the adjustment of the first multiple reference voltage values ​​and the second multiple reference voltage values.

[0008] A method is described. The method may include: writing data to at least one memory cell of a first plurality of memory cells at a first time, wherein the first plurality of memory cells are coupled to a first word line associated with a block of memory cells; initiating a read operation to read the data at a second time after the first time based at least in part on the written data; determining a duration between the first time and the second time based at least in part on initiating the read operation; adjusting first multiple reference voltage values ​​of a first multiple reference voltage associated with a first word line associated with a block storing data and second multiple reference voltage values ​​of a second multiple reference voltage associated with a second word line associated with a block storing data based at least in part on determining the duration between the first time and the second time, wherein the first multiple reference voltage values ​​are different from the second multiple reference voltage values; and reading data from at least one memory cell associated with the first word line based at least in part on adjusting the first multiple reference voltage values ​​and the second multiple reference voltage values. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting reference voltage adjustment of a group of word lines according to examples as disclosed herein is described.

[0010] Figure 2 An example of a system supporting reference voltage adjustment of a group of word lines according to examples as disclosed herein is described.

[0011] Figure 3 An example of a circuit supporting reference voltage adjustment for a group of word lines according to examples as disclosed herein is described.

[0012] Figure 4A and 4B A block diagram illustrating support for reference voltage adjustment of a group of word lines according to examples as disclosed herein.

[0013] Figure 5 An example of a process flow diagram is illustrated that supports reference voltage adjustment for a group of word lines according to examples as disclosed herein.

[0014] Figure 6 A block diagram of a memory device supporting reference voltage adjustment of a group of word lines is shown according to examples as disclosed herein.

[0015] Figure 7 A flow chart illustrating one or more methods of supporting reference voltage adjustment for a group of word lines according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0016] Some memory devices, such as non-volatile memory devices (e.g., memory systems including non-volatile memory cells such as NAND memory cells), may include one or more blocks (e.g., one or more blocks of memory cells). In some examples, a block may include a set of one or more word lines that may each be coupled to one or more memory cells. In some examples, a memory cell may be configured to store one or more bits of data, and a reference voltage (or set of reference voltages) may be used to determine a value (e.g., a logical value) stored to a corresponding memory cell. However, as the memory device ages, the ability of the memory cell to maintain a charge may degrade. Therefore, some memory devices may utilize a block family error avoidance (BFEA) scheme to adjust the reference voltage of a block in order to reduce any errors that may be generated attributable to the ability of the cell to maintain a corresponding charge for a sustained period of time. However, such a scheme is performed on a block-by-block basis and may not provide sufficient granularity for avoiding errors. Therefore, a system capable of performing BFEA on groups of word lines may be beneficial.

[0017] A system capable of performing BFEA on groups of word lines is described herein. In some examples, a memory system may be configured to determine the duration that data has been stored to a corresponding memory cell (or set of memory cells), and a set of reference voltage values ​​associated with the corresponding memory cell (or set of memory cells) may be adjusted based on the age of the data. For example, a memory system may include a plurality of word line groups (WGRs) each including a set of word lines. Each word line set may be coupled to a set of memory cells. Based on the age of the data stored to one or more memory cells of the WGR, the voltage values ​​of one or more reference voltages of the WGR may be adjusted to compensate for the ability of the cell to maintain a corresponding charge over time. In some examples, a first adjustment to the voltage level of the one or more reference voltages may be determined for the entire block, and a second adjustment to the voltage level of the one or more reference voltages may be determined for individual WGRs in the group. The resulting voltage level of the reference voltage may be based on both the first adjustment and the second adjustment. Thus, by utilizing a BFEA scheme based on the WGR, the system's ability to accurately sense a set of memory cells that have stored data for a relatively long duration may be improved.

[0018] First, in reference Figure 1 and 2 Features of the present disclosure are described in the context of systems, devices, and circuits. Figures 3 to 5 Features of the present disclosure are described in the context of circuits, block diagrams, and process flow diagrams of the present disclosure. These and other features of the present disclosure are described by reference to Figure 6 and 7 The context of an apparatus diagram and flow chart involving reference voltage adjustment for word line groups is further illustrated and described in that context.

[0019] Figure 1 An example of a system 100 supporting reference voltage adjustment of a group of word lines according to examples as disclosed herein is illustrated. The system 100 includes a host system 105 coupled with a memory system 110.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0021] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or any other computing device that includes a memory and a processing device.

[0022] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). The host system 105 may use the memory system 110 (for example) to write data to the memory system 110 and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0023] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DIMM socket interface supporting DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0024] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells (eg, non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but the memory system 110 may include any number of memory devices 130. In addition, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface), and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled and communicate with the memory devices 130 to perform operations that may generally be referred to as access operations at the memory devices 130, such as reading data, writing data, erasing data, or refreshing data, as well as other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry with dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or another memory that may store operating codes (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or another memory that may be used by the memory system controller 115, such as for internal storage or calculations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may act as a cache for the memory system controller 115. For example, if read from or written to the memory device 130, the data may be stored in the local memory 120, and the data may be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0029] Although Figure 1 The example of the memory system 110 in FIG. 1 has been illustrated as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 that may be respectively internal to the memory device 130 to perform the functions attributed herein to the memory system controller 115. In general, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof in some cases. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115, or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As illustrated in FIG. 1 , memory device 130 - a may include a local controller 135 - a and memory device 130 - b may include a local controller 135 - b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a respective set of blocks 170, wherein each block 170 may include a respective set of pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLC) if configured to each store two bits of information, triple-level cells (TLC) if configured to each store three bits of information, quad-level cells (QLC) if configured to each store four bits of information, or more generally, multi-level memory cells. Multi-level memory cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0034] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which parallel operations may occur. For example, blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, may be operated on in parallel, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, parallel operations in different planes 165 may be subject to one or more restrictions, such as parallel operations on memory cells in different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but can be erased at a second level of granularity (e.g., at a block granularity level). That is, a page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and a block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Additionally, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0037] In some cases, the memory system controller 115 or the local controller 135 may perform operations of the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. In order to avoid waiting for all pages 175 in a block 170 to have invalid data in order to erase and reuse the block 170, an algorithm called "garbage collection" may be invoked to allow a block 170 to be erased and released as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting a block 170 containing valid and invalid data, selecting a page 175 in a block containing valid data, copying valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking data in a previously selected page 175 as invalid, and erasing the selected block 170. Thus, the number of erased blocks 170 may be increased so that more blocks 170 may be used to store subsequent data (eg, data subsequently received from the host system 105).

[0038] The system 100 may include any number of non-transitory computer-readable media that support reference voltage adjustment for a group of word lines. For example, the host system 105, the memory system controller 115, or the memory device 130 (e.g., the local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0039] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0040] In some examples, the memory system controller 115 may adjust one or more reference voltages (or a set of reference voltages) associated with the memory device 130. For example, the memory device 130 may be arranged (e.g., physically arranged) into word line groups (e.g., WGRs), and the set of reference voltages may be used to determine the logic state stored to any one of the WGRs. In some cases, the memory system controller 115 may determine the duration that data has been stored to one or more memory cells associated with the WGR, and may adjust the voltage value of the one or more reference voltages based on the duration. Thus, when data is read from a memory cell of the WGR (e.g., from the memory device 130), the adjusted reference voltage value may be used to determine the logic value stored to the corresponding memory cell. Adjusting the reference voltage value based on the WGR may improve the ability of the memory system 110 to accurately sense a set of memory cells that have stored data for a relatively long duration.

[0041] Figure 2 An example of a system 200 supporting reference voltage adjustment for a word line group according to an example as disclosed herein is described. The system 200 may be as described in reference Figure 1The system 200 may include a memory system 210 configured to store data received from a host system 205 and to send the data to the host system 205 if requested by the host system 205 using an access command (e.g., a read command or a write command). The system 200 may be implemented as described in reference Figure 1 Aspects of the described system 100. For example, memory system 210 and host system 205 can be instances of memory system 110 and host system 105, respectively.

[0042] The memory system 210 may include a memory device 240 to store data transferred between the memory system 210 and the host system 205, such as in response to receiving an access command from the host system 205, as described herein. The memory device 240 may include a memory device 240 as described in reference to Figure 1 For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0043] The memory system 210 may include a storage controller 230 for controlling the transfer of data directly into and out of the memory devices 240, such as for storing data, retrieving data, and determining memory locations in which data is to be stored and from which data is to be retrieved. The storage controller 230 may communicate with the memory devices 240 directly or via a bus (not shown) using a protocol specific to each type of memory device 240. In some cases, a single storage controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, the memory system 210 may include multiple storage controllers 230, such as a different storage controller 230 for each type of memory device 240. In some cases, the storage controller 230 may be implemented as described with reference to FIG. Figure 1 Aspects of the local controller 135 are described.

[0044] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may be used to translate data between the host system 205 and the memory device 240 (e.g., as shown by the data path 250), and may be collectively referred to as data path components.

[0045] Using buffer 225 to temporarily store data during transfer can allow data to be buffered while commands are being processed, thereby reducing latency between commands and allowing arbitrary data sizes associated with commands. This can also allow bursts of commands to be handled, and once the burst has stopped, the buffered data can be stored or transmitted (or both). Buffer 225 can include relatively fast memory (e.g., some type of volatile memory, such as SRAM or DRAM), or a hardware accelerator, or both, to allow data to be quickly stored to and retrieved from buffer 225. Buffer 225 can include a data path switching component for bidirectional data transfer between buffer 225 and other components.

[0046] Temporary storage of data within buffer 225 may refer to storage of data in buffer 225 during execution of an access command. That is, after completion of an access command, the associated data may no longer be maintained in buffer 225 (e.g., may be overwritten with data from additional access commands). Additionally, buffer 225 may be a non-cacheable buffer. That is, data may not be read directly from buffer 225 by host system 205. For example, a read command may be added to a queue without requiring an operation to match an address with an address already in buffer 225 (e.g., without requiring a cache address match or lookup operation).

[0047] The memory system 210 may further include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be a memory system controller 215 as described in reference Figure 1 An example of a memory system controller 115 is depicted. Bus 235 may be used to communicate between system components.

[0048] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. This may be beneficial, for example, if more than one access command from host system 205 is processed in parallel by memory system 210. Command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively, as examples of possible implementations. However, queues (if used) may be located anywhere within memory system 210.

[0049] Data transferred between the host system 205 and the memory device 240 may take a different path than non-data information (e.g., commands, status information) in the memory system 210. For example, system components in the memory system 210 may communicate with each other using the bus 235, while data may use the data path 250 through data path components instead of the bus 235. The memory system controller 215 may control how and whether data is transferred between the host system 205 and the memory device 240 by communicating with the data path components over the bus 235 (e.g., using a protocol specific to the memory system 210).

[0050] If the host system 205 transmits an access command to the memory system 210, the command may be received by the interface 220, for example, according to a protocol (e.g., a UFS protocol or an eMMC protocol). Therefore, the interface 220 may be considered as the front end of the memory system 210. After receiving each access command, the interface 220 may communicate the command to the memory system controller 215, for example, via the bus 235. In some cases, each command may be added to the command queue 260 by the interface 220 to communicate the command to the memory system controller 215.

[0051] The memory system controller 215 may determine that an access command has been received based on a communication from the interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving a command from the command queue 260. After the command has been retrieved from the command queue 260, for example, by the memory system controller 215, the command may be removed from the command queue 260. In some cases, the memory system controller 215 may cause the interface 220 to remove the command from the command queue 260, for example, via the bus 235.

[0052] After determining that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this can mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this can mean receiving data from the host system 205 and moving the data to the memory device 240.

[0053] In either case, the memory system controller 215 may use the buffer 225 for, among other things, temporary storage of data received from or sent to the host system 205. The buffer 225 may be considered an intermediate end of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0054] To process a write command received from the host system 205, the memory system controller 215 may first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, e.g., via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the write command.

[0055] In some cases, the buffer queue 265 may be used to control a command stream associated with data stored in the buffer 225, including write commands. The buffer queue 265 may include access commands associated with data currently stored in the buffer 225. In some cases, commands in the command queue 260 may be moved to the buffer queue 265 by the memory system controller 215 and may remain in the buffer queue 265 while the associated data is stored in the buffer 225. In some cases, each command in the buffer queue 265 may be associated with an address at the buffer 225. That is, a pointer indicating the location in the buffer 225 where the data associated with each command is stored may be maintained. Using the buffer queue 265, multiple access commands may be received sequentially from the host system 205 and at least a portion of the access commands may be processed in parallel.

[0056] If the buffer 225 has sufficient space to store the write data, the memory system controller 215 may cause the interface 220 to transmit an indication of availability to the host system 205 (e.g., a "ready to transfer" indication), for example, according to a protocol (e.g., a UFS protocol or an eMMC protocol). When the interface 220 subsequently receives data associated with a write command from the host system 205, the interface 220 may use the data path 250 to transfer the data to the buffer 225 for temporary storage. In some cases, the interface 220 may obtain the location of the stored data within the buffer 225 from the buffer 225 or the buffer queue 265. The interface 220 may indicate to the memory system controller 215, for example, via the bus 235, whether the data transfer to the buffer 225 has been completed.

[0057] Once the write data has been stored in the buffer 225 by the interface 220, the data may be transferred out of the buffer 225 and stored in the memory device 240. This may be accomplished using the storage controller 230. For example, the memory system controller 215 may cause the storage controller 230 to retrieve the data from the buffer 225 and transfer the data to the memory device 240 using the data path 250. The storage controller 230 may be considered the back end of the memory system 210. The storage controller 230 may indicate to the memory system controller 215, for example, via the bus 235, that the data transfer to the memory device in the memory device 240 has been completed.

[0058] In some cases, the storage queue 270 may be used to assist in the transfer of write data. For example, the memory system controller 215 may push (e.g., via the bus 235) a write command from the buffer queue 265 to the storage queue 270 for processing. The storage queue 270 may include an entry for each access command. In some examples, the storage queue 270 may additionally include: a buffer pointer (e.g., an address) that may indicate a location in the buffer 225 where data associated with the command is stored; and a storage pointer (e.g., an address) that may indicate a location in the memory device 240 associated with the data. In some cases, the storage controller 230 may obtain the location within the buffer 225 from which the data is obtained from the buffer 225, the buffer queue 265, or the storage queue 270. The storage controller 230 may manage the location of the storage data within the memory device 240 (e.g., to perform wear leveling, garbage collection, and the like). Entries may be added to the storage queue 270, for example, by the memory system controller 215. After the transfer of the data is complete, the entry may be removed from the storage queue 270, for example, by the storage controller 230 or the memory system controller 215.

[0059] To process a read command received from the host system 205, the memory system controller 215 may again first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, e.g., via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the read command.

[0060] In some cases, the buffer queue 265 may be used to assist in buffer storage of data associated with a read command in a similar manner as discussed above with respect to a write command. For example, if the buffer 225 has sufficient space to store the read data, the memory system controller 215 may cause the memory controller 230 to retrieve the data associated with the read command from the memory device 240 and store the data in the buffer 225 using the data path 250 for temporary storage. The memory controller 230 may indicate to the memory system controller 215, e.g., via the bus 235, when the data transfer to the buffer 225 has been completed.

[0061] In some cases, the storage queue 270 may be used to assist in the transfer of read data. For example, the memory system controller 215 may push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 may obtain a location within the memory device 240 from which data is retrieved from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 may obtain the location of the storage data within the buffer 225 from the buffer queue 265. In some cases, the storage controller 230 may obtain the location of the storage data within the buffer 225 from the storage queue 270. In some cases, the memory system controller 215 may move the command processed by the storage queue 270 back to the command queue 260.

[0062] Once the data has been stored in the buffer 225 by the memory controller 230, the data may be transferred out of the buffer 225 and sent to the host system 205. For example, the memory system controller 215 may cause the interface 220 to retrieve the data from the buffer 225 using the data path 250 and transfer the data to the host system 205, e.g., according to a protocol (e.g., a UFS protocol or an eMMC protocol). For example, the interface 220 may process commands from the command queue 260 and may indicate to the memory system controller 215, e.g., via the bus 235, that the data transfer to the host system 205 has been completed.

[0063] The memory system controller 215 may execute the received commands according to an order (e.g., a first-in, first-out order according to the order of the command queue 260). For each command, the memory system controller 215 may cause data corresponding to the command to be moved into and out of the buffer 225, as discussed above. The command may remain in the buffer queue 265 while the data is moved into and stored within the buffer 225. If processing of the command has been completed (e.g., if data corresponding to the access command has been transferred out of the buffer 225), the command may be removed from the buffer queue 265, such as by the memory system controller 215. If a command is removed from the buffer queue 265, the address that previously stored data associated with the command may be used to store data associated with a new command.

[0064] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue a command indicating one or more LBAs, and the memory system controller 215 may identify the one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the storage controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the storage controller 230 and the storage controller 230 may be omitted.

[0065] In some examples, the memory system controller 215 may adjust one or more reference voltages (or a set of reference voltages) associated with the memory device 240. For example, the memory device 130 may be arranged (e.g., physically arranged) into word line groups (e.g., WGRs), and the set of reference voltages may be used to determine the logic state stored to any one of the WGRs. In some cases, the memory system controller 215 may determine the duration that data has been stored to one or more memory cells associated with the WGR, and may adjust the voltage value of the one or more reference voltages based on the duration. Thus, when data is read from a memory cell of the WGR (e.g., from the memory device 240), the adjusted reference voltage value may be used to determine the logic value stored to the corresponding memory cell. Adjusting the reference voltage value based on the WGR may improve the ability of the memory system 210 to accurately sense a set of memory cells that have stored data for a relatively long duration.

[0066] Figure 3An example of a circuit 300 that supports reference voltage adjustment of a word line group according to an example as disclosed herein is illustrated. The circuit 300 may be included in a memory system 110 and may include one or more components of a memory device 130. For example, the circuit 300 may illustrate an example of a block 170-a that includes an array of memory cells 305. Each of the memory cells 305 may be located at an intersection of a word line 310 (e.g., WL) and a bit line 315 (e.g., BL), or may otherwise be accessed according to the intersection. The block 170-a may include a plurality of word line groups 340 (e.g., WGR 340) that each include a set of word lines 310. In some cases, data may be written to one or more memory cells 305 of a word line group 340-a, and a duration may occur before the data is read. Due to the electrical properties of the memory cells 305 (e.g., due to leakage), the charge stored to the respective memory cells 305 may change (e.g., dissipate) over time. Thus, controller 330 may determine the duration that data has been stored to memory cells 305 of WGR 340, and may adjust the voltage values ​​of one or more reference voltages used to read memory cells of WGR 340. Adjusting the reference voltage values ​​based on WGR may improve the ability of circuit 300 to accurately sense a set of memory cells 305 that have stored data for a relatively long duration.

[0067] In some examples, the circuit 300 may include a row decoder 325 and a column decoder 320. The word lines 310 and the bit lines 315 may be coupled to the row decoder 325 and the column decoder 320, respectively, for controlling various biases or activations of the corresponding access lines. In some examples, the row decoder 325 and the column decoder 320 may be components of the local controller 135, which may support access operations (e.g., writing logic states to the memory cells 305 or sensing logic states stored in the memory cells 305), as well as other operations and signaling thereof. The row decoder 325 and the column decoder 320 may be coupled to a controller 330 configured to perform various techniques of the BFEA scheme described herein. In various examples, the controller 330 may be included in the memory system controller 115, included in the local controller 135, or distributed between the memory system controller 115 and the local controller 135, as well as other configurations.

[0068] Memory cells 305 may be arranged physically or electrically within a block 170-a. In some examples, a subset of word lines 310 may be associated with respective WGRs 340. For example, word lines WLa1 through WLai may be associated with WGR 340-a, word lines WLb1 through WLbi may be associated with WGR 340-b, and word lines WLn1 through WLni may be associated with WGR 340-n. Although circuit 300 illustrates three (3) sets of WGRs 340, it may be understood that block 170-a may include any number of WGRs 340, and each WGR 340 may include any number of word lines 310. Thus, as used herein, a "block" may refer to an erasable portion of a memory device. A block may include one or more WGRs 340 associated with a set of word lines 310 and a plurality of memory cells 305.

[0069] In some examples, circuit 300 can be coupled to a host system (eg, reference 300) configured to send access commands to controller 330. Figure 1 The host system 105 described or referenced Figure 2 100-104) is coupled to the host system 205 described herein. An access command, which may be a read command or a write command, may be received by the controller 330 and may be decoded using the column decoder 320 and the row decoder 325. In some examples, the memory cells 305 of the block 170-a may be examples of multi-level cells each configured to store two or more bits of data. For example, a multi-level cell (MLC) may be capable of storing two (2) bits of data. In another example, a trilevel (or triple-level (TLC)) cell may be capable of storing three (3) bits of data. Thus, a TLC may store one of eight (8) potential voltage states representing different logical states (e.g., 000, 001, 010, 011, 100, 101, 110, and 111). To distinguish between the different states, the TLC may use seven (7) reference voltages. Thus, during a write operation, controller 330 may receive a command from the host system and may write data to one or more memory cells 305 of block 170-a. In some cases, a write command may cause data to be written to each memory cell 305 of WGR 340 or block 170-a.

[0070] After writing data to one or more memory cells 305 of block 170-a, controller 330 may initiate timing component 335. In some examples, timing component 335 may be used to determine the duration that data has been stored to the corresponding WGR 340 of block 170-a. For example, timing component 335 may determine (e.g., measure) the duration between when data is written to one or more memory cells of WGR 340 and when the data is subsequently read. Because data stored to any one memory cell 305 of WGR 340 may be represented by a charge, and because the charge may change over time (e.g., decrease due to leakage), timing component 335 may determine the duration that data has been stored to WGR 340, which may be used by controller 330 to adjust the value of one or more reference voltages used to determine the logic state written to memory cell 310. That is, adjusting the value of the reference voltage may allow circuit 300 to compensate for leakage based on WGR 340.

[0071] In some examples, the duration that data has been stored to block 170-a can be used to make an initial adjustment (e.g., a first adjustment) of one or more reference voltage values. For example, blocks 170 may be sorted into various bins based on the age of the data stored to the corresponding "bins." Thus, an initial adjustment of one or more reference voltage values ​​may be made for a block 170 based on which "bin" it is associated with. Thus, as used herein, a "bin" may refer to a logical grouping of data blocks 170 of the same or similar age for which one or more reference voltage values ​​are adjusted. For example, a first bin may represent data that has been stored for 1 to 2 hours, and a second bin may represent data that has been stored for 2 to 3 hours. Any time range may be associated with a bin. Because data may be written to each memory cell of block 170 during a single write operation, the data of the entire block 170 may be sorted into a single "bin," and thus one or more reference voltage values ​​of block 170 may be adjusted.

[0072] Circuit 300 may support any number of bins and each bin may be associated with a respective age range (e.g., a duration between when data was written to block 170 and the current time or when a read command for the data was received). In some examples, the ranges of bins may be preconfigured and may be stored (e.g., hard-coded) into a mapping that is managed or accessible by controller 330 or another component of memory device 130. The ranges may be set based on one or more test operations performed on memory device 130 and may be set to optimize the accuracy of reading data from memory cell 305 after various durations.

[0073] In addition, the reference voltage value adjustment performed by the controller 330 may refer to adjusting the voltage value of a "valley" that may be associated with the reference voltage. Different states stored by the memory cell may be characterized by a distribution of possible voltage thresholds for the particular state. Each state may have a 'normal' Gaussian distribution of voltage thresholds stored in the memory cell associated with each particular state. In this case, the reference voltage may be ideally located in the "valley" between the distributions of voltage thresholds associated with two adjacent states of the memory cell. For example, in order to determine whether a memory cell stores a first logic state or a second logic state, the charge stored to the corresponding memory cell 305 may be compared with a first reference voltage associated with the first logic state, the first reference voltage being positioned between a possible voltage level associated with the first logic state and a possible voltage level associated with the second logic state. Therefore, as used herein, a "valley" may refer to a midpoint voltage value between two logic states, which may be adjusted during BFEA operation as described herein. As an example, a memory cell configured to store three bits of data may be associated with seven (7) valley values ​​(e.g., seven midpoints between each of eight logic level values), and any of the valley values ​​(e.g., any of the reference voltage values) may be adjusted by a corresponding voltage value.

[0074] Additionally or alternatively, the controller 330 may be configured to make additional adjustments (e.g., a second adjustment) to one or more reference voltage values. For example, upon receiving a read command and determining the duration that data has been stored to the block 170, the controller 330 may adjust one or more reference voltage values ​​of the corresponding WGR. That is, the controller 330 may further adjust one or more reference voltage values ​​of each WGR 340 based on the duration that data has been stored to (or stored to) the corresponding memory cell 305 (in addition to the determined block-level adjustments). In some examples, the second adjustment may be a more granular adjustment than the first adjustment.

[0075] For example, the memory cells 305 associated with WGR 340-a may each be configured to store three bits of data, and thus the controller 330 may adjust the reference voltage values ​​of one or more of the word lines 310 WLa1 to WLai based on the age of the data stored to block 170-a. In some examples, the controller 330 may adjust only a subset of the reference voltage values ​​of WGR 340-a (e.g., the reference voltage values ​​associated with valleys 5 to 7). Additionally or alternatively, the controller 330 may adjust the reference voltages of the word lines 310 of WGR 340-b and WGR 340-n to the same or different voltage values. By adjusting the reference voltage values ​​based on WGR 340, the ability of the circuit 300 to accurately sense a set of memory cells 305 that have stored data for a relatively long duration may be improved.

[0076] Figure 4A An example of a block diagram 400-a that supports reference voltage adjustment for a word line group according to examples as disclosed herein. In some examples, block diagram 400-a may depict a mapping that is stored to a controller (e.g., reference Figure 3 The mapping may be stored in or accessible by the controller 330 described above and used by the controller to make a first adjustment of one or more reference voltage values ​​for the memory device. In some examples, the mapping may include reference voltage value adjustments for different valleys 405 (e.g., reference voltages used to distinguish different states stored by a memory cell) and bins 410 (e.g., time ranges for storing data in a memory cell). Although the mapping provides specific reference voltage adjustment values ​​for different valleys 405 and bins 410, Figure 4A The values ​​depicted in are for exemplary purposes only. Thus, a map may provide any set of reference voltage value adjustments to a controller or another component of a memory device, and the specific values ​​stored to the map may be a matter of design. Regardless of the specific values ​​stored to the map, adjusting the reference voltage values ​​of a memory device based on the duration that data has been stored to one or more memory cells may improve the ability of the memory device to accurately sense a set of memory cells that have stored data for a relatively long duration.

[0077] Figure 4A 1 and 2. The mapping illustrated in 2000 may include reference voltage value adjustments for respective valleys 405 and bins 410 associated with a block of a memory device (e.g., the mapping may be associated with a block-based adjustment of reference voltages for all memory cells within the block). As described herein, valley 405 may represent a midpoint voltage value between two states of a memory cell. For example, valley 405-a may be positioned between logic states 000 and 001, valley 405-b may be positioned between logic states 001 and 010, valley 405-c may be positioned between logic states 010 and 011, valley 405-d may be positioned between logic states 011 and 100, valley 405-e may be positioned between logic states 100 and 101, valley 405-f may be positioned between logic states 101 and 110, and valley 405-g may be positioned between logic states 110 and 111.

[0078] Therefore, although Figure 4ASeven (7) valleys are illustrated, but the map may include a different number of valleys 405. For example, seven (7) valleys may represent a TLC (e.g., a memory cell configured to store one of eight (8) logical states and thus associated with seven valleys), while three (3) valleys may represent an MLC, and one (1) valley may represent a single-level cell (SLC). Other configurations for other types of memory cells (e.g., SLC, MLC, TLC, QLC, etc.) may also be implemented. Thus, the number of valleys included in the map may depend on the type and configuration of the memory cells of the associated memory device.

[0079] In addition, the map may include multiple bins 410, which may refer to a logical arrangement (e.g., a logical grouping) of blocks of data having the same or similar age. For example, bin 410-a may be associated with a first age range (e.g., a first duration that data has been stored to one or more memory cells), bin 410-b may be associated with a second age range, and so on. In some cases, each subsequent bin 410 may be associated with relatively older data, and thus the associated memory cells may be less likely to retain a charge. That is, bin 410-g may be associated with a relatively higher reference voltage value adjustment than bin 410-a because the associated memory cells may be less likely to have retained the initial charge. Each bin 410 may be associated with a different age range, and the range of each bin 410 (and the number of bins 410 stored to the map) may be a matter of design.

[0080] In some examples, a controller of a memory device may make an initial reference voltage adjustment (e.g., a first adjustment) based on receiving a read command for data previously stored to a block of the memory device. For example, the controller may have started a timer when the data was initially written to the block. Thus, when a read command for the data is received, the controller may determine the age of the data based on the value of the timer (or based on the duration from the initial timestamp). In some examples, the controller may start (e.g., manage) multiple timers associated with different blocks of the memory device, and may determine which bin the corresponding data is associated with (e.g., which age range the value of the corresponding timer belongs to). In such an example, adjustments to the voltage value of the reference voltage may be made on a block-by-block basis (meaning that each reference voltage in the block may be adjusted).

[0081] In other examples, a controller or another component of the memory device may utilize a timestamp or another mechanism to determine a duration from when the data was initially written to the block and when a read command for the data was received. For example, the controller may record the time when the read command was received and may record when the corresponding write command was received. The controller may then determine the age of the data based on the duration between the respective timestamps.

[0082] After determining which bin the data of a block is associated with, the controller may adjust the reference voltage value (e.g., valley 405) of the corresponding block. As an example, the controller may determine (e.g., using a timer) that the data of the first block is associated with bin 410-a. Thus, the controller may adjust the reference voltage values ​​of valleys 1 to 7 (e.g., valleys 405-a to 405-g) by -20mV, -20mV, -40mV, -40mV, -50mV, -60mV, and -70mV, respectively. As described herein, these reference voltage value adjustments are merely exemplary, and the controller may adjust the reference voltage values ​​of valleys 1 to 7 by any value. After adjusting the reference voltage values ​​of the blocks, the controller (or another component of the memory device) may read the memory cells of the first block using the adjusted reference voltage values, however in some examples, the controller may make a second adjustment to the reference voltage values ​​(e.g., as a reference voltage) before performing a read operation. Figure 4B described).

[0083] Figure 4B An example of a block diagram 400-b illustrating reference voltage adjustment for a word line group according to examples as disclosed herein. In some examples, block diagram 400-b may depict a mapping that is stored to a controller (e.g., reference Figure 3 The mapping may include a second adjustment of one or more reference voltage values ​​for the memory device based on the duration 415 that data has been stored in the corresponding WGR 420 (e.g., the reference voltage value of the memory device). Figure 4A 405) of the valley value 405 described above. In such an example, the adjustment of the voltage value of the reference voltage can be made on a WGR-by-WGR basis (meaning that each reference voltage in the WGR can be adjusted). In some cases, block-based adjustment and WGR consideration-based adjustment can be utilized together. In such a case, a block level of adjustment can be determined, and then a WGR level adjustment can be made to further optimize the final voltage value of the reference voltage.

[0084] Although the mapping provides specific reference voltage adjustment values ​​for different WGRs 420, Figure 4B The values ​​depicted in are for exemplary purposes only. Figure 4BA mapping for adjusting a reference voltage value for a particular valley value may be specified, and thus an associated memory device may store different mappings for different valley values. Thus, a mapping may provide any set of reference voltage value adjustments to a controller or another component of the memory device, and the particular value (or number of mappings) stored to the mapping may be a matter of design. Regardless of the specific value stored to the mapping, adjusting the reference voltage value of the WGR of a memory device based on the duration that data has been stored to one or more memory cells may improve the ability of the memory device to accurately sense a set of memory cells that have stored data for a relatively long duration.

[0085] Figure 4B The mapping illustrated in FIG. 4 may include reference voltage value adjustments for WGR 420 based on the duration that data has been stored for the associated block. For example, the mapping may illustrate WGR0 420-a through WGR7 420-h, which may be reference voltage values. Figure 3 Each of the WGRs 420-a to 420-h may be associated with the same block, and the mapping may illustrate the reference voltage value adjustment of each WGR 420 for a particular valley. That is, based on the duration that data has been stored to one or more memory cells of the block, the reference voltage value of the WGR 420 of the block may be further adjusted for one or more valleys. In this way, Figure 4B The mapping described in can be configured to Figure 4A Used in conjunction with the mapping described in .

[0086] Figure 4B The mapping illustrated in further illustrates duration 1 415-a to duration 14 415-n. Each duration 415 may represent a time or time range (e.g., in hours) that data has been stored to the associated block. Thus, for exemplary purposes only, if data has been stored to one or more memory cells for the duration associated with duration 8 415-h, the reference voltage value of the WGR 420 of the block may be further adjusted (e.g., for a particular valley value) by 20 mV, 0 mV, 0 mV, 10 mV, 40 mV, 30 mV, 50 mV, and 80 mV.

[0087] Therefore, although Figure 4B Eight (8) WGRs 420 and fourteen (14) durations 415 are illustrated, but the map may include a different number of WGRs 420 and durations 415. That is, a block may include any number of WGRs, and that number of WGRs may be included in the map. Furthermore, the map may include any number of durations 415 (e.g., any number of age ranges), which may be a matter of design. However, in some cases, the map may be used to represent the number of WGRs 420 and durations 415. Figure 4B The mapping described may include Figure 4AThat is, the second adjustment made to the reference voltage values ​​of the various WGRs may be more granular than the first adjustment made to the reference voltage values ​​of the blocks.

[0088] In some cases, Figure 4B The reference voltage adjustments described in 420-c may be made relative to a single WGR 420. For example, the reference voltage adjustments may be made relative to WGR2 420-c, and thus the reference voltage value of WGR2 420-c may not be further adjusted. The WGR 420 relative to which the reference voltage adjustments are made may be a matter of design choice based on the ability of the memory cells of the WGR 420 to retain a corresponding charge over time. Additionally, the reference voltage adjustments may be made relative to the memory cells of the WGR 420. Figure 4A The single valley value 405 described is performed Figure 4B Therefore, Figure 4B The mappings illustrated in may illustrate reference voltage adjustments for valley 7 405-g, but the associated memory device may include corresponding mappings for further adjusting reference voltage values ​​for any valley 405. In some cases, the memory device may include at least three (3) mappings for further adjusting reference voltage values ​​for valley 5 405-e, valley 6 405-f, and valley 7 405-g based on WGR 420. Each mapping may include different reference voltage value adjustments than the other mappings.

[0089] In some examples, a controller of a memory device may perform a reference Figure 4A The described first adjustment is followed by a second reference voltage adjustment. For example, the controller may reference a timer (e.g., a value of a timer) used to make the first adjustment. After determining which duration 415 the data is associated with, the controller may further adjust the reference voltage values ​​of the WGR 420 of the block. As an example, the controller may determine that the data of the first block is associated with the duration 415-e, and may further adjust the reference voltage values ​​of WGR0 420-a to 420-h (e.g., for valley 7) by -20mV, 0mV, 0mV, -10mV, -30mV, -30mV, -40mV, and -70mV. After adjusting the reference voltage values ​​of WGR 420, the controller (or another component of the memory device) may read the memory cells of the first block using the adjusted reference voltage values.

[0090] In other examples, Figure 4BThe mapping illustrated in FIG. 4 may not include voltage values ​​(e.g., values ​​by which the reference voltage value is adjusted), and may instead include indicators for increasing or decreasing the bin 410 associated with the initial adjustment. For example, data associated with a block may be associated with bin 4 410-d, and the reference voltage value of each of the valleys 405 may be adjusted accordingly. However, when the reference voltage value is adjusted a second time (e.g., using the value specified by Figure 4B 1 ), as an example, the adjustment may be changed to bin +1 or bin -1. That is, if the data associated with the first block is associated with duration 415-e, the reference voltage values ​​of WGR0 420-a through WGR7 420-h for valley 7 may be adjusted by -340 mV (e.g., bin +1) or -210 mV (e.g., bin -1).

[0091] Depend on Figure 4B The described mapping can support bin + / - N adjustments, where N is less than the bin size contained in Figure 4A Any integer representing the total number of bins in the specified map. Figure 4B Whether the illustrated mapping includes voltage values ​​or bin + / -N adjustment values, utilizing a BFEA scheme on a WGR basis can improve the ability of an associated system to accurately sense a set of memory cells that have stored data for relatively long durations.

[0092] Figure 5 An example of a process flow diagram 500 for supporting reference voltage adjustment of a word line group according to examples as disclosed herein is illustrated. In some examples, the process flow diagram 500 may implement the process described herein with reference to Figure 3 , 4A 4B. Thus, the operations illustrated by process flow diagram 500 may be performed at or by host device 505 and memory system 510. In some cases, memory system 510 may include timer 515, memory controller 520, and one or more memory devices 525. Memory system 510 may support BFEA operations at both the block level and the WGR level, as described in reference to FIG. Figure 4A and 4B Performing a BFEA scheme on a WGR basis can improve the ability of the memory system 510 to accurately sense a set of memory cells that have stored data for a relatively long duration.

[0093] At 530, the host device 505 may transmit a write command to the memory system 510. The write command may be received by the memory controller 520 and may include data to be written to one or more memory cells of the memory device 525. In some cases, the write command may include data to be written to a block of memory cells of the memory device 525. At 535, the memory controller 520 may write the data to the address of the memory device 525 included in the write command.

[0094] At 540, the memory controller 520 may transmit signaling to the timer 515. The signaling may include instructions to start or may otherwise start the timer 515 based on writing data to the memory device 525 (e.g., at 535). In some cases, the timer 515 may be included in the memory controller 520, and thus the memory controller 520 may not transmit the signaling, and may instead start the timer based on writing data to the memory device 525. At 545, the timer 515 may be started. In some cases, the timer 515 may be started simultaneously with writing data to the memory device 525 (e.g., at 535).

[0095] At 550, the host device 505 may transmit a read command to the memory system 510. The read command may be received by the memory controller 520 and may be used for data previously written to the memory device 525 (eg, at 535).

[0096] At 555, the memory controller 520 may transmit signaling to the timer 515. The signaling may include a request to stop the timer 515 and transmit the value of the timer 515 to the memory controller 520. The value of the timer may be or may represent the duration that the data is stored to the memory device 525 (e.g., the age of the data). In some cases, the timer 515 may be included in the memory controller 520 and thus the memory controller 520 may not transmit the signaling, and may instead stop the timer 515 and determine its value. At 560, the timer 515 may transmit the value (e.g., the duration) to the memory controller 520.

[0097] At 565, the memory controller 520 may initiate a first reference voltage adjustment based on the value of the timer (eg, received at 560). The first reference voltage adjustment may be performed using a timer configured to adjust the reference voltage. Figure 4A Described and referenced Figure 4A That is, the adjustment may be made to the reference voltage value (e.g., reference Figure 4A The valley values ​​405 described above are performed and can be based on the age of the data and which bin (e.g., reference Figure 4A Which warehouse 410) is described?

[0098] At 570, the memory controller 520 may initiate a second reference voltage adjustment for the WGR of the block based on the value of the timer (eg, received at 560). The second reference voltage adjustment may be performed using the timer value determined by Figure 4B Described and referenced Figure 4B That is, one or more valley values ​​(e.g., reference Figure 4A The reference voltage value of the WGR of the block is adjusted by the valley value 405 described above. In some cases, the mapping referenced by the memory controller 520 may include actual voltage values, while in other examples, the mapping may utilize the bin + / - N method as described herein.

[0099] At 575, the memory controller 520 may read data from the memory device 525 using the adjusted reference voltage value. At 580, the data may be communicated from the memory device 525 to the memory controller 520. At 585, the data may be transmitted from the memory controller 520 to the host device 505, thereby satisfying the read command. As described herein, performing a BFEA scheme on a WGR basis may improve the ability of the memory system 510 to accurately sense a set of memory cells that have stored data for a relatively long duration.

[0100] Figure 6 A block diagram 600 is shown of a memory device 620 that supports reference voltage adjustment of a word line group according to examples as disclosed herein. The memory device 620 may be a memory device as described in reference to FIG. Figures 1 to 5 Memory device 620 or its various components may be examples of means for performing various aspects of reference voltage adjustment of WGR as described herein. For example, memory device 620 may include a write component 625, a read component 630, a timing component 635, a reference voltage value adjustment component 640, a threshold voltage component 645, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0101] The write component 625 may be configured as or otherwise support means for writing data to at least one memory cell of a first plurality of memory cells at a first time, wherein the first plurality of memory cells are coupled to a first word line associated with a block of memory cells.

[0102] The read component 630 may be configured as or otherwise support means for initiating a read operation to read data based at least in part on writing the data at a second time after the first time. In some examples, the read component 630 may be configured as or otherwise support means for reading data from at least one memory cell associated with the first word line based at least in part on adjusting the first plurality of reference voltage values ​​and the second plurality of reference voltage values. In some examples, the read component 630 may be configured as or otherwise support means for receiving a read command to read the data, wherein initiating the read operation is based at least in part on receiving the read command.

[0103] The timing component 635 can be configured as or otherwise support means for determining a duration between the first time and the second time based at least in part on starting the read operation. In some examples, the timing component 635 can be configured as or otherwise support means for starting a timer based at least in part on writing data to at least one memory cell of the first plurality of memory cells at the first time, wherein the duration between the first time and the second time is based at least in part on starting the timer.

[0104] The reference voltage value adjustment component 640 may be configured as or otherwise support a component for adjusting a first plurality of reference voltage values ​​of a first plurality of reference voltages associated with a first word line associated with a block of stored data and a second plurality of reference voltage values ​​of a second plurality of reference voltages associated with a second word line associated with the block of stored data based at least in part on determining a duration between a first time and a second time, wherein the first plurality of reference voltage values ​​are different from the second plurality of reference voltage values.

[0105] In some examples, the reference voltage value adjustment component 640 may be configured as or otherwise support means for determining a first adjustment set of a third plurality of reference voltage values ​​based at least in part on a duration between a first time and a second time, the first adjustment set being used by each memory cell in the block of memory cells, wherein the third plurality of reference voltage values ​​includes a first plurality of reference voltage values ​​and a second plurality of reference voltage values, and wherein adjusting the first plurality of reference voltage values ​​and the second plurality of reference voltage values ​​is based at least in part on the first adjustment set.

[0106] In some examples, the reference voltage value adjustment component 640 may be configured as or otherwise support means for determining a second adjustment set of the first plurality of reference voltage values ​​based at least in part on determining the first adjustment set, wherein the second adjustment set includes adjusting a respective plurality of reference voltage values ​​for each word line associated with the block of memory cells, and wherein adjusting the first plurality of reference voltage values ​​is based at least in part on the second adjustment set.

[0107] In some examples, to support determining a second adjustment set of the first plurality of reference voltage values, the reference voltage value adjustment component 640 may be configured as or otherwise support means for adjusting the first plurality of reference voltage values ​​associated with the first plurality of memory cells. In some examples, to support determining a second adjustment set of the first plurality of reference voltage values, the reference voltage value adjustment component 640 may be configured as or otherwise support means for refraining from adjusting the second plurality of reference voltage values ​​associated with the second plurality of memory cells.

[0108] In some examples, the reference voltage value adjustment component 640 may be configured as or otherwise support means for determining a second adjustment set of a third plurality of reference voltage values ​​based at least in part on determining a second adjustment set of a third plurality of reference voltage values ​​associated with the block of memory cells, wherein adjusting the first plurality of reference voltages associated with the first plurality of memory cells is based at least in part on determining the second adjustment set of the third plurality of reference voltage values.

[0109] In some examples, the reference voltage value adjustment component 640 may be configured as or otherwise support means for identifying an adjustment index associated with a first word line associated with the block based at least in part on determining a duration between a first time and a second time, wherein the adjustment index indicates a third adjustment set of a third plurality of reference voltage values, and wherein adjusting the first plurality of reference voltage values ​​is based at least in part on the third adjustment set.

[0110] In some examples, to support adjusting the first plurality of reference voltages associated with the first plurality of memory cells, the reference voltage value adjustment component 640 may be configured as or otherwise support means for adjusting the value of the first reference voltage by a first value. In some examples, to support adjusting the first plurality of reference voltages associated with the first plurality of memory cells, the reference voltage value adjustment component 640 may be configured as or otherwise support means for adjusting the value of the second reference voltage by a second value different from the first value.

[0111] In some examples, threshold voltage component 645 can be configured as or otherwise support means for determining that an adjustment of the first plurality of reference voltage values ​​exceeds an adjustment of the threshold voltage value based at least in part on determining a duration between the first time and the second time.

[0112] In some examples, a first reference voltage of the first plurality of reference voltages distinguishes between a first state and a second state storable by the memory cell, and a second reference voltage of the first plurality of reference voltages distinguishes between the second state and a third state storable by the memory cell.

[0113] In some instances, the memory cells are configured to store three bits of information using eight states. In some instances, at least the first plurality of memory cells are not accessed during a duration between the first time and the second time. In some instances, a second plurality of memory cells coupled to the second word line is associated with the memory cell block.

[0114] Figure 7 A flow chart illustrating a method 700 for supporting reference voltage adjustment of a word line group according to an example as disclosed herein is shown. The operations of the method 700 may be implemented by a memory device or components thereof as described herein. For example, the method 700 may be implemented by a memory device or components thereof as described herein. Figures 1 to 6 The described memory device performs the operations of method 700. In some examples, the memory device may execute instruction sets to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0115] At 705, the method may include writing data to at least one memory cell of a first plurality of memory cells at a first time, wherein the first plurality of memory cells are coupled to a first word line associated with a block of memory cells. The operation of 705 may be performed according to examples as disclosed herein. In some examples, the operation may be performed by reference to Figure 6 Aspects of the operations of write component 625 performing 705 are described.

[0116] At 710, the method may include initiating a read operation to read the data at a second time after the first time based at least in part on writing the data. The operation of 710 may be performed according to examples disclosed herein. In some examples, the operation may be performed as described in reference to Figure 6 Aspects of the operations of the read component 630 are described as performing 710 .

[0117] At 715, the method may include determining a duration between the first time and the second time based at least in part on the start of the read operation. The operation of 715 may be performed according to examples disclosed herein. In some examples, the operation may be performed by referring to Figure 6 Aspects of the operations of the timing component 635 described above are performed by 715 .

[0118] At 720, the method may include adjusting a first plurality of reference voltage values ​​associated with a first word line associated with a block storing data and a second plurality of reference voltage values ​​associated with a second word line associated with a block storing data based at least in part on determining a duration between the first time and the second time, wherein the first plurality of reference voltage values ​​are different from the second plurality of reference voltage values. The operation of 720 may be performed according to examples as disclosed herein. In some examples, the operation may be performed by a method as described in reference to Figure 6Aspects of the operation of the reference voltage value adjustment component 640 are described as performing 720 .

[0119] At 725, the method may include reading data from at least one memory cell associated with the first word line based at least in part on adjusting the first plurality of reference voltage values ​​and the second plurality of reference voltage values. The operation of 725 may be performed according to examples as disclosed herein. In some examples, the operation may be performed by the reference Figure 6 Aspects of the operations of the read component 630 are described as performing 725 .

[0120] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0121] Aspect 1: A method, apparatus, or non-transitory computer-readable medium, comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: writing data to at least one memory cell of a first plurality of memory cells at a first time, wherein the first plurality of memory cells are coupled to a first word line associated with a block of memory cells; initiating a read operation at a second time after the first time to read the data based at least in part on writing the data; determining a duration between the first time and the second time based at least in part on initiating the read operation; adjusting a first plurality of reference voltage values ​​of a first plurality of reference voltages associated with the first word line associated with the block storing the data, and a second plurality of reference voltage values ​​of a second plurality of reference voltages associated with a second word line associated with the block storing the data based at least in part on determining the duration between the first time and the second time, wherein the first plurality of reference voltage values ​​are different from the second plurality of reference voltage values; and reading the data from the at least one memory cell associated with the first word line based at least in part on adjusting the first plurality of reference voltage values ​​and the second plurality of reference voltage values.

[0122] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for the following operations: determining a first adjustment set of a third plurality of reference voltage values ​​based at least in part on the duration between the first time and the second time, the first adjustment set being used by each memory cell in the memory cell block, wherein the third plurality of reference voltage values ​​include the first plurality of reference voltage values ​​and the second plurality of reference voltage values, and wherein adjusting the first plurality of reference voltage values ​​and the second plurality of reference voltage values ​​is based at least in part on the first adjustment set.

[0123] Aspect 3: The method, apparatus or non-transitory computer-readable medium according to Aspect 2, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for the following operations: determining a second adjustment set of the first plurality of reference voltage values ​​based at least in part on determining the first adjustment set, wherein the second adjustment set includes adjusting a corresponding plurality of reference voltage values ​​for each word line associated with the memory cell block, and wherein adjusting the first plurality of reference voltage values ​​is based at least in part on the second adjustment set.

[0124] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to Aspect 3, wherein determining the second adjustment set of the first plurality of reference voltage values ​​includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for the following operations: adjusting the first plurality of reference voltage values ​​associated with the first plurality of memory cells; and refraining from adjusting the second plurality of reference voltage values ​​associated with the second plurality of memory cells.

[0125] Aspect 5: A method, apparatus or non-transitory computer-readable medium according to any one of Aspects 2 to 4, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for the following operations: determining that the adjustment of the first plurality of reference voltage values ​​exceeds the threshold voltage value adjustment based at least in part on determining the duration between the first time and the second time; and determining the second adjustment set of the third plurality of reference voltage values ​​based at least in part on determining a second adjustment set of the third plurality of reference voltage values ​​associated with the memory cell block, wherein adjusting the first plurality of reference voltages associated with the first plurality of memory cells is based at least in part on determining the second adjustment set of the third plurality of reference voltage values.

[0126] Aspect 6: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 2 to 5, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for the following operations: based at least in part on determining the duration between the first time and the second time, identifying an adjustment index associated with the first word line associated with the block, wherein the adjustment index indicates a third adjustment set of the third plurality of reference voltage values, and wherein adjusting the first plurality of reference voltage values ​​is based at least in part on the third adjustment set.

[0127] Aspect 7: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for the following operations: starting a timer based at least in part on writing the data to at least one of the first plurality of memory cells at the first time, wherein the duration between the first time and the second time is based at least in part on starting the timer.

[0128] Aspect 8: A method, apparatus, or non-temporary computer-readable medium according to any one of Aspects 1 to 7, wherein a first reference voltage among the first plurality of reference voltages distinguishes between a first state and a second state that can be stored by a memory cell, and a second reference voltage among the first plurality of reference voltages distinguishes between the second state and a third state that can be stored by the memory cell.

[0129] Aspect 9: The method, apparatus, or non-transitory computer-readable medium of aspect 8, wherein the memory cell is configured to store three bits of information using eight states.

[0130] Aspect 10: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 8 to 9, wherein adjusting the first plurality of reference voltages associated with the first plurality of memory cells includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: adjusting the value of the first reference voltage by a first value; and adjusting the value of the second reference voltage by a second value different from the first value.

[0131] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 to 10, wherein at least the first plurality of memory cells are not accessed during the duration between the first time and the second time.

[0132] Aspect 12: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1 to 11, wherein a second plurality of memory cells coupled to the second word line are associated with the block of memory cells.

[0133] Aspect 13: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 12, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for the following operations: receiving a read command to read the data, wherein initiating the read operation is based at least in part on receiving the read command.

[0134] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0135] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0136] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be open or closed based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0137] The term "coupled" refers to a condition of moving from an open circuit relationship between components, in which signals are currently unable to communicate between the components via a conductive path, to a closed circuit relationship between the components, in which signals are able to communicate between the components via the conductive path. If a component, such as a controller, couples other components together, then the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

[0138] The term "isolation" refers to a relationship between components where a signal is currently unable to flow between the components. If an open circuit exists between the components, then the components are isolated from each other. For example, components separated by a switch located between two components are isolated from each other when the switch is open. If a controller isolates two components, then the controller implements the following changes: the signal is prevented from flowing between the components using the conductive path that previously permitted the signal to flow.

[0139] As used herein, the term "layer" or "level" refers to a number or piece of a geometric structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a film. A layer or level may include different elements, components, and / or materials. In some examples, a layer or level may be composed of two or more sub-layers or sub-levels.

[0140] The terms "if," "when," "based on," or "based at least in part on" are used interchangeably. In some instances, if the terms "if," "when," "based on," or "based at least in part on" are used to describe a conditional action, a conditional process, or a connection between parts of a process, the terms are interchangeable.

[0141] In addition, the term "directly in response to" or "directly in response to" may refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action that is independent of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, so that no other intermediate conditions or actions occur between an earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between an earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on", "at least partially based on" or "in response to" some other step, action, event or condition may be performed in addition or alternatively (e.g., in an alternative instance) "directly in response to" or "directly in response to" such other condition or action.

[0142] The devices including memory arrays discussed herein may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping means.

[0143] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may make the channel conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "cut off" or "deactivated".

[0144] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferable" or "advantageous" over other examples. The specific implementation includes specific details that provide an understanding of the described technology. However, these technologies may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form in order to avoid confusing the concepts of the described examples.

[0145] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0146] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features implementing the functions may also be physically located at various locations, including distribution so that parts of the functions are implemented at different physical locations.

[0147] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or another programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0148] As used herein, including in the claims, "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list such as at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based at least in part on."

[0149] Computer-readable media include both non-transitory computer storage media and communication media, including any media that helps to transfer a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. As an example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage device, or can be used to carry or store required program code components in the form of instructions or data structures and can be accessed by a general or special computer, or any other non-transitory media accessed by a general or special processor. In addition, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or another remote source, then the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of media. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0150] The description herein is provided to enable a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a controller associated with the memory device, wherein the controller is configured to cause the apparatus to: writing data to at least one memory cell of a first plurality of memory cells at a first time, wherein the first plurality of memory cells are coupled to a first word line associated with a block of memory cells; initiating a read operation to read the data at a second time after the first time based at least in part on writing the data; determining a duration between the first time and the second time based at least in part on initiating the read operation; adjusting, based at least in part on determining the duration between the first time and the second time, a first plurality of reference voltage values ​​of a first plurality of reference voltages associated with the first word line associated with the block storing the data and a second plurality of reference voltage values ​​of a second plurality of reference voltages associated with a second word line associated with the block storing the data, wherein the first plurality of reference voltage values ​​are different than the second plurality of reference voltage values; as well as The data is read from the at least one memory cell associated with the first word line based at least in part on adjusting the first plurality of reference voltage values ​​and the second plurality of reference voltage values.

2. The device of claim 1, wherein the controller is further configured to cause the device to: Based at least in part on the duration between the first time and the second time, determining a first adjustment set of a third plurality of reference voltage values, the first adjustment set being used by each memory cell in the block of memory cells, wherein the third plurality of reference voltage values ​​includes the first plurality of reference voltage values ​​and the second plurality of reference voltage values, and wherein adjusting the first plurality of reference voltage values ​​and the second plurality of reference voltage values ​​is based at least in part on the first adjustment set.

3. The device of claim 2, wherein the controller is further configured to cause the device to: Based at least in part on determining the first adjustment set, a second adjustment set of the first plurality of reference voltage values ​​is determined, wherein the second adjustment set includes adjusting a respective plurality of reference voltage values ​​for each word line associated with the block of memory cells, and wherein adjusting the first plurality of reference voltage values ​​is based at least in part on the second adjustment set.

4. The apparatus of claim 3, wherein determining the second adjusted set of the first plurality of reference voltage values ​​is configured such that the apparatus: adjusting the first plurality of reference voltage values ​​associated with the first plurality of memory cells; and Adjustment of the second plurality of reference voltage values ​​associated with a second plurality of memory cells is refrained.

5. The device of claim 2, wherein the controller is further configured to cause the device to: determining that an adjustment of the first plurality of reference voltage values ​​exceeds a threshold voltage value adjustment based at least in part on determining the duration between the first time and the second time; and determining the second adjusted set of the third plurality of reference voltage values ​​associated with the block of memory cells based at least in part on determining a second adjusted set of the third plurality of reference voltage values, wherein adjusting the first plurality of reference voltages associated with the first plurality of memory cells is based at least in part on determining the second adjusted set of the third plurality of reference voltage values.

6. The device of claim 2, wherein the controller is further configured to cause the device to: Based at least in part on determining the duration between the first time and the second time, identifying an adjustment index associated with the first word line associated with the block, wherein the adjustment index indicates a third adjustment set of the third plurality of reference voltage values, and wherein adjusting the first plurality of reference voltage values ​​is based at least in part on the third adjustment set.

7. The device of claim 1, wherein the controller is further configured to cause the device to: A timer is initiated based at least in part on writing the data to the at least one memory cell of the first plurality of memory cells at the first time, wherein the duration between the first time and the second time is based at least in part on initiating the timer.

8. The apparatus of claim 1 , wherein a first reference voltage of the first plurality of reference voltages distinguishes between a first state and a second state that can be stored by a memory cell, and a second reference voltage of the first plurality of reference voltages distinguishes between the second state and a third state that can be stored by the memory cell.

9. The apparatus of claim 8, wherein: The memory cell is configured to store three bits of information using eight states.

10. The apparatus of claim 8, wherein adjusting the first plurality of reference voltages associated with the first plurality of memory cells is configured such that the apparatus: adjusting the value of the first reference voltage by a first value; and The value of the second reference voltage is adjusted to a second value different from the first value.

11. The apparatus of claim 1, wherein at least the first plurality of memory cells are not accessed during the duration between the first time and the second time.

12. The apparatus of claim 1, wherein a second plurality of memory cells coupled to the second word line are associated with the block of memory cells.

13. The device of claim 1, wherein the controller is further configured to cause the device to: A read command is received to read the data, wherein initiating the read operation is based at least in part on receiving the read command.

14. A non-transitory computer-readable medium storing code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: writing data to at least one memory cell of a first plurality of memory cells at a first time, wherein the first plurality of memory cells are coupled to a first word line associated with a block of memory cells; initiating a read operation to read the data at a second time after the first time based at least in part on writing the data; determining a duration between the first time and the second time based at least in part on initiating the read operation; adjusting, based at least in part on determining the duration between the first time and the second time, a first plurality of reference voltage values ​​of a first plurality of reference voltages associated with the first word line associated with the block storing the data and a second plurality of reference voltage values ​​of a second plurality of reference voltages associated with a second word line associated with the block storing the data, wherein the first plurality of reference voltage values ​​are different than the second plurality of reference voltage values; as well as The data is read from the at least one memory cell associated with the first word line based at least in part on adjusting the first plurality of reference voltage values ​​and the second plurality of reference voltage values.

15. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Based at least in part on the duration between the first time and the second time, determining a first adjustment set of a third plurality of reference voltage values, the first adjustment set being used by each memory cell in the block of memory cells, wherein the third plurality of reference voltage values ​​includes the first plurality of reference voltage values ​​and the second plurality of reference voltage values, and wherein adjusting the first plurality of reference voltage values ​​and the second plurality of reference voltage values ​​is based at least in part on the first adjustment set.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Based at least in part on determining the first adjustment set, a second adjustment set of the first plurality of reference voltage values ​​is determined, wherein the second adjustment set includes adjusting a respective plurality of reference voltage values ​​for each word line associated with the block of memory cells, and wherein adjusting the first plurality of reference voltage values ​​is based at least in part on the second adjustment set.

17. The non-transitory computer-readable medium of claim 16, wherein the instructions to determine the second adjusted set of the first plurality of reference voltage values, when executed by the processor of the electronic device, further cause the electronic device to: adjusting the first plurality of reference voltage values ​​associated with the first plurality of memory cells; and Adjustment of the second plurality of reference voltage values ​​associated with a second plurality of memory cells is refrained.

18. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: determining that an adjustment of the first plurality of reference voltage values ​​exceeds a threshold voltage value adjustment based at least in part on determining the duration between the first time and the second time; and determining the second adjusted set of the third plurality of reference voltage values ​​associated with the block of memory cells based at least in part on determining a second adjusted set of the third plurality of reference voltage values, wherein adjusting the first plurality of reference voltages associated with the first plurality of memory cells is based at least in part on determining the second adjusted set of the third plurality of reference voltage values.

19. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Based at least in part on determining the duration between the first time and the second time, identifying an adjustment index associated with the first word line associated with the block, wherein the adjustment index indicates a third adjustment set of the third plurality of reference voltage values, and wherein adjusting the first plurality of reference voltage values ​​is based at least in part on the third adjustment set.

20. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A timer is initiated based at least in part on writing the data to the at least one memory cell of the first plurality of memory cells at the first time, wherein the duration between the first time and the second time is based at least in part on initiating the timer.

21. The non-transitory computer-readable medium of claim 14, wherein a first reference voltage of the first plurality of reference voltages distinguishes between a first state and a second state capable of being stored by a memory cell, and a second reference voltage of the first plurality of reference voltages distinguishes between the second state and a third state capable of being stored by the memory cell.

22. The non-transitory computer-readable medium of claim 21, wherein: The memory cell is configured to store three bits of information using eight states.

23. The non-transitory computer-readable medium of claim 21, wherein the instructions to adjust the first plurality of reference voltages associated with the first plurality of memory cells, when executed by the processor of the electronic device, further cause the electronic device to: adjusting the value of the first reference voltage by a first value; and The value of the second reference voltage is adjusted to a second value different from the first value.

24. The non-transitory computer-readable medium of claim 14, wherein at least the first plurality of memory cells are not accessed during the duration between the first time and the second time.

25. A method comprising: writing data to at least one memory cell of a first plurality of memory cells at a first time, wherein the first plurality of memory cells are coupled to a first word line associated with a block of memory cells; initiating a read operation to read the data at a second time after the first time based at least in part on writing the data; determining a duration between the first time and the second time based at least in part on initiating the read operation; adjusting, based at least in part on determining the duration between the first time and the second time, a first plurality of reference voltage values ​​of a first plurality of reference voltages associated with the first word line associated with the block storing the data and a second plurality of reference voltage values ​​of a second plurality of reference voltages associated with a second word line associated with the block storing the data, wherein the first plurality of reference voltage values ​​are different than the second plurality of reference voltage values; as well as The data is read from the at least one memory cell associated with the first word line based at least in part on adjusting the first plurality of reference voltage values ​​and the second plurality of reference voltage values.

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