Memory devices and their operation methods

Abstract

This document provides a memory device and a method of operating the same. The memory device may include: a plurality of memory cells; a programming operation executor configured to perform a plurality of programming cycles on the plurality of memory cells; a step voltage calculator configured to calculate a step voltage, which is the amplitude difference between programming voltages applied in any two consecutive programming cycles; a reference bit determiner configured to determine a reference failure number based on the amplitude of the step voltage; and a verification result generator configured to generate verification result information based on a comparison between the reference failure number and the number of conducting cells identified in verification operations included in the programming cycles of the plurality of memory cells.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to electronic devices, and more specifically, to memory devices and methods of operating the memory devices. Background Technology

[0002] Memory devices are storage devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Memory devices are broadly classified into volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices are memory devices in which stored data is lost when power is interrupted. Representative examples of volatile memory devices include Static Random Access Memory (SRAM), Dynamic RAM (DRAM), and Synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices in which stored data is retained even when power is interrupted. Representative examples of non-volatile memory devices include Read-Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Flash Memory, Phase-Change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), and Ferroelectric RAM (FRAM). Flash Memory is basically classified into NOR and NAND types. Summary of the Invention

[0004] Embodiments of this disclosure may provide a memory device. The memory device may include: a plurality of memory cells; a programming operation executor configured to perform a plurality of programming cycles on the plurality of memory cells; a step voltage calculator configured to calculate a step voltage, the step voltage being the amplitude difference between programming voltages applied in any two consecutive programming cycles within the plurality of programming cycles; a reference bit determiner configured to determine a reference failure number based on the amplitude of the step voltage; and a verification result generator configured to generate verification result information based on a comparison between the reference failure number and the number of conducting cells identified in verification operations included in the programming cycles within the plurality of memory cells.

[0005] Embodiments of this disclosure may provide a method for operating a memory device comprising a plurality of memory cells. The method may include: performing a plurality of programming cycles on the plurality of memory cells; calculating a step voltage, the step voltage being the amplitude difference between programming voltages applied in any two consecutive programming cycles within the plurality of programming cycles; determining a reference failure number based on the amplitude of the step voltage; and generating verification result information based on a comparison between the reference failure number and the number of active cells identified in verification operations included in the programming cycles within the plurality of programming cycles.

[0006] Embodiments of this disclosure may provide a memory device. The memory device may include a plurality of memory cells; a programming operation executor configured to perform a plurality of programming cycles on the plurality of memory cells; and a verification result generator configured to generate verification result information based on a comparison between a reference failure bit count and the number of conducting cells identified in verification operations included in each of the plurality of memory cells within the plurality of programming cycles, wherein the magnitude of the programming voltage used in each of the plurality of programming cycles increases by a step voltage for each subsequent programming cycle in the plurality of programming cycles, and the reference failure bit count has a larger number of bits as the magnitude of the step voltage increases. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0008] Figure 2 This is an example Figure 1 A diagram of the structure of a memory device.

[0009] Figure 3 This is an example Figure 2 A diagram showing the structure of any one of the multiple storage blocks BLK1 to BLKz.

[0010] Figure 4 This is a diagram illustrating the threshold voltage distribution of multiple memory cells based on the programming operations of the memory device.

[0011] Figure 5 This is a diagram illustrating the programming operations of a memory device.

[0012] Figure 6 This is a diagram illustrating the verification operation in the programming operation of a memory device.

[0013] Figure 7 This is a diagram illustrating the programming operation of a memory device according to an embodiment of the present disclosure.

[0014] Figure 8This is a diagram illustrating a programmable voltage information storage device.

[0015] Figure 9 This is a diagram illustrating the first reference bit depth corresponding to the amplitude of the step voltage.

[0016] Figure 10 This is a diagram illustrating the second reference bit position corresponding to the number of programming and erasing operations.

[0017] Figure 11 This is a diagram illustrating the third reference bit position corresponding to the word line position.

[0018] Figure 12 This is a diagram illustrating the reference failure bit count determined by taking into account the step voltage magnitude, the number of programming and erasing operations, and the word line position.

[0019] Figure 13 This is a flowchart illustrating the programming operation of a memory device according to an embodiment of the present disclosure.

[0020] Figure 14 This is a block diagram illustrating a memory card system that applies a memory system according to an embodiment of the present disclosure.

[0021] Figure 15 This is a block diagram illustrating a solid-state drive (SSD) system that applies a memory system according to an embodiment of the present disclosure.

[0022] Figure 16 This is a block diagram illustrating a user system that applies a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0023] Specific structural or functional descriptions of embodiments of the present disclosure as illustrated in this specification or application are provided to describe implementations based on the concept of the present disclosure. Implementations based on the concept of the present disclosure may be practiced in various forms and should not be construed as limited to the implementations described in this specification or application.

[0024] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0025] Reference Figure 1 The memory system 50 may include a memory device 100 and a memory controller 200. The memory system 50 may be a device for storing data under the control of a host 300, such as a mobile phone, smartphone, MP3 player, laptop, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0026] The memory system 50 can be manufactured as any of a variety of storage devices based on a host interface that serves as a means of communication with the host 300. For example, the memory system 50 can be implemented as any of a variety of storage devices, such as solid-state drives (SSDs), multimedia cards (such as MMC, embedded MMC (eMMC), miniaturized MMC (RS-MMC), or micro MMC), secure digital cards (such as SD, mini SD, or micro SD), universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, high-speed PCI (PCI-E) card-type storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0027] The memory system 50 can be manufactured in any of a variety of package types, such as POP, SIP, SOC, MCP, COB, WFP, or WSP.

[0028] The memory device 100 can store data. The memory device 100 can operate in response to the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) comprising a plurality of memory cells for storing data.

[0029] Each of the multiple memory cells can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0030] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A single memory block may include multiple pages. In an embodiment, a page may be a unit for storing or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0031] In embodiments, the memory device 100 may be implemented as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive RAM (RRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Transfer Torque RAM (STT-RAM). For ease of description, this specification assumes that the memory device 100 is NAND flash memory.

[0032] Memory device 100 can receive commands and addresses from memory controller 200 and can access a region of the memory cell array selected by an address. Memory device 100 can perform operations instructed by commands on the region selected by the address. For example, memory device 100 can perform write operations (i.e., programming operations), read operations, and erase operations. During a write operation, memory device 100 can program data into the region selected by the address. During a read operation, memory device 100 can read data from the region selected by the address. During an erase operation, memory device 100 can erase data stored in the region selected by the address.

[0033] In an implementation, the programming operation may include multiple programming cycles. Each programming cycle may include a programming voltage application operation and a verification operation. The programming voltage application operation may be an operation of increasing a threshold voltage of multiple memory cells by using a programming voltage. The verification operation may be an operation of identifying whether the threshold voltage of each memory cell has reached the threshold voltage corresponding to a target programming state. In an implementation, the verification operation may be performed for each of the multiple programming states. Verification operations for all programming states may be performed in each programming cycle, or alternatively, verification operations for all programming states may be performed only in a preset programming cycle. In other implementations, a programming state corresponding to the verification operation to be performed in each programming cycle may be preset.

[0034] In detail, the verification operation can be an operation to identify whether the threshold voltage of multiple memory cells is greater than the verification voltage. For example, in the verification operation, multiple memory cells having a threshold voltage greater than the verification voltage can be identified as "cut-off cells". Cut-off cells can be represented by the logic value "0". The threshold voltage of the multiple memory cells identified as "cut-off cells" in the verification operation can be determined as having reached the threshold voltage corresponding to the target programming state. On the other hand, during the verification operation, multiple memory cells having a threshold voltage less than or equal to the verification voltage can be identified as "on cells". On cells can be represented by the logic value "1". The threshold voltage of the multiple memory cells identified as "on cells" in the verification operation can be determined as not having reached the threshold voltage corresponding to the target programming state.

[0035] The result of performing a verification operation can indicate "verification passed" or "verification failed". Verification passed indicates that the number of memory cells identified as active is less than a reference failure bit. Verification failed indicates that the number of memory cells identified as active is equal to or greater than the reference failure bit. In other words, the reference failure bit can be a reference number used to determine which of the two results, "verification passed" or "verification failed," corresponds to the outcome of the verification operation.

[0036] The memory controller 200 can control the overall operation of the memory system 50.

[0037] When power is applied to the memory system 50, the memory controller 200 can run firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host 300, a flash translation layer (FTL) that controls communication between the host 300 and the memory device 100, and a flash interface layer (FIL) that controls communication with the memory device 100.

[0038] In this embodiment, the memory controller 200 can receive data and logical block addresses (LBAs) from the host 300, and can translate the logical block addresses (LBAs) into physical block addresses (PBAs), which indicate the addresses of a plurality of memory cells included in the memory device 100 and in which data is to be stored. In this specification, the terms "logical block address (LBA)" and "logical address" are used interchangeably. Similarly, the terms "physical block address (PBA)" and "physical address" are used interchangeably.

[0039] The memory controller 200 can control the memory device 100 in response to a request received from the host 300, causing it to perform write, read, or erase operations. During a write operation, the memory controller 200 can provide the memory device 100 with a write command, a physical block address, and data. During a read operation, the memory controller 200 can provide the memory device 100 with a read command and a physical block address. During an erase operation, the memory controller 200 can provide the memory device 100 with an erase command and a physical block address.

[0040] In this implementation, the memory controller 200 can autonomously generate commands, addresses, and data regardless of whether it receives a request from the host 300, and can send the generated commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide the memory device 100 with commands, addresses, and data required to perform read and write operations involved in wear leveling, read recycling, garbage collection, etc.

[0041] In one implementation, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 based on an interleaving scheme to improve operational performance. The interleaving scheme can be a scheme for controlling the memory devices 100 such that the operations of at least two memory devices 100 overlap with each other.

[0042] The host 300 can communicate with the memory system 50 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM) communication methods.

[0043] Figure 2 This is an example Figure 1 A diagram of the structure of a memory device.

[0044] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0045] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to address decoder 121 via row lines RL. Memory blocks BLK1 to BLKz are connected to page buffer group 123 via bit lines BL1 to BLm. Each of memory blocks BLK1 to BLKz may include multiple memory cells. In embodiments, the multiple memory cells may be non-volatile memory cells. Multiple memory cells connected to the same word line are defined as a page. In other words, memory cell array 110 may include multiple pages. In embodiments of this disclosure, each of the memory blocks BLK1 to BLKz included in memory cell array 110 may include multiple dummy cells. For a dummy cell, one or more dummy cells may be connected in series between a drain select transistor and multiple memory cells, and between a source select transistor and multiple memory cells.

[0046] Each of the plurality of memory cells in the memory device 100 may be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0047] Peripheral circuitry 120 can drive memory cell array 110. In this example, under the control of control logic 130, peripheral circuitry 120 can drive memory cell array 110 to perform programming, reading, and erasing operations. In other examples, peripheral circuitry 120 can, under the control of control logic 130, apply various operating voltages to row lines RL and bit lines BL1 to BLm or discharge the applied voltages.

[0048] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a page buffer group 123, a data input / output circuit 124, and a sensing circuit 125.

[0049] Address decoder 121 is connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to embodiments of this disclosure, word lines may include normal word lines and dummy word lines. According to embodiments, row lines RL may also include pipe select lines.

[0050] Address decoder 121 can operate under the control of control logic 130. Address decoder 121 receives address ADDR from control logic 130.

[0051] Address decoder 121 can decode the block address in the received address ADDR. Address decoder 121 can select at least one of the memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can decode the row address RADD in the received address ADDR. Address decoder 121 can select at least one word line WL of the selected memory block by applying the voltage provided by voltage generator 122 to at least one word line WL according to the decoded row address RADD.

[0052] During programming operations, address decoder 121 may apply a programming voltage to the selected word line and a pass voltage with a level lower than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 may apply a verification voltage to the selected word line and a verification pass voltage with a level higher than the verification voltage to the unselected word line.

[0053] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and a read pass voltage that is higher than the read voltage to the unselected word line.

[0054] Erasure operations on memory device 100 are performed on a block-by-block basis. During the erase operation, the address ADDR input to memory device 100 includes the block address. Address decoder 121 can decode the block address and select a memory block based on the decoded block address. During the erase operation, address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0055] Address decoder 121 can decode the column address in the received address ADDR. The decoded column address can be sent to page buffer set 123. In an embodiment, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0056] Voltage generator 122 can generate multiple operating voltages Vop using the external power supply voltage provided to memory device 100. Voltage generator 122 can operate under the control of control logic 130.

[0057] In this embodiment, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 can be used as the operating voltage of the memory device 100.

[0058] In this implementation, voltage generator 122 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. Voltage generator 122 can use either an external or internal power supply voltage to generate multiple operating voltages Vop. Voltage generator 122 can generate various voltages required by the memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0059] The voltage generator 122 may include multiple pump capacitors for receiving an internal power supply voltage to generate multiple operating voltages Vop with various voltage levels, and can generate multiple operating voltages Vop by selectively enabling the multiple pump capacitors under the control of control logic 130.

[0060] The generated operating voltage Vop can be provided to the memory cell array 110 by the address decoder 121.

[0061] Page buffer group 123 includes first page buffer PB1 to m-th page buffer PBm. First page buffer PB1 to m-th page buffer PBm are respectively connected to memory cell array 110 via first bit line BL1 to m-th bit line BLm. First page buffer PB1 to m-th page buffer PBm operate under the control of control logic 130.

[0062] Page buffers PB1 through PBm can send / receive data DATA to / from data input / output circuit 124. During programming operations, page buffers PB1 through PBm receive the data DATA to be stored through data input / output circuit 124 and data line DL.

[0063] During programming operations, page buffers PB1 through PBm can transmit the data DATA to be stored, received via data input / output circuit 124, to the selected memory cell via bit lines BL1 through BLm when a programming pulse is applied to the selected word line. Based on the received data DATA, multiple memory cells in the selected page can be programmed. Multiple memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have increased threshold voltages. The threshold voltages of multiple memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, page buffers PB1 through PBm read the data DATA stored in the selected memory cell from the selected memory cell via bit lines BL1 through BLm.

[0064] During a read operation, page buffer group 123 can read data DATA from multiple memory cells in the selected page via bit lines BL1 to BLm, and can store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0065] During an erase operation, page buffer group 123 can float bit lines BL1 to BLm. In one embodiment, page buffer group 123 may include column select circuitry.

[0066] In one implementation, while multiple data entries stored in some of the multiple page buffers included in the page buffer group 123 are being programmed into the memory cell array 110, the remaining page buffers can receive new data from the memory controller 200 and then store the new data.

[0067] The data input / output circuit 124 can be connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 can operate in response to the control logic 130.

[0068] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). During reading operations, the data input / output circuit 124 may output data DATA received from the first page buffer PB1 to the m-th page buffer PBm included in the page buffer group 123 to the external controller.

[0069] During a read or verification operation, the sensing circuit 125 can generate a reference current in response to an enable bit signal VRYBIT generated by the control logic 130, and can output a pass signal or a failure signal to the control logic 130 by comparing a sensed voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current. The enable bit signal VRYBIT can be a reference failure bit number. The amplitude of the sensed voltage VPB can vary based on the number of memory cells identified as active. Alternatively, the amplitude of the sensed voltage VPB can vary based on the number of memory cells identified as off. In one embodiment, the sensing circuit 125 can generate a reference voltage based on the reference failure bit number, compare this reference voltage with a sensed voltage VPB determined based on the number of memory cells identified as active, and then output a pass signal or a failure signal to the control logic 130. In this example, when the amplitude of the sensed voltage VPB is less than the amplitude of the reference voltage, the sensing circuit 125 can output a pass signal to the control logic 130. In another example, when the magnitude of the sensed voltage VPB is less than the magnitude of the reference voltage, the sensed circuit 125 can output a failure signal to the control logic 130.

[0070] Control logic 130 can be connected to address decoder 121, voltage generator 122, page buffer group 123, data input / output circuit 124, and sensing circuit 125. Control logic 130 can control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0071] Control logic 130 can control peripheral circuit 120 by generating various types of signals in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, row address RADD, page buffer control signal PBSIGNALS, and enable bit signal VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, row address RADD to address decoder 121, page buffer control signal PBSIGNALS to page buffer group 123, and enable bit signal VRYBIT to sensing circuit 125. In addition, control logic 130 can determine whether the verification operation has passed or failed in response to pass signal PASS or failure signal FAIL output from sensing circuit 125.

[0072] Figure 1 The programmable operation controller 140 shown may be included in Figure 2In the illustrated memory device 100, a programming operation controller 140 can control programming operations performed on a plurality of memory cells. The programming operation controller 140 may include peripheral circuitry 120 and a memory cell array 110. The programming operation controller 140 can drive the memory cell array 110 to perform programming operations. The programming operation controller 140 can control the peripheral circuitry 120 such that the operating voltage to be used in the programming operation is applied to the row lines RL and bit lines BL1 to BLm.

[0073] Figure 1 The programming operation controller 140 shown may include a page buffer group 123 and a sensing circuit 125. The programming operation controller 140 may determine the magnitude of the sensed voltage VPB based on the number of memory cells identified as active during the verification operation. The programming operation controller 140 may generate a reference voltage based on the number of reference failure bits. The programming operation controller 140 may determine whether the verification passed or failed by comparing the magnitude of the reference voltage with the magnitude of the sensed voltage VPB. The programming operation controller 140 may determine whether to execute a programming loop based on the result of performing the verification operation.

[0074] Figure 3 This is an example Figure 2 A diagram showing the structure of any one of the multiple storage blocks BLK1 to BLKz.

[0075] Storage block BLKi indicator Figure 2 The storage blocks shown are any one of the storage blocks BLK1 to BLKz, BLKi.

[0076] Reference Figure 3 Multiple word lines arranged in parallel to each other can be connected between a first select line and a second select line. Here, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). Specifically, the memory block BLKi can include multiple string STs connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be individually connected to string STs, while the source line SL can be collectively connected to string STs. String STs can be configured equally; therefore, the string ST connected to the first bit line BL1 will be described in detail by example.

[0077] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. As shown in the figure, a single string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and may include more memory cells than the plurality of memory cells MC1 to MC16.

[0078] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Multiple memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different string STs can be connected to the source select line SSL, the gate of the drain select transistor DST included in different string STs can be connected to the drain select line DSL, and the gates of the multiple memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16 respectively. A group of memory cells included in different string STs but connected to the same word lines can be referred to as a "physical page (PG)". Therefore, the memory block BLKi can include the same number of physical pages (PGs) as the number of word lines WL1 to WL16.

[0079] A memory cell can store one bit of data. This cell is typically designated as a "single-level cell (SLC)". In this case, a physical page (PG) can store the data corresponding to a logical page (LPG). The data corresponding to a logical page (LPG) can include the same number of data bits as the number of cells included in a physical page (PG).

[0080] A memory cell can store two or more bits of data. In this case, a physical page (PG) can store data corresponding to two or more logical pages (LPG).

[0081] Figure 4 This is a diagram illustrating the threshold voltage distribution of multiple memory cells based on the programming operations of the memory device.

[0082] exist Figure 4 In the graph, the horizontal axis indicates the threshold voltage Vth of multiple memory cells, and the vertical axis indicates the number of memory cells (cell #).

[0083] Reference Figure 4 The threshold voltage distribution of multiple memory cells can be changed from the initial state to the final programmed state based on programming operations.

[0084] exist Figure 4 The description is based on the assumption that the programming data of the TLC scheme uses one of the memory cells to store three bits of data.

[0085] The initial state can be a state where no programming operation has been performed and the threshold voltage distribution of multiple memory cells is in the erase state E.

[0086] The final programming state can be a distribution of threshold voltages across multiple memory cells to which programming operations are performed. Each of the multiple memory cells to which programming operations are performed can have a threshold voltage corresponding to any one of the multiple programming states. For example, when programming data in a three-level cell (TLC) scheme that stores three bits of data in a single memory cell, the multiple programming states can indicate an erase state E and first programming states PV1 through seventh programming states PV7. In an implementation, each of the multiple memory cells to which programming operations are performed can have a threshold voltage corresponding to either erase state E or any one of the first programming states PV1 through seventh programming states PV7. Through programming operations, the threshold voltage of each memory cell in its initial state can be increased to the threshold voltage corresponding to either erase state E or any one of the first programming states PV1 through seventh programming states PV7.

[0087] Each memory cell can have either an erase state E or a programming state PV1 through PV7 as its target programming state. The target programming state can be determined based on the data to be stored in the corresponding memory cell. Through appropriate programming operations, multiple memory cells can have a threshold voltage corresponding to the target programming state in the final programming state.

[0088] Figure 5 This is a diagram illustrating the programming operations of a memory device.

[0089] exist Figure 5 In the graph, the horizontal axis indicates time, and its vertical axis indicates the voltage V applied to the word line. The voltage V applied to the word line can include the programming voltage Vpgm and the verification voltage V_vfy.

[0090] exist Figure 5 In this example, we assume that the data is programmed using a TLC scheme that stores three bits of data in one of the memory cells. However, the scope of this disclosure is not limited to this, and a single memory cell can be programmed to store two bits of data or four or more bits of data.

[0091] Reference Figure 5 The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. The memory device 100 can perform the programming operation by executing multiple programming cycles PL1 to PLn, such that each selected memory cell connected to the selected word line has a threshold voltage corresponding to any one of the multiple programming states. For example, when programming a single memory cell in a TLC scheme, the memory device 100 can perform the programming operation by executing multiple programming cycles PL1 to PLn, such that the memory cell has a threshold voltage corresponding to the erase state E and any one of the first programming states PV1 to the seventh programming states PV7.

[0092] Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation (PGM step) and a verification operation (verification step).

[0093] The programming voltage application operation (PGM step) can be an operation that applies a programming voltage to a selected word line connected to the selected memory cell. For example, memory device 100 can apply a first programming voltage Vpgm1 to the selected word line connected to the selected memory cell in a first programming cycle PL1. After applying the first programming voltage Vpgm1 to the selected word line, the corresponding threshold voltage of the selected memory cell can be a threshold voltage corresponding to a target programming state among a plurality of programming states.

[0094] A verification operation (verification step) may be an operation of applying a verification voltage to a selected word line connected to a selected memory cell. A verification operation (verification step) may be an operation of determining whether a corresponding threshold voltage of the selected memory cell corresponds to a threshold voltage among multiple programming states. A verification operation (verification step) may be an operation of applying verification voltages corresponding to each target programming state of the selected memory cell.

[0095] In the implementation, during the first programming cycle PL1, after applying a first programming voltage Vpgm1 to the selected word line connected to the selected memory cell, the memory device 100 may apply a first verification voltage V_vfy1 to a seventh verification voltage V_vfy7 to the selected word line. In this case, a verification operation (verification step) can be performed on multiple memory cells having a first programming state as the target programming state using the first verification voltage V_vfy1. A verification operation (verification step) can be performed on multiple memory cells having a second programming state as the target programming state using the second verification voltage V_vfy2. A verification operation (verification step) can be performed on multiple memory cells having a third programming state as the target programming state using the third verification voltage V_vfy3. A verification operation (verification step) can be performed on multiple memory cells having a fourth programming state as the target programming state using the fourth verification voltage V_vfy4. A verification operation (verification step) can be performed on multiple memory cells having a fifth programming state as the target programming state using the fifth verification voltage V_vfy5. Verification operations (verification steps) can be performed on multiple memory cells having a sixth programming state as the target programming state using a sixth verification voltage V_vfy6. Verification operations (verification steps) can be performed on multiple memory cells having a seventh programming state as the target programming state using a seventh verification voltage V_vfy7. The amplitudes of the verification voltages V_vfy1 to V_vfy7 can increase in the direction from the first verification voltage V_vfy1 to the seventh verification voltage V_vfy7. Specifically, for the amplitudes of the verification voltages V_vfy1 to V_vfy7, the first verification voltage V_vfy1 can be the lowest, while the seventh verification voltage V_vfy7 can be the highest. However, the number of verification voltages is not limited to this embodiment.

[0096] It can be determined that multiple memory cells that have passed the verification operation (verification step) using the respective verification voltages V_vfy1 to V_vfy7 have a threshold voltage corresponding to the target programming state. These multiple memory cells that have passed the verification operation (verification step) can be disabled for programming in the second programming cycle PL2. A programming disable voltage can be applied to the bit lines connected to the disabled memory cells.

[0097] It can be determined that the multiple memory cells that failed in the verification steps using the respective verification voltages V_vfy1 to V_vfy7 do not have the threshold voltage corresponding to the target programming state. The multiple memory cells that failed in the verification steps can then execute the second programming loop PL2.

[0098] In the second programming cycle PL2, the memory device 100 may apply a second programming voltage Vpgm2, which is a unit voltage ΔVpgm higher than the first programming voltage Vpgm1, to the selected word line connected to the selected memory cell. Thereafter, the memory device 100 may perform the verification operation (verification step) of the second programming cycle PL2 in the same manner as the verification operation (verification step) of the first programming cycle PL1.

[0099] Subsequently, the memory device 100 can execute the subsequent programming cycle a preset number of times in the same manner as the second programming cycle PL2.

[0100] In this implementation, the programming operation may fail if it is not completed within a preset number of programming loops. The programming operation can succeed if it is completed within the preset number of programming loops. The completion of the programming operation can be determined based on whether all selected memory cells have passed the verification operation (verification step). If all selected memory cells have passed the verification operation (verification step), subsequent programming loops may not be executed.

[0101] In this implementation, the programming voltage can be determined based on the Incremental Step Pulse Programming (ISPP) method. As multiple programming cycles PL1 to PLn are repeated, the level of the programming voltage can be increased or decreased in stages (i.e., according to step voltages). In other words, the step voltage can be the amplitude difference between the programming voltages applied in any two consecutive programming cycles among the multiple programming cycles PL1 to PLn. The number of times the programming voltage is applied, the voltage level of the programming voltage, the voltage application time, etc., used in each programming cycle can be determined in various forms under the control of the memory controller 200.

[0102] Figure 6 This is a diagram illustrating the verification operation in the programming operation of a memory device.

[0103] Reference Figure 6 The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation (PGM step) and a verification operation (verification step). The verification operation (verification step) may include a sensing period (sensing) and a comparison period (comparison).

[0104] The sensing period (sensing) can be a period in which the voltage of the bit line, which changes based on the threshold voltage of the selected memory cell, is sensed when a verification voltage is applied to the selected word line connected to the selected memory cell. The memory device 100 can identify the threshold voltage of the selected memory cell based on the change in the bit line voltage. In an example, when the threshold voltage of a memory cell is greater than the verification voltage, the voltage of the bit line connected to that memory cell can be maintained. Here, a memory cell having a threshold voltage greater than the verification voltage can be identified as a cutoff cell. The threshold voltage of a memory cell identified as a "cutoff cell" can be determined as having reached the threshold voltage corresponding to the target programming state. On the other hand, when the threshold voltage of a memory cell is less than or equal to the verification voltage, the voltage of the bit line connected to that memory cell can be reduced. Here, a memory cell having a threshold voltage less than or equal to the verification voltage can be identified as a "conducting cell." The threshold voltage of a memory cell identified as a "conducting cell" can be determined as not having reached the threshold voltage corresponding to the target programming state.

[0105] The comparison period can be the time period during which the number of memory cells identified as active cells is compared with a reference failure bit. The reference failure bit can be a reference bit used to determine which of "verification passed" and "verification failed" corresponds to the result of the verification operation (verification step).

[0106] Figure 6 The graph shown in the lower part illustrates the threshold voltage distribution of multiple memory cells as the memory device 100 executes multiple programming cycles PL1 to PLn. Furthermore, Figure 6 The lower part of the graph shows that the horizontal axis indicates the threshold voltage Vth of multiple memory cells, and its vertical axis indicates the number of memory cells (cell #).

[0107] Reference Figure 6 The graph in the lower part of the diagram shows that each of the multiple programming cycles PL1 to PLn may include a comparison period (comparison). During the comparison period of each of the multiple programming cycles PL1 to PLn, the memory device 100 may compare the number of memory cells Num fb identified as active cells using the verification voltage V_vfy with the reference failure number Ref fb. In one example, the verification operation (verification step) can pass when the number of memory cells Num fb identified as active cells using the verification voltage V_vfy is less than the reference failure number Ref fb. In another example, the verification operation (verification step) may fail when the number of memory cells Num fb identified as active cells using the verification voltage V_vfy is equal to or greater than the reference failure number Ref fb.

[0108] However, during the programming voltage application operation (PGM step), the degree to which the threshold voltage of each memory cell increases may differ from one another. For example, during the programming voltage application operation (PGM step), the threshold voltage of any one of the multiple memory cells may increase more than the threshold voltage of another memory cell. Furthermore, the magnitude of the programming voltage used in any of the multiple programming cycles PL1 to PLn may be a step voltage larger than the magnitude of the programming voltage used in the programming cycle preceding that programming cycle. The step voltage may be the difference between the magnitude of the programming voltage used in the current programming cycle among the multiple programming cycles PL1 to PLn and the magnitude of the programming voltage used in the previous programming cycle. In the example, when memory device 100 performs a verification operation (verification step) on the selected memory cell in the second programming cycle PL2, the step voltage may be the difference between the magnitude of the programming voltage used in the second programming cycle PL2 and the magnitude of the programming voltage used in the first programming cycle PL1. In another example, the step voltage may be a unit voltage ΔVpgm, such as... Figure 5 As shown.

[0109] The step voltage amplitude can be increased as multiple programming cycles PL1 to PLn are executed. As the step voltage amplitude increases with the execution of multiple programming cycles PL1 to PLn, the number of memory cells with a threshold voltage greater than the verification voltage V_vfy can increase. As the step voltage amplitude increases, the reference failure number Ref fb for determining pass or fail in the verification operation (verification step) can change. For example, as the step voltage amplitude increases, the reference failure number Ref fb can increase.

[0110] Figure 7 This is a diagram illustrating the programming operation of a memory device according to an embodiment of the present disclosure.

[0111] Reference Figure 7 The programming operation controller 140 included in the memory device 100 may include a programming operation executor 150, a step voltage calculator 160, a reference bit determiner 170, and a verification result generator 180.

[0112] The programming operation executor 150 can be a circuit that performs programming operations on a plurality of memory cells selected from a plurality of memory cells. The programming operation may include multiple programming cycles. Each programming cycle may include a programming voltage application operation and a verification operation.

[0113] The programming operation executor 150 can execute any of a plurality of programming cycles, and afterwards can provide programming voltage information V_inf to the step voltage calculator 160. The programming voltage information V_inf can be information about the magnitude of the programming voltage used in one of the plurality of programming cycles. The programming operation executor 150 can provide programming-related information Pgm_inf to the reference bit determiner 170. The programming-related information Pgm_inf can include the number of programming and erase operations performed on the selected memory cell and information about the location of the selected word line connected to the selected memory cell.

[0114] The programming actuator 150 can identify the threshold voltage of the selected memory cell by using a verification voltage. The programming actuator 150 can provide the verification result generator 180 with the number Num fb of the selected memory cells that are identified as active cells by using the verification voltage.

[0115] The step voltage calculator 160 may include a programmable voltage information storage unit 161.

[0116] The programming voltage information storage 161 can store information about the magnitude of the programming voltage used in one of the multiple programming cycles.

[0117] The step voltage calculator 160 can calculate the step voltage Vstep based on information about the programming voltage amplitude stored in the programming voltage information storage 161. More specifically, the step voltage calculator 160 can calculate the step voltage Vstep, which is the difference between the amplitude of the programming voltage used in any programming cycle among multiple programming cycles and the amplitude of the programming voltage used in the programming cycle immediately preceding said programming cycle. In other words, the step voltage Vstep can be the amplitude difference between the programming voltages applied in any two consecutive programming cycles among multiple programming cycles. For example, assuming that the programming operation executor 150 performs a programming voltage application operation (PGM step) on the selected memory cell in the first programming cycle PL1 and the second programming cycle PL2, refer to... Figure 5 Here, the step voltage calculator 160 can determine the step voltage Vstep as the difference between the magnitude of the second programming voltage Vpgm2 applied to the selected memory cell in the second programming cycle PL2 and the magnitude of the first programming voltage Vpgm1 applied to the selected memory cell in the first programming cycle PL1.

[0118] The magnitude of the step voltage Vstep can vary based on the extent to which multiple programming loops are performed on the selected memory cell. Specifically, the magnitude of the step voltage Vstep can be increased based on the number of times the multiple programming loops are executed. For example, refer to... Figure 5The amplitude of the step voltage Vstep in the second programming cycle PL2 (which is the difference between the amplitude of the second programming voltage Vpgm2 and the amplitude of the first programming voltage Vpgm1) can be smaller than the amplitude of the step voltage Vstep in the nth programming cycle PLn (which is the difference between the amplitude of the nth programming voltage Vpgmn and the amplitude of the (n-1)th programming voltage Vpgmn-1).

[0119] The step voltage calculator 160 can provide the calculated step voltage Vstep to the reference bit determiner 170.

[0120] The reference bit determiner 170 may include a reference bit information storage 171.

[0121] The reference bit information storage 171 can store information about the number of reference failure bits. The information about the number of reference failure bits may include a first reference bit corresponding to the magnitude of the step voltage Vstep, a second reference bit corresponding to the number of programming and erasing operations performed on the selected memory cell, and a third reference bit corresponding to the position of the selected word line connected to the selected memory cell.

[0122] The reference bit determiner 170 may be a circuit that determines the reference failure number Ref fb based on the magnitude of the step voltage Vstep. The reference bit determiner 170 may receive the step voltage Vstep calculated by the step voltage calculator 160. In one embodiment, the reference bit determiner 170 may determine the reference failure number Ref fb as a first reference number corresponding to the magnitude of the step voltage Vstep by using information about the reference failure number stored in the reference bit information storage 171. The first reference number may have a larger number of bits as the magnitude of the step voltage Vstep increases. In other embodiments, the reference bit determiner 170 may determine the reference failure number Ref fb as the sum of the first reference number and a second reference number corresponding to the number of programming and erasing operations performed on the selected memory cell. The second reference number may have a larger number of bits as the number of programming and erasing operations performed on the selected memory cell increases. In other embodiments, the reference bit determiner 170 may determine the reference failure number Ref fb as the sum of the first reference number and a third reference number corresponding to the position of the selected word line connected to the selected memory cell. As the selected word line is positioned closer to the select line, the third reference bit can have a smaller number of bits. The select line can be a drain select line (DSL) or a source select line (SSL), such as... Figure 3 As shown. In other embodiments, the reference bit determiner 170 may determine the sum of the first reference bit number, the second reference bit number, and the third reference bit number as the reference failure bit number Ref fb.

[0123] The reference bit determiner 170 can use the information about the number of reference failure bits stored in the reference bit information storage 171 to determine the reference failure number Ref fb, and can provide the reference failure number Ref fb to the verification result generator 180.

[0124] The verification result generator 180 may be a circuit that compares the number of memory cells identified as active units, Num fb, with the reference failure number Ref fb, and generates verification result information Vfy r based on the comparison result. Specifically, when the number of memory cells identified as active units, Num fb, is less than the reference failure number Ref fb, the verification result generator 180 can generate verification result information Vfy r indicating "pass" and provide the verification result information to the programming operation executor 150. When the number of memory cells identified as active units, Num fb, is equal to or greater than the reference failure number Ref fb, the verification result generator 180 can generate verification result information Vfy r indicating "failure" and provide the verification result information to the programming operation executor 150.

[0125] Subsequently, the programming operation executor 150 can determine whether to execute a subsequent programming cycle based on the verification result information Vfyr provided by the verification result generator 180. In one example, when receiving verification result information Vfyr indicating "pass," the programming operation executor 150 may not execute the subsequent programming cycle. In another example, when receiving verification result information Vfyr indicating "pass," the programming operation executor 150 may skip the verification operation in the subsequent programming cycle. In other words, when receiving verification result information Vfyr indicating "pass," the programming operation executor 150 may exclude the verification operation in the subsequent programming cycle and only perform the programming voltage application operation. In yet another example, when receiving verification result information Vfyr indicating "failure," the programming operation executor 150 may execute the subsequent programming cycle.

[0126] Figure 8 This is a diagram illustrating a programmable voltage information storage device.

[0127] Reference Figure 8The programming voltage information storage 161 included in the step voltage calculator 160 can store information about the amplitude of the programming voltage. More specifically, the programming voltage information storage 161 can store information about the amplitude of the first programming voltage Vpgm1 used in the programming voltage application operation of the first programming cycle PL1. The programming voltage information storage 161 can also store information about the amplitude of the programming voltage, ranging from the second programming voltage Vpgm2 to the nth programming voltage Vpgmn, used in each programming voltage application operation of each programming cycle from the second programming cycle PL2 to the nth programming cycle PLn. In this way, the programming voltage information storage 161 can store information about the amplitude of the programming voltage used in each programming voltage application operation of multiple programming cycles. Furthermore, Figure 7 The step voltage calculator 160 shown can calculate the step voltage based on the information about the programming voltage stored in the programming voltage information storage 161.

[0128] Figure 9 This is a diagram illustrating the first reference bit depth corresponding to the amplitude of the step voltage.

[0129] Reference Figure 9 The reference bit information storage 171 can store a first reference bit number corresponding to the amplitude of the step voltage. Figure 9 Tables 1 and 2 show the data based on the... Figure 7 The first reference number Ref fb1 and Ref fb11 are determined by the amplitudes of the step voltages Vstep1 and Vstep2 calculated by the step voltage calculator 160 shown. In one embodiment, referring to Table 1, when the amplitude of the step voltage Vstep1 is greater than 400mV and less than or equal to 450mV, the first reference number Ref fb1 can be determined to be 50. That is, the first reference number Ref fb1 corresponding to the amplitude of the step voltage Vstep1 greater than 400mV and less than or equal to 450mV can be determined to be 50. Furthermore, the first reference number Ref fb1 corresponding to the amplitude of the step voltage greater than 450mV and less than or equal to 500mV can be determined to be 50+a. The first reference number Ref fb1 can be determined based on the range in which the amplitude of the step voltage Vstep1 falls. The first reference number Ref fb1 corresponding to the amplitude of the step voltage Vstep1 can be determined based on Table 1. Furthermore, as shown in Table 1, the first reference number Ref fb1 can increase as the amplitude of the step voltage Vstep1 increases.

[0130] In the implementation, referring to Table 2, the amplitude of the step voltage Vstep2 can be increased regularly. In other words, the amplitude of the step voltage Vstep2 can be increased according to a preset amplitude. Table 2 provides an example where the amplitude of the step voltage Vstep2 is increased by 50mV. Referring to Table 2, when the amplitude of the step voltage Vstep2 is 400mV, the first reference number Ref fb11 can be determined to be 50. When the amplitude of the step voltage Vstep2 is 450mV, the first reference number Ref fb11 can be determined to be 50+a. In this way, the first reference number Ref fb11 corresponding to the amplitude of the step voltage Vstep2 can be determined based on Table 2. Furthermore, as the amplitude of the step voltage Vstep2 increases, the first reference number Ref fb11 can be increased.

[0131] Figure 10 This is a diagram illustrating the second reference bit number corresponding to the number of programming and erasing operations.

[0132] Reference Figure 10 The reference bit information storage 171 can store a second reference bit Ref fb2 corresponding to the number of programming and erasing operations E / W Cnt performed on the selected memory cell. (Ref...) Figure 10 As shown in Table 3, when the number of programming and erasing operations performed on the selected memory cell, E / W Cnt, is less than the first reference count value Ref Cnt1, the second reference bit length Ref fb2 can be 0. When the number of programming and erasing operations performed on the selected memory cell, E / W Cnt, is equal to or greater than the first reference count value Ref Cnt1 and less than the second reference count value Ref Cnt2, the second reference bit length Ref fb2 can be b. When the number of programming and erasing operations performed on the selected memory cell, E / W Cnt, is equal to or greater than the second reference count value Ref Cnt2 and less than the third reference count value Ref Cnt3, the second reference bit length Reffb2 can be 2b. As shown in Table 3, the second reference bit length Ref fb2 can increase as the number of programming and erasing operations performed on the selected memory cell, E / W Cnt, increases.

[0133] Figure 11 This is a diagram illustrating the third reference bit position corresponding to the word line position.

[0134] See Figure 11Table 4 shows that reference bit information storage 171 can store a third reference bit Ref fb3 corresponding to the position of the selected word line connected to the selected memory cell. In a 3D memory cell structure, the characteristics of the memory cell can vary based on the location of the memory cell. Specifically, the closer the memory cell is to the center, the better its characteristics can be. The closer the memory cell is to the edge, the worse its characteristics can be.

[0135] exist Figure 11 In this context, it is assumed that in a 3D memory cell structure, the multiple memory cells connected to the eighth word line WL8 are located at the very center. These multiple memory cells connected to the eighth word line WL8 can have better memory cell characteristics than other memory cells. That is, when a programming voltage is applied to the eighth word line WL8, the threshold voltage increase of the multiple memory cells connected to the eighth word line WL8 can be greater than the threshold voltage increase of other memory cells. Compared to other memory cells, the multiple memory cells connected to the eighth word line WL8 can include multiple memory cells with threshold voltages greater than the verification voltage. Therefore, during the verification operation of the multiple memory cells connected to the eighth word line WL8, the third reference bit Ref fb3 can be higher than the third reference bit Ref fb3 of other memory cells. Figure 11 The text describes how, when the selected word line is the eighth word line (WL8), the corresponding third reference bit Ref fb3, which is 0, is the maximum reference bit. The third reference bit Ref fb3 corresponding to the eighth word line (WL8) can be the largest. Furthermore, as the selected word line gets closer to the select line, the characteristics of the selected memory cell connected to the selected word line deteriorate; therefore, the third reference bit Ref fb3 can be lower. For example, when the selected word line is the sixth word line (WL6), the third reference bit Ref fb3 can be determined to be -2c. The third reference bit Ref fb3 can decrease as the selected word line gets closer to the select line. That is, the third reference bit Ref fb3 corresponding to the word line closest to the select line can have the smallest number of bits. In other words, the third reference bit Ref fb3 corresponding to the most central word line can have the largest number of bits, while the third reference bit Ref fb3 corresponding to the word line closest to the select line can have the smallest number of bits. The select line can be a drain select line (DSL) or a source select line (SSL), such as... Figure 3 As shown.

[0136] Figure 12 This is a diagram illustrating the reference failure bit count determined by taking into account the step voltage magnitude, the number of programming and erasing operations, and the word line position.

[0137] Figure 7 The reference bit determiner 170 shown can determine the number of reference failure bits based on information about the number of reference failure bits stored in the reference bit information storage 171. This information may include a first reference bit corresponding to the magnitude of the step voltage, a second reference bit corresponding to the number of programming and erasing operations performed on the selected memory cell, and a third reference bit corresponding to the position of the selected word line. In other words, the number of reference failure bits can be determined by considering the magnitude of the step voltage, the number of programming and erasing operations, and the position of the selected word line.

[0138] Describe it by example Figure 12 The table shown illustrates this. When the step voltage amplitude is greater than 500mV and less than or equal to 550mV, the first reference bit number can be set to 50+2a. When the number of programming and erasing operations performed on the selected memory cell is equal to or greater than the first reference count value and less than the second reference count value, the second reference bit number can be set to b. When the selected word line corresponds to the seventh word line, the third reference bit number can be set to -c. That is, considering the step voltage amplitude, the number of programming and erasing operations, and the position of the selected word line, the reference failure bit number Ref fb can be set to 50+2a+bc. The reference bit determiner 170 can provide the determined reference failure bit number Ref fb to the verification result generator 180.

[0139] As referenced above Figures 9 to 11 As described, the memory device 100 can determine a first reference number of bits based on the magnitude of the step voltage. The memory device 100 can determine a second reference number of bits based on the number of programming and erasing operations performed on the selected memory cell. The memory device 100 can determine a third reference number of bits based on the position of the selected word line. The memory device 100 can determine a reference failure number of bits based on the first, second, and third reference numbers. Specifically, the memory device 100 can determine the reference failure number of bits by summing at least one of the second and third reference numbers with the first reference number of bits.

[0140] According to embodiments of this disclosure, the memory device 100 can reduce the number of times it performs a programming voltage application operation or a verification operation by changing the reference failure bit number based on the amplitude of the step voltage, the number of programming and erasing operations, and the position of the selected word line.

[0141] Figure 13 This is a flowchart illustrating the programming operation of a memory device according to an embodiment of the present disclosure.

[0142] Reference Figure 13In step S1301, the memory device 100 may apply a programming voltage to the word lines connected to the multiple memory cells in any of the multiple programming cycles.

[0143] In step S1303, the memory device 100 may apply a verification voltage to the word lines connected to the plurality of memory cells in the programming cycle.

[0144] In step S1305, the memory device 100 can calculate a step voltage, which is the difference between the magnitude of the programming voltage applied in the programming cycle and the magnitude of the programming voltage applied directly in the programming cycle preceding the programming cycle.

[0145] In step S1307, the memory device 100 may determine the reference failure bit number based on the amplitude of the step voltage. In an embodiment, the memory device 100 may determine a first reference bit number corresponding to the amplitude of the step voltage as the reference failure bit number. Specifically, the amplitude of the step voltage Vstep may increase with the number of executions of multiple programming loops. As the amplitude of the step voltage increases, the first reference bit number may have a larger number of bits.

[0146] In step S1309, the memory device 100 can compare the number of conducting cells identified by using a verification voltage among a plurality of memory cells with a reference failure bit. The reference failure bit may include at least one of a first reference bit, a second reference bit, and a third reference bit.

[0147] In step S1311, the memory device 100 may generate verification result information based on the comparison result. In one example, when the number of conducting cells identified by using the verification voltage is less than the reference failure bit number, the memory device 100 may generate verification result information indicating "pass". In another example, when the number of conducting cells identified by using the verification voltage is equal to or greater than the reference failure bit number, the memory device 100 may generate verification result information indicating "failure".

[0148] Figure 14 This is a block diagram illustrating a memory card system that applies a memory system according to an embodiment of the present disclosure.

[0149] Reference Figure 14 The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0150] Memory controller 2100 can be coupled to memory device 2200. Memory controller 2100 can access memory device 2200. For example, memory controller 2100 can control read operations, write operations, erase operations, and background operations of memory device 2200. Memory controller 2100 can provide an interface between memory device 2200 and a host computer. Memory controller 2100 can run firmware for controlling memory device 2200. Memory controller 2100 can be configured with the above-mentioned reference... Figure 1 The memory controller 200 described herein is implemented in the same manner. The memory device 2200 can be implemented in the same manner as described above. Figure 1 The memory device 100 described is implemented in the same manner.

[0151] In some implementations, the memory controller 2100 may include components such as RAM, a processor, a host interface, a memory interface, and error correction circuitry.

[0152] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) based on specific communication standards or protocols. In embodiments, the memory controller 2100 can communicate with external devices via at least one of various communication standards or protocols such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe). In embodiments, connector 2300 can be defined by at least one of the aforementioned communication standards or protocols.

[0153] In an implementation, the memory device 2200 may be implemented as any of a variety of non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), or spin-transfer torque magnetic RAM (STT-MRAM).

[0154] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure a memory card such as a PC card (PCMCIA), a compact flash (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, micro MMC, or eMMC), an SD card (SD, mini SD, micro SD, or SDHC), or a universal flash memory (UFS).

[0155] Figure 15 This is a block diagram illustrating a solid-state drive (SSD) system that applies a memory system according to an embodiment of the present disclosure.

[0156] Reference Figure 15 The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals with the host 3100 through a signal connector 3001 and can receive power through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memory modules 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0157] According to embodiments of this disclosure, the SSD controller 3210 can perform the above-mentioned... Figure 1 The functions of the memory controller 200 are described.

[0158] SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to signals received from host 3100. In implementations, these signals can be signals based on the interface between host 3100 and SSD 3200. For example, the signals can be signals defined according to at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe).

[0159] Auxiliary power supply 3230 can be connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can be supplied with power from host 3100 and can be charged. When the power supply from host 3100 is not stable, auxiliary power supply 3230 can supply power to SSD 3200. In implementations, auxiliary power supply 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply 3230 can be located in the motherboard and can provide auxiliary power to SSD 3200.

[0160] Buffer memory 3240 can be used as buffer memory for SSD 3200. For example, buffer memory 3240 can temporarily store data received from host 3100 or data received from multiple flash memory modules 3221 to 322n, or it can temporarily store metadata (e.g., mapping tables) of flash memory modules 3221 to 322n. Buffer memory 3240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0161] Figure 16 This is a block diagram illustrating a user system that applies a memory system according to an embodiment of the present disclosure.

[0162] Reference Figure 16 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0163] Application processor 4100 can run components included in user system 4000, operating system (OS), or user programs. In some embodiments, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0164] Memory module 4200 can be used as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In embodiments, application processor 4100 and memory module 4200 may be packaged based on a package stack (POP) and then provided as a single semiconductor package.

[0165] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi. In an embodiment, network module 4300 may be included in application processor 4100.

[0166] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send the data stored in storage module 4400 to application processor 4100. In embodiments, storage module 4400 can be implemented as a non-volatile semiconductor memory device, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In embodiments, storage module 4400 can be provided as a removable storage medium (i.e., a removable drive) such as an external drive for user system 4000 or a memory card.

[0167] In an implementation, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be configured as described above. Figure 1 The memory device 100 described herein operates in the same manner. The storage module 4400 can operate in the same manner as described above. Figure 1 The memory system 50 described operates in the same manner.

[0168] User interface 4500 may include an interface for inputting data or instructions to application processor 4100 or outputting data to external devices. In embodiments, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may also include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0169] According to this disclosure, a memory device capable of reducing the time required for programming operations and a method for operating the memory device can be provided.

[0170] Cross-reference to related applications

[0171] This application claims priority to Korean Patent Application No. 10-2022-0010803, filed on January 25, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: Multiple memory units; A programming operation executor that performs multiple programming cycles on the plurality of memory units; A step voltage calculator that calculates the step voltage, which is the amplitude difference between programming voltages applied in any two consecutive programming cycles among the plurality of programming cycles; A reference bit determiner that determines the number of reference failure bits based on the magnitude of the step voltage; as well as A verification result generator generates verification result information based on a comparison between the reference failure bit count and the number of active units identified in the verification operations included in the programming loops of the plurality of memory cells. The amplitude of the step voltage increases as the number of executions of the plurality of programming loops increases.

2. The memory device according to claim 1, wherein, The reference bit determiner includes a reference bit information storage unit that stores information about the number of reference failure bits, and Information regarding the reference failure bits includes a first reference bit corresponding to the magnitude of the step voltage, a second reference bit corresponding to the number of programming and erasing operations performed on the plurality of memory cells, and a third reference bit corresponding to the position of the word lines connected to the plurality of memory cells.

3. The memory device according to claim 2, wherein, The reference bit determiner determines the first reference bit number as the reference failure bit number.

4. The memory device according to claim 2, wherein, The first reference bit depth increases with the increase of the step voltage amplitude.

5. The memory device according to claim 2, wherein, As the number of programming and erasing operations performed on the plurality of memory cells increases, the second reference bit has a larger number of bits.

6. The memory device according to claim 2, wherein, The closer the word line is to the selection line, the smaller the number of bits the third reference bit has.

7. The memory device according to claim 2, wherein, The reference bit determiner determines the sum of at least one of the second reference bit and the third reference bit with the first reference bit as the reference failure bit.

8. The memory device according to claim 1, wherein, The verification result generator: When the number of the conducting units is less than the number of reference failure bits, verification result information indicating that the verification operation has passed is generated; When the number of the conducting units is equal to or greater than the number of reference failure bits, verification result information indicating failure in the verification operation is generated; as well as The verification result information is provided to the programming operation executor.

9. The memory device according to claim 8, wherein, When the programming operation executor receives the verification result information indicating that the verification operation has passed, it executes the programming loop following the programming loop in the plurality of programming loops, thereby excluding the verification operation in subsequent programming loops.

10. A method of operating a memory device comprising a plurality of memory cells, the method comprising the steps of: Multiple programming loops are executed on the plurality of memory units; Calculate the step voltage, which is the amplitude difference between the programming voltages applied in any two consecutive programming cycles among the plurality of programming cycles; The reference failure bit number is determined based on the amplitude of the step voltage; as well as Based on the comparison between the reference failure bit count and the number of active units identified in the verification operations included in the programming loops of the plurality of memory cells, verification result information is generated. As the number of executions of the multiple programming loops increases, the amplitude of the step voltage increases.

11. The method according to claim 10, wherein, The reference failure bit number is determined to be a first reference bit number corresponding to the amplitude of the step voltage.

12. The method according to claim 11, wherein, As the amplitude of the step voltage increases, the first reference bit depth has a larger number of bits.

13. The method according to claim 11, wherein, The reference failure bit is determined to be the sum of the first reference bit and the second reference bit, the second reference bit corresponding to the number of programming and erasing operations performed on the plurality of memory cells.

14. The method according to claim 13, wherein, As the number of programming and erasing operations performed on the plurality of memory cells increases, the second reference bit has a larger number of bits.

15. The method according to claim 11, wherein, The reference failure bit is determined to be the sum of the first reference bit and the third reference bit, wherein the third reference bit corresponds to the position of the word line connected to the plurality of memory cells.

16. The method according to claim 15, wherein, The closer the word line is to the selection line, the smaller the number of bits the third reference bit has.

17. A memory device comprising: Multiple memory units; A programming operation executor that performs multiple programming cycles on multiple memory units; as well as A verification result generator generates verification result information based on a comparison between the reference failure bit count and the number of active units identified in the verification operations included in each of the plurality of memory cells within the plurality of programming loops. The magnitude of the programming voltage used in each of the plurality of programming cycles is increased by a step voltage for each subsequent programming cycle. Wherein, as the amplitude of the step voltage increases, the reference failure bit length has a larger number of bits, and As the number of executions of the multiple programming loops increases, the amplitude of the step voltage increases.

18. The memory device according to claim 17, wherein, The reference failure bit length increases with the number of programming and erasing operations performed on the plurality of memory cells, and decreases as the word line connected to the plurality of memory cells gets closer to the select line.

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