Phased array chip communication method, apparatus, device, and storage medium

Abstract

Embodiments of the present disclosure provide phased array chip communication methods, devices, equipment and storage media, which are applied to the technical field of chips. The method comprises: obtaining the chip type of each phased array chip in a phased array; when the chip types of each phased array chip in the phased array are consistent, controlling the enabling control bit of the chip number mode trigger register in each phased array chip in the phased array according to a preset number instruction to select the same number enabling signal, so as to determine the number mode according to the number enabling signal, number each chip in the phased array, so that each phased array chip in the phased array enters the corresponding number mode and generates the corresponding chip number, and then realizes communication with each phased array chip in the phased array. In this way, different number modes can be triggered to number each chip in the phased array, a more flexible and convenient number mode is provided, and the communication efficiency of the phased array chip is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computers, in particular to the technical field of chips, and specifically to a phased array chip communication method and device, equipment and a storage medium. BACKGROUND

[0002] A phased array, that is, a phase compensation (or delay compensation) array, can be used for receiving and transmitting, and its working principle is to appropriately shift the phase (or delay) of the signals of the array elements arranged in a certain rule to obtain the deflection of the array beam, and to simultaneously compensate the phase (or delay) in different directions to obtain multiple beams. A chip for phased array transceiving, that is, a phased array chip, needs to communicate with each chip in a phased array chip networking.

[0003] The original phased array chip is generally a gallium arsenide (GaAs) chip, and the digital control function is not perfect. A simple serial peripheral interface (SPI) four-wire communication mode is used, such as clk, csb, sdi and sdo, and the numbering mode is not flexible and convenient. The current multi-channel phased array chip based on a complementary metal oxide semiconductor (CMOS) processing technology has more flexible digital control, and therefore, the current numbering mode cannot meet the communication needs of the phased array chip, resulting in a complex phased array chip communication mode, which further affects the communication efficiency of the phased array chip. SUMMARY

[0004] The present disclosure provides a phased array chip communication method, device, equipment and a storage medium.

[0005] According to a first aspect of the present disclosure, a phased array chip communication method is provided. The method comprises:

[0006] Obtaining the chip type of each phased array chip in the phased array;

[0007] When the chip types of each phased array chip in the phased array are consistent, according to a preset numbering instruction, the enabling control bit of the chip numbering mode trigger register in each phased array chip in the phased array is selected to select the same numbering enabling signal, so that each phased array chip in the phased array enters the corresponding numbering mode and generates the corresponding chip number, to realize communication with each phased array chip in the phased array.

[0008] According to the preset numbering instruction, the enable control bits of the chip numbering mode trigger register in each phased array chip in the phased array are controlled to select the same numbering enable signal, so that each phased array chip in the phased array enters the corresponding numbering mode and generates the corresponding chip number.

[0009] According to the hardware numbering instruction, the enable control bits of the chip numbering register in each phased array chip in the phased array are controlled to select the same hardware numbering enable signal, and the same hardware numbering enable signal is used to allow a high-low level signal connected to a receiving pin, so that each phased array chip in the phased array reads the high-low level signal and generates the corresponding chip number; wherein the corresponding chip number of each phased array chip in the phased array is a binary number corresponding to the high-low level signal.

[0010] According to the preset numbering instruction, the enable control bits of the chip numbering mode trigger register in each phased array chip in the phased array are controlled to select the same numbering enable signal, so that each phased array chip in the phased array enters the corresponding numbering mode and generates the corresponding chip number.

[0011] According to the software numbering instruction, the enable control bits of the chip numbering mode trigger register in each phased array chip in the phased array are controlled to select the same software numbering enable signal, and the same software numbering enable signal is used to allow a preset number to be written into the chip numbering register, so that each phased array chip in the phased array reads the preset number and generates the corresponding chip number; wherein the corresponding chip number of each phased array chip in the phased array is the preset number.

[0012] According to the preset numbering instruction, the enable control bits of the chip numbering mode trigger register in each phased array chip in the phased array are controlled to select the same numbering enable signal, so that each phased array chip in the phased array enters the corresponding numbering mode and generates the corresponding chip number.

[0013] According to the automatic numbering instruction, the enable control bit of the chip numbering mode trigger register in each phased array chip in the phased array is selected to have the same automatic numbering enable signal. The same automatic numbering enable signal is used to allow the reception of the flag code number transmitted by each stage of the chip that has accumulated the count in the previous stage, so that each phased array chip in the phased array can read the flag code number and generate the corresponding chip number; wherein, the chip number corresponding to each phased array chip in the phased array is the flag code number.

[0014] In addition to the aspects described above and any possible implementations, a further implementation is provided, wherein the method further includes:

[0015] When the chip types of each phased array chip in the phased array are inconsistent, the enable control bit of the chip numbering mode trigger register of each type of phased array chip in the phased array is controlled to select different numbering enable signals according to the preset numbering instruction corresponding to each chip type. This enables each phased array chip in the phased array to enter the corresponding numbering mode and generate the corresponding chip number, so as to realize communication with each phased array chip in the phased array.

[0016] In addition to the aspects described above and any possible implementations, a further implementation is provided, wherein the method further includes:

[0017] When the chip types of each phased array chip in the phased array are inconsistent, the target chip type is determined from the chip types of each phased array chip in the phased array according to the preset selection rules.

[0018] According to the preset number instruction corresponding to the target chip type, the enable control bit of the chip number mode trigger register in each phased array chip in the phased array is controlled to select the same number enable signal, so that each phased array chip in the phased array enters the corresponding number mode and generates the corresponding chip number, so as to realize communication with each phased array chip in the phased array.

[0019] In addition to the aspects and any possible implementations described above, a further implementation is provided in which, after each phased array chip in the phased array enters the corresponding numbering mode and generates the corresponding chip number, the method further includes:

[0020] Displays the chip number corresponding to each phased array chip in the phased array.

[0021] According to a second aspect of this disclosure, a phased array chip communication device is provided. The device includes:

[0022] The acquisition module is used to acquire the chip type of each phased array chip in the phased array;

[0023] The control module is used to control the enable control bit of the chip number mode trigger register of each phased array chip in the phased array to select the same number enable signal according to the preset number instruction when the chip type of each phased array chip in the phased array is the same. This enables each phased array chip in the phased array to enter the corresponding number mode and generate the corresponding chip number, so as to realize communication with each phased array chip in the phased array.

[0024] According to a third aspect of this disclosure, an electronic device is provided. The electronic device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the method described above.

[0025] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the method described above.

[0026] This application provides a phased array chip communication method, apparatus, device, and storage medium. It can obtain the chip type of each phased array chip in the phased array. When the chip types of each phased array chip in the phased array are consistent, it controls the enable control bit of the chip numbering mode trigger register in each phased array chip to select the same numbering enable signal according to a preset numbering instruction. This allows the numbering mode to be determined based on the numbering enable signal, and each chip in the phased array is numbered. This enables each phased array chip to enter the corresponding numbering mode and generate a corresponding chip number, thereby achieving communication with each phased array chip. Based on this, by setting different preset numbering instructions, the enable control bit of the chip numbering mode trigger register in the chip can be controlled to select different numbering enable signals, thereby triggering different numbering modes to number each chip in the phased array, thus providing a more flexible and convenient numbering method and improving the communication efficiency of the phased array chips.

[0027] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0028] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of this disclosure. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0029] Figure 1 A flowchart of a phased array chip communication method according to an embodiment of the present disclosure is shown;

[0030] Figure 2 A schematic diagram showing the phased array chip connection relationship corresponding to the software numbering instructions according to an embodiment of the present disclosure is provided.

[0031] Figure 3 A schematic diagram showing the phased array chip connection relationship corresponding to the automatic numbering instructions according to an embodiment of the present disclosure is provided.

[0032] Figure 4 A block diagram of a phased array chip communication device according to an embodiment of the present disclosure is shown;

[0033] Figure 5 A block diagram of an exemplary electronic device capable of implementing embodiments of the present disclosure is shown. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0035] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0036] In this disclosure, by setting different preset numbering instructions, the enable control bit of the chip numbering method trigger register in the chip can be controlled to select different numbering enable signals, thereby triggering different numbering methods to number each chip in the phased array, thus providing a more flexible and convenient numbering method and improving the communication efficiency of the phased array chip.

[0037] Figure 1 A flowchart of a phased array chip communication method 100 according to an embodiment of the present disclosure is shown.

[0038] In box 110, obtain the chip type of each phased array chip in the phased array.

[0039] In some embodiments, the phased array may include phased array chips of the same chip type or phased array chips of different chip types. The chip types may include GaAs chips, silicon carbide (SiC) chips, gallium nitride (GaN) chips, silicon-based chips, and CMOS chips.

[0040] In some embodiments, the chip type of each phased array chip in the phased array can be obtained through an acquisition module in a control device connected to the phased array chip. The control device can be a phased array chip communication device.

[0041] In box 120, when the chip type of each phased array chip in the phased array is the same, according to the preset numbering instruction, the enable control bit of the chip numbering mode trigger register of each phased array chip in the phased array is controlled to select the same numbering enable signal, so that each phased array chip in the phased array enters the corresponding numbering mode and generates the corresponding chip number, so as to realize communication with each phased array chip in the phased array.

[0042] In some embodiments, the preset numbering instruction may be an instruction set according to the chip type to control the enable control bit of the trigger register for the chip numbering method reserved in each phased array chip to select the numbering enable signal and trigger the numbering method of each phased array chip in the phased array.

[0043] For example, it is inconvenient to number CMOS chips by identifying the high and low levels of pins. In other words, to reduce lead costs, CMOS chips may not use hardware numbering. In this case, the numbering method of CMOS chips can be set to software numbering or automatic numbering, which are more flexible and convenient numbering methods.

[0044] For example, GaAs chips can be conveniently numbered by identifying the high and low levels of the pins, which is a hardware numbering mode. GaAs chips can be set to use hardware numbering, which is a more suitable numbering method.

[0045] In some embodiments, a chip number trigger register reserved within the phased array chip is used to receive a preset number instruction. The enable control bit of this register selects and stores the same number enable signal according to the preset number instruction.

[0046] In some embodiments, before selecting the same number enable signal for the enable control bit of the chip numbering mode trigger register in each phased array chip in the control phased array, the register can be initialized before selecting the chip numbering mode to avoid interference from other external factors that could cause confusion in the chip numbering mode.

[0047] In some embodiments, the numbering enable signal includes 00, 01, and 10, where 00 represents the numbering enable signal for hardware numbering mode, 01 represents the numbering enable signal for software numbering mode, and 10 represents the numbering enable signal for automatic numbering mode.

[0048] In some embodiments, when the chip number stored in the phased array chip trigger register is 00, it can indicate that the phased array chip is in hardware numbering mode; when the chip number stored in the phased array chip trigger register is 01, it can indicate that the phased array chip is in software numbering mode; when the chip number stored in the phased array chip trigger register is 10, it can indicate that the phased array chip is in automatic numbering mode.

[0049] For example, when the chip type is GaAs chip, the preset number instruction can be used to trigger the enable control bit of the trigger register of each phased array chip in the phased array to be selected as 00 for storage, so that each phased array chip in the phased array is hardware numbered according to 00, and the corresponding chip number is generated.

[0050] For example, when the chip type is a CMOS chip, the preset number instruction can be used to trigger the enable control bit of the trigger register in each phased array chip in the phased array to select 0 or 1 for storage, so that each phased array chip in the phased array is hardware numbered according to 0 or 1, and the corresponding chip number is generated.

[0051] In some embodiments, after the enable control bit of the chip numbering mode trigger register in each phased array chip in the phased array selects the same numbering enable signal, that is, after each phased array chip in the phased array determines the numbering mode, the connection relationship of each phased array chip in the phased array can be arranged according to the numbering mode of each phased array chip in the phased array. Then, based on the connection relationship, each phased array chip generates the corresponding chip number according to the numbering mode determined by the received numbering enable signal to complete the numbering.

[0052] In some embodiments, to communicate with each phased array chip in the phased array, the host computer needs to identify the chip name, i.e., the chip number, of each phased array chip and establish communication with that chip based on the identified chip number. Therefore, when the host computer communicates with the phased array chip, the phased array chip needs to provide a more flexible and convenient numbering method so that the host computer can identify and communicate with it.

[0053] According to the embodiments of this disclosure, the following technical effects are achieved:

[0054] By acquiring the chip type of each phased array chip in the phased array, when the chip types of each phased array chip in the phased array are consistent, the enable control bit of the chip numbering mode trigger register in each phased array chip in the phased array is controlled according to the preset numbering instruction to select the same numbering enable signal. In order to determine the numbering mode based on the numbering enable signal, each chip in the phased array is numbered, so that each phased array chip in the phased array enters the corresponding numbering mode and generates the corresponding chip number, thereby realizing communication with each phased array chip in the phased array. Based on this, by setting different preset numbering instructions, the enable control bit of the chip numbering mode trigger register in the chip can be controlled to select different numbering enable signals, thereby triggering different numbering modes to number each chip in the phased array, thus providing a more flexible and convenient numbering method and improving the communication efficiency of the phased array chips.

[0055] In some embodiments, the aforementioned preset numbering instruction is a hardware numbering instruction. The aforementioned method of controlling the enable control bit of the chip numbering mode trigger register in each phased array chip to select the same numbering enable signal according to the preset numbering instruction, so that each phased array chip enters the corresponding numbering mode and generates the corresponding chip number, includes:

[0056] According to the hardware numbering instruction, the enable control bit of the chip number register in each phased array chip in the phased array is selected to have the same hardware number enable signal. The same hardware number enable signal is used to allow the high and low level signals connected to the receiving pin, so that each phased array chip in the phased array can read the high and low level signals and generate the corresponding chip number; wherein, the chip number corresponding to each phased array chip in the phased array is the binary number corresponding to the high and low level signals.

[0057] In some embodiments, when the preset numbering instruction is a hardware numbering instruction, it indicates that the chip type of each phased array chip in the phased array is a chip suitable for the hardware numbering method.

[0058] In some embodiments, when the same hardware number enable signal is used to enable high and low level signals for receiving pin connections, during the process of establishing the connection relationships of each phased array chip in the phased array, each phased array chip reserves several pad pins as numbered pads. Based on this, during the process of generating the corresponding chip number for each phased array chip in the phased array, i.e., when numbering the phased array chip, the phased array chip internally receives the high and low level signals of the pin connections and reads the high and low levels of the pin connections. Low level is 0, and high level is 1. The read binary number is used as the number of the phased array chip.

[0059] According to the embodiments of this disclosure, the following technical effects are achieved:

[0060] By setting a preset numbering instruction as a hardware numbering instruction, a hardware numbering method is provided for phased array chips that are suitable for hardware numbering, thereby further improving the communication efficiency of phased array chips.

[0061] In some embodiments, the aforementioned preset numbering instruction is a software numbering instruction. The aforementioned method of controlling the enable control bit of the chip numbering mode trigger register in each phased array chip to select the same numbering enable signal according to the preset numbering instruction, so that each phased array chip enters the corresponding numbering mode and generates the corresponding chip number, includes:

[0062] According to the software numbering instruction, the enable control bit of the chip numbering mode trigger register in each phased array chip in the phased array is selected to have the same software numbering enable signal. The same software numbering enable signal is used to allow the receiving of a preset number to be written into the chip number register, so that each phased array chip in the phased array can read the preset number and generate the corresponding chip number; wherein, the chip number corresponding to each phased array chip in the phased array is the preset number.

[0063] In some embodiments, when the preset numbering instruction is a software numbering instruction, it indicates that the chip type of each phased array chip in the phased array is a chip suitable for the software numbering method.

[0064] In some embodiments, when the same software number enable signal is used to allow the receiving of writing a preset number into the chip number register, each phased array chip in the phased array retains its chip number register during the process of establishing the connection relationship between each phased array chip. Based on this, the preset number can be written into the chip number register via SPI serial communication.

[0065] like Figure 2 As shown, in serial communication mode, it is not necessary to obtain the chip number of the chip itself. The phased array chip communication device and each phased array chip in the phased array can be constructed into a stack-like structure. Data on a chain is read sequentially by a preset number, and the read preset number is used as the number of the phased array chip.

[0066] For example, when a phased array includes three phased array chips, the CSB of the phased array chip communication device (Master) is connected to the CSB of each of the three phased array chips. The SDO of the phased array chip communication device is connected to the SDI of the first phased array chip (Chip1), the SDO of the first phased array chip is connected to the SDI of the second phased array chip (Chip2), the SDO of the second phased array chip is connected to the SDI of the third phased array chip (Chip3), and the SDO of the third phased array chip is connected to the SDI of the phased array chip communication device. Based on this, the phased array chip communication device is connected to the three phased array chips in series as a chain for serial communication.

[0067] According to the embodiments of this disclosure, the following technical effects are achieved:

[0068] By setting the preset numbering instruction as the software numbering instruction, a software numbering method is provided for phased array chips that are suitable for software numbering, thereby further improving the communication efficiency of phased array chips.

[0069] In some embodiments, the aforementioned preset numbering instruction is an automatic numbering instruction. The aforementioned method of controlling the enable control bit of the chip numbering mode trigger register in each phased array chip to select the same numbering enable signal according to the preset numbering instruction, so that each phased array chip enters the corresponding numbering mode and generates the corresponding chip number, includes:

[0070] According to the automatic numbering instruction, the enable control bit of the chip numbering mode trigger register in each phased array chip in the phased array is selected to have the same automatic numbering enable signal. The same automatic numbering enable signal is used to allow the reception of the flag code number transmitted by each stage of the chip that is accumulated and counted by the previous stage chip, so that each phased array chip in the phased array reads the flag code number to generate the corresponding chip number; wherein, the chip number corresponding to each phased array chip in the phased array is the flag code number.

[0071] In some embodiments, when the preset numbering instruction is an automatic numbering instruction, it indicates that the chip type of each phased array chip in the phased array is a chip suitable for automatic numbering.

[0072] In some embodiments, when the same software number enable signal is used to allow the number of flag codes transmitted by each stage of the chip to receive the accumulated count of the previous stage chip, in the process of setting up the connection relationship of each phased array chip in the phased array, the SDI and SDO of each phased array chip in the phased array are cascaded, and the SDI of the first stage chip is connected to a fixed level.

[0073] like Figure 3 As shown, the SDI of the first-stage chip (Chip#0) is grounded and connected to a fixed level. The SDO of the first-stage chip is connected to the SDI of the second-stage chip (Chip#1), the SDO of the second-stage chip is connected to the SDI of the third-stage chip (Chip#2), the SDO of the third-stage chip is connected to the SDI of the fourth-stage chip (Chip#3), and so on, cascading the SDI and SDO of each phased array chip in the phased array.

[0074] Based on this, after power-on, each phased array chip in the phased array outputs one frame of flag code through SDO, and then transmits the received flag code to the next level chip. The next level chip automatically accumulates the count, reads the number of flag codes, and uses the number of flag codes received by each phased array chip as the chip number of that phased array chip.

[0075] According to the embodiments of this disclosure, the following technical effects are achieved:

[0076] By setting the preset numbering command to an automatic numbering command, an automatic numbering method is provided for phased array chips suitable for automatic numbering, thereby further improving the communication efficiency of phased array chips.

[0077] In some embodiments, the above method further includes:

[0078] When the chip types of each phased array chip in the phased array are inconsistent, the enable control bit of the chip numbering mode trigger register of each type of phased array chip in the phased array is controlled to select different numbering enable signals according to the preset numbering instruction corresponding to each chip type. This enables each phased array chip in the phased array to enter the corresponding numbering mode and generate the corresponding chip number, so as to realize communication with each phased array chip in the phased array.

[0079] In some embodiments, when the chip types of each phased array chip in the phased array are inconsistent, to improve the adaptability of the corresponding numbering methods for each type of phased array chip, a numbering method corresponding to the chip type of the phased array chip can be selected according to the chip type to complete the numbering of the phased array chips. The selection of the numbering method corresponding to the chip type of each phased array chip can be found in the above-described hardware numbering, software numbering, and automatic numbering methods, which will not be elaborated further here for the sake of convenience and brevity.

[0080] According to the embodiments of this disclosure, the following technical effects are achieved:

[0081] By controlling the enable control bit of the chip numbering mode trigger register in each phased array chip to select different numbering enable signals according to the preset numbering instructions corresponding to each chip type, different numbering modes are provided for phased array chips of different chip types in the phased array, thereby enhancing the adaptability of chip numbering modes.

[0082] In some embodiments, the above method further includes:

[0083] When the chip types of each phased array chip in the phased array are inconsistent, the target chip type is determined from the chip types of each phased array chip in the phased array according to the preset selection rules.

[0084] According to the preset number instruction corresponding to the target chip type, the enable control bit of the chip number mode trigger register in each phased array chip in the phased array is controlled to select the same number enable signal, so that each phased array chip in the phased array enters the corresponding number mode and generates the corresponding chip number, so as to realize communication with each phased array chip in the phased array.

[0085] In some embodiments, preset selection rules can be set manually according to actual needs.

[0086] In some embodiments, when the chip types of each phased array chip in the phased array are inconsistent, to improve the compatibility of the corresponding numbering method of the phased array, a target chip type can be determined from the chip types of each phased array chip according to a preset selection rule, and then the phased array chips in the phased array can be numbered according to the numbering method corresponding to the target chip type, thus completing the numbering of the phased array chips. Numbering the phased array chips in the phased array according to the numbering method corresponding to the target chip type can refer to the above-mentioned hardware numbering, software numbering, or automatic numbering methods, which will not be elaborated further here for the sake of convenience and brevity.

[0087] According to the embodiments of this disclosure, the following technical effects are achieved:

[0088] Based on the preset numbering instruction corresponding to the target chip type, the enable control bit of the chip numbering mode trigger register in each phased array chip in the phased array is controlled to select the same numbering enable signal, so as to provide the same chip numbering mode for phased array chips of different chip types in the phased array and enhance the compatibility of chip numbering.

[0089] In some embodiments, after each phased array chip in the phased array enters the corresponding numbering mode and generates the corresponding chip number, the method further includes:

[0090] Displays the chip number corresponding to each phased array chip in the phased array.

[0091] In some embodiments, the phased array chip communication device may include a display module, which can be used to display the chip number corresponding to each phased array chip in the phased array, so that when performing fault detection on each phased array chip in the phased array, the chip number corresponding to the faulty phased array chip can be directly displayed.

[0092] According to the embodiments of this disclosure, the following technical effects are achieved:

[0093] By displaying the chip number corresponding to each phased array chip in the phased array, faulty chips can be directly identified, allowing manufacturers to inspect them based on the chip number and recall the same batch of products with faulty chips after confirming the fault.

[0094] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0095] The above is an introduction to the method embodiments. The following describes the solution described in this disclosure further through device embodiments.

[0096] Figure 4 A block diagram of a phased array chip communication device 400 according to an embodiment of the present disclosure is shown. Figure 4 As shown, the device 400 includes:

[0097] The acquisition module 410 is used to acquire the chip type of each phased array chip in the phased array;

[0098] The control module 420 is used to control the enable control bit of the chip number mode trigger register of each phased array chip in the phased array to select the same number enable signal according to the preset number instruction when the chip type of each phased array chip in the phased array is the same, so that each phased array chip in the phased array enters the corresponding number mode and generates the corresponding chip number, so as to realize communication with each phased array chip in the phased array.

[0099] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the described module can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0100] The acquisition, storage, and application of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0101] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0102] Figure 5A schematic block diagram of an electronic device 500 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0103] Electronic device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in ROM 502 or a computer program loaded into RAM 503 from storage unit 508. RAM 503 can also store various programs and data required for the operation of electronic device 500. The computing unit 501, ROM 502, and RAM 503 are interconnected via bus 504. I / O interface 505 is also connected to bus 504.

[0104] Multiple components in electronic device 500 are connected to I / O interface 505, including: input unit 506, such as keyboard, mouse, etc.; output unit 507, such as various types of monitors, speakers, etc.; storage unit 508, such as disk, optical disk, etc.; and communication unit 509, such as network card, modem, wireless transceiver, etc. Communication unit 509 allows electronic device 500 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0105] The computing unit 501 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 501 performs the various methods and processes described above, such as method 100. For example, in some embodiments, method 100 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 500 via ROM 502 and / or communication unit 509. When the computer program is loaded into RAM 503 and executed by the computing unit 501, one or more steps of method 100 described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured to perform method 100 by any other suitable means (e.g., by means of firmware).

[0106] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0107] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0108] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0109] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including voice input, speech input, or tactile input).

[0110] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0111] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0112] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0113] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A phased array chip communication method, characterized in that, include: Obtain the chip type of each phased array chip in the phased array; When the chip types of each phased array chip in the phased array are consistent, according to the preset numbering instruction, the enable control bit of the chip numbering mode trigger register of each phased array chip in the phased array is controlled to select the same numbering enable signal, so that each phased array chip in the phased array enters the corresponding numbering mode and generates the corresponding chip number, so as to realize communication with each phased array chip in the phased array.

2. The method according to claim 1, characterized in that, The preset numbering instruction is a hardware numbering instruction. The step of controlling the enable control bit of the chip numbering mode trigger register in each phased array chip to select the same numbering enable signal according to the preset numbering instruction, so that each phased array chip enters the corresponding numbering mode and generates the corresponding chip number, includes: According to the hardware numbering instruction, the enable control bit of the chip number register in each phased array chip in the phased array is selected to have the same hardware numbering enable signal. The same hardware numbering enable signal is used to allow the high and low level signals connected to the receiving pin, so that each phased array chip in the phased array reads the high and low level signals and generates the corresponding chip number; wherein, the chip number corresponding to each phased array chip in the phased array is the binary number corresponding to the high and low level signals.

3. The method according to claim 1, characterized in that, The preset numbering instruction is a software numbering instruction. The step of controlling the enable control bit of the chip numbering mode trigger register in each phased array chip to select the same numbering enable signal according to the preset numbering instruction, so that each phased array chip enters the corresponding numbering mode and generates the corresponding chip number, includes: According to the software numbering instruction, the enable control bit of the chip numbering mode trigger register in each phased array chip in the phased array is selected to have the same software numbering enable signal. The same software numbering enable signal is used to allow the receiving of a preset number to be written into the chip number register, so that each phased array chip in the phased array reads the preset number and generates the corresponding chip number; wherein, the chip number corresponding to each phased array chip in the phased array is the preset number.

4. The method according to claim 1, characterized in that, The preset numbering instruction is an automatic numbering instruction. The step of controlling the enable control bit of the chip numbering mode trigger register in each phased array chip to select the same numbering enable signal according to the preset numbering instruction, so that each phased array chip enters the corresponding numbering mode and generates the corresponding chip number, includes: According to the automatic numbering instruction, the enable control bit of the chip numbering mode trigger register in each phased array chip in the phased array is selected to have the same automatic numbering enable signal. The same automatic numbering enable signal is used to allow the reception of the flag code number transmitted by each stage of the chip that has accumulated the count in the previous stage, so that each phased array chip in the phased array can read the flag code number and generate the corresponding chip number; wherein, the chip number corresponding to each phased array chip in the phased array is the flag code number.

5. The method according to claim 1, characterized in that, The method further includes: When the chip types of each phased array chip in the phased array are inconsistent, the enable control bit of the chip numbering mode trigger register of each type of phased array chip in the phased array is controlled to select different numbering enable signals according to the preset numbering instruction corresponding to each chip type. This enables each phased array chip in the phased array to enter the corresponding numbering mode and generate the corresponding chip number, so as to realize communication with each phased array chip in the phased array.

6. The method according to claim 1, characterized in that, The method further includes: When the chip types of each phased array chip in the phased array are inconsistent, the target chip type is determined from the chip types of each phased array chip in the phased array according to the preset selection rules. According to the preset number instruction corresponding to the target chip type, the enable control bit of the chip number mode trigger register in each phased array chip in the phased array is controlled to select the same number enable signal, so that each phased array chip in the phased array enters the corresponding number mode and generates the corresponding chip number, so as to realize communication with each phased array chip in the phased array.

7. The method according to any one of claims 1 to 6, characterized in that, After each phased array chip in the phased array enters the corresponding numbering mode and generates the corresponding chip number, the method further includes: Displays the chip number corresponding to each phased array chip in the phased array.

8. A phased array chip communication device, characterized in that, include: The acquisition module is used to acquire the chip type of each phased array chip in the phased array; The control module is used to control the enable control bit of the chip number mode trigger register of each phased array chip in the phased array to select the same number enable signal according to the preset number instruction when the chip type of each phased array chip in the phased array is the same. This enables each phased array chip in the phased array to enter the corresponding number mode and generate the corresponding chip number, so as to realize communication with each phased array chip in the phased array.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory that is communicatively connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in any one of claims 1-7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-7.

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