An acidic copper plating solution additive for through silicon via copper filling, an acidic copper plating solution and a through silicon via copper metal filling method

Abstract

The present application relates to the technical fields of semiconductor electroplating, in particular to an acidic copper plating solution additive for through silicon via (TSV) copper filling, an acidic copper plating solution and a copper metal filling method for TSV. The additive is composed of a carrier, a brightener and a leveling agent, and the carrier, the brightener and the leveling agent are in a mass ratio of (100-5000):(1-100):(5-200). The acidic copper plating solution provided by the present application uses water as a solvent, copper methanesulfonate or copper sulfate pentahydrate as a main salt, and adopts constant step current density for copper electroplating filling. In the applicable condition range, the present application can realize dense and complete filling of TSV with a hole diameter of 2-10 mu m, a hole depth of 16-300 mu m and a depth-diameter ratio of more than 8:1, and the filling layer is free of holes and gaps, thus meeting the application requirements in the field of 3D packaging.

Description

Technical Field

[0001] This invention relates to the field of semiconductor electronic electroplating technology, and in particular to an acidic copper plating solution additive for copper filling of through-silicon vias, an acidic copper plating solution, and a method for copper metal filling of through-silicon vias. Background Technology

[0002] Through-Silicon Vias (TSV) 3D packaging offers advantages such as high-density integration, low latency, and low power consumption, making it one of the core technologies in the future advanced microelectronics manufacturing and packaging industry. TSV technology achieves direct vertical interconnection between chips through a copper metal filling layer within the silicon via, minimizing electrical signal transmission distance and reducing signal latency and loss. The TSV process flow includes TSV etching, vapor deposition of a barrier layer and seed layer, copper plating, chemical mechanical polishing, wafer thinning, and wafer bonding; among these, the copper plating step is the most challenging and critical. In high depth-of-field structures, uneven material concentration and electric field distribution at the bottom and opening of the via can lead to voids and gaps in the copper filling layer, causing device failure.

[0003] Currently, advanced packaging technologies in the industry use through-silicon vias (TSVs) with apertures as low as 10μm and aspect ratios greater than 8:1, even reaching 30:1. However, existing copper plating processes struggle to achieve dense filling of these vias. To meet the future technological demands of the advanced packaging industry, a copper metal filling technology for TSVs with small apertures and high aspect ratios is urgently needed. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide an acidic copper plating solution additive for copper filling of through-silicon vias, an acidic copper plating solution, and a method for copper metal filling of through-silicon vias.

[0005] To address the aforementioned technical problems, one of the technical solutions provided by this invention is as follows:

[0006] An additive for acidic copper plating solution used for copper filling of through-silicon vias, the additive comprising a carrier, a brightener, and a leveling agent;

[0007] The carrier, brightener and leveling agent are composed of a mass ratio of (100-5000):(1-100):(5-200);

[0008] The carrier is one or a combination of several of the following: A) a polyetheramine with a molecular weight of 1,000 to 10,000; a polymer of 1,2-ethylenediamine with ethylene oxide and methyl propylene oxide; B) a polymer of methyl ethylene oxide with 1,2-ethylenediamine and ethylene oxide; and C) an ethylene oxide-propylene oxide block copolymer.

[0009] The brightener is sodium polydithiopropane sulfonate or sodium 3-mercaptopropane sulfonate.

[0010] The leveling agent is one or a combination of several of the following: a) diallyl dimethyl ammonium chloride and an amide-like substance; b) diallyl dimethyl ammonium chloride; c) polydiallyl dimethyl ammonium chloride; and d) poly(acrylamide-co-diallyl dimethyl ammonium chloride).

[0011] In a preferred embodiment, the amide substance includes one or a combination of several of acrylamide, N-vinylcaprolactam, allyl oxaliplatin, N,N-diallyl-2,2,2-trifluoroacetamide, and diallyl-N,N-diisopropylphosphamide.

[0012] In a preferred embodiment, the carrier, brightener, and leveling agent are composed in a mass ratio of (100–2500):(1.5–50):(5–150).

[0013] The second technical solution provided by this invention is as follows:

[0014] An acidic copper plating solution for copper filling of through-silicon vias, wherein the acidic copper plating solution uses water as a solvent, copper methanesulfonate or copper sulfate pentahydrate as the main salt, and contains additives as described in claim 1 or 2.

[0015] In a preferred embodiment, the acidic copper plating solution comprises: 30–280 g / L of copper methanesulfonate, 20–100 g / L of methanesulfonic acid, and 30–100 mg / L of chloride ions.

[0016] In a preferred embodiment, the acidic copper plating solution comprises: 120–240 g / L of copper sulfate pentahydrate, 30–80 g / L of sulfuric acid, and 30–100 mg / L of chloride ions.

[0017] In a preferred embodiment, the additive comprises: 20-500 mg / L of a carrier, 0.3-10 mg / L of a brightener, and 1-30 mg / L of a leveling agent.

[0018] In the technical solution provided by this invention, the suitable concentration of the carrier in the acidic copper plating solution is 20-500 mg / L. If the carrier concentration is lower than 20 mg / L, the copper deposition rate at the through-silicon via opening is too fast, resulting in holes at the bottom of the via. Increasing the carrier concentration further beyond 500 mg / L does not significantly improve the actual hole-filling effect and may lead to inclusions in the copper plating layer, affecting the conductivity, ductility, and other properties of the copper layer.

[0019] The appropriate concentration of brightener in acidic copper plating solution is 0.3–10 mg / L. Brightener is adsorbed at the bottom of the hole, which accelerates the copper deposition rate at the bottom of the hole and improves the density and flatness of the copper layer on the wafer surface, which is beneficial for subsequent chemical mechanical polishing. If the concentration of brightener is higher than 10 mg / L, it is difficult to achieve dense filling of silicon through holes from top to bottom.

[0020] The suitable concentration of the leveling agent in acidic copper plating solution is 1–30 mg / L. The leveling agent has the ability to inhibit copper deposition. The adsorption strength of the leveling agent increases with the increase of convection intensity, resulting in a much higher adsorption amount at the orifice than at the bottom, which helps to achieve dense "top-down" filling of the through-silicon vias. When the leveling agent concentration is higher than 30 mg / L, the difference in adsorption amount at the orifice and bottom does not induce a significant difference in copper deposition rate, leading to premature sealing of the orifice during the filling process. Simultaneously, due to excessive inhibition of copper deposition, the copper grains on the wafer surface are coarse, resulting in a rough appearance.

[0021] The third technical solution provided by this invention is as follows:

[0022] A method for filling a through-silicon via with copper metal includes the following steps:

[0023] (1) The conductive silicon wafer is placed in a vacuum chamber for vacuum treatment, and then transferred to a water tank for immersion under vacuum. The water tank is preferably a pure water tank. The silicon wafer includes an upper surface, a lower surface, and a through-hole structure. The through-hole structure includes an opening embedded in the upper surface of the wafer, a side wall extending from the front surface of the wafer, and a bottom. The depth of the through-hole structure is more than 16 μm and less than 300 μm, the aperture is more than 2 μm and less than 10 μm, and the depth-to-diameter ratio is more than 8:1.

[0024] (2) The silicon wafer after vacuum immersion is placed in the plating solution and electroplated at 22-30°C using a constant step current density in 2-4 stages, and the step current density increases step by step.

[0025] It is worth noting that the study found that at temperatures below 22°C, the allowable current density for the process is low, leading to reduced via filling efficiency; while at temperatures above 30°C, the surface copper layer is rough, which is not conducive to subsequent chemical mechanical polishing. Furthermore, this invention specifically uses a low current density in the initial stage to increase the conductive layer thickness; subsequently, the current density is increased for via filling; as the through-silicon vias are filled from top to bottom, the aspect ratio decreases, at which point a high current density can be used for the final filling.

[0026] In a preferred embodiment, in step (1), the soaking time is 30s to 2min, and during the soaking process, ultrasound or stirring is applied to help completely remove the air in the silicon through-hole so as to facilitate the filling of metallic copper.

[0027] In a preferred embodiment, in step (2), the wafer cathode moves or rotates during the electroplating process, and the anode is a phosphorus-containing copper plate, a platinum-plated titanium mesh, or an iridium-coated titanium mesh. The current density range for each stage is 0.01–1.0 A / dm³. 2 .

[0028] In some embodiments, for a through-silicon via with a aperture of 3 μm and a depth of 45 μm, the stepped current densities are as follows: the current density of the first stage is 0.1 A / dm. 2 The time was 20 minutes; the current density in the second stage was 0.3 A / dm³. 2 The time is 40 minutes;

[0029] In some embodiments, for a through-silicon via with a aperture of 5 μm and a depth of 50 μm, the stepped current densities are as follows: the current density of the first stage is 0.1 A / dm. 2 The time was 20 minutes; the current density in the second stage was 0.3 A / dm³. 2 The time was 90 minutes; the current density in the third stage was 0.5 A / dm³. 2 The time is 30 minutes.

[0030] In summary, this application includes at least one of the following beneficial technical effects:

[0031] (1) This invention achieves dense and void-free through-holes with a diameter of less than 10μm and an aspect ratio of more than 8:1 by combining the synergistic effect of the carrier, brightener and leveling agent with a stepped DC current electroplating method. This solves the problems of unstable electrical signal transmission and open circuit caused by holes and gaps in the process of filling small diameter and high aspect ratio through-holes in the 3D packaging field.

[0032] (2) The carrier in this invention has a strong effect of inhibiting copper deposition, which can significantly inhibit the copper deposition rate at the orifice and prevent the copper layer void phenomenon caused by the excessively fast copper deposition rate at the orifice.

[0033] (3) The leveling agent in this invention has mixed characteristics that inhibit copper deposition and whose adsorption capacity is affected by diffusion. Through the synergistic effect of the leveling agent, carrier and brightener under specific components and specific ratios, the effect of copper metal in inhibiting copper deposition at the orifice is much stronger than that at the bottom of the orifice, thereby achieving dense filling of the through-silicon via from top to bottom.

[0034] Other features and beneficial effects of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other beneficial effects of the invention can be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Unless otherwise specified, the positional relationships shown in the drawings in the following description are based on the direction in which the components are drawn in the figure.

[0036] Figures 1-2 These are metallographic images of the through-silicon via cross-sections when the additive ratio is appropriate, as shown in Examples 1 and 2 of the present invention.

[0037] Figures 3-5 These are metallographic images of the through-silicon via cross-sections when the additive ratio is inappropriate in Comparative Examples 1-3 of this invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The technical features designed in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0039] In the description of this invention, it should be noted that all terms used in this invention (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains, and should not be construed as limiting the invention; it should be further understood that the terms used in this invention should be understood to have the same meaning as those in the context of this specification and in the relevant field, and should not be understood in an idealized or overly formal sense, except as expressly defined in this invention.

[0040] The technical solution of the present invention will be further illustrated and described below through specific embodiments. However, the scope of protection of the present invention is not limited thereto.

[0041] An acidic copper plating solution additive for copper filling of through-silicon vias (TSVs), the acidic copper plating solution, and a method for copper metal filling of TSVs.

[0042] Examples 1 to 3

[0043] The preparation and usage of an acidic copper plating solution containing additives (taking 1L as an example) are as follows:

[0044] (1) Prepare the additive mixture:

[0045] Accurately weigh 10-50g of carrier, weigh the brightener at a mass ratio of carrier to brightener of 10-50:0.1-10, dissolve and dilute to 1L to obtain additive mixture A; accurately weigh 1-10g of leveling agent, dissolve and dilute to 1L to obtain additive mixture B.

[0046] (2) Preparation of copper plating base solution:

[0047] The composition of the copper methanesulfonate base solution is: copper methanesulfonate 30-280 g / L, methanesulfonic acid 20-100 g / L, chloride ions 30-100 mg / L;

[0048] The composition of the copper sulfate base solution is: copper sulfate pentahydrate 120-240 g / L, sulfuric acid 30-80 g / L, chloride ion 30-100 mg / L;

[0049] Chloride ions are added in the form of sodium chloride solution or hydrochloric acid solution.

[0050] (3) Prepare an acidic copper plating solution containing additives:

[0051] Add 1-10 ml / L of additive mixture A and 1-5 ml / L of additive mixture B to the copper plating base solution.

[0052] The conductive silicon wafer is degreased with an acidic degreasing solution (40°C, 3 min), rinsed with deionized water, and then placed in a vacuum chamber. The vacuum is evacuated to below 0.05 bar and held for 1 min. It is then transferred to a pure water bath under vacuum and immersed for 1 min. After removal, it is placed in an electroplating solution. A phosphorus-containing copper plate, a platinum-plated titanium mesh, or an iridium-coated titanium mesh is used as the anode, and a stepped current density is applied. During electroplating, the wafer cathode moves or rotates. Under suitable additive ratios and process conditions, dense filling of through-hole copper can be achieved. The silicon wafer includes an upper surface, a lower surface, and a through-hole structure. The through-hole structure includes an opening embedded in the upper surface of the wafer, a sidewall extending from the front surface of the wafer, and a bottom. The depth of the through-hole structure is greater than 16 μm and less than 300 μm, the aperture is greater than 2 μm and less than 10 μm, and the aspect ratio is greater than 8:1.

[0053] The specific through-hole structure of silicon wafers, electroplating solution composition, process conditions, and filling effect are shown in Tables 1 and 2 below. Figures 1 to 3 As shown.

[0054] Table 1 Implementation conditions and filling effect of specific embodiments

[0055]

[0056]

[0057] Table 2 shows the specific implementation conditions and filling effects of the comparative model.

[0058]

[0059]

[0060]

[0061] The examples and comparative examples show that dense filling cannot be achieved when one of the conditions of the additive is not met. An unreasonable ratio of the additives or an incorrect selection of additives will lead to poor final filling effect.

[0062] When the diameter of the through-silicon via is increased to 10–50 μm and the depth-to-diameter ratio is 3:1–20:1, the results obtained are the same as those in the above embodiments.

[0063] Furthermore, those skilled in the art should understand that although many problems exist in the prior art, each embodiment or technical solution of the present invention can be improved in only one or a few aspects, without necessarily solving all the technical problems listed in the prior art or the background art simultaneously. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as a limitation on that claim.

[0064] Although this document frequently uses terms such as leveling agent, carrier, and brightener, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of the invention; interpreting them as any additional limitation would contradict the spirit of the invention. The terms "first," "second," etc. (if present) in the specification, claims, and accompanying drawings of the embodiments of the invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for filling through-silicon vias with copper metal, characterized in that, Includes the following steps: (1) The conductive silicon wafer is placed in a vacuum chamber for vacuum treatment, and then transferred to a water bath for immersion under vacuum. The silicon wafer includes an upper surface, a lower surface, and a through-hole structure. The through-hole structure includes an opening embedded in the upper surface of the wafer, a sidewall extending from the front surface of the wafer, and a bottom. The depth of the through-hole structure is more than 16 μm and less than 300 μm, the aperture is more than 2 μm and less than 10 μm, and the depth-to-diameter ratio is more than 8:

1. (2) The silicon wafer after vacuum immersion is placed in the plating solution and electroplated at 22-30 °C using a constant step current density of 2-4 stages, wherein the step current density increases step by step; the plating solution is an acidic copper plating solution, with water as solvent, copper methanesulfonate or copper sulfate pentahydrate as main salt, and additives added; the additives are composed of carrier, brightener and leveling agent in a mass ratio of (100-5000):(1-100):(5-200); The carrier is one or a combination of several of the following: A) a polyetheramine with a molecular weight of 1,000 to 10,000; a polymer of 1,2-ethylenediamine with ethylene oxide and methyl propylene oxide; B) a polymer of methyl ethylene oxide with 1,2-ethylenediamine and ethylene oxide; and C) an ethylene oxide-propylene oxide block copolymer. The brightener is sodium polydithiopropane sulfonate or sodium 3-mercaptopropane sulfonate. The leveling agent is one or a combination of several of the following: a) diallyl dimethyl ammonium chloride and an amide-like substance; b) diallyl dimethyl ammonium chloride; c) polydiallyl dimethyl ammonium chloride; and d) poly(acrylamide-co-diallyl dimethyl ammonium chloride).

2. The method for filling silicon vias with copper metal according to claim 1, characterized in that: The amides include one or a combination of several of acrylamide, N-vinylcaprolactam, allyl oxychloride, N,N-diallyl-2,2,2-trifluoroacetamide, and diallyl-N,N-diisopropylphosphamide.

3. The method for filling silicon vias with copper metal according to claim 1, characterized in that: The carrier, brightener and leveling agent are composed of a mass ratio of (100-2500):(1.5-50):(5-150).

4. The method for filling silicon vias with copper metal according to claim 1, characterized in that, The acidic copper plating solution contains: 30–280 g / L of copper methanesulfonate, 20–100 g / L of methanesulfonic acid, and 30–100 mg / L of chloride ions.

5. The method for filling silicon vias with copper metal according to claim 1, characterized in that... The acidic copper plating solution contains: 120-240 g / L of copper sulfate pentahydrate, 30-80 g / L of sulfuric acid, and 30-100 mg / L of chloride ions.

6. The method for filling silicon vias with copper metal according to claim 1, characterized in that, The additives include: 20–500 mg / L of carrier, 0.3–10 mg / L of brightener, and 1–30 mg / L of leveling agent.

7. The method for filling silicon vias with copper metal according to claim 1, characterized in that: In step (1), the soaking time is 30s to 2min, and ultrasound or stirring is applied during the soaking process.

8. The method for filling through-silicon vias with copper metal according to claim 1, characterized in that: In step (2), the wafer cathode moves or rotates during the electroplating process, and the anode is a phosphorus copper plate, a platinum titanium mesh, or an iridium oxide titanium mesh. The current density range for each stage is 0.01–1.0 A / dm³. 2 .

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