A PWM-controlled optical phased array row-column folded phase shifter drive system

Abstract

The present invention discloses a PWM-controlled, row-column folded phase shifter drive system for an optical phased array. The system includes a PWM-generating logic circuit and an LDO (Low-Dropout) linear regulator (LDO) with a precise output voltage and low ripple to generate a stable PWM drive signal. The phase shifter section arranges the thermo-optical phase shifters in a folded row-column configuration, connecting the positive electrodes of the phase shifters in the same column together as a drive circuit, and the negative electrodes of the phase shifters in the same row together as an enable circuit. An FPGA control circuit controls the low-level on / off switching of the enable circuit while simultaneously outputting a PWM signal to the drive circuit to address a specific phase shifter in the row or column, thereby achieving the desired time-sharing multiplexing function for the phase shifter drive. This design can reduce the optical path length of the chip, optimize the heater adjustment and switching mechanism, and significantly reduce the number of required drivers.

Description

Technical Field

[0001] The present invention relates to the technical field of optical phased arrays, and in particular to an array-type thermo-optical phase shifter driving system. Background Art

[0002] With the development of silicon-based optoelectronics technology, pure solid-state lidar (LiDAR) based on optical phased array (OPA) principles is expected to become a mainstream technology due to its excellent performance, compact size, and high degree of integration. Its main operating principle is that a laser light source passes through an optical beam splitter and enters an optical waveguide array. A drive circuit controls a phase shifter on the waveguide to change the phase of the light wave, and the phase difference between the waveguides is used to achieve beam scanning.

[0003] Currently, thermo-optical phase shifters (TOPS) play an important role in optical phased arrays because they require a shorter phase modulator, resulting in a smaller size and facilitating further integration. Optical phased arrays require TOPS devices with high tuning efficiency and fast switching times, specifically, a small Form of Material (FOM) (the product of the thermal time constant τ and the tuning efficiency Pπ). However, the long thermal time constant of TOPS makes it difficult to reduce heating and cooling times, which is disadvantageous for large-scale photonic integrated circuits (PICs). Furthermore, DC-driven TOPS devices are currently widely used, resulting in a quadratic increase in phase shift with applied voltage. This, combined with the nonlinearity of incompletely fabricated heaters and the temperature-dependent electrical properties of silicon, results in a nonlinear device response, which can increase the complexity of the feedback system used to drive the thermo-optical phase shifter. Summary of the Invention

[0004] Purpose of the Invention: In response to the above-mentioned prior art, a phased array row-column folded phase shifter drive system based on PWM control is proposed to solve the problems of the existing optical phased array drive circuits being highly complex, the heating and cooling processes of the thermo-optical phase shifters being too long, and the insufficient utilization of individual phase shifters.

[0005] Technical solution: A PWM-controlled optical phased array row-column folded phase shifter drive system, comprising a controller, an FPGA switch control circuit, a first switch array, an FPGA-generated PWM circuit, an LDO power supply circuit array, a row-column folded phase shifter array, and a second switch array;

[0006] The row-column folded phase shifter array includes thermo-optical phase shifters arranged in an array of M columns and N rows. The positive electrodes of the thermo-optical phase shifters in the same column are connected together as a driving circuit, and the negative electrodes of the thermo-optical phase shifters in the same row are connected together as an enabling circuit. The thermo-optical phase shifters in each column are grouped together, and a group of thermo-optical phase shifters controls one waveguide.

[0007] Each enable circuit is grounded via a switch in a first switch array, which is controlled by the FPGA switch control circuit; each drive circuit is connected to the LDO power circuit array via a switch in a second switch array, which is controlled by a PWM drive signal output by a PWM circuit generated by the FPGA;

[0008] The controller is used to control the FPGA switch control circuit and the FPGA PWM generation circuit. During operation, only one enable circuit is enabled at a low level at a time, and each drive circuit is loaded with a PWM wave of different duty cycles through the second switch array to achieve phase adjustment; each enable circuit is sequentially selected according to a period that is less than the thermal conduction time constant of the thermo-optical phase shifter.

[0009] Furthermore, a monitor array is included for sensing the output direction and phase of the light beam in each waveguide, and inputting the sensed sensed sensed sensed sensed sensed phase of the light beam in each waveguide into the controller as a feedback signal for feedback control.

[0010] Furthermore, in the row-column folded phase shifter array, each driving circuit corresponds to a PWM driving signal, and each thermo-optical phase shifter and the enabling circuit in each driving circuit are time-division multiplexed controlled in the same cycle.

[0011] Furthermore, each unit in the LDO power supply circuit array includes a voltage divider sampling circuit, a reference voltage, an error amplifier circuit and a transistor switch circuit; the external voltage V in The output end of the transistor switch circuit is connected, and the voltage sampling circuit uses the series resistors R1 and R2 to measure the voltage V in The reference voltage is generated by the bandgap voltage reference; the error amplifier circuit converts the voltage V collected by the voltage divider sampling circuit into FB The voltage is input to the non-inverting input terminal of the comparator in the error amplifier circuit and compared with the reference voltage at the inverting input terminal. The comparison result is amplified and output to the control electrode of the transistor switch circuit to control the conduction of the transistor switch circuit.

[0012] Beneficial Effects: The present invention provides a phased array drive circuit and row-column folded phase shifter array based on PWM control. The drive circuit comprises a PWM-generating logic circuit and an LDO (Low-Dropout) linear regulator (LDO) with a precise output voltage and low ripple to produce a stable PWM drive signal. The phase shifter utilizes a highly efficient spiral thermo-optical phase shifter, which is arranged in a folded row-column configuration. The positive electrodes of the phase shifters in the same column are connected together as a drive circuit, while the negative electrodes of the phase shifters in the same row are connected together as an enable circuit. An FPGA control circuit controls the low-level switching of the enable circuit and simultaneously outputs a PWM signal to the drive circuit to address a specific phase shifter in the row or column, thereby achieving the desired time-division multiplexing function for the phase shifter drive. This design can reduce the optical path length of the chip, optimize the heater adjustment and switching mechanism, and significantly reduce the number of required drivers. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a system block diagram of a phased array phase shifter array driving circuit according to an embodiment of the present invention;

[0014] Figure 2 is a schematic diagram of an expandable row-column folded phase shifter array according to the present invention;

[0015] Figure 3 Schematic diagram of the LDO structure according to an embodiment of the present invention;

[0016] Figure 4 This is a schematic diagram of an error amplifier circuit of an LDO main structure according to an embodiment of the present invention;

[0017] Figure 5 A schematic diagram of a logic circuit for generating PWM signals and switching signals for an FPGA according to an embodiment of the present invention;

[0018] Figure 6 Schematic diagram of the internal logic circuits of U2 and U5 in the FPGA circuit according to an embodiment of the present invention;

[0019] Figure 7 Schematic diagram of the internal logic circuit of U6 in the FPGA circuit according to an embodiment of the present invention;

[0020] Figure 8 Schematic diagram of timing waveforms according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further explained below with reference to the accompanying drawings.

[0022] like Figure 1As shown, a PWM-controlled optical phased array row-column folded phase shifter driving system includes a controller 1, an FPGA switch control circuit 2, a first switch array 3, an FPGA generated PWM circuit 4, an LDO power supply circuit array 5, a row-column folded phase shifter array 6, a monitor array 7, and a second switch array 12.

[0023] like Figure 2 As shown, multiple thermo-optic phase shifters are arranged in a folded row-column arrangement, divided into M columns and N rows. The positive electrodes of the thermo-optic phase shifters in the same column are connected together as a drive circuit, and the negative electrodes of the thermo-optic phase shifters in the same row are connected together as an enable circuit. The thermo-optic phase shifters in each column are grouped together, and a group of thermo-optic phase shifters controls one waveguide. This type of thermo-optic phase shifter array is called a row-column folded phase shifter array. This structure reduces the number of electrical connections required for the M×N thermo-optic phase shifters in a phased array from 2M×N (when each phase shifter is driven individually) to M+N, significantly reducing circuit complexity.

[0024] The switch signal generated by the FPGA switch control circuit 2 sets the level of the enable circuit to a low level (GND). At the same time, the FPGA generates a PWM circuit 4 that connects the corresponding drive circuit to the LDO output terminal, so that the voltage connected to the drive circuit is a high level (V+). This can address and start a specific thermo-optical phase shifter in the phase shifter array. Each drive circuit in the row-column folded phase shifter array 6 corresponds to a PWM drive signal, thereby realizing the time-division multiplexing function of the phase shifter drive. The key to time-division multiplexing is that the N phase shifters in the same column will be driven within the equivalent time of their corresponding PWM drive signals. This scalable row-column folded phase shifter design can reduce the optical path length of the chip, optimize the adjustment and switching mechanism of the heater, and greatly reduce the number of required drivers.

[0025] Specifically, its negative electrode serves as the enable terminal, grounded only when the switch is closed by a switching signal, allowing the phase shifter to conduct. The positive electrode of the phase shifter serves as the drive terminal. The phase shifter is activated only when the enable terminal is grounded and the drive terminal is at a high level; otherwise, it remains idle. To ensure that a specific phase shifter is accurately and uniquely activated when a drive signal is applied to a specific drive line, only one enable line is enabled at a time, while the remaining enable lines remain disabled. Therefore, rows are only enabled when the voltage is low. Once a row in the row-column folded phase shifter array is enabled, any thermo-optical phase shifter in that row can be driven by setting that column to a high voltage (V+). If the phase shifters in each column are considered a group, the M×N phase shifters are divided into M groups, each of which is connected to a waveguide. A group of phase shifters controls one waveguide. At any given time, at least one phase shifter in each group is activated, ensuring that the optical signals in each waveguide have the corresponding phase difference. Because only one enable line is enabled at a time, all phase shifters in the same row are enabled at the same time. By relying on the large time constant of the thermo-optical phase shifter to average the power in the phase shifter during the drive cycle and maintaining a sufficiently fast refresh cycle, the waveguide in each phase shifter maintains a constant temperature.

[0026] The present invention employs a closed-loop controlled optical phased array system, using PWM control signals to a second switch array 12 via LDOs to achieve time-division multiplexing of the phase shifters in a row-column folded phase shifter array. The controller 1 generates control signals directly from a given register file or lookup table, sending write data commands to the FPGA control circuit 2 and the FPGA-generated PWM circuit 4. However, for practical operation, calibration is required to account for external influences (such as temperature and process variations). To this end, sensors in the monitor array 7 sense the output direction and phase of the light beam. Based on this sensor feedback, the feedback controller 1 calculates the optical path difference (OPD) required for each unit and then sends adjustment signals to the FPGA control circuit and FPGA-generated PWM circuit to adjust the OPD of each unit. After the beam is adjusted, the sensors again sense the output direction and phase, feeding this information back to the control system. Based on this feedback, the control system performs the next round of OPD adjustment, forming a closed-loop control system that can adapt to optical interference and fluctuations in complex environments.

[0027] Figure 1 Each unit in the LDO power supply circuit array 5 is as follows Figure 3 As shown, it is divided into four parts, namely, the voltage dividing sampling circuit 8, the error amplifier circuit 9, the reference voltage 10 and the transistor switch circuit 11. Among them, the external voltage V in The output end is connected to the transistor switch circuit, and the voltage divider sampling circuit uses two resistors R1 and R2 to measure the external voltage V in The error amplifier circuit collects the voltage VFB Input to the comparator non-inverting input terminal and the reference voltage V ref , that is, the expected output voltage is compared, and then the comparison result is amplified. Reference voltage V ref It is generated using a bandgap voltage reference to minimize the effects of temperature changes on the reference. The purpose of the transistor adjustment circuit is to output the amplified signal from the comparator to the control electrode of the transistor switching circuit, that is, the gate of the MOS tube, so that the amplified signal controls the conduction voltage of the MOS tube, forming a negative feedback regulation loop.

[0028] In this negative feedback regulation loop, when the final output voltage drops due to load changes or other reasons, the voltage across the two series voltage divider resistors will also drop, and then the collected voltage will drop. The collected voltage is compared with the reference voltage V at the inverting end. ref In contrast, the error amplifier will reduce its output, causing the transistor gate potential to drop. The input voltage is connected to the source of the transistor, so V s The voltage remains unchanged, which makes |V gs |The voltage difference increases, the output current I sd The error amplifier circuit generates an error voltage by comparing the error between the sampled voltage and the reference voltage Vref. This voltage then adjusts the transistor voltage drop to maintain a constant output voltage. Assuming the reference voltage is stable, the error amplifier is a key factor influencing the performance of the linear regulator.

[0029] The error amplifier circuit 9 in the LDO power supply circuit is as follows Figure 4 As shown, Iin_Dn_5u indicates the required input current of 5μA, and Dn refers to the downward current direction. The error amplifier circuit affects the LDO's output voltage accuracy, the closed-loop system's power supply rejection ratio, and provides sufficient gain to drive the power transistor. A folded op amp can provide high gain and improve the power supply rejection ratio. The zero-pole distribution determines the LDO loop stability. Cascode compensation can be used to separate the poles of the folded op amp to improve loop stability. Here, an NMOS input folded cascode op amp is used. NM0-NM6 and PM0-PM5 collectively form the error amplifier. NM0, NM1, and PM0-PM3 provide large output resistance to achieve high gain. NM4, NM5, PM4, and PM5 are bias circuits.

[0030] For silicon photonic heaters, the thermal time constant τ is typically in the range of 10μs to 500μs, which makes the regulation or switching mechanism of the heater relatively slow. Figure 2Taking the 3×3 matrix folded phase shifter array in [1] as an example, we explore the scenario where each phase shifter in a column is energized for at most one-third of the cycle. This time-division multiplexing scheme is effective only when the large time constant of the thermo-optical phase shifter is relied upon to average the power in the phase shifter during the drive cycle. When the refresh cycle is sufficiently fast and shorter than the thermal conduction time constant in the phase shifter, the waveguide in each phase shifter maintains a constant temperature, thus avoiding phase shift drift due to temperature changes and achieving a stable phase shift. Here, τ is assumed to be 80 μs. To keep the thermal time constant significantly longer than the drive cycle, we assume a drive cycle of T = 6 μs and f ≈ 166.7 kHz.

[0031] In this invention, the logic circuit is divided into two modules. One module generates a switching signal that controls the enable circuit of the phase shifter array. The enable circuit is connected to ground via a switch. The switching signal controls the on / off state of the switch, thereby controlling whether the enable circuit is connected to a low level. The other module generates a PWM signal with an adjustable duty cycle. The PWM signal is connected to the second switch array 12 to control the on / off state and on-time of each switch therein, ultimately driving each phase shifter.

[0032] generate Figure 8 The FPGA logic circuit principles of the PWM signal and the switch signal shown are basically the same. The present invention is represented by the same logic circuit schematic diagram. Its core idea is to use counters Cnt0 and Cnt1 to respectively realize the timing and time-sharing and phase-sharing functions. Cnt0 is used to count the 2us time, and Cnt1 is used to mark the number of 2us in a drive cycle T. The only difference is that the data and commands entered in the program are different.

[0033] Specifically, to achieve the required functionality, the design utilizes two counters, Cnt0 and Cnt1. Assuming a 20ps clock cycle, register Cnt0 counts 2us, or 2,000,000ps. The clock needs to count 100,000 cycles before restarting from 0. Register Cnt1, on the other hand, marks the number of 2us in a drive cycle, T. Since every three 2us constitutes a drive cycle, T, Cnt1 restarts from 0 after counting three 2us, or one drive cycle. Therefore, Cnt1 cycles through 0, 1, 2, 0, 1, 2, and so on, representing the activation intervals of three different phase shifters in the same column within a drive cycle.

[0034] Specifically, for a single drive cycle, the PWM wave period is designed to be T = 6s. For the PWM signal generation module, the high-level duty cycle for the first 2s is 70%, with a duration of 1.4us = 1400,000ps. The clock needs to transition from high to low after counting 1400,000 / 20 = 70,000 cycles. Similarly, the high-level duty cycle for the second 2s is 30%, with a duration of 0.6us = 600,000ps. The clock needs to transition from high to low after counting 600,000 / 20 = 30,000 cycles. For the third 2s, the high-level duration is 1us = 1,000,000ps, with a duty cycle of 50%. The clock needs to transition from high to low after counting 1,000,000 / 20 = 50,000 cycles. Because the signal is time-division multiplexed across three phase shifters, each phase shifter is accessible only for one-third of the time, resulting in an effective operating duty cycle of 1 / 3 = 33.3%.

[0035] Therefore, if Cnt1 = 0 and Cnt0 counts to 70,000-1 cycles, the output signal out goes low until Cnt0 restarts its next count. If Cnt1 = 1 and Cnt0 counts to 30,000-1 cycles, the output signal out goes low until Cnt0 restarts its next count. If Cnt1 = 2 and Cnt0 counts to 50,000-1 cycles, the output signal out goes low until Cnt0 restarts its next count. At all other times, the output signal out goes high once counter Cnt0 starts counting again from 0.

[0036] For FPGA switch control circuit 2: the switch signal controls the switch through high-low level conversion so that each enable line is connected to the ground within 1 / N cycles, and 1 / 3 is taken as an example in the example. If a certain enable line is connected to the ground within the first 2s of the cycle to start the phase shifter of that row, then the switch signal should be high in the first 2s, thereby controlling the switch to close and enable the line to be grounded. It is low in the second and third 2s, so that each phase shifter is powered on for a maximum of one-third of the cycle, and remains idle for the rest of the time. Therefore, if Cnt1=0, the output signal out becomes a high level; if Cnt1=1 or Cnt1=2, the output signal out becomes a low level, and the final result is as follows Figure 7 The switching signal of line 1 is enabled as shown, and the overall cycle is consistent with the cycle of the PWM signal.

[0037] The overall schematic diagram of the logic circuit for generating PWM signals and switching signals by FPGA designed according to the above design ideas is as follows Figure 5 As shown, the internal logic circuit diagram of U2 and U5 in the FPGA circuit is as follows Figure 6 and Figure 7As shown in the figure, U1, U4, B1~B6 are AND gates in the logic circuit; U3A, U3B, A1-A6 are identity comparators in the logic circuit, which are used to compare whether two numbers or logical expressions are equal. When the two inputs are equal, the identity comparator outputs the logical value "true"; otherwise, it outputs the logical value "false"; U2A and U5A are adders in the logic circuit, which are used to add two or more binary numbers to produce an output result; U2D, U5D and D1 are NOT gates in the logic circuit; U2B, U2C, U5B, U5C, C1~C4 are multiplexers in the logic circuit, the bottom pin is the selection signal, the two pins on the left are inputs, and the right pin is output. The selection signal (0 or 1) is used to control the output of a certain input signal; U2E, U5E, E1 are D flip-flops with reset terminals. When the circuit is powered on, the logic of the circuit is in an uncertain state. The arrival of the reset pulse initializes the circuit to the Q=0 state. Subsequently, under the control of the clock, the data at output terminal D is set to output terminal Q on each rising clock edge. I1-I16 are input signals calculated based on the above design principles, the required PWM signal, the switching signal period, and the PWM wave duty cycle. For example, in the example, I1 is the 32-bit binary number 1, which is input to the adder to complete the calculation of Cnt0 <= Cnt0 + 1, thereby implementing the self-increment of counter Cnt0 by 1.

[0038] The reason for choosing to generate Figure 8 The PWM wave shown is used to control the phase shifter for the following reasons: Since the effective value of the square wave voltage is the voltage value of the constant voltage source when the work done by the square wave is the same, it is expressed as The high level duration in one cycle T is t1, so the effective voltage of the PWM wave is a is the duty cycle. Therefore, the power of the PWM wave is: When the voltage is fixed, the PWM output power is proportional to the duty cycle a of the PWM wave. For a PWM signal with a fixed amplitude, a linear increase in the PWM duty cycle results in an equally linear phase shift induced by the heater. Compared to a DC drive signal, the phase shifter exhibits a much more linear response to a fixed-amplitude PWM signal. Therefore, using a digital PWM signal to drive a thermo-optical phase shifter is more effective and enables linear control of the device.

[0039] To achieve high scalability and minimize chip area, drivers are shared between different channels. For example, using three-way time-division multiplexing, each phase shifter is powered for at most one-third of the cycle, remaining idle for the remainder. The number of thermo-optical phase shifters that can be time-multiplexed in the same driver channel is proportional to the phase shifter's time constant, which is typically in the microsecond range. This allows for the multiplexing of a larger number of control lines, N.

[0040] In summary, the present invention uses a PWM control signal, stabilized by an LDO, to control the low-level on / off switching of the enable circuit. Simultaneously, it outputs a PWM signal with an adjustable duty cycle, which is then fed into the driver circuit to address a specific phase shifter within a row or column, thereby achieving the desired time-division multiplexing function for phase shifter drive. This design reduces the chip's optical path length, optimizes the heater's regulation and switching mechanisms, and significantly reduces the number of required drivers, thereby reducing circuit complexity and overall power consumption.

[0041] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A PWM-controlled optical phased array row-column folded phase shifter drive system, characterized in that: It includes a controller (1), an FPGA switch control circuit (2), a first switch array (3), an FPGA generated PWM circuit (4), an LDO power supply circuit array (5), a row-column folded phase shifter array (6), and a second switch array (12); The row-column folded phase shifter array (6) comprises thermo-optical phase shifters arranged in an array of M columns and N rows, wherein the positive electrodes of the thermo-optical phase shifters in the same column are connected together as a driving circuit, and the negative electrodes of the thermo-optical phase shifters in the same row are connected together as an enabling circuit; Each column of thermo-optic phase shifters is regarded as a group, and a group of thermo-optic phase shifters controls one waveguide. Each enabling circuit is grounded through each switch in a first switch array (3), and the first switch array (3) is controlled by the FPGA switch control circuit (2); each driving circuit is connected to the LDO power supply circuit array (5) through each switch in a second switch array (12), and the second switch array (12) is controlled by a PWM driving signal output by a PWM circuit (4) generated by the FPGA; The controller (1) is used to control the FPGA switch control circuit (2) and the FPGA generation PWM circuit (4); when in operation, only one enable circuit is enabled at a low level at the same time, and each drive circuit is loaded with PWM waves of different duty cycles through a second switch array (12) to achieve phase adjustment; each enable circuit is sequentially selected according to a cycle, and the cycle is less than the thermal conduction time constant of the thermo-optical phase shifter.

2. The optical phased array row-column folded phase shifter driving system based on PWM control according to claim 1, characterized in that: It also includes a monitor array (7) for sensing the output direction and phase of the light beam in each waveguide, and inputting the sensed direction and phase into the controller (1) as a feedback signal for feedback control.

3. The optical phased array row-column folded phase shifter driving system based on PWM control according to claim 1 or 2, characterized in that: In the row-column folded phase shifter array (6), each driving circuit corresponds to a PWM driving signal, and each thermo-optical phase shifter and the enabling circuit in each driving circuit are time-division multiplexed controlled in the same cycle.

4. The optical phased array row-column folded phase shifter driving system based on PWM control according to claim 1 or 2, characterized in that: Each unit in the LDO power supply circuit array (5) includes a voltage dividing sampling circuit (8), a reference voltage (10), an error amplifying circuit (9) and a transistor switching circuit (11); the external voltage V in The output end of the transistor switch circuit (11) is connected, and the voltage sampling circuit (8) is connected to the voltage V through the resistor R1 and the resistor R2 in series. in The reference voltage (10) is generated by the bandgap voltage reference; the error amplifier circuit (9) converts the voltage V collected by the voltage divider sampling circuit (8) into FB The voltage is input to the non-inverting input terminal of the comparator in the error amplifier circuit (9) and compared with the reference voltage (10) at the inverting input terminal. The comparison result is amplified and output to the control electrode of the transistor switch circuit (11) to control the conduction of the transistor switch circuit (11).

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