A SerDes DC balance encoding and decoding device and method

Abstract

The present invention relates to the field of communication technologies, and particularly to a SerDes DC balance encoding and decoding device and method. It includes: a DC balance encoding module and a DC balance decoding module. The DC balance encoding module includes: a parallel data receiver for receiving N-bit parallel data; a register 1 for storing the received N-bit parallel data; a register 2 for storing the N-bit parallel data received in the previous cycle or initial data; an encoder 1 for performing positive polarity encoding on the data of register 1 and register 2; an encoder 2 for performing negative polarity encoding on the data of register 1 and register 2; a "01" counter 1 for performing "01" counting on the data of encoder 1 to determine whether "0" or "1" is in the majority among the encoding bits. The present invention can achieve miniaturized design of the system and improve the system integration level. Moreover, while not reducing the effective data transmission rate, it enables the transmitted data to have DC balance characteristics.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and particularly to a SerDes DC balance encoding and decoding device and method. Background Art

[0002] With the continuous development of information devices, people's requirements for the rate and quality of data transmission are getting higher and higher. The ways of data transmission mainly include serial and parallel. With the increase in data transmission rate, problems such as channel interference, clock synchronization, channel skew, and the number of connecting lines have hindered the development of parallel data transmission. In the field of high-speed data transmission, serial transmission has great advantages. Serial transmission will greatly reduce the number of transmission cables and facilitate wiring connection. At the same time, because the number of connecting lines is reduced, problems such as channel skew and channel interference are also solved. Further, through the development of the technology of embedding clock information into serial data, the problem of clock synchronization of transceiver chips is also solved. Therefore, in the field of high-speed data transmission, such as SATA, PCI-E, SONET, etc., serial data transmission is adopted. We collectively refer to such circuits for serial-to-parallel conversion and parallel-to-serial conversion as SerDes circuits.

[0003] SerDes circuits solve the problem of data transmission at the physical layer. When transmitting data through a serial port, interface protocols such as CML, VML, and LVDS are often used. Common serial port connection methods are divided into two types: DC coupling and AC coupling. In DC coupling, the transceiver is directly connected through a cable. In AC coupling, the DC information between the transceivers can be isolated through capacitors, which further improves the quality and reliability of data transmission. However, the AC coupling connection method has high requirements for the data transmitted through the cable, that is, the data is required to have DC balance characteristics, otherwise the transmission error rate will increase. In order to further improve the quality of data transmission and signal integrity, we perform encoding and decoding on the data at the encoding layer to further improve the data transmission performance.

[0004] Common DC balance encoding methods include Manchester encoding, 8B / 10B encoding, etc. However, these encodings need to introduce redundant bits for expansion to achieve the purpose of DC balance. For example, at a constant transmission rate, the effective data transmitted by Manchester encoding is only 50%, and the effective data transmitted by 8B / 10B encoding is only 80%. Summary of the Invention

[0005] The purpose of the present invention is to provide a SerDes DC balance encoding and decoding device, which realizes the miniaturized design of the system and improves the system integration degree. Another purpose of the present invention is to provide a SerDes DC balance encoding and decoding method, which is used on the SerDes DC balance encoding and decoding device to make the transmitted data have DC balance characteristics without reducing the effective data transmission rate.

[0006] To solve the above technical problems, the present invention provides a SerDes DC balance encoding and decoding device, including:

[0007] A DC balance encoding module, including: a parallel data receiver for receiving N-bit parallel data; a register 1 for storing the received N-bit parallel data; a register 2 for storing the N-bit parallel data received in the previous cycle or initial data; an encoder 1 for performing positive polarity encoding on the data in register 1 and register 2; an encoder 2 for performing negative polarity encoding on the data in register 1 and register 2; a "01" counter 1 for performing "01" counting on the data of encoder 1 to determine whether "0" or "1" is in the majority in the encoding bits; a "01" counter 2 for performing "01" counting on the data of encoder 2 to determine whether "0" or "1" is in the majority in the encoding bits; a DC balance controller 1 for controlling the operation of "01" counter 1 and "01" counter 2, calculating whether the difference in the number of "01" in the transmitted data exceeds a threshold T, and selecting the data of encoder 1 or encoder 2 for transmission after judgment; a serial-to-parallel converter for converting N-bit encoded data into 1-bit serial data for output; a phase-locked loop 1 for multiplying the local parallel data clock by N for use by the serial-to-parallel converter; and a DC balance decoding module.

[0008] Preferably, the DC balance decoding module includes: a serial-to-parallel converter for converting 1-bit serial data into N-bit encoded data for input; a register 3 for storing the received N-bit encoded data; a register 4 for storing the N-bit encoded data received in the previous cycle or initial data; a decoder 1 for performing positive polarity decoding on the data in register 1 and register 2; a decoder 2 for performing negative polarity decoding on the data in register 1 and register 2; a "01" counter 3 for performing "01" counting on the data of decoder 1 to determine whether "0" or "1" is in the majority in the encoding bits; a "01" counter 4 for performing "01" counting on the data of decoder 2 to determine whether "0" or "1" is in the majority in the encoding bits; a DC balance controller 2 for controlling the operation of "01" counter 3 and "01" counter 4, calculating whether the difference in the number of "01" in the received data exceeds a threshold T, and selecting the data of decoder 1 or decoder 2 for transmission after judgment; a parallel data transmitter for transmitting N-bit parallel data; and a phase-locked loop 2 for multiplying the local parallel data clock by N for use by the serial-to-parallel converter.

[0009] The present invention also provides the following technical solution: an encoding and decoding method for a SerDes DC balance encoding and decoding device, including a DC balance encoding method and a DC balance decoding method.

[0010] Preferably, the DC balance encoding method includes the following steps:

[0011] (1) Phase-locked loop 1 supplies a clock signal with a stable frequency of f, providing an N-times frequency multiplication clock for the parallel-to-serial converter;

[0012] (2) The parallel data receiver receives N-bit parallel data sent from the upper level and sends it to register 1; at the same time, it transfers the data of register 1 in the previous cycle to register 2; the parallel data reception operating frequency is the local clock frequency f;

[0013] (3) Encoder 1 performs positive polarity encoding on the data of register 1 and register 2, such as an exclusive OR operation, and calculates the dominant situation of the number of "01" in the encoding result through "01" counter 1; Encoder 2 performs negative polarity encoding on the data of register 1 and register 2, such as an inclusive OR operation, and calculates the dominant situation of the number of "01" in the encoding result through "01" counter 2;

[0014] (4) Determine whether the difference in the number of "01" in the data already sent by DC balance controller 1 exceeds the threshold T. If it does not exceed the threshold T, select the encoder data corresponding to the polarity selected in the previous cycle for transmission, and then refresh and calculate the difference in the number of "01" in the data already sent; if it exceeds the threshold T, then select the encoder data corresponding to the opposite polarity selected in the previous cycle for transmission, and then refresh and calculate the difference in the number of "01" in the data already sent;

[0015] (5) Convert the N-bit encoded data selected by DC balance controller 1 into a 1-bit signal through the parallel-to-serial converter for serial transmission. At this time, the serial data transmission rate is N times the parallel reception data rate;

[0016] (6) Repeat the encoding and transmission operations in (2) to (5).

[0017] Preferably, the DC balance decoding method includes the following steps:

[0018] (1) Phase-locked loop 2 supplies a clock signal with a stable frequency of f, providing an N-times frequency multiplication clock for the serial-to-parallel converter;

[0019] (2) Send the N-bit encoded data received by the serial-to-parallel converter to register 3, and calculate the dominant situation of the number of "01" in the data of register 3 through "01" counter 3; at the same time, transfer the data of register 3 in the previous cycle to register 4, and calculate the dominant situation of the number of "01" in the data of register 4 through "01" counter 4;

[0020] (3) Decoder 1 performs positive polarity decoding on the data of register 3 and register 4, such as an exclusive OR operation; Decoder 2 performs negative polarity encoding on the data of register 1 and register 2, such as an inclusive OR operation;

[0021] (4) Determine whether the difference in the number of received data "01" counted by the DC balance controller 2 at this time exceeds the threshold T. If it does not exceed the threshold T, select the decoder data corresponding to the polarity selected in the previous cycle for transmission, and then refresh and calculate the difference in the number of received data "01"; if it exceeds the threshold T, then select the encoder data corresponding to the opposite polarity selected in the previous cycle for transmission, and then refresh and calculate the difference in the number of transmitted data "01".

[0022] (5) Parallelly transmit the N-bit decoded data selected by the DC balance controller 2 through a parallel-to-serial converter. At this time, the transmission rate of the parallel data sent is the same as the local input clock frequency f.

[0023] (6) Repeat the decoding and transmission operations in (2) to (5).

[0024] Preferably, in the decoding method, for the serially transmitted data encoded by DC balance, under long-term statistics, the number of "0"s and "1"s transmitted is the same.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The present invention includes a SerDes DC balance encoding and decoding device and method, which specifically belongs to the field of communication technology; the SerDes DC balance encoding and decoding device of the present invention includes a parallel data receiver, register 1, register 2, encoder 1, encoder 2, "01" counter 1, "01" counter 2, DC balance controller 1, parallel-to-serial converter, phase-locked loop 1, serial-to-parallel converter, register 3, register 4, decoder 1, decoder 2, "01" counter 3, "01" counter 4, DC balance controller 2, parallel data transmitter, phase-locked loop 2. The SerDes DC balance encoding and decoding device of the present invention can implement SerDes DC balance encoding and decoding, realize the miniaturized design of the system, and improve the system integration degree. Moreover, while not reducing the effective data transmission rate, the transmitted data has the DC balance characteristic. Description of the Drawings

[0027] Figure 1 is a schematic structural diagram of the SerDes DC balance encoding and decoding device of the present invention.

[0028] Figure 2 is a flowchart of the SerDes DC balance encoding method of the present invention.

[0029] Figure 3 is a flowchart of the SerDes DC balance decoding method of the present invention. Detailed Embodiments

[0030] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0031] As Figure 1 shown, the present invention provides a SerDes DC balance encoding and decoding device, including a SerDes DC balance encoding module and a SerDes DC balance decoding module.

[0032] The SerDes DC balance encoding module includes a parallel data receiver for receiving N-bit parallel data; a register 1 for storing the received N-bit parallel data; a register 2 for storing the N-bit parallel data received in the previous cycle or initial data; an encoder 1 for performing positive polarity encoding on the data in register 1 and register 2; an encoder 2 for performing negative polarity encoding on the data in register 1 and register 2; a "01" counter 1 for performing "01" counting on the data of encoder 1 to determine whether "0" or "1" is in the majority in the encoded bits; a "01" counter 2 for performing "01" counting on the data of encoder 2 to determine whether "0" or "1" is in the majority in the encoded bits; a DC balance controller 1 for controlling the operation of the "01" counter 1 and the "01" counter 2, calculating whether the difference in the number of "01" in the transmitted data exceeds a threshold T, and selecting the data of encoder 1 or encoder 2 for transmission after judgment; a serial-to-parallel converter for converting N-bit encoded data into 1-bit serial data for output; a phase-locked loop 1 for multiplying the local parallel data clock by N for use by the serial-to-parallel converter.

[0033] The SerDes DC balance decoding module includes a serial-to-parallel converter for converting 1-bit serial data into N-bit encoded data for input; a register 3 for storing the received N-bit encoded data; a register 4 for storing the N-bit encoded data received in the previous cycle or initial data; a decoder 1 for performing positive polarity decoding on the data in register 1 and register 2; a decoder 2 for performing negative polarity decoding on the data in register 1 and register 2; a "01" counter 3 for performing "01" counting on the data of decoder 1 to determine whether "0" or "1" is in the majority in the encoded bits;; a "01" counter 4 for performing "01" counting on the data of decoder 2 to determine whether "0" or "1" is in the majority in the encoded bits;; a DC balance controller 2 for controlling the operation of the "01" counter 3 and the "01" counter 4, calculating whether the difference in the number of "01" in the received data exceeds a threshold T, and selecting the data of decoder 1 or decoder 2 for transmission after judgment; a parallel data transmitter for transmitting N-bit parallel data; a phase-locked loop 2 for multiplying the local parallel data clock by N for use by the serial-to-parallel converter.

[0034] A SerDes DC balance encoding and decoding method according to an embodiment of the present invention is applied to a SerDes DC balance encoding and decoding device.

[0035] As Figure 2 shown in the SerDes DC balance encoding method, it includes the following steps:

[0036] Step 201: The phase-locked loop 1 supplies a stable clock signal with a frequency of f to provide an N-times frequency multiplication clock for the parallel-to-serial converter;

[0037] Step 202: The parallel data receiver receives N-bit parallel data sent by the upper level and sends it to register 1; at the same time, the data of register 1 in the previous cycle is passed to register 2; the parallel data reception operating frequency is the local clock frequency f.

[0038] Step 203: Encoder 1 performs positive polarity encoding on the data of register 1 and register 2, such as an exclusive OR operation;

[0039] Step 204: Encoder 2 performs negative polarity encoding on the data of register 1 and register 2, such as an inclusive OR operation;

[0040] Step 205: Calculate the dominance situation of the number of "01" in the encoding result through the "01" counter 1;

[0041] Step 206: Calculate the dominance situation of the number of "01" in the encoding result through the "01" counter 2;

[0042] Step 207: Determine whether the difference in the number of "01" in the data already sent counted by the DC balance controller 1 exceeds the threshold T;

[0043] Step 208: If it does not exceed the threshold T, enter step 208, and select the encoder data corresponding to the polarity selected in the previous cycle for transmission;

[0044] Step 209: If it exceeds the threshold T, enter step 209, then select the encoder data corresponding to the opposite polarity selected in the previous cycle for transmission;

[0045] Step 210: Refresh and calculate the difference in the number of "01" in the data already sent;

[0046] Step 211: Convert the N-bit encoded data selected by the DC balance controller 1 into a 1-bit signal through the parallel-to-serial converter for serial transmission. At this time, the serial data transmission rate is N times the parallel reception data rate;

[0047] As Figure 3 shown in the SerDes DC balance decoding method, it includes the following steps:

[0048] Step 301: The phase-locked loop 2 supplies a clock signal with a stable frequency of f to provide an N-fold frequency clock for the serial-to-parallel converter.

[0049] Step 302: Send the N-bit encoded data received by the serial-to-parallel converter to register 3; at the same time, transfer the data of register 3 in the previous cycle to register 4.

[0050] Step 303: Calculate the dominance of the number of "01" in the data of register 3 through the "01" counter 3.

[0051] Step 304: Calculate the dominance of the number of "01" in the data of register 4 through the "01" counter 4.

[0052] Step 305: The decoder 1 performs positive polarity decoding on the data of register 3 and register 4, such as an exclusive OR operation.

[0053] Step 306: The decoder 2 performs negative polarity encoding on the data of register 1 and register 2, such as an inclusive OR operation.

[0054] Step 307: Determine whether the difference in the number of "01" in the data received by the DC balance controller 2 has exceeded the threshold T.

[0055] Step 308: If the threshold T is not exceeded, go to step 308 and select the decoder data corresponding to the polarity selected in the previous cycle for transmission.

[0056] Step 309: If the threshold T is exceeded, go to step 309 and select the encoder data corresponding to the opposite polarity selected in the previous cycle for transmission.

[0057] Step 310: Refresh and calculate the difference in the number of "01" in the data already sent.

[0058] Step 311: Parallelly transmit the N-bit decoded data selected by the DC balance controller 2 through the parallel-to-serial converter. At this time, the transmission rate of the parallel data sent is the same as the local input clock frequency f.

[0059] Furthermore, for the serial data encoded by DC balance transmitted by the DC balance encoding and decoding method, in a long-term statistics, the number of "0" and "1" transmitted is the same.

[0060] The DC balance encoding and decoding method does not introduce a coding method with redundant bits and will not reduce the effective data transmission rate.

[0061] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the scope of protection of the claims.

Claims

1. A SerDes DC balance encoding and decoding device, characterized in that Comprising: DC balance encoding module, comprising: Parallel data receiver, configured to receive N-bit parallel data; Register 1, configured to store the received N-bit parallel data; Register 2, configured to store the N-bit parallel data received in the previous cycle or initial data; Encoder 1, configured to perform positive polarity encoding on the data of Register 1 and Register 2; Encoder 2, configured to perform negative polarity encoding on the data of Register 1 and Register 2; "01" counter 1, configured to perform "01" counting on the data of Encoder 1 to determine whether "0" or "1" is in the majority in the encoded bits; "01" counter 2, configured to perform "01" counting on the data of Encoder 2 to determine whether "0" or "1" is in the majority in the encoded bits; DC balance controller 1, configured to control the operation of "01" counter 1 and "01" counter 2, calculate whether the difference in the number of "01" of the transmitted data exceeds the threshold T, and select the data of Encoder 1 or Encoder 2 for transmission after judgment; Parallel-to-serial converter, configured to convert the N-bit encoded data into 1-bit serial data for output; Phase-locked loop 1, configured to multiply the local parallel data clock by N for the operation of the parallel-to-serial converter; DC balance decoding module; The DC balance decoding module, comprising: Serial-to-parallel converter, configured to convert 1-bit serial data into N-bit encoded data for input; Register 3, configured to store the received N-bit encoded data; Register 4, configured to store the N-bit encoded data received in the previous cycle or initial data; Decoder 1, configured to perform positive polarity decoding on the data of Register 1 and Register 2; Decoder 2, configured to perform negative polarity decoding on the data of Register 1 and Register 2; "01" counter 3, configured to perform "01" counting on the data of Decoder 1 to determine whether "0" or "1" is in the majority in the encoded bits; "01" counter 4, configured to perform "01" counting on the data of Decoder 2 to determine whether "0" or "1" is in the majority in the encoded bits; DC balance controller 2, configured to control the operation of "01" counter 3 and "01" counter 4, calculate whether the difference in the number of "01" of the received data exceeds the threshold T, and select the data of Decoder 1 or Decoder 2 for transmission after judgment; Parallel data transmitter, configured to transmit N-bit parallel data; Phase-locked loop 2, configured to multiply the local parallel data clock by N for the operation of the serial-to-parallel converter.

2. A coding and decoding method for a SerDes DC balance coding and decoding device, which uses a SerDes DC balance coding and decoding device as described in claim 1, characterized in that, Including a DC balance encoding method and a DC balance decoding method; Wherein, the DC balance encoding method includes the following steps: S11: The phase-locked loop 1 supplies a clock signal with a stable frequency of f to provide an N-fold frequency clock for the parallel-to-serial converter; S12: The parallel data receiver receives the N-bit parallel data sent by the upper level and sends it to Register 1; at the same time, the data of Register 1 in the previous cycle is transferred to Register 2; the operating frequency of the parallel data reception is the local clock frequency f; S13: The encoder 1 performs an exclusive OR operation on the data in register 1 and register 2 for positive polarity encoding, and calculates the dominant situation of the number of "01" in the encoding result through the "01" counter 1; the encoder 2 performs an exclusive NOR operation on the data in register 1 and register 2 for negative polarity encoding, and calculates the dominant situation of the number of "01" in the encoding result through the "01" counter 2. S14: Determine whether the difference in the number of "01" in the data already sent counted by the DC balance controller 1 exceeds the threshold T. If it does not exceed the threshold T, select the encoder data corresponding to the polarity selected in the previous cycle for transmission, and then refresh and calculate the difference in the number of "01" in the data already sent; if it exceeds the threshold T, then select the encoder data corresponding to the opposite polarity selected in the previous cycle for transmission, and then refresh and calculate the difference in the number of "01" in the data already sent. S15: Convert the N-bit encoded data selected by the DC balance controller 1 into a 1-bit signal through a parallel-to-serial converter for serial transmission. At this time, the serial data transmission rate is N times the parallel received data rate. S16: Repeat the encoding and transmission operations of S12~S15. The DC balance decoding method includes the following steps: S21: The phase-locked loop 2 supplies a stable clock signal with a frequency of f, and provides an N-fold frequency clock for the serial-to-parallel converter. S22: Send the N-bit encoded data received by the serial-to-parallel converter to register 3, and calculate the dominant situation of the number of "01" in the data of register 3 through the "01" counter 3; at the same time, transfer the data of register 3 in the previous cycle to register 4, and calculate the dominant situation of the number of "01" in the data of register 4 through the "01" counter 4. S23: The decoder 1 performs an exclusive OR operation on the data in register 3 and register 4 for positive polarity decoding; the decoder 2 performs an exclusive NOR operation on the data in register 1 and register 2 for negative polarity encoding. S24: Determine whether the difference in the number of "01" in the data already received counted by the DC balance controller 2 exceeds the threshold T. If it does not exceed the threshold T, select the decoder data corresponding to the polarity selected in the previous cycle for transmission, and then refresh and calculate the difference in the number of "01" in the data already received; if it exceeds the threshold T, then select the encoder data corresponding to the opposite polarity selected in the previous cycle for transmission, and then refresh and calculate the difference in the number of "01" in the data already sent. S25: Parallelly transmit the N-bit decoded data selected by the DC balance controller 2 through the serial-to-parallel converter. At this time, the transmission rate of the parallel data sent is the same as the local input clock frequency f. S26: Repeat the decoding and transmission operations of S22~S25.

3. The encoding and decoding method of a SerDes DC balance encoding and decoding device according to claim 2, wherein, In the decoding method, for the serially transmitted data encoded by DC balance, in the long-term statistics, the number of "0" and "1" transmitted is the same.

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