A table lookup method, device and computer equipment based on FPGA

Abstract

The application discloses a table lookup method and device based on FPGA, wherein the method comprises the following steps: acquiring the number of network ports of a first terminal node based on FPGA; generating a table lookup model of the first terminal node based on a plurality of distributed RAMs in the FPGA and parallel setting, each RAM being configured with preset table lookup information; receiving current configuration information sent by a second terminal node for establishing a communication relationship; and obtaining a table lookup result by simultaneously matching the preset table lookup information configured by each RAM with the current configuration information based on the table lookup model. The application does not need to sequentially match the preset table lookup information configured by each RAM, can improve the table lookup matching speed, can guarantee the matching accuracy of the table lookup, and can quickly achieve the table lookup purpose without additional hardware resources.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FPGA lookup table technology, in particular to a lookup table method and device based on FPGA and computer equipment. BACKGROUND

[0002] In the design of various field programmable gate arrays (FPGA), considering the actual application scene, some large-capacity memories are generally externally hung to store a large number of table items, such as double data rate (DDR) and quad data rate (QDR). Although these off-chip memories have large capacity and low cost, they have slow access speed. FPGA needs to frequently read and write table items in off-chip memory during operation, at which time the read and write speed of off-chip memory will become the working bottleneck of FPGA. At present, in order to increase the lookup table performance of off-chip memory, multiple off-chip memories are generally added for parallel lookup table, which significantly increases the product design cost.

[0003] In related technologies, the high integrity ARINC664 protocol is a kind of avionics bus with extremely high safety in the aviation field, and has extremely high requirements for network real-time and determinacy, and is usually implemented by using large-scale FPGA chips. The network delay requirement is in the order of microseconds, each terminal node has thousands of network ports, each port has its specific configuration information, and the data that does not meet the configuration information needs to be filtered in the data receiving process to avoid the influence of abnormal data on network performance.

[0004] However, after the initialization configuration of each terminal node is completed, thousands of network ports receive configuration information, and each network port compares the local network configuration information with the received current network configuration information one by one, uploads the data to the upper computer when the matching is successful, and discards the data if the matching fails. This way compares the data in sequence, discards the data if the current configuration information is incorrect, and processes the next packet of data after finding the final confirmation result through thousands of times of searching. This way not only greatly limits the data receiving efficiency, but also leads to low lookup table efficiency. SUMMARY

[0005] Therefore, the technical problem to be solved by the present application is to overcome the problems of increasing product design cost by increasing multiple off-chip memories for parallel lookup table and low lookup table efficiency caused by sequentially matching lookup table information in the prior art, so as to provide a lookup table method and device based on FPGA and computer equipment.

[0006] According to a first aspect, an embodiment of the present application provides a lookup table method based on FPGA, comprising the following steps:

[0007] obtaining a network port number of a first terminal node based on FPGA;

[0008] generating a table lookup model of the first terminal node based on a plurality of distributed RAMs in the FPGA, each of the RAMs being configured with preset table lookup information, based on the network port number;

[0009] receiving current configuration information sent by a second terminal node for establishing a communication relationship;

[0010] obtaining a table lookup result by simultaneously matching the preset table lookup information configured in each of the RAMs with the current configuration information based on the table lookup model.

[0011] Optionally, the generating the table lookup model of the first terminal node based on a plurality of distributed RAMs in the FPGA, each of the RAMs being configured with preset table lookup information, based on the network port number, comprises:

[0012] setting a first preset value, the first preset value being a number of ports to be connected for each of the RAMs;

[0013] determining a first target number of the plurality of distributed and parallel RAMs based on the network port number and the first preset value;

[0014] configuring and storing the preset table lookup information in each of the RAMs;

[0015] concatenating the first target number of the RAMs through a bus to obtain the table lookup model.

[0016] Optionally, the generating the table lookup model of the first terminal node based on a plurality of distributed RAMs in the FPGA, each of the RAMs being configured with preset table lookup information, based on the network port number, comprises:

[0017] setting a second preset value, the second preset value being a number of ports to be connected for each of the table lookup units;

[0018] determining a second target number of the plurality of distributed and parallel table lookup units based on the network port number and the second preset value;

[0019] determining a third target number of the plurality of distributed and parallel RAMs in each of the table lookup units;

[0020] configuring and storing the preset table lookup information in each of the RAMs;

[0021] concatenating the third target number of the RAMs and the second target number of the table lookup units through a bus to obtain the table lookup model.

[0022] Optionally, the matching the preset lookup table information with the current configuration information simultaneously based on the lookup table model to obtain a lookup table result comprises:

[0023] analyzing the preset lookup table information to obtain first website identification information;

[0024] analyzing the current configuration information to obtain second website identification information;

[0025] matching the first website identification information with the second website identification information;

[0026] if the first website identification information and the second website identification information match successfully, uploading the matched lookup table result to an external host computer;

[0027] if the first website identification information and the second website identification information fail to match, discarding the current configuration information.

[0028] Optionally, the first website identification information and the second website identification information comprise virtual link parameters, website parameters and identification parameters.

[0029] According to a second aspect, an embodiment of the present application provides a lookup table device based on FPGA, comprising the following modules:

[0030] a port quantity obtaining module, configured to obtain a network port quantity of a first terminal node based on FPGA;

[0031] a lookup table model generating module, configured to generate, based on the network port quantity, a lookup table model of the first terminal node based on a plurality of distributed RAMs arranged in parallel inside the FPGA, each RAM being configured with preset lookup table information;

[0032] a configuration information receiving module, configured to receive current configuration information sent by a second terminal node for establishing a communication relationship;

[0033] a lookup table result matching module, configured to match, based on the lookup table model, the preset lookup table information of each RAM with the current configuration information simultaneously to obtain a lookup table result.

[0034] Optionally, the lookup table model generating module comprises:

[0035] a first preset value determining sub-module, configured to set a first preset value, the first preset value being a quantity of to-be-connected ports of each RAM;

[0036] a first target quantity determining sub-module, configured to determine, based on the network port quantity and the first preset value, a first target quantity of the plurality of distributed RAMs arranged in parallel;

[0037] The first lookup table information configuration submodule is configured to configure and store the preset lookup table information in each RAM.

[0038] The first lookup table model generation submodule is configured to cascade the first target number of the RAMs through a bus to obtain the lookup table model.

[0039] Optionally, the lookup table model generation module further comprises:

[0040] The second preset value setting submodule is configured to set a second preset value, the second preset value being a number of to-be-connected ports of each lookup table unit.

[0041] The second target number determination submodule is configured to determine a second target number of the distributed parallel lookup table units based on the number of network ports and the second preset value.

[0042] The third target number determination submodule is configured to determine a third target number of the distributed parallel RAMs in each lookup table unit.

[0043] The second lookup table information configuration submodule is configured to configure and store the preset lookup table information in each RAM.

[0044] The second lookup table model generation submodule is configured to cascade the third target number of the RAMs and the second target number of the lookup table units through a bus to obtain the lookup table model.

[0045] According to a third aspect, an embodiment of the present application provides a computer readable storage medium, the computer readable storage medium storing computer instructions, the computer instructions being used to make the computer execute the FPGA-based lookup table method in the first aspect or any of the implementation manners of the first aspect.

[0046] According to a fourth aspect, an embodiment of the present application provides a computer device, comprising a memory and a processor, the memory and the processor being in communication connection with each other, the memory storing computer instructions, and the processor executing the computer instructions to execute the FPGA-based lookup table method in the first aspect or any of the implementation manners of the first aspect.

[0047] The technical scheme of the present application has the following advantages:

[0048] The application discloses a table lookup method and device based on FPGA, wherein the method comprises the following steps: acquiring the number of network ports of a first terminal node based on FPGA; generating a table lookup model of the first terminal node based on a plurality of distributed RAMs in the FPGA and parallel setting, each RAM being configured with preset table lookup information; receiving current configuration information sent by a second terminal node for establishing a communication relationship; and obtaining a table lookup result by simultaneously matching the preset table lookup information configured in each RAM with the current configuration information based on the table lookup model. The application does not need to sequentially match the preset table lookup information configured in each RAM, which can not only improve the table lookup matching speed, but also ensure the matching accuracy of the table lookup, and additionally, the table lookup purpose can be quickly achieved without additional hardware resources. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the specific embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0050] Figure 1 A flow chart of a specific example of the table lookup method based on FPGA in the embodiments of the present application;

[0051] Figure 2 A flow chart of another specific example of the table lookup method based on FPGA in the embodiments of the present application;

[0052] Figure 3 A schematic diagram of the table lookup model based on a plurality of distributed RAMs in the FPGA and parallel setting in the embodiments of the present application;

[0053] Figure 4 A flow chart of another specific example of the table lookup method based on FPGA in the embodiments of the present application;

[0054] Figure 5 A flow chart of another specific example of the table lookup method based on FPGA in the embodiments of the present application;

[0055] Figure 6 A structural block diagram of the table lookup device based on FPGA in the embodiments of the present application;

[0056] Figure 7 A hardware structure schematic diagram of the computer device in the embodiments of the present application. DETAILED DESCRIPTION

[0057] The technical solutions of the present application will be described clearly and completely below in conjunction with the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0058] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0059] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements; it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0060] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0061] In the field of FPGA lookup table technology, it is usually implemented by sequential lookup table method or increasing multiple off-chip memories for parallel lookup table. The former is easy to cause low lookup table efficiency, and the latter is easy to increase the product design cost. For example: the prior art uses sequential lookup table method. When a network message arrives and needs to be looked up, based on the source IP, destination IP, source port, destination port number and protocol number, the table items configured in the RAM are read out from the RAM starting from the 0 address, and the lookup table result is obtained by further comparison and matching. This method needs a large amount of time to read the configured table items, so it leads to low lookup table efficiency.

[0062] Therefore, the embodiment of the present application provides a lookup table method based on FPGA, as shown in Figure 1 The method comprises the following steps:

[0063] Step S11: Obtain the number of network ports of a first terminal node based on FPGA.

[0064] Specifically, the first terminal node is a terminal node internally configured with an FPGA, for example, the high integrity ARINC 664 protocol is a highly safe avionics bus in the aviation field, which has extremely high requirements for network real-time and determinacy, and is usually implemented by using an FPGA circuit or an FPGA chip. The ARINC 664 protocol has a network delay requirement in the microsecond level, each terminal node has thousands of network ports, each network port has specific configuration information, and in the data receiving process, data that does not meet the configuration information needs to be filtered to avoid abnormal data affecting network performance.

[0065] For example, if the number of network ports of the first terminal node based on the FPGA is 4096 network ports, the number of network ports of the first terminal node based on the FPGA is 4096.

[0066] Step S12: Based on the number of network ports, a lookup table model of the first terminal node based on a plurality of distributed RAMs in the FPGA is generated, and each RAM is configured with preset lookup table information.

[0067] For example, a lookup table model of a 16X1 small RAM block (16 addresses, each address stores one data bit) is generated based on the number of network ports of the first terminal node, and the matching target can be obtained through at most 16 polling, the function interface is simple, and the lookup table efficiency is greatly improved. Based on the number of network ports of the first terminal node, the polling times can be adjusted by adjusting the size of the RAM block, such as increasing the capacity of a single RAM block to 32x1 / 64x1 / 128x1, etc., which can increase the lookup table times and reduce the number of RAM cascades to achieve the purpose of simplifying the lookup table model, such as reducing the capacity of a single RAM block to 8X1 / 4X1, etc., which can reduce the lookup table times but need to increase the number of RAM cascades.

[0068] In a specific embodiment, the above step S12 is shown as follows: Figure 2 Based on the number of network ports, a lookup table model of the first terminal node based on a plurality of distributed RAMs in the FPGA is generated, and each RAM is configured with preset lookup table information, including:

[0069] Step S21: A first preset value is set, and the first preset value is a port to be connected of each RAM.

[0070] Step S22: Based on the number of network ports and the first preset value, a first target number of the plurality of distributed and parallel RAMs is determined.

[0071] Step S23: The preset lookup table information is configured and stored in each RAM.

[0072] Step S24: Cascade the first target number of RAMs through a bus to obtain a lookup table model.

[0073] For example, if the number of network ports is 256 and the first preset value is 16, then the first target number of distributed parallel RAMs is 256 / 16 = 16. After configuring and storing preset lookup information in each RAM, the 16 RAMs are cascaded through a bus to obtain a lookup model. Specifically, the preset lookup information includes preset virtual link parameters (VL), preset URL parameters (IP), and preset identifier parameters (UDP).

[0074] Furthermore, such as Figure 3 As shown, taking a 16x1 RAM lookup table model as an example, each 4-bit address in a single small 16x1 RAM block corresponds to a unique output. The 56 address lines of this 16x1 small RAM block are connected together, while the data lines are independent. Each 4-bit address in each small lookup table unit corresponds to a unique 56-bit data. Due to the address width limitation, a single lookup table unit can hold 16 56-bit data entries. Each lookup requires 16 queries to traverse the entire lookup table. Therefore, obtaining a unique 56-bit data address from a small lookup table unit requires a maximum of 16 lookup operations. Using a 100MHz clock as an example, the lookup delay is 160ns, significantly improving lookup efficiency.

[0075] The FPGA-based lookup method in this embodiment generates a lookup model for the first terminal node based on the number of network ports, using multiple distributed RAMs configured in parallel within the FPGA. This eliminates the need to add more off-chip memory to the FPGA, thereby further reducing product costs. Furthermore, by cascading multiple distributed RAMs in parallel via a bus, the lookup efficiency can be further improved.

[0076] In another, more specific implementation, step S13 above, as follows: Figure 4 As shown, based on the number of network ports, a lookup table model for the first terminal node is generated, which is based on multiple distributed RAMs configured in parallel within the FPGA. Each RAM is configured with preset lookup table information, including:

[0077] Step S41: Set a second preset value, which is the number of ports to be connected for each lookup unit;

[0078] Step S42: Based on the number of network ports and the second preset value, determine the second target number of distributed parallel table lookup units;

[0079] Step S43: Determine the number of third targets for distributing and parallelizing multiple RAMs in each lookup unit;

[0080] Step S44: configuring and storing preset lookup table information in each RAM;

[0081] Step S45: cascading the third target number of RAMs and the second target number of lookup table units through a bus to obtain a lookup table model.

[0082] Exemplarily, the number of network ports is 4096, and the second preset value is 16. Then, the second target number of lookup table units distributed in parallel is 4096 / 16 = 256, and the 256 lookup table units are cascaded through a bus. On this basis, the third target number of RAMs distributed in parallel in each lookup table unit is 16. After configuring and storing preset lookup table information in each RAM, 16 RAMs distributed in parallel and 256 lookup table units distributed in parallel are cascaded through a bus to obtain a lookup table model. The second preset value is the number of network ports connected to each lookup table unit. Specifically, the preset lookup table information includes virtual link parameters (VL), Internet Protocol (IP) parameters, and identification parameters (UDP).

[0083] Step S13: receiving current configuration information sent by the second terminal node for establishing a communication relationship.

[0084] Step S14: based on the lookup table model, simultaneously matching the preset lookup table information configured by each RAM with the current configuration information to obtain a lookup table result.

[0085] In a specific embodiment, as shown in Figure 5 Step S14: based on the lookup table model, simultaneously matching the preset lookup table information configured by each RAM with the current configuration information to obtain a lookup table result, includes:

[0086] Step S51: parsing preset lookup table information to obtain first Internet Protocol (IP) identification information.

[0087] Specifically, the preset lookup table information can be parsed into first Internet Protocol (IP) identification information using a common data parsing method. The first Internet Protocol (IP) identification information includes preset virtual link parameters (VL) + preset Internet Protocol (IP) parameters + preset identification parameters (UDP).

[0088] Step S52: parsing current configuration information to obtain second Internet Protocol (IP) identification information.

[0089] Specifically, the current configuration information can be parsed into second Internet Protocol (IP) identification information using the same method. The second Internet Protocol (IP) identification information includes current virtual link parameters (VL) + current Internet Protocol (IP) parameters + current identification parameters (UDP).

[0090] Step S53: matching the first Internet Protocol (IP) identification information with the second Internet Protocol (IP) identification information.

[0091] Step S54: If the first URL identification information matches the second URL identification information successfully, upload the matched table result to the external host computer.

[0092] Step S55: If the first URL identification information fails to match the second URL identification information, discard the current configuration information.

[0093] Exemplarily, in actual application, the number of network ports of the first terminal node is 4096, i.e., the configuration table item is 4096, and the table lookup efficiency can be further improved by increasing the table lookup capacity. Specifically, 256 small table lookup units are cascaded to realize 56-bit table lookup with a depth of 4096, the low four-bit address is connected together, and the high eight-bit address controls the write operation of each table lookup unit through address coding. In the write configuration phase, the high eight-bit address determined by each table lookup unit will correspond to an enabled table lookup (0x00 enables table lookup 0, 0x01 enables table lookup 1, and so on), and then a unique 56-bit data is determined by the low four-bit address. After the write operation is completed, the write enable signal will no longer be enabled. After obtaining a 56-bit data to be matched each time, the polling table starts, and 256 small table lookup units simultaneously poll the four-bit address to check whether there is a 56-bit data that can be matched in the internal. Assuming that the low four-bit address of the small table lookup unit 0 is 0x04, the matching is successful, the table lookup unit 0 will output HIT[0] = 1, and the address decoding of HIT[0] corresponds to the address 0x00 and the configuration address 0x004.

[0094] The table lookup unit is added in the FPGA inside the first terminal node to generate a table lookup model, and when the current configuration data is received through the network port, the expected data result can be correctly matched in 16 clock cycles. The signal definition of the network port of the first terminal node is shown in Table 1.

[0095] Table 1

[0096]

[0097]

[0098] In a specific example, the execution steps of the FPGA-based table lookup method in the embodiment are as follows:

[0099] First step: write table lookup unit information, after the device board is powered on, write the configuration table information into the table lookup through the control of WR_EN, WR_DATA[55-0], ADDR[11-0];

[0100] Second step: after the configuration, the WR_EN signal will not be used, when there is configuration data, the RD_EN enables 256 16x256_ lookup table units to be respectively increased from ADDR[3-0]=0000 to ADDR[3-0]=1111, if one table item of the 256 16x256_ lookup table units matches in the process, the HIT[n] signal is set to 1; the lookup table ends;

[0101] Third step: the CMP_ADDR[11-4] address information is recovered by address decoding of the HIT[n], and when the lookup table, the target address ADDR[3-0] is CMP_ADDR[3-0], at this time, the CMP_ADDR[11-0] is the matched address obtained.

[0102] Therefore, in the embodiment of the application, the FPGA-based lookup table method obtains the network port quantity of the first terminal node based on FPGA; based on the network port quantity, a lookup table model of the first terminal node based on the parallel setting of a plurality of distributed RAMs in the FPGA is generated, each RAM is configured with preset lookup table information; current configuration information for establishing a communication relationship sent by a second terminal node is received; and based on the lookup table model, the preset lookup table information of each RAM is matched with the current configuration information to obtain a lookup table result. The application does not need to sequentially match the preset lookup table information of each RAM, which not only can improve the lookup table matching speed, but also can guarantee the matching accuracy of the lookup table, and in addition, the lookup table purpose can be quickly realized without additional hardware resources.

[0103] Based on the same concept, the embodiment of the application also provides a FPGA-based lookup table device, as shown in the figure, comprising the following modules: Figure 6 As shown in the figure, comprising the following modules:

[0104] The port quantity acquisition module 61 is used for obtaining the network port quantity of the first terminal node based on FPGA.

[0105] The lookup table model generation module 62 is used for generating, based on the network port quantity, a lookup table model of the first terminal node based on the parallel setting of a plurality of distributed RAMs in the FPGA, each RAM is configured with preset lookup table information.

[0106] The configuration information receiving module 63 is used for receiving current configuration information for establishing a communication relationship sent by a second terminal node.

[0107] The lookup table result matching module 64 is used for matching, based on the lookup table model, the preset lookup table information of each RAM with the current configuration information to obtain a lookup table result.

[0108] In a specific embodiment, the lookup table model generation module 62 comprises:

[0109] The first preset value determination submodule is used to set the first preset value, which is the number of ports to be connected for each RAM.

[0110] The first target quantity determination submodule is used to determine the first target quantity of multiple RAMs in a distributed parallel setting based on the number of network ports and a first preset value.

[0111] The first lookup information configuration submodule is used to configure and store preset lookup information in each RAM;

[0112] The first lookup table model generation submodule is used to cascade a first target number of RAMs through a bus to obtain a lookup table model.

[0113] In one specific implementation, the lookup model generation module 62 further includes:

[0114] The second preset value determination submodule is used to set the second preset value, which is the number of ports to be connected for each lookup unit.

[0115] The second target quantity determination submodule is used to determine the second target quantity of multiple table lookup units in a distributed parallel setting based on the number of network ports and a second preset value.

[0116] The third target quantity determination submodule is used to determine the third target quantity of multiple RAMs that are distributed and set in parallel in each lookup unit;

[0117] The second lookup information configuration submodule is used to configure and store preset lookup information in each RAM;

[0118] The second lookup model generation submodule is used to cascade the third target number of RAM and the second target number of lookup units through a bus to obtain the lookup model.

[0119] In one specific implementation, the table lookup result matching module 64 includes:

[0120] The first parsing submodule is used to parse the preset lookup table information to obtain the first URL identifier information.

[0121] The second parsing submodule is used to parse the current configuration information to obtain the second URL identifier information.

[0122] The data matching submodule is used to match the first URL identifier information with the second URL identifier information.

[0123] The data upload submodule is used to upload the lookup results to an external host computer if the first URL identifier information and the second URL identifier information match successfully.

[0124] The data discarding submodule is configured to discard the current configuration information if the first URL identification information and the second URL identification information fail to match.

[0125] In a specific embodiment, the first URL identification information and the second URL identification information include a virtual link parameter, a URL parameter and an identification parameter.

[0126] The functions and effects of the modules and submodules of the FPGA-based table lookup device in the embodiments of the present application have been described above, and thus will not be described again. The FPGA-based table lookup device in the embodiments of the present application does not need to sequentially match the preset table lookup information configured by each RAM, and can not only improve the table lookup matching speed, but also ensure the matching accuracy of the table lookup. In addition, the FPGA-based table lookup device can quickly achieve the table lookup purpose without additional hardware resources.

[0127] Obviously, the above embodiments are merely examples for clear illustration, rather than limitation on the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments need not and cannot be exhausted. The obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A table lookup method based on FPGA, characterized in that, Includes the following steps: Obtain the number of network ports of the first terminal node based on the FPGA; Based on the number of network ports, a lookup table model for the first terminal node is generated based on multiple distributed RAMs set up in parallel within the FPGA, with each RAM configured with preset lookup table information. Receive current configuration information sent by the second terminal node to establish a communication relationship; Based on the lookup model, the lookup result is obtained by simultaneously matching the preset lookup information configured in each RAM with the current configuration information; Based on the number of network ports, a lookup table model is generated for the first terminal node, which is based on multiple distributed RAMs configured in parallel within the FPGA. Each RAM is configured with preset lookup table information, including: Set a first preset value, where the first preset value is the number of ports to be connected for each RAM; Based on the number of network ports and the first preset value, determine the first target number of distributed parallel settings for multiple RAMs; Configure and store the preset lookup table information in each RAM; The first target number of RAMs are cascaded through a bus to obtain the lookup table model.

2. The FPGA-based table lookup method according to claim 1, characterized in that, Based on the number of network ports, a lookup table model is generated for the first terminal node, which is based on multiple distributed RAMs configured in parallel within the FPGA. Each RAM is configured with preset lookup table information, including: Set a second preset value, which is the number of ports to be connected for each lookup unit; Based on the number of network ports and the second preset value, determine the second target number of distributed parallel table lookup units; Determine the number of third targets that are distributed and parallelized in each lookup unit, including multiple RAMs. Configure and store the preset lookup table information in each RAM; The lookup table model is obtained by cascading the third target number of RAMs and the second target number of lookup units through a bus.

3. The FPGA-based table lookup method according to claim 1, characterized in that, The step of obtaining a lookup result based on the lookup model by simultaneously matching the preset lookup information configured in each RAM with the current configuration information includes: The first URL identifier information is obtained by parsing the preset lookup table information; The second URL identifier information is obtained by parsing the current configuration information; Match the first URL identifier information with the second URL identifier information; If the first URL identifier information matches the second URL identifier information, the matched lookup result is uploaded to an external host computer. If the first URL identifier information fails to match the second URL identifier information, the current configuration information will be discarded.

4. The FPGA-based table lookup method according to claim 3, characterized in that, The first URL identification information and the second URL identification information include virtual link parameters, URL parameters, and identification parameters.

5. A table lookup device based on FPGA, characterized in that, Includes the following modules: The port quantity acquisition module is used to obtain the number of network ports of the first terminal node based on the FPGA. The lookup model generation module is used to generate a lookup model for the first terminal node based on the number of network ports, which is set up in parallel by multiple distributed RAMs inside the FPGA, and each RAM is configured with preset lookup information. The configuration information receiving module is used to receive the current configuration information sent by the second terminal node for establishing a communication relationship; The lookup result matching module is used to obtain the lookup result by simultaneously matching the preset lookup information configured in each RAM with the current configuration information based on the lookup model. The lookup table model generation module includes: The first preset value determination submodule is used to set the first preset value, wherein the first preset value is the number of ports to be connected for each RAM. The first target quantity determination submodule is used to determine the first target quantity of multiple RAMs to be set up in a distributed parallel manner based on the number of network ports and the first preset value; The first lookup information configuration submodule is used to configure and store the preset lookup information in each RAM; The first lookup table model generation submodule is used to cascade the first target number of RAMs through a bus to obtain the lookup table model.

6. The FPGA-based table lookup device according to claim 5, characterized in that, The lookup table model generation module also includes: The second preset value setting submodule is used to set the second preset value, which is the number of ports to be connected for each lookup unit; The second target quantity determination submodule is used to determine the second target quantity of multiple table lookup units set up in a distributed parallel manner based on the number of network ports and the second preset value; The third target quantity determination submodule is used to determine the third target quantity of multiple RAMs that are distributed and set in parallel in each of the table lookup units; The second lookup information configuration submodule is used to configure and store the preset lookup information in each RAM; The second lookup model generation submodule is used to cascade the third target number of RAMs and the second target number of lookup units through a bus to obtain the lookup model.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the FPGA-based table lookup method according to any one of claims 1 to 4.

8. A computer device, characterized in that, include: A memory and a processor are interconnected, the memory stores computer instructions, and the processor executes the computer instructions to perform the FPGA-based lookup method according to any one of claims 1 to 4.

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