Multi-layer convolutional brain chip based on full pulse HMAX model

Abstract

The application discloses a kind of multilayer convolutional brain-like chips based on full pulse HMAX model, chip uses layer type configurable multi-core architecture, overall by global controller, several cascaded pulse convolution kernel, interlayer shared learning engine and output pulse decoder four parts are formed.The global controller is mainly responsible for the transmission, interaction and control of processor internal and external data.Pulse convolution processing kernel is the core module of processor, it is connected in turn, and the pulse data output by the previous processing kernel is received by the next processing kernel.When a certain network layer is in learning state, the network layer will call interlayer shared learning engine module to complete on-chip learning.Output pulse decoder decodes AER data output, thereby realizing classification function, and the result is output externally.The application can realize efficient on-chip learning and inference of full pulse HMAX model, and solves the problems of low recognition rate, insufficient performance and poor energy efficiency of existing edge brain-like chips.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of neuromorphic brain-like computing chip, in particular to a multi-layer convolutional brain-like chip based on a full-pulse HMAX model. BACKGROUND

[0002] In recent years, the field of neuromorphic brain-like computing chip has attracted widespread attention and has made some progress. Platform-level and edge-end brain-like chips have been constantly emerging. With the continuous development of brain-like computing chips, their high energy efficiency and low power consumption characteristics have enabled more and more researchers to develop edge-oriented brain-like computing chips to meet the demand for intelligent processing chips in resource and power-constrained edge scenarios.

[0003] However, existing edge-oriented neuromorphic chips often only support on-chip learning and inference of shallow fully connected networks, and cannot achieve end-to-end on-chip learning and inference of multi-layer pulse convolutional networks, resulting in low recognition rate of the network and failing to meet the demand of edge application scenarios with high recognition rate requirements.

[0004] Therefore, it is necessary to develop a multi-layer convolutional brain-like chip based on a full-pulse HMAX model. SUMMARY

[0005] The purpose of the present application is to provide a multi-layer convolutional brain-like chip based on a full-pulse HMAX model to achieve high energy efficiency and high performance of end-to-end pulse convolutional network on-chip learning and inference.

[0006] In order to achieve the above-mentioned purpose, the multi-layer convolutional brain-like chip based on a full-pulse HMAX model of the present application integrates a full-pulse HMAX model, which includes an input layer, a convolutional layer S1, a pooling layer C1, a convolutional layer S2, a pooling layer C2 and a fully connected layer FC. Each layer is composed of a plurality of neurons, the neurons use neurons that can only emit a pulse once, and all neurons of the full-pulse HMAX model can only emit a pulse once during learning and inference.

[0007] The multi-layer convolutional brain-like chip uses a multi-core architecture with configurable layer types, which includes a global controller, a plurality of pulse convolutional kernels, an inter-layer shared learning engine and an output pulse decoder.

[0008] The global controller is connected to each pulse convolutional kernel, the inter-layer shared learning engine and the output pulse decoder. The plurality of pulse convolutional kernels are connected in sequence, and the last pulse convolutional kernel is connected to the output pulse decoder. Each pulse convolutional kernel is also connected to the inter-layer shared learning engine.

[0009] The global controller is used to be responsible for the transmission, interaction and control of the multi-layer convolutional brain-like chip and external data.

[0010] The pulse convolution kernel is used to realize a combination of a convolution layer and a pooling layer, or an operation of a full connection layer;

[0011] The output pulse decoder realizes a classification function by decoding the output AER data, and outputs the result.

[0012] Optionally, the calculation model of the neuron is:

[0013] V(k) = V(k-1) + w i(k)

[0014] In the formula, k represents a current input event, k-1 represents a previous input event, w i(k) represents a synaptic weight corresponding to the current event input; V(k) represents a membrane potential of the neuron after the current input event arrives; and V(k-1) represents a membrane potential of the neuron before the current input event arrives.

[0015] Optionally, the update of the convolution layer weight adopts an unsupervised STDP algorithm;

[0016] For learning triggered by a post-synaptic pulse, the update formula is as follows:

[0017]

[0018] Wherein, A is a learning rate; and Δw is an update change amount of the weight.

[0019] Optionally, the update of the classification layer weight adopts a supervised STDP algorithm;

[0020] During the input event process, if the neuron emitting the pulse does not match the label of the current input event, an error value e = -1 triggers the update of the synaptic weight of the current time at which the input pulse appears; after all the input events end, if the neuron emitting the pulse does not match the label of the input event, an error value e = 1 triggers the update of the synaptic weight of the current time at which the input pulse appears; and the update formula is as follows:

[0021]

[0022] Wherein, A is a learning rate; and Δw is an update change amount of the weight.

[0023] Optionally, the pulse convolution kernel comprises a processing kernel controller, a processing unit array, an intra-cell membrane potential finder and an inter-kernel pulse data scheduler; the processing kernel controller is connected with the processing unit array, the intra-cell membrane potential finder and the inter-kernel pulse data scheduler respectively, and the processing unit array is connected with the intra-cell membrane potential finder; the processing unit array comprises a plurality of processing units, and is configured to store network parameters and perform network operations; the intra-cell membrane potential finder is configured to find the maximum membrane potential stored in the kernel and find the final winner and perform on-chip learning of the convolution layer.

[0024] Optionally, the processing unit comprises a membrane potential storage, a weight storage, a pooling information storage, a calculation unit, a pooling unit and an intra-cell pulse scheduler; the intra-cell membrane potential finder is connected with the membrane potential storage; the calculation unit is connected with the membrane potential storage, the weight storage and the pooling unit respectively; the pooling unit is connected with the pooling information storage and the intra-cell pulse scheduler respectively.

[0025] The membrane potential storage is configured to store neuron membrane potentials; the weight storage is configured to store weights; and the pooling information storage is configured to store pooling information.

[0026] The calculation unit is configured to complete different data processing functions of neurons in learning and inference.

[0027] The pooling unit is configured to realize a pooling function according to current output pulse information and stored pooling information.

[0028] The intra-cell pulse scheduler is configured to be responsible for scheduling pulse data generated in the processing unit, and finally the pulse data is taken out by the inter-kernel pulse data scheduler in the pulse convolution kernel and sent to the next pulse convolution kernel corresponding to the network layer.

[0029] Optionally, the inter-layer shared learning engine comprises a local controller, a channel inhibition register, a position inhibition register, a weight update module and a presynaptic pulse information storage; the local controller is connected with the channel inhibition register, the position inhibition register, the weight update module and the presynaptic pulse information storage respectively; and the presynaptic pulse information storage is connected with the weight update module.

[0030] The channel inhibition register is configured to store channel inhibition information and output to the connected pulse convolution kernel in the convolution layer learning stage, so that the pulse data processing stage of the neuron subjected to inhibition is skipped.

[0031] The weight update module is configured to realize weight update calculation in the on-chip learning process; the weight update module can support input weight upper and lower bound limitation, random update and output weight truncation through parameter configuration.

[0032] The presynaptic pulse information memory is responsible for storing current presynaptic pulse information.

[0033] Optionally, when the channel and neighborhood of a certain neuron of the convolution layer are side-inhibited, only the inhibited channel and corresponding two-dimensional address information are recorded; when the side-inhibition information is needed, the channel and corresponding two-dimensional address information are combined to jointly determine.

[0034] Optionally, the computing unit adopts a reconfigurable design, and by configuring the "only increase" and "normal detection" signals, the running modes and functions of the convolution layer network feedforward state in the learning state, the winner finding state of the convolution layer in the learning state, the normal inference state and the internal state quantity initialization can be realized.

[0035] Optionally, the computing unit supports an event skipping function, and whether to set the skip signal high is determined by judging whether the information of the current neuron meets the skipping condition.

[0036] The beneficial effects of the present application are as follows:

[0037] (1) The all-pulse HMAX model composed of cumulative firing neurons capable of emitting only one pulse is proposed, which greatly reduces the chip operation amount and improves the chip processing speed and energy efficiency;

[0038] (2) Based on the unsupervised / supervised hybrid STDP learning rule, on-chip learning of the all-pulse HMAX model is realized, and excellent recognition performance is achieved;

[0039] (3) The multi-layer convolutional brain chip based on the all-pulse HMAX model realizes end-to-end on-chip learning and inference of the multi-layer pulse convolution network at low cost, has excellent recognition, inference and learning performance, and greatly meets the demand of edge applications for intelligent chips with low power consumption, high energy efficiency and high performance. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 FIG. 1 is a schematic diagram of the all-pulse HMAX model in the present embodiment;

[0041] Figure 2 FIG. 3 is a schematic diagram of the architecture of the multi-layer convolutional brain chip based on the all-pulse HMAX model in the present embodiment;

[0042] Figure 3 FIG. 5 is a schematic diagram of the computing unit in the present embodiment;

[0043] Figure 4 FIG. 7 is a schematic diagram of the pooling unit in the present embodiment;

[0044] Figure 5 FIG. 9 is a schematic diagram of the weight update module in the present embodiment;

[0045] Figure 6 Figure 1 is a schematic diagram of an output pulse decoder in the embodiment. DETAILED DESCRIPTION

[0046] Other advantages and effects of the present application can be easily understood by those skilled in the art from the description of the embodiments of the present application. The present application can also be implemented or applied in other different embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be understood that the preferred embodiments are only for illustrating the present application, but not for limiting the protection scope of the present application.

[0047] It should be noted that the diagrams provided in the following embodiments only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the diagrams, but not drawn according to the number, shape and size of the components in actual implementation. The shape, number and ratio of the components in actual implementation can be arbitrarily changed, and the layout of the components can be more complex.

[0048] In the embodiment, a neuron that can only emit one pulse is used based on the full pulse HMAX model, and the neuron calculation model is as follows:

[0049] V(k) = V(k-1) + w i(k)

[0050] In the formula, k represents the current input event, k-1 represents the previous input event, w represents the synaptic weight corresponding to the current event input, V(k) represents the membrane potential of the neuron after the current input event arrives, and V(k-1) represents the membrane potential of the neuron before the current input event arrives. i(k)

[0051] Since the convolution layer has a large number of neurons, in order to ensure the sparsity of the output pulse of the convolution layer, all the neurons in the embodiment can only emit one pulse (Fire Once) whether in learning or reasoning. Therefore, the neuron used in the embodiment can be named as single-spike IF neuron (Single-Spike IF, SS-IF). Based on the neuron calculation model, the full pulse HMAX model of the input layer-convolution layer S1, the pooling layer C1, the convolution layer S2, the pooling layer C2 and the fully connected layer FC is constructed, as shown in Figure 1 Each layer is composed of a plurality of neurons.

[0052] In the embodiment, a hybrid unsupervised / supervised pulse time-dependent plasticity (Spike Timing Dependent Plasticity, STDP) learning rule is used to realize the on-chip learning of the full pulse HMAX model.​

[0053] In this embodiment, the unsupervised STDP algorithm is mainly used for updating the weights of the convolution layer.

[0054] Since the scheme of combining the Time to First Spike (TTFS) with the SS-IF neuron is adopted, for the occurrence of the presynaptic and postsynaptic pulses in the convolution layer, only 1 or 0 is needed to express. Since the specific time of the pulse occurrence is ignored and only whether the pulse exists is considered, the increase and decrease of the weight can be simplified as addition and subtraction. At this time, for the learning triggered by the postsynaptic pulse, the update formula is as shown in the following formula:

[0055]

[0056] In the formula, A is the learning rate. Aw is the update change of the weight.

[0057] In the learning triggered by the postsynaptic pulse, when the spike flag is 0, the postsynaptic pulse will perform a weight inhibition operation. The reason is that since the SS-IF neuron is adopted, when the output neuron emits a pulse, if no pulse generated by the input layer is detected, it can be considered that the synaptic connection is irrelevant to the output and the inhibition operation needs to be performed. It can be seen that in the learning triggered by the postsynaptic pulse, the enhancement and inhibition are respectively performed according to whether the input layer pulse exists, so in this embodiment, only the learning triggered by the postsynaptic pulse is retained, thereby reducing the algorithm complexity and saving the hardware resource consumption.

[0058] In the process of the pulse neural network processing the input pulse, the time of the emission pulse of the postsynaptic neuron and the size of the membrane potential when the emission pulse is emitted reflect the matching degree of the corresponding synaptic weight and the input pulse sequence. In order to select the postsynaptic neuron with the highest matching degree, it is necessary to select the neuron with the highest matching degree based on the two factors to perform learning, so that the neuron can better extract the features of the input pulse sequence.

[0059] Therefore, in this embodiment, the two factors of the emission pulse time and the size of the membrane potential of the emission pulse neuron are combined, and for the pulse convolution layer, the mechanism of selecting the neuron with the largest membrane potential among the neurons emitting pulses as the winner at the end of each time step in which the relevant STDP pulse event occurs and performing update based on the input pulse information is adopted.

[0060] However, in the middle layer of the pulse neural network, in order to improve the learning efficiency, in the learning of the entire input image event, multiple winners are often allowed to appear, so that multiple learning is performed. When a winner is selected and learned, a side inhibition operation will be performed on the remaining neurons, which will inhibit the learning function of part of the neurons, thereby improving the sparsity of the learned features.

[0061] In this embodiment, the side inhibition mechanism for learning function is as follows:

[0062] When a neuron in a certain channel in the convolution layer wins, the corresponding synaptic weight will learn the input features within the r x r (r is the inhibition diameter) range centered on the position of the winner neuron. At this time, in order to improve the feature extraction capability of the network and avoid other convolution kernels from learning similar features, all neurons in the channel where the neuron is located and within the r x r (r is the inhibition diameter) range will be inhibited. At this time, the inhibited neurons will not be able to participate in the subsequent winner selection process and will not be able to participate in learning before the next image is input. By introducing such a nonlinear operation, the deep pulse convolution network can extract more non-repetitive features.

[0063] The supervised STDP algorithm is mainly used for updating the weights of the fully connected layer. The supervised STDP algorithm is based on the error triggered learning of the pulse emission of the fully connected layer neurons for realizing classification. During the input event process, if the neuron emitting the pulse does not match the label of the current input event, the error value e = -1 will trigger the update of the synaptic weight that has appeared the input pulse at the current time. After all the input events end, if the neuron that matches the label of the input event does not emit the pulse, the error value e = 1 will trigger the update of the synaptic weight that has appeared the input pulse. The update formula is as follows:

[0064]

[0065] In the formula, A is the learning rate. Δw is the update change of the weight.

[0066] As shown in Figure 2 In this embodiment, a multi-layer convolutional brain chip based on the full pulse HMAX model is provided. The multi-layer convolutional brain chip integrates the full pulse HMAX model described in this embodiment. The multi-layer convolutional brain chip adopts a multi-core architecture with configurable layer types. The multi-core architecture includes a global controller, a plurality of pulse convolution kernels, an inter-layer shared learning engine, and an output pulse decoder. The global controller is connected to each pulse convolution kernel, the inter-layer shared learning engine, and the output pulse decoder. The plurality of pulse convolution kernels are connected in sequence. The last pulse convolution kernel is connected to the output pulse decoder. Each pulse convolution kernel is connected to the inter-layer shared learning engine.

[0067] In this embodiment, the global controller is responsible for the transmission, interaction, and control of internal and external data of the multi-layer convolutional brain chip.

[0068] In this embodiment, the pulse convolution kernel is the core module for implementing the deep pulse convolution network function of the multi-layer convolution brain chip. Each pulse convolution kernel is responsible for implementing a combination of a convolution layer and a pooling layer, or the operation of a fully connected layer. When a network layer (including a convolution layer S1, a pooling layer C1, a convolution layer S2, a pooling layer C2, and a fully connected layer FC, when implementing the convolution layer, the function of the pooling layer is also implemented synchronously, and an additional pulse convolution kernel is not needed) is in a learning state, the network layer calls the inter-layer shared learning engine to complete on-chip learning. In this embodiment, the multi-layer convolution brain chip is provided with three pulse convolution kernels. The three pulse convolution kernels are connected in sequence, and the pulse data output by the previous pulse convolution kernel is received by the next pulse convolution kernel. In this way, each pulse convolution kernel can be processed in a pipeline manner, thereby improving the running speed of the multi-layer convolution brain chip.

[0069] In this embodiment, the pulse convolution kernel is internally composed of a processing core controller, a processing unit array, an intra-cell membrane potential finder, and an intra-cell pulse data scheduler. The processing core controller is connected with the processing unit array, the intra-cell membrane potential finder, and the inter-core pulse data scheduler, respectively. The processing unit array is connected with the intra-cell membrane potential finder.

[0070] As shown in Figure 2 , in this embodiment, the processing unit array is composed of a plurality of processing units. The number of processing units in each pulse convolution kernel can be configured by comprehensive parameters. The processing units are used for storing network parameters and performing network operations in the pulse convolution kernel, and are the core part of the pulse convolution kernel.

[0071] As shown in Figure 2 , in this embodiment, the processing unit includes a membrane potential memory, a weight memory, a pooling information memory, a calculation unit, a pooling unit, and an intra-cell pulse scheduler. The intra-cell membrane potential finder is connected with the membrane potential memory. The calculation unit is connected with the membrane potential memory, the weight memory, and the pooling unit, respectively. The pooling unit is connected with the pooling information memory and the intra-cell pulse scheduler, respectively.

[0072] As shown in Figure 2 , in this embodiment, the membrane potential memory is used for storing the membrane potential of a neuron. The weight memory is used for storing the weight. The pooling information memory is used for storing the pooling information.

[0073] As shown in Figure 2 , in this embodiment, the intra-cell membrane potential finder is used for finding the maximum membrane potential stored in the internal storage, and finding the final winner and performing on-chip learning of the convolution layer.

[0074] As shown in Figure 2As shown, in the embodiment, the computing unit is a core data processing module of the processing unit, and is configured to complete different data processing functions of neurons in learning and reasoning. In order to support different functions with lower hardware resource consumption, in the embodiment, the computing unit adopts a reconfigurable design, and by configuring the "only increase" and "normal detection" signals, the following running modes and functions can be realized: convolutional layer network feedforward state in learning state, winner finding state of the convolutional layer in learning state, normal reasoning state, and internal state variable initialization, thereby greatly reducing the hardware resource consumption. In addition, the event skipping function is supported, and by judging whether the information of the current neuron meets the skipping condition (such as emitting a pulse or performing learning), it is determined whether to set the skipping signal high, and then all the processing is skipped, thereby further reducing the energy consumption.

[0075] As shown, Figure 3 In the embodiment, the computing unit adopts a reconfigurable design, and by configuring the "only increase" and "normal detection" signals, different functions can be realized. For the processing of the convolutional layer network feedforward state in the learning state, the membrane potential detection operation of the convolutional layer in the learning state occurs at the end of each time step, rather than after each input pulse arrives and is processed. Therefore, in this state, the "only increase" signal is 1, and the "normal detection" signal is 0. If the skipping condition (the current neuron emits a pulse or the current processing channel triggers learning) is not met, the accumulated membrane potential is written back to the memory. For the data path of the intracellular membrane potential finding state of the convolutional layer in the learning state, in this state, the "only increase" signal and the "normal detection" signal are both 0, and at this time, the result of comparing the output membrane potential with the threshold value is output. Similarly, by judging whether the skipping condition (the current neuron emits a pulse or the current processing channel triggers learning) is met, it is determined whether to set the skipping signal high and perform the skipping processing. For the normal reasoning of the convolutional layer and the reasoning and learning state of the fully connected layer, the "only increase" signal is 0, and the "normal detection" signal is 1, which is used to select the neuron membrane potential accumulation and judge the result after the membrane potential. After the skipping judgment (whether a pulse is emitted), it is determined whether to write the result back to the membrane potential memory. When the "only increase" signal and the "normal detection" signal are both 1, the internal variable initialization can be realized.

[0076] As shown, Figure 4As shown, in the embodiment, the pooling unit realizes the pooling function according to the current output pulse information and the stored pooling information. The pooling unit can be configured to have a maximum pooling function of four pooling windows of 1x1, 2x2, 4x4 and 8x8. When the calculation unit calculates that a certain neuron emits a pulse, the address of the neuron is sent to the pooling unit. By reading the pooling information memory, it is determined whether the corresponding pooling neuron of the neuron emitting the current pulse has generated a pulse. If not, the current pulse address and the corresponding pooled pulse address are outputted, and the corresponding pooling neuron (in the embodiment, the pooling neuron is the SS-IF neuron after being pooled) emits pulse information. Since the network uses SS-IF neurons, all neurons can only emit a pulse, and therefore the data bit width of the pooling information memory is only 1 bit, and 1 and 0 respectively represent whether the corresponding pooling neuron has emitted a pulse. In summary, by consuming a small amount of logic and storage resources, multiple types of pooling operations can be flexibly supported. Figure 2 As shown, in the embodiment, the intra-unit pulse scheduler is used to schedule the pulse data generated in the processing unit, and finally the inter-core pulse data scheduler in the pulse convolution kernel takes out and sends the pulse data to the pulse convolution kernel corresponding to the next network layer. Since the network uses a layer-by-layer learning mechanism, the learning actions of each network layer are performed in sequence, so when the network is in a learning state, only one network layer needs to perform on-chip learning operations. Therefore, in order to reduce the number of repeated circuits and reduce hardware resource consumption, the inter-layer shared learning engine design is adopted in the embodiment. When a certain network layer is in a learning state, the network layer calls the learning module to complete the on-chip learning.

[0077] In the prior art, since the convolution layer has a lateral inhibition mechanism during learning, the inhibited neuron information needs to be recorded to avoid its learning function. Assuming that the number of rows, columns and channels of the feature map is H, W and C respectively, if the lateral inhibition information of each neuron in the feature map is stored, HxWxC storage space is consumed, and therefore a large amount of memory resources are consumed, which is not conducive to the edge terminal with limited resources. In order to overcome this defect, the lateral inhibition information storage mechanism of separating channels and two-dimensional positions is innovatively proposed in the embodiment. When the channel and neighborhood of a certain neuron are inhibited, only the inhibited channel and the corresponding related two-dimensional address information need to be recorded. When the lateral inhibition information is needed, only the two information needs to be combined to judge together, and the same effect can be achieved, thereby avoiding storing the lateral inhibition information of all neurons. The memory resources required by the present application are only HxW+C, which greatly reduces the memory demand compared with the prior art.

[0078] As shown, Figure 2As shown in the figure, in this embodiment, the inter-layer shared learning engine includes five parts: a local controller, a channel inhibition register, a position inhibition register, a weight update module, and a pre-synaptic pulse information storage. The local controller is connected with the channel inhibition register, the position inhibition register, the weight update module, and the pre-synaptic pulse information storage, and the pre-synaptic pulse information storage is connected with the weight update module.

[0079] As shown in the figure, Figure 2 As shown in the figure, in this embodiment, the inter-channel inhibition register is used to store channel inhibition information and output to the connected pulse convolution kernel in the convolution layer learning stage, so that the pulse data processing stage of the inhibited neuron is skipped.

[0080] As shown in the figure, Figure 5 As shown in the figure, in this embodiment, the weight update module is used to realize the weight update calculation in the on-chip learning process, and is a key module for completing on-chip learning. Through parameter configuration, the weight update module can support input weight upper and lower limit restriction, random update, output weight truncation and other functions.

[0081] When the weight update module performs unsupervised STDP learning, the random update module in it does not work. Since the pre-synaptic pulse information is binary data of 0 and 1, when calculating, the weight only performs addition operation with the learning rate, and the pre-synaptic pulse information only indicates whether there is an input pulse, so that the required learning rate is selected. When the learning rate is selected, since the unsupervised learning does not use the random update mechanism, the “random update effective” signal indicating whether the random update is effective is 0, and at this time the learning rate is directly output and added to the input weight. At the same time, in order to speed up the convergence of the convolution layer weight, the input weight will be subjected to weight upper and lower limit judgment. If the input weight has reached the upper limit or the lower limit, it is considered that the current weight has converged, and the weight update is not performed, and the input weight is directly used as the output. At this time, the “input weight upper and lower limit restriction” signal indicating that the input weight is subjected to upper and lower limit judgment is 1. Finally, since random update is not used in unsupervised learning, the result is directly sent to the weight upper and lower limit judgment, and if the updated weight exceeds the weight upper limit or is lower than the weight lower limit, it is set to the corresponding upper limit and lower limit, realizing weight hard truncation. The result after weight hard truncation is used as the final updated weight and is output. In supervised STDP learning, we use the random update mechanism. The high 8 bits of the selected learning rate are used as the basic weight change, and are added to the input 8-bit weight. At the same time, the low 8 bits of the learning rate are compared with the random number. If the low 8 bits of the learning rate are greater than the random number, the added weight is increased by 1 or decreased by 1 based on the sign bit of the learning rate, otherwise the added weight is not processed. Finally, the operation result is subjected to hard truncation and is output as the updated weight, realizing supervised learning.

[0082] AsFigure 2 As shown, in this embodiment, the presynaptic pulse information memory is responsible for storing the current presynaptic pulse information. Since the network uses SS-IF neurons for processing, the bit width of the presynaptic pulse information memory is only 1 bit, occupying a small amount of storage resources.

[0083] like Figure 6 As shown in this embodiment, the output pulse decoder is used to decode the output pulse data. After all input events have been processed, the network needs to determine whether the current classification result is correct or incorrect. At this time, the output pulse decoder will sequentially read the output pulse data of each of the pulse convolution kernels connected to it, and accumulate the values ​​stored in the registers of their corresponding labels. When a cluster is full, the register will be compared with the value in the label with the most emitted pulses, and the maximum value will be stored in the register of the label with the most emitted pulses. At the same time, the register of the label corresponding to the current neuron will be cleared, and the label pointed to by the current cluster will be incremented by 1. When the emitted pulse labels of all neurons have been read, the network will compare whether the label recorded in the register of the label with the most emitted pulses is equal to the current input label, and then output a correct or incorrect signal to complete the result judgment, thereby realizing the classification function and outputting the result.

[0084] The above embodiments are merely preferred embodiments provided to fully illustrate the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention.

Claims

1. A multi-layer convolutional brain-like chip based on a full-pulse HMAX model, characterized in that: The multi-layer convolutional brain chip integrates a full-pulse HMAX model, which includes an input layer, a convolutional layer S1, a pooling layer C1, a convolutional layer S2, a pooling layer C2 and a fully connected layer FC; each layer is composed of a plurality of neurons, the neurons are only capable of emitting a pulse, and all neurons of the full-pulse HMAX model can only emit a pulse during learning and reasoning; The multi-layer convolutional brain chip adopts a multi-core architecture with layer type configurable, which includes a global controller, a plurality of pulse convolutional kernels, an inter-layer shared learning engine and an output pulse decoder; The global controller is connected with each pulse convolutional kernel, the inter-layer shared learning engine and the output pulse decoder respectively; The plurality of pulse convolutional kernels are connected in sequence, and the last pulse convolutional kernel is connected with the output pulse decoder, and each pulse convolutional kernel is further connected with the inter-layer shared learning engine; The global controller is used for transmission, interaction and control of the multi-layer convolutional brain chip and external data; The pulse convolutional kernel is used for realizing a combination of a convolutional layer and a pooling layer, or a calculation of a fully connected layer; The output pulse decoder decodes AER data output, thereby realizing a classification function and outputting a result.

2. The multi-layer convolutional brain chip based on the full-pulse HMAX model according to claim 1, characterized in that: The calculation model of the neuron is as follows: V(k) = V(k - 1) + w i(k) In the formula, k represents the current input event, k-1 represents the previous input event, w i(k) represents the synaptic weight corresponding to the current event input; V(k) represents a neuron membrane potential after a current input event arrives; V(k-1) represents a neuron membrane potential before a current input event arrives.

3. The multi-layer convolutional brain chip based on the full-pulse HMAX model according to claim 2, characterized in that: The update of the convolutional layer weight adopts an unsupervised STDP algorithm; For learning triggered by a post-synaptic pulse, the update formula is as follows: Wherein, A is a learning rate, and Δw is an update change of the weight.

4. The multi-layer convolutional brain chip based on the full-pulse HMAX model according to claim 2, characterized in that: The update of the fully connected layer weight adopts a supervised STDP algorithm; During the input event, if a neuron emitting a pulse does not match a label of the current input event, an error value e=-1 will trigger an update of a synaptic weight of a neuron emitting an input pulse at a current time; After all input events end, if a neuron matching the label of the input event does not emit a pulse, an error value e=1 will trigger an update of a synaptic weight of a neuron emitting an input pulse; the update formula is as follows: Wherein, A is a learning rate, and Δw is an update change of the weight.

5. The multi-layer convolutional brain chip based on a full-pulse HMAX model according to any one of claims 1 to 4, characterized in that: The pulse convolutional kernel includes a processing kernel controller, a processing unit array, an intra-cell membrane potential finder and an inter-kernel pulse data scheduler; the processing kernel controller is connected with the processing unit array, the intra-cell membrane potential finder and the inter-kernel pulse data scheduler respectively, and the processing unit array is connected with the intra-cell membrane potential finder; wherein, the processing unit array includes a plurality of processing units, which are used for storing network parameters and executing network operations; the intra-cell membrane potential finder is used for finding a maximum membrane potential stored internally, and finding a final winner and executing on-chip learning of a convolutional layer.

6. The multi-layer convolutional brain chip based on the full-pulse HMAX model according to claim 5, characterized in that: The processing unit comprises a membrane potential storage, a weight storage, a pooling information storage, a calculation unit, a pooling unit and an intra-unit pulse scheduler, the intra-unit membrane potential finder is connected with the membrane potential storage, the calculation unit is connected with the membrane potential storage, the weight storage and the pooling unit respectively, the pooling unit is connected with the pooling information storage and the intra-unit pulse scheduler respectively; The membrane potential storage is used for storing the membrane potential of the neuron. The weight storage is used for storing the weight. The pooling information storage is used for storing the pooling information. The calculation unit is used for completing different data processing functions of the neuron in learning and reasoning. The pooling unit is used for realizing the pooling function according to the current output pulse information and the stored pooling information. The intra-unit pulse scheduler is used for scheduling the pulse data generated in the processing unit, and finally the pulse data is taken out by the inter-core pulse data scheduler in the pulse convolution kernel and sent to the pulse convolution kernel corresponding to the next network layer.

7. The multi-layer convolutional brain chip based on the full-pulse HMAX model according to claim 5, characterized in that: The inter-layer shared learning engine comprises a local controller, a channel inhibition register, a position inhibition register, a weight update module and a presynaptic pulse information storage; the local controller is connected with the channel inhibition register, the position inhibition register, the weight update module and the presynaptic pulse information storage respectively, and the presynaptic pulse information storage is connected with the weight update module; The channel inhibition register is used for storing channel inhibition information and outputting to the connected pulse convolution kernel in the convolution layer learning stage, so that the pulse data processing stage of the inhibited neuron is skipped. The weight update module is used for realizing the weight update calculation in the on-chip learning process, and the weight update module can support the input weight upper and lower bound limit, random update and output weight truncation through parameter configuration. The presynaptic pulse information storage is responsible for storing the current presynaptic pulse information.

8. The multi-layer convolutional brain chip based on the full-pulse HMAX model according to claim 5, characterized in that: When the channel and neighborhood of a neuron in the convolution layer are side inhibited, only the inhibited channel and corresponding two-dimensional address information are recorded; when the side inhibition information is needed, the channel and corresponding two-dimensional address information are combined to determine together.

9. The multi-layer convolutional brain chip based on the full-pulse HMAX model according to claim 6, characterized in that: The calculation unit adopts a reconfigurable design, and through configuration of "only increase" and "normal detection" signals, the running modes and functions of the convolution layer network feedforward state in the learning state, the winner finding state of the convolution layer in the learning state, the normal reasoning state and the internal state quantity initialization can be realized.

10. The multi-layer convolutional brain chip based on a full-pulse HMAX model according to claim 6, characterized in that: The calculation unit supports the event skipping function, and whether to set high the skip signal is determined by judging whether the information of the current neuron meets the skip condition.

Images