Differential signal testing method, circuit and device

Abstract

The present application proposes a differential signal testing method, circuit, and device, wherein the differential signal testing method controls an n-stage cascaded switching switch group to power on and obtain a differential signal to be tested, and during testing, outputs a switching control signal to each switching switch to switch the communication channel and / or communication rate of the differential signal. At the same time, the communication state of the differential signal is determined according to the output signal of each output end of the switching switch group, thereby switching the communication channel of the differential signal, performing external stress testing on the differential signals of different communication channels in turn, and determining the design defects of the differential signal. The channel is then adjusted later to improve the stability of the signal, and the test efficiency is improved by automatically switching the communication channel of the differential signal.

Description

Technical Field

[0001] The present application belongs to the field of signal testing technology, and in particular relates to a differential signal testing method, circuit, and device. Background Art

[0002] Differential transmission is a signal transmission technology that differs from the traditional method of using one signal line and one ground line. Differential transmission transmits signals on both lines, with the two signals having the same amplitude and opposite phases. The signal transmitted on these two lines is called a differential signal. The signal receiver compares the difference between the two voltages to determine the logical state of the transmitter.

[0003] The communication capability of differential signals determines the effectiveness of the communication devices at both ends. Conventional testing involves manually or mechanically plugging and unplugging different input and output ports to switch the differential signal communication channel. This allows for external stress testing of the differential signal, thereby exposing design flaws and improving signal stability. However, manual or mechanical plugging and unplugging methods are inefficient. Summary of the Invention

[0004] The purpose of this application is to provide a differential signal testing method, aiming to solve the problem of low testing efficiency in traditional differential signal testing methods.

[0005] A first aspect of an embodiment of the present application provides a differential signal testing method, including:

[0006] Control the n-stage cascade switch group to power on and obtain the differential signal to be tested, wherein each stage of the switch group includes y n switches connected in parallel, each of the switches comprising a signal input terminal and y signal output terminals, the signal input terminal of each switch being connected to a signal output terminal of at least one different switch of the preceding stage, where n is a positive integer and y ≥ 2;

[0007] Outputting a switching control signal to each of the switching switches to switch the communication channel and / or communication rate of the differential signal;

[0008] The communication state of the differential signal is determined according to the output signals of the output terminals of the switching group.

[0009] Optionally, the step of determining the communication state of the differential signal according to the output signals of each output terminal of the switching switch group specifically includes:

[0010] Obtain the differential signal output by each switching of the n-stage cascade switch group;

[0011] The parameters of the differential signal outputted at each switching are compared with the preset threshold parameters, and the communication state of the differential signal is determined according to the comparison result.

[0012] Optionally, the parameters of the differential signal include at least bandwidth, attenuation ratio, amplitude and rate.

[0013] A second aspect of the embodiments of the present application provides a differential signal testing circuit, comprising an n-stage cascaded switching switch group and a controller, wherein the controller comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the differential signal testing method described above when executing the computer program;

[0014] Among them, each level of the switch group includes y n Switches are connected in parallel, each of the switches comprises a signal input terminal and y signal output terminals, the signal input terminal of each switch is connected to a signal output terminal of at least one different switch of the previous stage, n is a positive integer, y≥2.

[0015] Optionally, the memory stores truth table data;

[0016] The processor is configured to read the truth table data and output a matching switching control signal to each of the switching switches to switch the communication channel and / or communication rate of the differential signal.

[0017] Optionally, y=2, the control end of each switch is connected to the control end of the controller, and each switch includes a signal input end, a first signal output end, and a second signal output end;

[0018] A first signal output terminal of the i-th switch of the n-th switch group is connected one-to-one with a signal input terminal of the 2i-1-th switch of the n+1-th switch group, and a second signal output terminal of the i-th switch of the n-th switch group is connected one-to-one with a signal input terminal of the 2i-th switch of the n+1-th switch group. Each of the switches is triggered by a switch switching signal to connect one of its own signal input terminals and a first signal input terminal, or to trigger the connection between one of its own signal input terminals and a second signal input terminal, i∈[1, 2n], where n is a positive integer;

[0019] The differential signal test circuit further includes:

[0020] a signal input port, the signal input port being connected to the two signal input ends of the two switches of the switch group of the first stage, respectively, and being configured to input 2m groups of differential signals and output m groups of differential signals to each of the cascaded switches;

[0021] 2 n Signal output ports, 2 n The signal output port and the first to second switches of the switch group of the nth level n-1 The first signal output terminal and the second signal output terminal of the switching switch are connected one by one in sequence, and n The signal output port is connected to the second of the switch group of the nth level. n-1 +1 for switching the switch to 2 n The first signal output terminals and the second signal output terminals of the switches are connected one by one in sequence.

[0022] Optionally, m=2, and the signal input end, the first signal output end, and the second signal output end of each of the switches include two groups of differential signal ends.

[0023] Optionally, the switch includes a switching chip;

[0024] The switching chip includes two groups of differential signal input pins, two groups of first differential signal output pins and two groups of second differential signal output pins;

[0025] The differential signal input pin constitutes the signal input end of the switch, the first differential signal output pin constitutes the first signal output end of the switch, and the second differential signal output pin constitutes the second signal output end of the switch.

[0026] Optionally, the signal input port and the signal output port are Ethernet interfaces.

[0027] A third aspect of the embodiments of the present application provides a differential signal testing device, including the differential signal testing circuit described above.

[0028] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: the above-mentioned differential signal testing method controls the n-stage cascade switching switch group to power on and obtain the differential signal to be tested, and during the test, outputs a switching control signal to each switching switch to switch the communication channel and / or communication rate of the differential signal. At the same time, the communication state of the differential signal is determined according to the output signal of each output end of the switching switch group, thereby realizing the switching of the communication channel of the differential signal, performing external stress testing on the differential signals of different communication channels in turn, and determining the design defects of the differential signal, and adjusting the channel later to improve the stability of the signal, and improving the test efficiency by automatically switching the communication channel of the differential signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1A circuit diagram of a differential signal test circuit provided in an embodiment of the present application;

[0030] Figure 2 A schematic diagram of a flow chart of a differential signal testing method provided in an embodiment of the present application;

[0031] Figure 3 for Figure 2 A schematic flow chart of step S30 in the provided differential signal testing method;

[0032] Figure 4 A first structural diagram of a differential signal test circuit provided in an embodiment of the present application;

[0033] Figure 5 A second structural diagram of a differential signal test circuit provided in an embodiment of the present application;

[0034] Figure 6 A circuit diagram of a switching chip provided in an embodiment of the present application;

[0035] Figure 7 A schematic diagram of the structure of the Ethernet interface provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0038] The first aspect of the embodiment of the present application proposes a differential signal testing method, which simulates the plugging and unplugging of the high-speed interface by controlling the communication channel of the switching switch 11 of the switching switch group to implement external stress testing of the differential signal and improve the stability of the signal.

[0039] The switch group includes n groups, and each level of switch group includes y n There are switching switches 11 connected in parallel, each switching switch 11 includes a signal input terminal and y signal output terminals, the signal input terminal of each switching switch 11 is connected to a signal output terminal of at least one different switching switch 11 of the previous stage, n is a positive integer, y≥2.

[0040] For example, Figure 1 As shown, when y=2 and n=2, the switching switch group of the first stage includes 2 switching switches 11, and the switching switch group of the second stage includes 4 switching switches 11. The switching switch 11 includes two signal output terminals. At the same time, the two switching switches 11 of the latter stage are respectively connected to the two signal output terminals of the switching switch 11 of the previous stage. For example, the first switching switch 11 and the second switching switch 11 of the switching switch group of the second stage are respectively connected one-to-one with the two signal output terminals of the first switching switch 11 of the switching switch group of the first stage, thereby forming a cascade switching switch group in which the number of switching switches 11 increases exponentially. The switching switch 11 includes three working states, wherein - indicates not working, 0 indicates connecting the signal input terminal and the first signal output terminal, and 1 indicates connecting the signal input terminal and the second signal output terminal. Based on the switching mode of the switching switch 11, the number of communication channels of the communication device can also be switched, thereby switching the rate of the differential signal of the communication device.

[0041] In order to implement the stress test of the differential signal, the state of the differential signal is determined, such as Figure 2 As shown, the test methods for differential signals include:

[0042] Step S10: Control the n-stage cascade switch group to power on and obtain the differential signal to be tested.

[0043] Among them, the switching switch group is connected to the communication device to be tested directly or indirectly, and the communication device is used to output the differential signal to be tested. After the switching switch group is powered on by controlling the switching switch group, the differential signal to be tested is input to the switching switch group, and the corresponding output is selected by the switching switch group.

[0044] Step S20 : ​​Output a switching control signal to each switch 11 to switch the communication channel and / or communication rate of the differential signal.

[0045] The controller 12 selects the truth table data in the memory according to the control instruction, and triggers the output of a matching switching control signal to the corresponding switch 11, thereby switching the communication channel and / or communication rate of the differential signal.

[0046] For example, Figure 1As shown in Table 1, assuming m=2, n=2, including four differential signal pairs, which are respectively split into two groups of two switches 11 input to the first-stage switch group. Each switch 11 inputs high-speed differential signals of two differential signal pairs. In the table, 1-1 represents the first switch 11 of the first-stage switch group, 2-1 represents the first switch 11 of the second-stage switch group, 2-2 represents the second switch 11 of the second-stage switch group, 1-2 represents the second switch 11 of the first-stage switch group, 2-3 represents the third switch 11 of the second-stage switch group, and 2-4 represents the fourth switch 11 of the second-stage switch group.

[0047] The controller 12 controls the working state of each switching switch 11 according to the truth table data, thereby switching the communication channel of the differential signal. For example, when the truth table of 1-1 is 0 and the truth table of 2-1 is 0, and the truth table of other switching switches 11 is -, the two pairs of differential signals are output through the signal input end and the first signal output end of the first switching switch 11 of the first-level switching switch group and through the signal input end and the first signal output end of the first switching switch 11 of the second-level switching switch group, and the first signal output end of the first switching switch 11 of the second-level switching switch group includes 2 groups of first differential signal output pins, that is, includes 4 cores, where the core represents the number of channels of the differential signal. At this time, the differential signal is output at a communication rate of 4 cores.

[0048] Alternatively, when the truth table of 1-1 is 0, the truth table of 2-1 is 1, and the truth table of other switching switches 11 is -, the differential signal is output through the signal input end and the first signal output end of the first switching switch 11 of the first-level switching switch group and through the signal input end and the second signal output end of the first switching switch 11 of the second-level switching switch group, and the second signal output end of the first switching switch 11 of the second-level switching switch group includes 2 groups of second differential signal output pins, that is, includes 4 cores. At this time, the differential signal is also output at a 4-core communication rate, but the communication channel of the differential signal is switched from one signal output end of the first switching switch 11 of the second-level switching switch group to another signal output end, thereby realizing the switching of the communication channel.

[0049] Alternatively, when the truth table of 1-1 is 0, the truth table of 2-1 is 0, the truth table of 1-2 is 0, and the truth table of 2-3 is 0, and the truth table of the other switches 11 is -, then two pairs of differential signals are output through the signal input terminal and the first signal output terminal of the first switch 11 of the first-stage switch group and through the signal input terminal and the first signal output terminal of the first switch 11 of the second-stage switch group. At the same time, the other two pairs of differential signals are output through the signal input terminal and the first signal output terminal of the second switch 11 of the first-stage switch group. And output through the signal input end and the first signal output end of the third switching switch 11 of the second-level switching switch group. At this time, the first signal output end of the first switching switch 11 of the second-level switching switch group includes 2 groups of first differential signal output pins, that is, it includes 4 cores, and the first signal output end of the third switching switch 11 of the second-level switching switch group includes 2 groups of first differential signal output pins, that is, it includes 4 cores. The 4 pairs of differential signals are transmitted at an 8-core communication rate, which doubles the communication rate compared to the 4-core communication connection, thereby realizing the switching of the communication rate.

[0050] Other switching methods can be deduced in sequence according to the truth table data and will not be described in detail here.

[0051] 1-1 2-1 2-2 1-2 2-3 2-4 Functional Description 0 0 -- -- -- -- OUT1 output, 4 cores 0 1 -- -- -- -- OUT2 output, 4 cores 1 -- 0 -- -- -- OUT3 output, 4 cores 1 -- 1 -- -- -- OUT4 output, 4 cores 0 0 -- 0 0 -- OUT1 output, 8 cores 0 1 -- 0 1 -- OUT2 output, 8-core 1 -- 0 1 -- 0 OUT3 output, 8 cores 1 -- 1 1 -- 1 OUT4 output, 8 cores

[0052] Table 1

[0053] Step S30: determining the communication state of the differential signal according to the output signals of the output terminals of the switching switch group.

[0054] After each switch, the corresponding output signal is obtained, and the output signal is tested and judged by parameters to determine whether the output differential signal meets the communication requirements. The differential signal of each channel is subjected to external stress testing in turn to expose the hidden defects of the differential signal, and corresponding signal adjustments are made to improve the stability of the signal.

[0055] In this embodiment, the test method based on differential signals and the switch group can simulate the plugging and unplugging of high-speed signals. For example, after the differential signal is input, the signal is output from one of the signal output terminals of one of the switches 11 through the configuration of the truth table data to achieve normal communication. At this time, the truth table data is adjusted to forcibly disconnect the differential signal, and the signal is switched to another signal output terminal of the same switch 11 or to a signal output terminal of another switch 11, and so on. This is equivalent to simulating external interference to forcibly disconnect normal communication, and performing external stress tests on the differential signal in turn. This can be repeated many times to expose hidden design defects and improve signal stability. Compared with relying on human or mechanical plugging and unplugging, the test efficiency is greatly improved.

[0056] Alternatively, as Figure 3 As shown, step S30 specifically includes:

[0057] Step S31, obtaining a differential signal outputted by each switching of the n-stage cascaded switch group;

[0058] Step S32: Compare the parameters of the differential signal outputted at each switching with the preset threshold parameters, and determine the communication state of the differential signal according to the comparison result.

[0059] In this embodiment, after each channel switching, the controller 12 obtains the differential signal of the corresponding path through the corresponding sampling signal, detects and judges the parameters of the differential signal, and compares it with the preset threshold parameters. When the corresponding parameter is outside the preset threshold parameters, it indicates that the current differential signal is abnormal and needs to be adjusted. When the corresponding parameter is within the preset threshold parameters, it indicates that the differential signal after switching is normal. The differential signal is normal, thereby judging the communication status of the differential signal of each communication channel after switching.

[0060] According to the type of the differential signal, the parameters for determining its performance may be selected accordingly as required. Optionally, the parameters of the differential signal include at least bandwidth, attenuation ratio, amplitude, and rate.

[0061] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0062] Compared with the prior art, the beneficial effects of the embodiments of the present application are as follows: the above-mentioned differential signal testing method controls the n-stage cascade switching switch group to power on and obtain the differential signal to be tested, and during the test, outputs a switching control signal to each switching switch 11 to switch the communication channel and / or communication rate of the differential signal. At the same time, the communication state of the differential signal is determined according to the output signal of each output end of the switching switch group, thereby realizing the switching of the communication channel of the differential signal, performing external stress testing on the differential signals of different communication channels in turn, and determining the design defects of the differential signal, and adjusting the channel later to improve the stability of the signal, and improving the test efficiency by automatically switching the communication channel of the differential signal.

[0063] A second aspect of the present application provides a differential signal testing circuit 10, comprising an n-stage cascaded switch group and a controller 12. The controller 12 comprises a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the differential signal testing method described above are implemented.

[0064] Among them, each level of the switch group includes y nThere are switching switches 11 connected in parallel, each switching switch 11 includes a signal input terminal and y signal output terminals, the signal input terminal of each switching switch 11 is connected to a signal output terminal of at least one different switching switch 11 of the previous stage, n is a positive integer, y≥2.

[0065] In this embodiment, the switch group includes n groups, and each level of switch group includes y n There are switching switches 11 connected in parallel, each switching switch 11 includes a signal input terminal and y signal output terminals, the signal input terminal of each switching switch 11 is connected to a signal output terminal of at least one different switching switch 11 of the previous stage, n is a positive integer, y≥2.

[0066] For example, Figure 1 As shown, when y=2 and n=2, the switching switch group of the first stage includes 2 switching switches 11, and the switching switch group of the second stage includes 4 switching switches 11. The switching switch 11 includes two signal output terminals. At the same time, the two switching switches 11 of the latter stage are respectively connected to the two signal output terminals of the switching switch 11 of the previous stage. For example, the first switching switch 11 and the second switching switch 11 of the switching switch group of the second stage are respectively connected one-to-one with the two signal output terminals of the first switching switch 11 of the switching switch group of the first stage, thereby forming a cascade switching switch group in which the number of switching switches 11 increases exponentially. The switching switch 11 includes three working states, wherein - indicates not working, 0 indicates connecting the signal input terminal and the first signal output terminal, and 1 indicates connecting the signal input terminal and the second signal output terminal. Based on the switching mode of the switching switch 11, the number of communication channels of the communication device can also be switched, thereby switching the rate of the differential signal of the communication device.

[0067] Among them, the switching switch group is connected to the communication device to be tested directly or indirectly, and the communication device is used to output the differential signal to be tested. After the switching switch group is powered on by controlling the switching switch group, the differential signal to be tested is input to the switching switch group, and the corresponding output is selected by the switching switch group.

[0068] The controller 12 selects the truth table data in the memory according to the control instruction, and triggers the output of a matching switching control signal to the corresponding switch 11, thereby switching the communication channel and / or communication rate of the differential signal.

[0069] For example, Figure 1As shown in Table 1, assuming m=2, n=2, including four differential signal pairs, which are respectively split into two groups of two switches 11 input to the first-stage switch group. Each switch 11 inputs high-speed differential signals of two differential signal pairs. In the table, 1-1 represents the first switch 11 of the first-stage switch group, 2-1 represents the first switch 11 of the second-stage switch group, 2-2 represents the second switch 11 of the second-stage switch group, 1-2 represents the second switch 11 of the first-stage switch group, 2-3 represents the third switch 11 of the second-stage switch group, and 2-4 represents the fourth switch 11 of the second-stage switch group.

[0070] The controller 12 controls the working state of each switching switch 11 according to the truth table data, thereby switching the communication channel of the differential signal. For example, when the truth table of 1-1 is 0 and the truth table of 2-1 is 0, and the truth table of other switching switches 11 is -, the two pairs of differential signals are output through the signal input end and the first signal output end of the first switching switch 11 of the first-level switching switch group and through the signal input end and the first signal output end of the first switching switch 11 of the second-level switching switch group, and the first signal output end of the first switching switch 11 of the second-level switching switch group includes 2 groups of first differential signal output pins, that is, includes 4 cores, where the core represents the number of channels of the differential signal. At this time, the differential signal is output at a communication rate of 4 cores.

[0071] Alternatively, when the truth table of 1-1 is 0, the truth table of 2-1 is 1, and the truth table of other switching switches 11 is -, the differential signal is output through the signal input end and the first signal output end of the first switching switch 11 of the first-level switching switch group and through the signal input end and the second signal output end of the first switching switch 11 of the second-level switching switch group, and the second signal output end of the first switching switch 11 of the second-level switching switch group includes 2 groups of second differential signal output pins, that is, includes 4 cores. At this time, the differential signal is also output at a 4-core communication rate, but the communication channel of the differential signal is switched from one signal output end of the first switching switch 11 of the second-level switching switch group to another signal output end, thereby realizing the switching of the communication channel.

[0072] Alternatively, when the truth table of 1-1 is 0, the truth table of 2-1 is 0, the truth table of 1-2 is 0, and the truth table of 2-3 is 0, and the truth table of the other switches 11 is -, then two pairs of differential signals are output through the signal input terminal and the first signal output terminal of the first switch 11 of the first-stage switch group and through the signal input terminal and the first signal output terminal of the first switch 11 of the second-stage switch group. At the same time, the other two pairs of differential signals are output through the signal input terminal and the first signal output terminal of the second switch 11 of the first-stage switch group. And output through the signal input end and the first signal output end of the third switching switch 11 of the second-level switching switch group. At this time, the first signal output end of the first switching switch 11 of the second-level switching switch group includes 2 groups of first differential signal output pins, that is, it includes 4 cores, and the first signal output end of the third switching switch 11 of the second-level switching switch group includes 2 groups of first differential signal output pins, that is, it includes 4 cores. The 4 pairs of differential signals are transmitted at an 8-core communication rate, which doubles the communication rate compared to the 4-core communication connection, thereby realizing the switching of the communication rate.

[0073] Other switching methods can be deduced in sequence according to the truth table data and will not be described in detail here.

[0074] 1-1 2-1 2-2 1-2 2-3 2-4 Functional Description 0 0 -- -- -- -- OUT1 output, 4 cores 0 1 -- -- -- -- OUT2 output, 4 cores 1 -- 0 -- -- -- OUT3 output, 4 cores 1 -- 1 -- -- -- OUT4 output, 4 cores 0 0 -- 0 0 -- OUT1 output, 8 cores 0 1 -- 0 1 -- OUT2 output, 8-core 1 -- 0 1 -- 0 OUT3 output, 8 cores 1 -- 1 1 -- 1 OUT4 output, 8 cores

[0075] Table 1

[0076] After each switch, the controller 12 obtains the corresponding output signal after the switch, and performs parameter detection and judgment on the output signal to determine whether the output differential signal meets the communication requirements. It performs external stress testing on the differential signal of each channel in turn to expose the hidden defects of the differential signal, and performs corresponding signal adjustments to improve the stability of the signal.

[0077] In this embodiment, the controller 12 can simulate the plugging and unplugging of high-speed signals based on the differential signal testing method and the switching switch group. For example, after the differential signal is input, it is output from one of the signal output terminals of one of the switching switches 11 through the configuration of the truth table data to achieve normal communication. At this time, the truth table data is adjusted to forcibly disconnect the differential signal, and the signal is switched to another signal output terminal of the same switching switch 11 or to a signal output terminal of another switching switch 11, and so on. This is equivalent to simulating external interference to forcibly disconnect normal communication, and performing external stress tests on the differential signal in turn. This can be repeated many times to expose hidden design defects and improve signal stability. Compared with relying on human or mechanical plugging and unplugging, the test efficiency is greatly improved.

[0078] The value of y can be selected according to needs, such as 2, 3, etc. In an optional embodiment, y=2, and the control end of each switch 11 is connected to the control end of the controller 12. Each switch 11 includes a signal input end, a first signal output end, and a second signal output end.

[0079] A first signal output terminal of the i-th switch 11 of the n-th switch group is connected one-to-one with a signal input terminal of the 2i-1-th switch 11 of the n+1-th switch group, and a second signal output terminal of the i-th switch 11 of the n-th switch group is connected one-to-one with a signal input terminal of the 2i-th switch 11 of the n+1-th switch group. Each switch 11 is triggered by a switch switching signal to connect one of its own signal input terminals and a first signal input terminal, or to trigger the connection between one of its own signal input terminals and a second signal input terminal, i∈[1, 2n], where n is a positive integer;

[0080] The differential signal test circuit 10 further includes:

[0081] A signal input port IN, the signal input port IN is connected to two signal input terminals of two switches 11 of the first-stage switch group, and is configured to input 2m groups of differential signals and output m groups of differential signals to each of the cascaded switches 11;

[0082] 2 n Signal output port OUT, 2 n The signal output port OUT is connected to the first switch 11 to the second switch 2 of the n-th stage switch group. n-1 The first signal output terminal and the second signal output terminal of the switching switch 11 are connected one by one in sequence, and n The signal output port OUT is connected to the second n-1 +1 Switch 11 to 2 n The first signal output terminals and the second signal output terminals of the switches 11 are connected one by one in sequence.

[0083] In this embodiment, the signal input port IN is connected to the communication device to be tested, and multiple signal output ports OUT are respectively connected to the controller 12. The first communication device is connected to different signal output ports OUT by switching the switching switch group, thereby switching the communication channel of the differential signal and switching the communication rate.

[0084] Among them, the signal input port IN splits the input 2m high-speed differential signals into two groups, each of which includes 2 nThe first-stage switch group includes two switches 11, the second-stage switch group includes four switches 11, the third-stage switch group includes eight switches 11, and so on.

[0085] At the same time, the two switches 11 of the first-stage switch group are connected in parallel to the signal input port IN. The first switch 11 and the second switch 11 of the first-stage switch group respectively input m groups of high-speed differential signals.

[0086] The switching switch group of the latter stage is connected to the first signal output end and the second signal output end of the switching switch group of the former stage in sequence. For example, the signal input end of the first switching switch 11 of the switching switch group of the second stage is connected to the first signal output end of the first switching switch 11 of the switching switch group of the first stage, the signal input end of the second switching switch 11 of the switching switch group of the second stage is connected to the second signal output end of the first switching switch 11 of the switching switch group of the first stage, the signal input end of the third switching switch 11 of the switching switch group of the second stage is connected to the first signal output end of the second switching switch 11 of the switching switch group of the first stage, and the signal input end of the fourth switching switch 11 of the switching switch group of the second stage is connected to the second signal output end of the second switching switch 11 of the switching switch group of the first stage. When n=3, the first switching switch 11 of the switching switch group of the third stage is connected to the first signal output end of the first switching switch 11 of the switching switch group of the second stage, and the signal input end of the second switching switch 11 of the switching switch group of the third stage is connected to the first signal output end of the first switching switch 11 of the switching switch group of the second stage The signal input end of the third switch 11 of the third-level switch group is connected to the first signal output end of the second switch 11 of the second-level switch group, the signal input end of the fourth switch 11 of the third-level switch group is connected to the second signal output end of the second switch 11 of the second-level switch group, the fifth switch 11 of the third-level switch group is connected to the first signal output end of the third switch 11 of the second-level switch group, the signal input end of the sixth switch 11 of the third-level switch group is connected to the second signal output end of the third switch 11 of the second-level switch group, the signal input end of the seventh switch 11 of the third-level switch group is connected to the first signal output end of the fourth switch 11 of the second-level switch group, the signal input end of the eighth switch 11 of the third-level switch group is connected to the second signal output end of the fourth switch 11 of the second-level switch group, and so on.

[0087] At the same time, 2 n The signal output port OUT is connected to the same type of signal output terminals of two switches 11 at the same time, such as Figure 1As shown, assuming that n=2, the signal output ports OUT include 4, the first signal output port OUT1 is respectively connected to the first signal output end of the first switch 11 of the second-stage switch group and the first signal output end of the third switch 11 of the second-stage switch group, the second signal output port OUT2 is respectively connected to the second signal output end of the first switch 11 of the second-stage switch group and the second signal output end of the third switch 11 of the second-stage switch group, the third signal output port OUT3 is respectively connected to the first signal output end of the second switch 11 of the second-stage switch group and the first signal output end of the fourth switch 11 of the second-stage switch group, and the fourth signal output port OUT4 is respectively connected to the second signal output end of the second switch 11 of the second-stage switch group and the second signal output end of the fourth switch 11 of the second-stage switch group.

[0088] The controller 12 selects the truth table data in the memory according to the control instruction, and triggers the output of the matching switching control signal to the corresponding switching switch 11, thereby switching the communication channel and / or communication rate of the differential signal, and performing external stress testing on the differential signals of different communication channels in turn, and determining the design defects of the differential signal, and adjusting the channel later to improve the stability of the signal, and improve the test efficiency by automatically switching the communication channel of the differential signal.

[0089] Among them, in order to facilitate the connection of network communication equipment and controller 12, the signal input port IN and the signal output port OUT can select corresponding interface structures, such as Ethernet interface, USB interface, etc., optionally, in order to facilitate plugging and improving the application scenario of network communication, such as Figure 7 As shown, the signal input port IN and the signal output port OUT are Ethernet interfaces, corresponding to the channel number selection of the Ethernet interface. Optionally, m=2, and the signal input end, the first signal output end, and the second signal output end of each switch 11 include two sets of differential signal ends.

[0090] That is, signal input port IN splits the input differential signal into two groups before it passes through the first-stage switch 11: 1, 2, 3, and 6 form one group, and 4, 5, 7, and 8 form another group. 1, 2, 3, and 6 correspond to differential signals MDIA+, MDIA-, MDIB+, and MDIB-, respectively. These differential signals are input to the first-stage switch 11. When the truth value of 1-1 = 0, MDIA+, MDIA-, MDIB+, and MDIB- are switched through the first-stage switch 11 to MDIA0+, MDIA0-, MDIB0+, and MDIB0-, which are then output and serve as inputs to the first switch 11 of the second-stage switch group. When the truth value of 1-1 = 1, MDIA+, MDIA-, MDIB+, and MDIB- are switched through the first-stage switch 11 to MDIA1+, MDIA1-, MDIB1+, and MDIB1-, which are then output and serve as inputs to the second switch 11 of the second-stage switch group.

[0091] The switch 11 may be composed of a plurality of switches or a switch chip U1 structure. Optionally, the switch 11 includes the switch chip U1.

[0092] The switching chip U1 includes two groups of differential signal input pins, two groups of first differential signal output pins and two groups of second differential signal output pins;

[0093] The differential signal input pin constitutes a signal input end of the switch 11 , the first differential signal output pin constitutes a first signal output end of the switch 11 , and the second differential signal output pin constitutes a second signal output end of the switch 11 .

[0094] The switching chip U1 integrates multiple switching channels, which switch the corresponding differential signal input pins and differential signal output pins according to the received switching control signal, thereby realizing the switching of communication channels and switching of different communication rates.

[0095] The model of the switch chip U1 can be selected according to the requirements. Optionally, in order to match the Ethernet interface type, such as Figure 6 As shown, optionally, the model of the switching chip U1 is VL163.

[0096] Among them, the differential signal can be expanded to other high-speed differential signals, such as HDMI, MIPI, etc.

[0097] Furthermore, in order to ensure that the differential signal test circuit 10 is powered on and works normally, Figure 4 As shown, optionally, the differential signal test circuit 10 further includes a first power conversion circuit 13 and a second power conversion circuit 14;

[0098] The power input terminal of the first power conversion circuit 13 is configured to input a first DC power supply, the power output terminal of the first power conversion circuit 13 is respectively connected to the power input terminal of the second power conversion circuit 14 and the power terminals of each switch 11, and the output terminal of the second power conversion circuit 14 is connected to the power terminal of the controller 12;

[0099] The first power conversion circuit 13 is configured to convert the first DC power into a DC power and output a second DC power;

[0100] The second power conversion circuit 14 is configured to perform DC conversion on the second DC power and output a third DC power.

[0101] In this embodiment, the first power conversion circuit 13 receives a first DC power supply, which can be provided to an external device or to a previous adapter circuit. The first power conversion circuit 13 performs step-up and step-down conversion, and outputs a second DC power supply with a corresponding voltage to the switching switch 11 and the second power conversion circuit 14, thereby providing a working power supply for the switching switch 11. At the same time, the second power conversion circuit 14 performs step-up and step-down conversion on the second DC power supply, and outputs a third DC power supply with a corresponding voltage to the controller 12, thereby providing a working power supply for the controller 12. After the switching switch 11 and the controller 12 are powered on, the controller 12 outputs a corresponding switching control signal according to the received control instruction and in combination with its own truth table data, thereby switching the corresponding communication channel and / or realizing switching of the corresponding communication rate.

[0102] The first power conversion circuit 13 and the second power conversion circuit 14 can adopt corresponding DC / DC converters, such as Figure 5 As shown, optionally, the first power conversion circuit 13 includes a first voltage regulator 131 and a voltage divider circuit 132;

[0103] The power input terminal of the first voltage regulator 131 constitutes the power input terminal of the first power conversion circuit 13.

[0104] The power output terminal of the first voltage regulator 131 is connected to the power input terminal of the voltage divider circuit 132 and the power input terminal of the second power conversion circuit 14 respectively. The power output terminal of the voltage divider circuit 132 is connected to the power terminal of the switch 11.

[0105] Optionally, the second power conversion circuit 14 includes a second voltage regulator 141;

[0106] The power input terminal and the power output terminal of the second voltage regulator 141 constitute the power input terminal and the power output terminal of the second power conversion circuit 14 respectively.

[0107] Among them, the first voltage regulator 131 stabilizes the input first DC power supply and outputs it to achieve step-down conversion, and the output second DC power supply is input as input power to the voltage divider circuit 132 and the second voltage regulator 141. The second voltage regulator 141 and the voltage divider circuit 132 are respectively used to achieve step-down conversion and provide working voltage to the controller 12 and the switching switch 11 respectively.

[0108] The voltage divider circuit 132 may adopt a corresponding voltage divider resistor structure, such as Figure 6 As shown, optionally, the voltage divider circuit 132 includes a first voltage divider resistor and a second voltage divider resistor;

[0109] The first end of the first voltage divider resistor constitutes the power input end of the voltage divider circuit 132 , the second end of the first voltage divider resistor and the first end of the second voltage divider resistor are connected together to constitute the power output end of the voltage divider circuit 132 , and the second end of the second voltage divider resistor is grounded.

[0110] The first voltage-dividing resistor and the second voltage-dividing resistor can be Figure 6 The first resistor R1 and the second resistor R2, or the fourth resistor R4 and the fifth resistor R5, or the seventh resistor R7 and the eighth resistor R8, are specifically set according to the number and type of power pins of the switching chip U1.

[0111] A second aspect of an embodiment of the present application provides a differential signal testing device, including the differential signal testing circuit 10 as described above.

[0112] The present application also proposes a differential signal testing device, which includes a differential signal testing circuit 10. The specific structure of the differential signal testing circuit 10 refers to the above-mentioned embodiment. Since the differential signal testing device adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be described one by one here.

[0113] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A differential signal testing method, characterized in that: include: Control the n-stage cascade switch group to power on and obtain the differential signal to be tested, wherein each stage of the switch group includes y n switches connected in parallel, each of the switches comprising a signal input terminal and y signal output terminals, the signal input terminal of each switch being connected to a signal output terminal of at least one different switch of the preceding stage, where n is a positive integer and y ≥ 2; Outputting a switching control signal to each of the switching switches to switch the communication channel and / or communication rate of the differential signal; Determining the communication state of the differential signal according to the output signals of each output end of the switching switch group; The step of determining the communication state of the differential signal according to the output signals of each output terminal of the switching switch group specifically includes: Obtain the differential signal output by each switching of the n-stage cascade switch group; The parameters of the differential signal outputted at each switching are compared with the preset threshold parameters, and the communication state of the differential signal is determined according to the comparison result.

2. The differential signal testing method according to claim 1, wherein: The parameters of the differential signal include at least bandwidth, attenuation ratio, amplitude and rate.

3. A differential signal test circuit, characterized in that: A method for testing a differential signal comprising an n-stage cascaded switching switch group and a controller, wherein the controller comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the differential signal testing method according to any one of claims 1 to 2 when executing the computer program; Among them, each level of the switch group includes y n Switches are connected in parallel, each of the switches comprises a signal input terminal and y signal output terminals, the signal input terminal of each switch is connected to a signal output terminal of at least one different switch of the previous stage, n is a positive integer, y≥2.

4. The differential signal testing circuit according to claim 3, wherein: The memory stores truth table data; The processor is configured to read the truth table data and output a matching switching control signal to each of the switching switches to switch the communication channel and / or communication rate of the differential signal.

5. The differential signal testing circuit according to claim 3, wherein: y=2, the control end of each switch is connected to the control end of the controller, and each switch includes a signal input end, a first signal output end, and a second signal output end; A first signal output terminal of the i-th switch of the n-th switch group is connected one-to-one with a signal input terminal of the 2i-1-th switch of the n+1-th switch group, and a second signal output terminal of the i-th switch of the n-th switch group is connected one-to-one with a signal input terminal of the 2i-th switch of the n+1-th switch group. Each of the switches is triggered by a switch switching signal to connect one of its own signal input terminals and a first signal input terminal, or to trigger the connection between one of its own signal input terminals and a second signal input terminal, i∈[1, 2n], where n is a positive integer; The differential signal test circuit further includes: a signal input port, the signal input port being connected to the two signal input ends of the two switches of the switch group of the first stage, respectively, and being configured to input 2m groups of differential signals and output m groups of differential signals to each of the cascaded switches; 2 n Signal output ports, 2 n The signal output port and the first to second switching switches of the switching switch group of the nth level n-1 The first signal output terminal and the second signal output terminal of the switching switch are connected one by one in sequence, and n The signal output port is connected to the second of the switch group of the nth level. n-1 +1 for switching the switch to 2 n The first signal output terminals and the second signal output terminals of the switches are connected one by one in sequence.

6. The differential signal testing circuit according to claim 5, wherein: m=2, and the signal input end, the first signal output end, and the second signal output end of each switch include two groups of differential signal ends.

7. The differential signal testing circuit according to claim 6, wherein: The switching switch includes a switching chip; The switching chip includes two groups of differential signal input pins, two groups of first differential signal output pins and two groups of second differential signal output pins; The differential signal input pin constitutes the signal input end of the switch, the first differential signal output pin constitutes the first signal output end of the switch, and the second differential signal output pin constitutes the second signal output end of the switch.

8. The differential signal testing circuit according to claim 3, wherein: The signal input port and the signal output port are Ethernet interfaces.

9. A differential signal testing device, characterized in that: A test circuit comprising a differential signal as claimed in any one of claims 3 to 8.

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