Receiver miniaturized quantum key generation terminal

Abstract

The application provides a kind of receiver miniaturization quantum key generation terminal, including case (1), main control board (2), detector module (3), decoding light path (4), power (5) and fan (6), main control board (2) and decoding light path (4) left and right side by side setting, and the front end of main control board (2) and decoding light path (4) is in the inside of the front panel of case (1), detector module (3) is set up with decoding light path (4) front and back side by side, and the left end of detector module (3) and decoding light path (4) are all close to the right end of main control board (2);Power (5) is set in the rear of case (1), and blowing fan (6) is set in the side close to detector module (3).The application has the advantages that: on the premise of guaranteeing communication reliability, the miniaturization of receiver quantum key generation terminal is realized, and the heat design and force design meet the equipment use requirements through thermal simulation and force simulation test.

Description

Technical Field

[0001] This invention relates to the field of quantum communication technology, and in particular to a receiver quantum key generation terminal. Background Technology

[0002] With the rapid development of quantum communication technology, quantum key distribution (QKD) has gradually become a mature application technology. Based on the no-cloning principle and uncertainty principle of quantum mechanics, the keys generated by this technology have theoretically unconditional security and are mainly used in applications requiring high levels of confidentiality. Existing quantum key distribution hardware (or quantum key generation equipment) mainly consists of optical transceivers and electronic boards. The optical transceivers include a light source board, optical path components, and detectors, while the electronic boards are mainly used for data processing, key generation control, and key management.

[0003] When using quantum key distribution hardware, since the components in the electronic board and optical transceiver are all independently hashed devices, it is necessary to connect the multiple signal input / output interfaces of the electronic board to the corresponding interfaces of the light source board, optical path components and detectors of the optical transceiver to form a quantum key distribution system, and then put the assembled quantum key distribution system into practical application.

[0004] Those skilled in the art, when using the above-mentioned quantum key distribution hardware device, have discovered the following drawbacks:

[0005] Because the electronic boards, light source boards, optical path components, and detectors that make up a quantum key distribution system are scattered, the testing, maintenance, and management of the entire system are relatively dispersed and difficult to manage as a whole. Furthermore, when multiple quantum key distribution systems are used to form a quantum key distribution network, the networking between the quantum key distribution systems is complex, making management and maintenance even more difficult.

[0006] At present, with the gradual maturation of technology and products, my country's quantum communication industry has entered the promotion period of product application. However, compared with the widely used traditional cryptographic products, quantum secure communication metropolitan area network access equipment still has problems such as large product size, high cost, low reliability, inconvenient installation and debugging, and poor adaptability to application scenarios. The market expects to launch more economical, highly reliable, miniaturized, modular, easy-to-use, and flexibly expandable application scenarios (such as meeting the needs of networking, channel resources, environmental adaptability, and third-party integration) terminal QKD products to better meet the business access needs of metropolitan area users.

[0007] Patent application No. 201310464744.4 discloses a quantum key distribution terminal and system, which organically integrates the optical transceiver and electronic board in the quantum key distribution system into a whole through an electronic backplane. This provides a compact and highly integrated quantum key distribution terminal, enabling unified testing, maintenance, and management of all components in the quantum key distribution system. It achieves the integration and terminalization of the key distribution system and allows for flexible networking using the same quantum key distribution terminal to build point-to-point, local area network, or metropolitan area network-scale quantum key distribution systems. However, it does not yet meet the current miniaturization requirements.

[0008] Patent application No. 202022891432.X discloses a receiver chassis, which includes a two-layer housing, a front panel, and a bottom panel. The upper layer of the housing is a device mounting area, and the lower layer is a ventilation and heat dissipation area. The device mounting area can be used to mount various components of the receiver board, such as decoding, detection, and data processing components, allowing for compact assembly of these components. Additionally, a detector mounting slot is provided in the device mounting area, which is a through slot communicating with the ventilation and heat dissipation area. The heat dissipation end of the detector component is located within the ventilation and heat dissipation area, providing excellent heat dissipation and solving the problem of a large chassis size. Furthermore, the location of the heat dissipation end of the detector component within the ventilation and heat dissipation area prevents heat from dissipating to other components, thus avoiding changes to the operating environment of other components and ensuring stable operation of the receiver board assembly.

[0009] Patent application No. 202022891433.4 discloses a receiver device for quantum communication. The upper layer of the chassis is the equipment mounting area, and the lower layer is the ventilation and heat dissipation area. The self-calibration device, the electrical control device, and the optical module components are fixed in the equipment mounting area from top to bottom. By utilizing the layered design of the chassis, the ventilation and heat dissipation area is located in the lower area of ​​the chassis. It can achieve excellent heat dissipation without the need for additional heat pipe devices, and avoids the heat dissipation of the detector component's heat dissipation end to the optical and electrical components, ensuring the operating environment of the optical and electrical components and enabling stable operation of the optical and electrical components. Therefore, the receiver device of this application has the characteristics of good heat dissipation and compact structure and small size.

[0010] Both of the aforementioned patent documents describe a two-tiered design within the enclosure, with the upper tier for equipment installation and the lower tier for ventilation and heat dissipation. While this structure achieves the goal of placing the ventilation and heat dissipation area in the lower part of the enclosure, thus eliminating the need for additional heat pipes and providing excellent heat dissipation, its two-tiered design still falls short of current miniaturization requirements. This arrangement occupies a significant amount of cabinet space in terms of height, and the modules remain relatively dispersed, resulting in weak shock resistance.

[0011] Currently, in publicly available quantum secure communication technology solutions, the quantum key generation device, quantum key management device, and data encryption / decryption device are usually three independent devices. A single quantum secure communication system requires an entire cabinet, resulting in problems such as large equipment size, high cost, large installation workload, and inconvenient construction and debugging, which restricts the promotion and use of quantum secure communication systems. Summary of the Invention

[0012] The technical problem to be solved by this invention is to achieve miniaturization and good shock resistance of the receiver's quantum key generation terminal while ensuring communication reliability.

[0013] The present invention solves the above-mentioned technical problems through the following technical means: a miniaturized quantum key generation terminal for receivers, including a chassis (1), a main control board (2), a detector module (3), a decoding optical path (4), a power supply (5) and a fan (6). The main control board (2) and the decoding optical path (4) are arranged side by side, and the front ends of the main control board (2) and the decoding optical path (4) are pressed against the inside of the front panel of the chassis (1). The detector module (3) and the decoding optical path (4) are arranged side by side, and the left ends of the detector module (3) and the decoding optical path (4) are close to the right end of the main control board (2).

[0014] The power supply (5) is located at the rear of the chassis (1), and the blower fan (6) is located on the side near the detector module (3).

[0015] As an optimized technical solution, the power supply (5) includes two power supplies, AC and DC. The two power supplies (5) are arranged side by side at the rear of the chassis (1), behind the detector module (3), and the rear of the main control board (2) is left empty for wiring.

[0016] Alternatively, the power supply (5) includes two power supplies, AC and DC, which are arranged side by side at the rear of the chassis (1), behind the main control board (2) and the detector module (3), respectively.

[0017] As a technical solution, the main control board (2) includes one CPU or one FPGA, or one FPGA and one CPU, or multiple CPUs and / or multiple FPGAs. When there are multiple CPUs and / or multiple FPGAs, the multiple CPUs and multiple FPGAs are spatially staggered.

[0018] Specifically, the main control board (2) includes two FPGAs (22) and two CPUs (24). The two CPUs (24) are arranged in front with a left-right gap, and the two FPGAs (22) are arranged in the rear with a front-back gap. The foremost FPGA (22) is also located behind the CPU (24). From the main viewpoint, the two FPGAs (22) are located between the two CPUs (24) in the left-right direction.

[0019] Alternatively, the main control board (2) includes two FPGAs (22) and two CPUs (24). The two CPUs (24) are arranged in front with a left-right gap, and the two FPGAs (22) are arranged in the rear with a left-right gap. From the main viewpoint, the two FPGAs (22) are located behind the two CPUs (24), and the FPGAs (22) and CPUs (24) are staggered in front and behind.

[0020] As a technical solution, heat sinks are provided on the surface of the FPGA (22) and the CPU (24).

[0021] As a technical solution, the detector module (3) includes a heat sink (31), a PCB board (32), an integrated cooling APD, a shielding cover (33), and an optical fiber tray (34). The heat sink (31) serves as the main support. The PCB board (32) and the integrated cooling APD are both fixed on the heat sink (31). The integrated cooling APD is located inside the shielding cover (33). The shielding cover (33) is fixed on the PCB board (32) to shield the radio frequency circuit on the PCB board (32). The optical fiber tray (34) is fixed on the shielding cover (33).

[0022] As a technical solution, the chassis (1) is equipped with three fans (6) on both the left and right sides. The left fan is an intake fan and the right fan is a blower fan. The fans on the left and right sides are arranged in a front-to-back sequence along the inner edge of the side panel of the chassis (1).

[0023] Alternatively, the chassis (1) may have four blower fans (6) on the side near the detector module (3), while no fans are provided on the opposite side.

[0024] The advantages of this invention are:

[0025] Through optimized structural design, the receiver quantum key generation terminal was miniaturized while ensuring communication reliability, and it also has good shock resistance, thus making it possible to further miniaturize the quantum secure communication system.

[0026] The fan is positioned on the side closest to the detector module because the detector module needs to operate at a specific temperature. In order to stabilize its operation and avoid the influence of heat conduction from other modules in the space, it needs to be placed near the fan for heat dissipation.

[0027] The FPGA and CPU on the main control board are arranged to take into account their heat dissipation effect, and are staggered as much as possible while maintaining an effective gap to leave airflow. In addition, heat sinks are provided on the surface of both the FPGA and CPU for effective heat dissipation, so that the FPGA and CPU can maintain heat exchange efficiency in the working environment.

[0028] The decoding optical path is placed at the front of the chassis, so as not to obstruct the heat dissipation of the main control board components;

[0029] The two power supplies are arranged side by side or front and back at the rear of the chassis, which allows for high utilization of chassis space.

[0030] The terminal of this invention has been optimized in design, and the size parameters of some major components have been determined, so that the device layout in the entire terminal is compact and the space inside the chassis is utilized to the greatest extent possible. Attached Figure Description

[0031] Figure 1 This is an overall internal layout diagram of the miniaturized quantum key generation terminal for the receiver according to Embodiment 1 of the present invention;

[0032] Figure 2 This is an exploded view of the receiver-side miniaturized quantum key generation terminal according to Embodiment 1 of the present invention;

[0033] Figure 3 This is an assembly diagram of the receiver-side miniaturized quantum key generation terminal according to Embodiment 1 of the present invention;

[0034] Figure 4 This is an overall internal layout diagram of the miniaturized quantum key generation terminal for the receiver according to Embodiment 2 of the present invention;

[0035] Figure 5 This is an exploded view of the receiver-side miniaturized quantum key generation terminal according to Embodiment 2 of the present invention;

[0036] Figure 6 This is an assembly diagram of the receiver-side miniaturized quantum key generation terminal according to Embodiment 2 of the present invention;

[0037] Figure 7 This is a random vibration curve from the force simulation of the miniaturized quantum key generation terminal of the receiver in this embodiment of the invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] Please see Figures 1 to 3 As shown, the miniaturized quantum key generation terminal for the receiver in this embodiment of the invention mainly includes a chassis 1, a main control board 2, a detector module 3, a decoding optical path 4, a power supply 5, and a fan 6. The end where the power supply 5 is located is defined as the rear.

[0040] The main control board 2 and the decoding optical path 4 are arranged side by side, with the front ends of the main control board 2 and the decoding optical path 4 resting against the inside of the front panel of the chassis 1. The detector module 3 and the decoding optical path 4 are arranged side by side, with the left ends of the detector module 3 and the decoding optical path 4 being close to the right end of the main control board 2.

[0041] The power supply 5 includes two power supplies, one AC and one DC. The two power supplies 5 are arranged side by side at the rear of the chassis 1, behind the detector module 3. The rear of the main control board 2 is left empty for wiring.

[0042] Fans 6 are located on both the left and right sides of the chassis 1. There are three fans 6 on each side, with three on the left and three on the right. The three fans on the left are intake fans, and the three fans on the right are exhaust fans. These three fans are arranged sequentially along the inner edge of the side panel of chassis 1, with the last fan 6 located in front of the power supply 5. Forced air cooling is used inside chassis 1, with the airflow from right to left. The three fans 5 on the right side of chassis 1 blow cool air into the chassis 1, while the three fans 6 on the left side of chassis 1 extract hot air. Because the detector module 3 needs to operate at a specific temperature, the exhaust fans 6 are placed close to the detector module 3. Therefore, when the detector module 3 and the main control board 2 are positioned relative to each other... Figure 1 When the positions are swapped, all three blowing fans 6 are placed on the left side of the chassis 1, and the three suction fans 6 are placed on the right side of the chassis 1, with the airflow from left to right.

[0043] The specific combination, setup, and layout of each part are described in detail below.

[0044] The front panel of chassis 1 is the user interface. All external function interfaces of the whole machine are placed on the front panel. The two sides of chassis 1 are ventilation holes.

[0045] The main control board 2 includes two FPGAs 22 and two CPUs 24. The main control board 2 uses FPGAs 22 and CPUs 24 as the control core to realize the control of detector module 3, the control of decoding optical path 4, and the functions of detection pulse acquisition and key extraction. According to the preliminary evaluation, each configuration item (FPGA 22 or CPU 24) and its peripheral circuit occupy a PCB space of approximately 90*90mm, and the four configuration items occupy approximately 180*180mm. In addition, considering the external power supply, connectors, device heat dissipation, safety spacing, mounting holes, and compatibility with other customized solutions, the overall size of the main control board 2 is approximately L275*W180mm.

[0046] Two CPUs 24 are positioned at the front, spaced apart, and are of the same size, aligned in a straight line. Two FPGAs 22 are positioned at the rear, spaced apart, with the frontmost FPGA 22 also located behind the CPUs 24. These FPGAs are of the same size and aligned horizontally. From the main control board 2, the two FPGAs 22 are positioned between the two CPUs 24 in the left-right direction. Both the FPGAs 22 and CPUs 24 are high-power devices, and their arrangement on the main control board 2 is primarily for heat dissipation, with staggered placement and effective gaps to allow for airflow. Furthermore, for effective heat dissipation, FPGA heatsinks 222 and CPU heatsinks 242 are installed on the surface of the FPGAs 22 and CPUs 24, respectively, ensuring efficient heat exchange in a 45℃ operating environment.

[0047] This embodiment uses two CPUs and two FPGAs as an example. In actual use, there can be only one CPU or one FPGA, or one FPGA and one CPU, or multiple CPUs and / or multiple FPGAs. Alternatively, the FPGA can be placed in front and the CPU in the back. When there are multiple CPUs and / or multiple FPGAs, it is sufficient to ensure that they are spatially staggered to prevent the heat from one device from being carried to another device by the airflow.

[0048] The detector module 3 includes a heat sink 31, a PCB board 32, an integrated cooling APD (not shown in the figure), a shielding cover 33, and an optical fiber tray 34. The heat sink 31 serves as the main supporting structure. The PCB board 32 and the integrated cooling APD are both fixed to the heat sink 31. The integrated cooling APD is located inside the shielding cover 33, which is fixed to the PCB board 32 to shield the radio frequency circuits on the PCB board 32. The optical fiber tray 34 is fixed to the shielding cover 33. The PCB board 32 integrates a synchronization light discrimination circuit, a bias voltage generation circuit, a gate signal generation circuit, an avalanche signal extraction circuit, and a TEC temperature control circuit. Considering the related supporting structural components, the overall dimensions of the detector module 3 are approximately 180*150*40mm.

[0049] The decoding optical path 4 consists of discrete optical components: beam splitter BS, polarization beam splitter PBS, electric polarization controller EPC, wavelength division multiplexer, optical isolator, and supporting structural components. Its design dimensions are approximately L150*W120mm.

[0050] In the design of the power supply 5 of the present invention, based on the dimensions of the main control board 2, detector module 3 and decoding optical path 4 of the whole machine, and combined with the power and size standards of the power supply industry, the power supply's external dimensions are allocated as 165*50.5*40.5mm.

[0051] Currently, there are two standard power supply sizes in the communications industry: 185*73*40mm and 165*50*40.5mm. For miniaturization purposes, the optimized power supply size is 165*50.5*40.5mm.

[0052] The above layout allows chassis 1 to be a standard 19-inch 1U rackmount device, with a depth of 400-480mm.

[0053] Thermal design

[0054] The thermal design employs appropriate methods to control the temperature of all components within the miniaturized quantum key generation terminal at the receiver, ensuring that they do not exceed the maximum temperature required for stable operation under the ambient temperature conditions. This guarantees the safety of its normal operation and the reliability of its long-term operation. In terms of thermal design, the heat sources and their heat dissipation are first analyzed. Then, based on this data, the heat dissipation method and airflow are designed. Finally, thermal simulation is performed to determine the optimal design scheme.

[0055] 1. Overall thermal design objectives

[0056] The overall thermal design objective should meet the requirements of equipment reliability and the thermal environment for its expected operation. The overall thermal design objective for the receiver-side miniaturized quantum key generation terminal is as follows:

[0057] The temperature difference between the air inlet and outlet of the whole unit is ≤5℃;

[0058] The temperature rise of all components shall not exceed 35°C, and the case temperature of all components shall not exceed 80°C.

[0059] 2. Heat source analysis

[0060] The heat consumption statistics of the main components are shown in Table 1 below:

[0061] Table 1. Statistics on Heat Consumption of Major Components

[0062]

[0063] The total power consumption of the heat-generating components in the receiver's miniaturized quantum key generation terminal is 81.3W.

[0064] The operating environment temperature of the receiver's miniaturized quantum key generation terminal is 0–40℃. Ignoring the influence of altitude, based on the overall design of each submodule, the internal heat-generating devices with a power output of 2W or higher are determined as shown in Table 2 below:

[0065] Table 2. Statistics on thermal power consumption of heating devices with a power consumption of over 2W in miniaturized quantum key generation terminals for receivers.

[0066] NO. Location describe Dosage unit Single-chip power consumption (W) Total power consumption 1 main control board FPGA 2 indivual 9 18 2 main control board CPU 2 indivual 5 10

[0067] 3. Heat dissipation design

[0068] Chassis thermal design requires overall consideration of chassis power consumption and temperature rise of each component, and should be combined with the overall design method, application scenario and thermal requirements to conduct overall design analysis.

[0069] 3.1 Selection of heat dissipation method

[0070] Currently, the mainstream heat dissipation methods in the market include passive heat dissipation with heat sinks, air cooling, water cooling, and liquid cooling. In addition to these mainstream methods, there are also heat pipe cooling, thermoelectric cooling, and liquid nitrogen cooling.

[0071] Air cooling is the most common and widely used heat dissipation method. As an active cooling system, it effectively addresses typical heat dissipation needs and is a mature technology. Given its suitability for the communications industry, air cooling is prioritized in the heat dissipation design of miniaturized quantum key generation terminals for the receiver. Considering the high power consumption of some components, a design combining air cooling and heat sinks is employed to improve overall heat exchange efficiency.

[0072] After confirming air cooling, the air delivery method (blowing or suction) needs to be considered. The air blown out by the fan has a chaotic internal flow, resulting in higher heat exchange efficiency with the heatsink and higher air pressure, making it suitable as the air delivery method for air-cooled heatsinks. Therefore, from the perspective of heat exchange efficiency, this design chooses the "blowing" method, with the airflow from right to left.

[0073] 3.2 Fan Selection

[0074] Based on the preceding heat source analysis, the total power consumption of the heat-generating components is 81.3W. The internal temperature rise of the chassis is designed to be 5℃, requiring the fan airflow to dissipate all the heat. According to the heat balance equation:

[0075]

[0076] In the formula: L is the cooling air volume (m³ / s). 2 / s); Q is the heat generated by the device (kW); ρ is the density of air (kg / m³). 3 );C p t is the specific heat capacity of air (kJ / (kg·℃)); t0 is the outlet temperature of the cooling air (℃); t i The inlet temperature of the cooling air (°C).

[0077] The density of air, ρ, is taken as 1.29 kg / m³. 3 The specific heat capacity of air, C p Take 1.005 kJ / (kg·℃) as the inlet temperature t of the cooling air. i Taking 40℃ as the temperature and the outlet temperature t0 of the cooling air as 45℃, substituting these values ​​into the above formula, the calculated result is 0.75m. 3 / min.

[0078] Considering airflow leakage and improving heat dissipation reliability, a reliability factor of 1.2 is chosen based on experience. Therefore, the selected fan's airflow should be greater than 0.75 * 1.2 = 0.9 m³ / s. 3 / min.

[0079] Based on experience, fans exhibit the highest efficiency and reliability in the static pressure plateau region. The fan's airflow curve indicates that this plateau region is approximately 0.3–0.4 m. 3 Between / min, take 0.35m 3 / min, the required number of fans is N = 0.9m 3 / min÷0.35m 3 / min = 2.57, therefore 3 fans are needed.

[0080] Taking into account the internal volume of the chassis and to improve the reliability of the fans, a two-redundancy design is adopted, with an N+N redundancy design. The design uses 6 fans, 3 on each side, and selects four-wire adjustable speed fans.

[0081] In terms of structural design, the maintainability of the fan assembly should be considered. During fan maintenance, each fan can be installed or removed independently after opening the top cover of the chassis.

[0082] 4. Thermal simulation

[0083] After determining the component temperature rise, airflow, fan, and heat sink, thermal simulation will be performed on the chassis. Based on the thermal resistance of key components, the internal temperature change of the chassis will be simulated to determine whether the chassis heat dissipation can meet the requirements of component temperature rise. At the same time, the thermal simulation can determine whether the fan selection and airflow design are reasonable.

[0084] The operating environment of the receiver's miniaturized quantum key generation terminal is 0–40℃, with a simulation environment temperature deviation of ±5℃. Set to 45℃, thermal simulation was performed using simulation software. The simulated temperature rise of various devices with a power output of 2W or higher is shown in Table 3 below.

[0085] Table 3. Simulation Temperature Statistics for Devices Above 2W

[0086] NO. Location describe Single-chip power consumption <![CDATA[Device junction temperature T J > <![CDATA[Simulated device case temperature T C > Simulation device junction temperature 1 main control board FPGA-1 9W 100℃ 69.12℃ 71.46℃ 2 main control board FPGA-2 9W 100℃ 70.54℃ 72.88℃ 3 main control board CPU-1 5W 125℃ 66.64℃ 70.89℃ 4 main control board CPU-2 5W 125℃ 67.86℃ 72.11℃

[0087] The simulation results show that the chassis heat dissipation can meet the temperature rise requirements of the components, and the selection of the fan and the design of the air duct are reasonable.

[0088] Force Design:

[0089] Finite element simulation software can simulate the required random vibration environment. Modal analysis and random vibration analysis were performed on the reduced chassis model to obtain the inherent characteristics and vibration response characteristics of the structure.

[0090] 1. Finite element modeling

[0091] Before performing finite element analysis, the model needs to be simplified to improve computational efficiency while ensuring model accuracy. The simplification of the finite element model follows these principles:

[0092] Key parts should not be simplified, such as those where structural failure may occur;

[0093] Remove redundant components and replace them by applying constraints;

[0094] Modify the components and replace them with simpler geometric structures;

[0095] Remove features with relatively small geometric dimensions, such as chamfers and round holes;

[0096] Based on the load and constraints, a symmetric model should be considered.

[0097] 2. Simulation Model Description

[0098] 2.1 Model Structure and Materials

[0099] Chassis 1, as a sheet metal assembly, is a typical plate shell structure. The weight of the structure is mainly concentrated in the heat sink of the chassis and detector module, the power supply, and the PCB. Other parts can be simplified in the model. The material parameters are shown in Table 4 below:

[0100] Table 4. Mechanical Properties of Materials

[0101] Part of use Material type <![CDATA[Density g / cm 3 > Elastic modulus GPa Yield strength MPa chassis Cold-rolled steel sheet - Q235 7.9 206 280 Detector heat sink Aluminum-6061 2.7 70 55.2 power supply Cold-rolled steel sheet - Q235 7.9 206 280 main control board PCB-FR4 2 20 269

[0102] 2.2 Contact Properties

[0103] The various structural components within the receiver's miniaturized quantum key generation terminal are connected by screws: the power supply, main control board, and detector module are connected to the chassis base plate by screws, and the decoding optical path is connected to the chassis base plate by screws.

[0104] 2.3 Random Vibration Analysis

[0105] The application environment for the receiver's miniaturized quantum key generation terminal is a communication equipment room environment, which must meet the relevant requirements in GB / T4857.23-2012 "Basic Tests for Packaging and Transport Packages - Part 23: Random Vibration Test Method".

[0106] The random vibration input adopts the conditions specified in the Highway Transportation Severity II chart, such as... Figure 7 As shown, random vibration along the z-axis was analyzed using simulation software to examine the stress distribution.

[0107] 3. Results of mechanical analysis

[0108] Mechanical analysis was performed on the miniaturized quantum key generation terminal for the receiver, and the stiffness and strength of the terminal structure and key components were verified based on the analysis results. The analysis showed that the structure of this invention does not yield and meets the design requirements.

[0109] Example 2

[0110] Please see Figures 4 to 6 The difference between this embodiment and Embodiment 1 lies in the arrangement of the FPGA, CPU, power supply, and fan; the remaining structures are identical. The following description focuses only on the structural differences.

[0111] Two power supplies 5' are arranged side by side at the rear of the chassis 1, one behind the detector module 3 and the other behind the main control board 2. Wiring space is left between the main control board 2, the decoding optical path 4, the detector module 3, and the side wall of the chassis 1.

[0112] The right side of chassis 1 has four fans 6', while the left side has no fans. The four fans 6' are arranged sequentially along the inner edge of the side panel of chassis 1, with the rearmost fan 6' located in front of the power supply 4. The frontmost fan 6' is roughly positioned towards the decoding optical path 4. Chassis 1 uses forced air cooling, with the airflow from right to left. The fans 6' are placed closer to the detector module 3. Therefore, when the detector module 3 and the main control board 2 are positioned relative to each other... Figure 1 When the positions of the fans are swapped, all four fans 6' will be located on the left side of the chassis 1, with the airflow from left to right.

[0113] Two CPUs 24' are positioned at the front, spaced apart, and are of the same size but staggered. Two FPGAs 22' are positioned at the rear, also of the same size but staggered. Overall, the FPGAs and CPUs are offset from each other. From the main control board 2, the two FPGAs 22' are located behind the two CPUs 24', roughly at the four corners of a parallelogram. Both the FPGAs and CPUs 24' are high-power devices, and their arrangement on the main control board 2 prioritizes heat dissipation, staggering them while maintaining effective airflow. Furthermore, heat sinks 222' and 242' are installed on the surfaces of both the FPGAs and CPUs 24', ensuring efficient heat exchange even at a 45°C operating temperature.

[0114] Similarly, this embodiment uses two CPUs and two FPGAs as an example. In actual use, there can be only one CPU or one FPGA, or one FPGA and one CPU, or multiple CPUs and / or multiple FPGAs. Alternatively, the FPGA can be placed in front and the CPU in the back. When there are multiple CPUs and / or multiple FPGAs, it is sufficient to ensure that they are spatially staggered so that the heat from one device is not carried by the airflow to another device.

[0115] In this embodiment, since the power supply 5' is placed side by side, the placement space is larger than that of the power supply in Embodiment 1. Therefore, the size of the power supply can be made slightly larger than the 165*50.5*40.5mm size in Embodiment 1, as long as it can fit into the rear of the chassis 1.

[0116] Thermal design:

[0117] The thermal design employs appropriate methods to control the temperature of all components within the miniaturized quantum key generation terminal at the receiver, ensuring that they do not exceed the maximum temperature required for stable operation under the ambient temperature conditions. This guarantees the safety of its normal operation and the reliability of its long-term operation. In terms of thermal design, the heat sources and their heat dissipation are first analyzed. Then, based on this data, the heat dissipation method and airflow are designed. Finally, thermal simulation is performed to determine the optimal design scheme.

[0118] 1. Overall thermal design objectives

[0119] The overall thermal design objective should meet the requirements of equipment reliability and the thermal environment for its expected operation. The overall thermal design objective for the receiver-side miniaturized quantum key generation terminal is as follows:

[0120] The temperature difference between the air inlet and outlet of the whole unit is ≤5℃;

[0121] The temperature rise of all components shall not exceed 35°C, and the case temperature of all components shall not exceed 80°C.

[0122] 2. Heat source analysis

[0123] The heat consumption statistics of the main components are shown in Table 5 below:

[0124] Table 5. Statistics on Heat Consumption of Major Components

[0125]

[0126] The total power consumption of the heat-generating components in the receiver's miniaturized quantum key generation terminal is 81.3W.

[0127] The operating environment temperature of the receiver's miniaturized quantum key generation terminal is 0–40℃. Ignoring the influence of altitude, based on the overall design of each submodule, the internal heat-generating devices with a power consumption of 2W or higher are determined as shown in Table 6 below:

[0128] Table 6. Statistics on the thermal power consumption of heating devices with a power consumption of over 2W in the miniaturized quantum key generation terminal of the receiver.

[0129] NO. Location describe Dosage unit Single-chip power consumption (W) Total power consumption 1 main control board FPGA 2 indivual 9 18 2 main control board CPU 2 indivual 5 10

[0130] 3. Heat dissipation design

[0131] Chassis thermal design requires overall consideration of chassis power consumption and temperature rise of each component, and should be combined with the overall design method, application scenario and thermal requirements to conduct overall design analysis.

[0132] 3.1 Selection of heat dissipation method

[0133] Currently, the mainstream heat dissipation methods in the market include passive heat dissipation with heat sinks, air cooling, water cooling, and liquid cooling. In addition to these mainstream methods, there are also heat pipe cooling, thermoelectric cooling, and liquid nitrogen cooling.

[0134] Air cooling is the most common and widely used heat dissipation method. As an active cooling system, it effectively addresses typical heat dissipation needs and is a mature technology. Given its suitability for the communications industry, air cooling is prioritized in the heat dissipation design of miniaturized quantum key generation terminals for the receiver. Considering the high power consumption of some components, a design combining air cooling and heat sinks is employed to improve overall heat exchange efficiency.

[0135] After confirming air cooling, the air delivery method (blowing or suction) needs to be considered. The air blown out by the fan has a chaotic internal flow, resulting in higher heat exchange efficiency with the heatsink and higher air pressure, making it suitable as the air delivery method for air-cooled heatsinks. Therefore, from the perspective of heat exchange efficiency, this design chooses the "blowing" method, with the airflow from right to left.

[0136] 3.2 Fan Selection

[0137] Based on the preceding heat source analysis, the total power consumption of the heat-generating components is 81.3W. The internal temperature rise of the chassis is designed to be 5℃, requiring the fan airflow to dissipate all the heat. According to the heat balance equation:

[0138]

[0139] In the formula: L is the cooling air volume (m³ / s). 2 / s); Q is the heat generated by the device (kW); ρ is the density of air (kg / m³). 3 );C p t is the specific heat capacity of air (kJ / (kg·℃)); t0 is the outlet temperature of the cooling air (℃); t i The inlet temperature of the cooling air (°C).

[0140] The density of air, ρ, is taken as 1.29 kg / m³. 3 The specific heat capacity of air, C p Take 1.005 kJ / (kg·℃) as the inlet temperature t of the cooling air. i Taking 40℃ as the temperature and the outlet temperature t0 of the cooling air as 45℃, substituting these values ​​into the above formula, the calculated result is 0.75m. 3 / min.

[0141] Considering airflow leakage and improving heat dissipation reliability, a reliability factor of 1.2 is chosen based on experience. Therefore, the selected fan's airflow should be greater than 0.75 * 1.2 = 0.9 m³ / s. 3 / min.

[0142] Based on experience, fans exhibit the highest efficiency and reliability in the static pressure plateau region. The fan's airflow curve indicates that this plateau region is approximately 0.3–0.4 m. 3 Between / min, take 0.35m 3 / min, the required number of fans is N = 0.9m 3 / min÷0.35m 3 / min = 2.57, therefore 3 fans are needed.

[0143] Taking into account the internal volume of the chassis and to improve the reliability of the fans, an N+1 redundancy design is adopted, which uses 4 fans and selects four-wire adjustable speed fans.

[0144] In terms of structural design, the maintainability of the fan assembly should be considered. During fan maintenance, each fan can be installed or removed independently after opening the top cover of the chassis.

[0145] 4. Thermal simulation

[0146] After determining the component temperature rise, airflow, fan, and heat sink, thermal simulation will be performed on the chassis. Based on the thermal resistance of key components, the internal temperature change of the chassis will be simulated to determine whether the chassis heat dissipation can meet the requirements of component temperature rise. At the same time, the thermal simulation can determine whether the fan selection and airflow design are reasonable.

[0147] The operating environment of the receiver's miniaturized quantum key generation terminal is 0–40℃, with a simulation environment temperature deviation of ±5℃. Set to 45℃, thermal simulation was performed using simulation software. The simulated temperature rise of various devices with a power output of 2W or higher is shown in Table 7 below.

[0148] Table 7. Statistics of Simulation Temperatures for Devices with a Power of 2W or Higher

[0149] NO. Location describe Single-chip power consumption <![CDATA[Device junction temperature T J > <![CDATA[Simulated device case temperature T C > Simulation device junction temperature 1 main control board FPGA-1 9W 100℃ 79.59℃ 81.93℃ 2 main control board FPGA-2 9W 100℃ 79.64℃ 81.98℃ 3 main control board CPU-1 5W 125℃ 72.25℃ 76.50℃ 4 main control board CPU-2 5W 125℃ 73.63℃ 77.88℃

[0150] The simulation results show that the chassis heat dissipation can meet the temperature rise requirements of the components, and the selection of the fan and the design of the air duct are reasonable.

[0151] Force Design:

[0152] Finite element simulation software can simulate the required random vibration environment. Modal analysis and random vibration analysis were performed on the reduced chassis model to obtain the inherent characteristics and vibration response characteristics of the structure.

[0153] 1. Finite element modeling

[0154] Before performing finite element analysis, the model needs to be simplified to improve computational efficiency while ensuring model accuracy. The simplification of the finite element model follows these principles:

[0155] Key parts should not be simplified, such as those where structural failure may occur;

[0156] Remove redundant components and replace them by applying constraints;

[0157] Modify the components and replace them with simpler geometric structures;

[0158] Remove features with relatively small geometric dimensions, such as chamfers and round holes;

[0159] Based on the load and constraints, a symmetric model should be considered.

[0160] 2. Simulation Model Description

[0161] 2.1 Model Structure and Materials

[0162] The chassis, as a sheet metal assembly, is a typical plate shell structure. The weight of the structure is mainly concentrated in the chassis, the heat sink of the detector module, the power supply, and the PCB. Other parts can be simplified in the model. The material parameters are shown in Table 8 below:

[0163] Table 8. Mechanical Properties of Materials

[0164] Part of use Material type <![CDATA[Density g / cm 3 > Elastic modulus GPa Yield strength MPa chassis Cold-rolled steel sheet - Q235 7.9 206 280 Detector heat sink Aluminum-6061 2.7 70 55.2 power supply Cold-rolled steel sheet - Q235 7.9 206 280 main control board PCB-FR4 2 20 269

[0165] 2.2 Contact Properties

[0166] The various structural components within the receiver's miniaturized quantum key generation terminal are connected by screws: the power supply, main control board, and detector module are connected to the chassis base plate by screws, and the decoding optical path is connected to the chassis base plate by screws.

[0167] 2.3 Random Vibration Analysis

[0168] The application environment for the receiver's miniaturized quantum key generation terminal is a communication equipment room environment, which must meet the relevant requirements in GB / T4857.23-2012 "Basic Tests for Packaging and Transport Packages - Part 23: Random Vibration Test Method".

[0169] The random vibration input adopts the conditions specified in the Highway Transportation Severity II chart, such as... Figure 7 As shown, random vibration along the z-axis was analyzed using simulation software to examine the stress distribution.

[0170] 3. Results of mechanical analysis

[0171] Mechanical analysis was performed on the miniaturized quantum key generation terminal for the receiver, and the stiffness and strength of the terminal structure and key components were verified based on the analysis results. The analysis showed that the structure of this invention does not yield and meets the design requirements.

[0172] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A receiver-side miniaturized quantum key generation terminal, comprising a chassis (1), a main control board (2), a detector module (3), a decoding optical path (4), a power supply (5), and a fan (6), characterized in that: The main control board (2) and the decoding optical path (4) are arranged side by side on the bottom plate of the chassis (1), and the front ends of the main control board (2) and the decoding optical path (4) are pressed against the inside of the front panel of the chassis (1). The detector module (3) and the decoding optical path (4) are arranged side by side, and the left ends of the detector module (3) and the decoding optical path (4) are close to the right end of the main control board (2). The power supply (5) is located on the rear bottom plate of the chassis (1), the blower fan (6) is located on the side close to the detector module (3), and the air duct is set on the left and right. The main control board (2) includes a CPU and / or an FPGA, which are staggered in the air duct.

2. The receiver-side miniaturized quantum key generation terminal as described in claim 1, characterized in that: The power supply (5) includes two power supplies, AC and DC. The two power supplies (5) are arranged side by side at the rear of the chassis (1) and behind the detector module (3). The rear of the main control board (2) is left empty for wiring.

3. The receiver-side miniaturized quantum key generation terminal as described in claim 1, characterized in that: The power supply (5) includes two power supplies, AC and DC, which are arranged side by side at the rear of the chassis (1), behind the main control board (2) and the detector module (3), respectively.

4. The receiver-side miniaturized quantum key generation terminal as described in claim 1, characterized in that: The main control board (2) includes one CPU or one FPGA, or one FPGA and one CPU, or multiple CPUs and / or multiple FPGAs. When there are multiple CPUs and / or multiple FPGAs, the multiple CPUs and multiple FPGAs are spatially staggered.

5. A receiver-side miniaturized quantum key generation terminal as described in claim 4, characterized in that: The main control board (2) includes two FPGAs (22) and two CPUs (24). The two CPUs (24) are arranged in front with a left-right gap, and the two FPGAs (22) are arranged in the back with a front-back gap. The frontmost FPGA (22) is also located behind the CPU (24). From the main viewpoint, the two FPGAs (22) are located between the two CPUs (24) in the left-right direction.

6. A receiver-side miniaturized quantum key generation terminal as described in claim 4, characterized in that: The main control board (2) includes two FPGAs (22) and two CPUs (24). The two CPUs (24) are arranged in front with a left-right gap, and the two FPGAs (22) are arranged in the rear with a left-right gap. From the main viewpoint, the two FPGAs (22) are located behind the two CPUs (24), and the FPGAs (22) and CPUs (24) are staggered in front and behind.

7. A receiver-side miniaturized quantum key generation terminal as described in claim 4, characterized in that: Heat sinks are provided on the surface of the FPGA (22) and the CPU (24).

8. A receiver-side miniaturized quantum key generation terminal as described in claim 1, characterized in that: The detector module (3) includes a heat sink (31), a PCB board (32), an integrated cooling APD, a shielding cover (33), and an optical fiber tray (34). The heat sink (31) serves as the main support. The PCB board (32) and the integrated cooling APD are both fixed on the heat sink (31). The integrated cooling APD is located inside the shielding cover (33). The shielding cover (33) is fixed on the PCB board (32) to shield the radio frequency circuit on the PCB board (32). The optical fiber tray (34) is fixed on the shielding cover (33).

9. A receiver-side miniaturized quantum key generation terminal as described in claim 1, characterized in that: The chassis (1) has three fans (6) on both the left and right sides. The left fan is an intake fan and the right fan is a blower fan. The fans on the left and right sides are arranged in a front-to-back sequence along the inner edge of the side panel of the chassis (1).

10. A receiver-side miniaturized quantum key generation terminal as described in claim 1, characterized in that: The chassis (1) has four blower fans (6) on the side closest to the detector module (3), and no fans are provided on the opposite side.

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