A data detection system and detection method based on SPI bus communication

Abstract

The application discloses a kind of based on SPI bus communication data detection system and detection method, the based on SPI bus communication data detection system includes host computer, slave and data detection unit;The host computer is used to send enable signal to slave then carries out data communication with slave, and receives the data sent by slave in real time;The slave is used to receive the enable signal of host computer and the data sent by host computer, and sends data to host computer by MOSI signal line, completes data communication with host computer.The application provides a kind of based on SPI bus communication data detection system and detection method, solves the problem that SPI data communication cannot identify whether slave receives correct communication data due to no response signal;At the same time, also solve the problem that bus is busy or idle when SPI data communication, so as to improve the reliability of SPI data communication.

Description

TECHNICAL FIELD

[0001] The application relates to a system and a method for detecting SPI bus communication data. BACKGROUND

[0002] At present, SPI (Serial Perripheral Interface) is a serial peripheral interface. In the existing SPI bus communication technology of a digital chip, the SPI serial bus is mainly applied to data communication between a chip outside a chip and the chip. A chip for sending data is usually called a host, and a chip for receiving data is usually called a slave. In SPI bus communication, there is only one host (Master) and one or more slaves (Slave). The host and the slave each have four data signal lines, mainly including a serial clock line SCLK, a master-out-slave-in signal line MOSI, a master-in-slave-out signal line MISO and a chip select signal line CS. The four data lines of the host and the slave are connected respectively. When the chip select signal line CS of the host is enabled, data communication between the chips can be realized.

[0003] As shown in Figure 1 When there is one host and one slave for data communication, in the case that the SCLK, MOSI and MISO three data signal lines of the host and the slave have been connected, only the chip select signal ends CS of the host and the slave need to be connected and an enable signal needs to be sent to the slave, so that data communication between the chips can be realized.

[0004] In the existing SPI data communication technology, when the host sends data to the slave, the SPI bus transmits high bits first and then transmits low bits during data transmission. The data line is high to represent logic '1' and low to represent logic '0'. After one byte of data is transmitted, the next byte of data can be transmitted without response. The SPI bus works in a synchronous mode. The clock line sends data to the data line at the rising edge or the falling edge of the clock line. The receiver reads data from the data line at the next falling edge or the next rising edge, completes one bit of data transmission, and completes one byte of data transmission in eight clock periods. The slave does not send a response signal to the host after receiving the data sent by the host.

[0005] When the SPI data communication is carried out between chips, when the host sends an enabling signal to the chip select signal end of the slave to be communicated, the slave is selected for data communication, the host sends data to the slave byte by byte, each byte of data has no start bit, stop bit and response bit, only the sending of each byte of data is continuously carried out until the data is sent. In this data transmission case, when the host sends data to the slave, the slave does not send a response signal to the host to feed back to the host whether the current slave receives the data sent by the host, and cannot know whether the slave correctly receives the data. If the data received by the slave is incorrect, the data transmission cannot be stopped. Moreover, it is unable to judge whether the current state of the bus is in a busy state or an idle state. In this case, the data transmission between chips is carried out, the bandwidth utilization rate is low, and the reliability of the data transmission between chips is low. SUMMARY

[0006] The technical problem to be solved by the present application is to overcome the shortcomings of the prior art. The present application provides a SPI bus communication data detection system and a detection method, which solves the problem that the SPI data communication cannot identify whether the slave correctly receives the communication data due to the lack of a response signal. At the same time, the problem that the SPI data communication cannot identify whether the bus is busy or idle is also solved, thereby improving the reliability of the SPI data communication. When the SPI bus is detected to be in an idle state, the data communication between the host and other slaves can be carried out, and the utilization rate of the SPI bus is submitted. Moreover, because the data detection unit is connected outside the SPI data communication, the communication rate between chips is not affected during the data detection unit collects data.

[0007] To solve the above technical problems, the technical scheme of the present application is as follows:

[0008] The present application provides a SPI bus communication data detection system, which comprises a host, a slave and a data detection unit.

[0009] The host is used to send an enabling signal to the slave and then carry out data communication with the slave, and receive data sent by the slave in real time.

[0010] The slave is used to receive the enabling signal of the host and the data sent by the host, and send data to the host through the MOSI signal line, so as to complete the data communication with the host.

[0011] The data detection unit is used to collect the data sent by the host and the data received by the slave, then carry out data logic calculation on the data sent by the host and the data received by the slave, and feed back the data calculation result to the host, so that the host controls whether the data continues to be received and sent.

[0012] Further, the data detection unit comprises a data acquisition unit, a numerical logic calculation unit, a data feedback unit and a data reset unit.

[0013] The input end of the data acquisition unit receives data sent by the host and data received by the slave, the output end of the data acquisition unit is connected with the input end of the numerical logic calculation unit, the output end of the numerical logic calculation unit is connected with the input end of the data feedback unit, the output end of the data feedback unit is connected with the host, and the data reset unit is connected with the data acquisition unit, the numerical logic calculation unit and the data feedback unit respectively.

[0014] Further, the data acquisition unit comprises a host data acquisition module and a slave data acquisition module.

[0015] The host data acquisition module is used for acquiring data sent by the host, and the host data acquisition module comprises a host FIFO data buffer.

[0016] The slave data acquisition module is used for acquiring data received by the slave, and the slave data acquisition module comprises a slave FIFO data buffer.

[0017] Further, the numerical logic calculation unit is used for arranging current data acquired by the data acquisition unit bit by bit and calculating new data results through XOR gates and AND gates, and the numerical logic calculation unit comprises four XOR gates, one FIFO data buffer and three AND gates.

[0018] Further, the data feedback unit is used for storing the calculation results of the numerical logic calculation unit and feeding back the results to the host.

[0019] Further, the data reset unit is used for adding reset signals to each module in the data detection unit, and clearing and resetting the data of the data acquisition unit, the numerical logic calculation unit and the data feedback unit.

[0020] Another aspect of the application provides a detection method of the SPI bus communication data detection system, which comprises the following steps:

[0021] In step S1, the data acquisition unit in the data detection unit starts to acquire data of the host and the slave in communication, places the acquired host sending data in the host FIFO data buffer of the data acquisition unit, and places the acquired slave receiving data in the slave FIFO data buffer of the data acquisition unit.

[0022] Step S2, the numerical logic calculation unit reads data from the FIFO data buffer of the host and the FIFO data buffer of the slave in the data acquisition unit respectively, arranges the data sent by the host and the data received by the slave in sequence according to the order of reading data, forms new combined data, and temporarily stores the new combined data in the FIFO data buffer of the numerical logic calculation unit;

[0023] Step S3, each two adjacent data in the new combined data are subjected to logical calculation and output, and it is judged whether the data sent by the host and the data received by the slave are consistent;

[0024] Step S4, the judgment result of the numerical logic calculation unit is output to the data feedback unit, and the judgment result is fed back to the host through the data feedback unit, and the host decides whether the data can continue to be transmitted and received according to the judgment result, and completes the detection of one frame of data;

[0025] Step S5, after completing the detection of one frame of data, the data reset unit clears the data of each module in the data detection unit.

[0026] Further, in the step S2, the numerical logic calculation unit reads data from the FIFO data buffer of the host and the FIFO data buffer of the slave in the data acquisition unit respectively, arranges the data sent by the host and the data received by the slave in sequence according to the order of reading data, forms new combined data, and specifically includes the following steps:

[0027] The numerical logic calculation unit reads one data in the host sending data from the host FIFO data buffer according to the reading order, then reads one data in the slave receiving data from the slave FIFO data buffer, and then circulates three times according to the reading order;

[0028] At the same time of reading data, one data in the host sending data and one data in the slave receiving data are arranged in sequence according to the reading order, and new combined 8-bit data are formed.

[0029] Further, in the step S3, each two adjacent data in the new combined data are subjected to logical calculation and output, and it is judged whether the data sent by the host and the data received by the slave are consistent, and specifically includes the following steps:

[0030] Step S31, each two adjacent data in the new combined 8-bit data are input into an exclusive OR gate for logical calculation, if the two input data are the same, the output result is 1; if the two input data are different, the output result is 0;

[0031] Step S32, after 4 XOR gate calculations, 4-bit output data is obtained, and the 4-bit output data is input into 2 first-level AND gates for logical calculation and output, and the output data of the 2 first-level AND gates is input into a second-level AND gate for logical calculation;

[0032] If the output result of the second-level AND gate is 1, it indicates that the host sending data and the slave receiving data are consistent; if the output result of the second-level AND gate is 0, it indicates that the host sending data and the slave receiving data are inconsistent.

[0033] Further, in the step S4, the judgment result of the numerical logical calculation unit is output to the data feedback unit, and the judgment result is fed back to the host through the data feedback unit, and the host determines whether the data can continue to be transmitted and received according to the judgment result, and specifically includes the following steps:

[0034] The judgment result of the numerical logical calculation unit is output to the data feedback unit.

[0035] When the host sending data and the slave receiving data are inconsistent, a low level 0 is output, the data feedback unit feeds back the result 0 to the host, and the interrupt unit of the SPI controller of the host determines to interrupt the data transmission and reception.

[0036] When the host sending data and the slave receiving data are consistent, a high level 1 is output, the data feedback unit feeds back the result 1 to the host, and the interrupt unit of the SPI controller of the host does not act.

[0037] By adopting the above technical scheme, the present application has the following beneficial effects:

[0038] 1. When the SPI data communication is performed between the host and the slave, the data detection system is added outside the SPI communication system to detect the data received by the slave and the data sent by the host, perform numerical logical calculation, and feed back the logical calculation result to the host, and if the data is incorrect when the host receives the calculation result, the host performs interrupt operation. By the present application, whether the data sent by the host to the slave is transmitted correctly can be detected, and if the data transmission is incorrect, the host interrupts the transmission and reception of the data by using the interrupt unit. And the idle or busy state of the bus can be detected by the detection system. And because the data detection unit is connected outside the SPI data communication, the communication rate between chips will not be affected during data detection.

[0039] 2. When the SPI data communication is performed between the host and the slave, the data detection unit is added to detect the correctness of the data transmission and reception of the host and the slave, so as to drive the interrupt unit of the SPI communication controller of the host to control the data transmission and reception. The data detection unit can also be used to detect the idle and busy states of the SPI bus, and when it is detected that the SPI bus is in the idle state, the data communication between the host and other slaves can be performed, and the utilization rate of the SPI bus is improved. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the SPI communication circuit between the master and slave devices of the present invention;

[0041] Figure 2 This is a schematic diagram of the data detection system based on SPI bus communication according to the present invention.

[0042] Figure 3 This is a schematic diagram of the logic calculation of the numerical logic calculation unit of the present invention;

[0043] Figure 4 This is a flowchart of the detection method of the present invention. Detailed Implementation

[0044] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0045] Example 1

[0046] like Figure 2 As shown, this embodiment provides a data detection system based on SPI bus communication, which includes a host, a slave, and a data detection unit.

[0047] like Figure 1 As shown, in this embodiment, the host device sends an enable signal to the slave device and then communicates with the slave device via data, and receives data sent by the slave device in real time. The slave device receives the enable signal from the host and the data sent by the host, and sends data back to the host via the MOSI signal line to complete data communication with the host.

[0048] like Figure 2 As shown, the data detection unit in this embodiment is used to collect data sent by the host and data received by the slave, then perform data logic calculations on the data sent by the host and the data received by the slave, and feed the data calculation results back to the host. The host is equipped with an SPI controller, and the interrupt unit of the SPI controller controls whether data continues to be sent and received.

[0049] like Figure 2 As shown, the data detection unit in this embodiment includes a data acquisition unit, a data logic unit, a data feedback unit, and a data reset unit;

[0050] The input end of the data acquisition unit receives data sent by the host and data received by the slave, the output end of the data acquisition unit is connected with the input end of the numerical logic calculation unit, the output end of the numerical logic calculation unit is connected with the input end of the data feedback unit, the output end of the data feedback unit is connected with the host, and the data reset unit is connected with the data acquisition unit, the numerical logic calculation unit and the data feedback unit respectively.

[0051] Specifically, the data acquisition unit of the embodiment comprises a host data acquisition module and a slave data acquisition module.

[0052] The host data acquisition module is used for acquiring data being sent by the host, and the host data acquisition module comprises a host FIFO data buffer.

[0053] The slave data acquisition module is used for acquiring data being received by the slave, and the slave data acquisition module comprises a slave FIFO data buffer.

[0054] Specifically, the numerical logic calculation unit of the embodiment is used for arranging current data collected by the data acquisition unit bit by bit and calculating new data results through XNOR gates and AND gates, and the numerical logic calculation unit comprises four XNOR gates, one FIFO data buffer and three AND gates.

[0055] Specifically, the data feedback unit of the embodiment is used for storing calculation results of the numerical logic calculation unit and feeding back the results to the host.

[0056] Specifically, the data reset unit of the embodiment is used for adding reset signals to each module in the data detection unit, and the main function is to clear and reset data of the data acquisition unit, the numerical logic calculation unit and the data feedback unit, so as to carry out the next data detection.

[0057] Embodiment Two

[0058] As shown in Figure 4 The embodiment provides a detection method of a communication data detection system based on an SPI bus, which comprises the following steps.

[0059] In step S1, the data acquisition unit in the data detection unit starts to acquire data being communicated by the host and the slave, places the acquired host sending data in the host FIFO data buffer of the data acquisition unit, and places the acquired slave receiving data in the slave FIFO data buffer of the data acquisition unit.

[0060] Step S2, the numerical logic calculation unit reads data from the FIFO data buffer of the host and the FIFO data buffer of the slave in the data acquisition unit respectively, arranges the data sent by the host and the data received by the slave in sequence according to the reading sequence, forms new combined data, and temporarily stores the new combined data in the FIFO data buffer of the numerical logic calculation unit, and specifically includes the following steps:

[0061] The numerical logic calculation unit reads data according to the reading sequence, that is, one bit of the data sent by the host is read first, and then one bit of the data received by the slave is read; one bit of the data sent by the host is read from the FIFO data buffer of the host first, and then one bit of the data received by the slave is read from the FIFO data buffer of the slave, and then the reading sequence is cycled three times, as shown in the following table: Figure 3 The FIFO buffer in the numerical logic calculation unit can store 8 bits of data, and after the reading sequence is cycled according to the above reading sequence, 8 bits of data sent and received by the host and the slave are read, including 4 bits of data sent by the host and 4 bits of data received by the slave.

[0062] At the same time of reading data, one bit of the data sent by the host and one bit of the data received by the slave are arranged in sequence according to the reading sequence, and 8 bits of new combined data are formed.

[0063] Step S3, each two adjacent bits of the new combined data are subjected to logical calculation and output, to determine whether the data sent by the host and the data received by the slave are consistent, and specifically includes the following steps:

[0064] Step S31, each two adjacent bits of the 8 bits of new combined data are input into an XNOR gate for logical calculation, if the two input data are the same, the output result is 1; if the two input data are different, the output result is 0;

[0065] Step S32, after being calculated by 4 XNOR gates, 4 bits of output data are obtained, the 4 bits of output data are input into 2 first-level AND gates for logical calculation and output, and the output data of the 2 first-level AND gates are input into a second-level AND gate for logical calculation; the logical relationship of the AND gate is that if both of the two input data are 1, the output result is 1, and if one of the input data is 0, the output result is 0;

[0066] If the output result of the second-level AND gate is 1, it indicates that the data sent by the host and the data received by the slave are consistent; if the output result of the second-level AND gate is 0, it indicates that the data sent by the host and the data received by the slave are inconsistent.

[0067] Step S4, output the result of the numerical logic calculation unit to the data feedback unit, and feed back the result to the host through the data feedback unit, and determine whether the data can continue to be transmitted according to the result, so as to complete the detection of a frame of data, which specifically includes the following steps:

[0068] Output the result of the numerical logic calculation unit to the data feedback unit;

[0069] When the host sends data and the slave receives data are inconsistent, output low level 0, and feed back the result 0 to the host through the data feedback unit, and the interrupt unit of the SPI controller of the host determines to interrupt the data transmission;

[0070] When the host sends data and the slave receives data are consistent, output high level 1, and feed back the result 1 to the host through the data feedback unit, and the interrupt unit of the SPI controller of the host does not act;

[0071] When the data acquisition unit does not collect the data transmitted by the host and the slave, it can represent that the SPI bus is currently in an idle state, and the data communication between other slaves and the host can be carried out.

[0072] Step S5, when the detection of a frame of data is completed, the data reset unit clears the data of each module in the data detection unit, so as to carry out the next data detection.

[0073] In the embodiment, the output result is high level "1" valid, and the logic gate can be adjusted according to the requirement, if the output result is low level "0" valid, the XNOR gate can be replaced by XOR gate, and the logical relationship of the XOR gate is that two input data are different, and then output 1, and the same is output 0. At the same time, the AND gate is replaced by OR gate, and the logical relationship of the OR gate is that two input data are both 0, and then the output result is 0, otherwise it is 1, so as to realize the same purpose.

[0074] The above embodiment further describes the technical problems, technical solutions and beneficial effects solved by the present application in detail, and it should be understood that the above description is only a specific embodiment of the present application, and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A system for detecting communication data based on SPI bus, characterized in that, It includes a host, a slave and a data detection unit; The host is used for sending an enabling signal to the slave, then performing data communication with the slave, and receiving data sent by the slave in real time; The slave is used for receiving the enabling signal of the host and data sent by the host, and sending data to the host through a MOSI signal line, so as to complete data communication with the host; The data detection unit is used for collecting data sent by the host and data received by the slave, then performing data logic calculation on the data sent by the host and the data received by the slave, and feeding back data calculation results to the host, so that the host controls whether data continues to be transmitted and received; The data detection unit comprises a data collection unit, a numerical logic calculation unit, a data feedback unit and a data reset unit; The input end of the data collection unit receives data sent by the host and data received by the slave, the output end of the data collection unit is connected with the input end of the numerical logic calculation unit, the output end of the numerical logic calculation unit is connected with the input end of the data feedback unit, the output end of the data feedback unit is connected with the host, and the data reset unit is connected with the data collection unit, the numerical logic calculation unit and the data feedback unit respectively; The data collection unit comprises a host data collection module and a slave data collection module; The host data collection module is used for collecting data sent by the host, and comprises a host FIFO data buffer; The slave data collection module is used for collecting data received by the slave, and comprises a slave FIFO data buffer; The data feedback unit is used for storing calculation results of the numerical logic calculation unit, and feeding back the results to the host; The detection method of the data detection system based on SPI bus communication comprises the following steps: In step S1, the data collection unit in the data detection unit starts to collect data of the host and the slave which are communicating, places the collected host sending data in the host FIFO data buffer of the data collection unit, and places the collected slave receiving data in the slave FIFO data buffer of the data collection unit; In step S2, the numerical logic calculation unit reads data from the FIFO data buffer of the host and the FIFO data buffer of the slave in the data collection unit respectively, arranges the host sending data and the slave receiving data in sequence according to the order of reading data, forms new combined data, and temporarily stores the new combined data in the FIFO data buffer in the numerical logic calculation unit; In step S3, each two adjacent data in the new combined data are subjected to logic calculation and output, and it is judged whether the host sending data and the slave receiving data are consistent; In step S4, the judgment result of the numerical logic calculation unit is output to the data feedback unit, the judgment result is fed back to the host through the data feedback unit, and the host decides whether data can continue to be transmitted and received according to the judgment result, so as to complete one frame of data detection; In step S5, when one frame of data detection is completed, the data reset unit clears data in each module in the data detection unit.

2. The SPI bus communication data detection system based on claim 1, characterized in that: The numerical logic calculation unit is used for arranging the current data collected by the data collection unit bit by bit and calculating new data results through XOR gates and AND gates.

3. The SPI bus communication data detection system of claim 1, wherein: The data reset unit is used for adding reset signals to each module in the data detection unit, and clearing and resetting the data of the data collection unit, the numerical logic calculation unit and the data feedback unit.

4. The SPI bus communication data detection system of claim 1, wherein, In step S2, the numerical logic calculation unit reads data from the FIFO data buffer of the host and the FIFO data buffer of the slave in the data collection unit, arranges the data sent by the host and the data received by the slave in sequence according to the order of reading data, and forms new combined data, which specifically includes the following steps: The numerical logic calculation unit reads one bit of data from the host FIFO data buffer, and then reads one bit of data from the slave FIFO data buffer according to the reading order, and then loops three times according to the reading order. At the same time of reading data, one bit of data sent by the host and one bit of data received by the slave are arranged in sequence according to the reading order, and new combined 8-bit data is formed.

5. The SPI bus communication data detection system of claim 4, wherein, In step S3, each two adjacent bits of the new combined data are calculated and output through logic calculation to determine whether the data sent by the host and the data received by the slave are consistent, which specifically includes the following steps: Step S31, input each two adjacent bits of the new combined 8-bit data into the XOR gate for logic calculation, if the two input data are the same, the output result is 1; if the two input data are different, the output result is 0; Step S32, after calculating by the four XOR gates, four output data are obtained, the four output data are input into two primary AND gates for logic calculation and output, and the output data of the two primary AND gates are input into a secondary AND gate for logic calculation; If the output result of the secondary AND gate is 1, it means that the data sent by the host and the data received by the slave are consistent; if the output result of the secondary AND gate is 0, it means that the data sent by the host and the data received by the slave are inconsistent.

6. The SPI bus communication data detection system of claim 5, wherein, In step S4, the judgment result of the numerical logic calculation unit is output to the data feedback unit, and the judgment result is fed back to the host through the data feedback unit, and the host decides whether the data can continue to be transmitted according to the judgment result, which specifically includes the following steps: The judgment result of the numerical logic calculation unit is output to the data feedback unit; When the data sent by the host and the data received by the slave are inconsistent, a low level 0 is output, the result 0 is fed back to the host by the data feedback unit, and the interrupt unit of the SPI controller of the host decides to interrupt the data transmission and reception; When the data sent by the host and the data received by the slave are consistent, a high level 1 is output, the result 1 is fed back to the host by the data feedback unit, and the interrupt unit of the SPI controller of the host does not act.

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