Gallium nitride power transistors

Abstract

The present invention relates to a gallium nitride (GaN) power transistor (100), comprising: a buffer layer (110); a barrier layer (111) deposited on the buffer layer (110), wherein a gate region (112) is formed on the top of the barrier layer (111); a p-type doped gallium nitride (Gallium Nitride, GaN) A p-type doped GaN layer (113) is deposited on the barrier layer (111) at the gate region (112); and a metal gate layer (114) is deposited on top of the p-type doped GaN layer (113), wherein the metal gate layer (114) contacts the p-type doped GaN layer (113) to form a Schottky barrier (115); wherein the thickness of the p-type doped GaN layer (113), the metal type of the metal gate layer (114), and the p-type doping concentration of the p-type doped GaN layer (113) are based on the known relationship of the pGaN Schottky gate depletion region thickness to the p-type doping concentration and the gate metal type.

Description

Technical Field

[0001] The present invention relates to the field of gallium nitride (GaN) technology for power device applications. Specifically, the present invention relates to a GaN power transistor, and more particularly to a GaN power field-effect transistor (FET) with stable pGaN Schottky operation and a metal-semiconductor junction of such a GaN power transistor. Background Art

[0002] Over the past 15 to 20 years, the semiconductor industry has been actively developing gallium nitride (GaN) technology to replace traditional silicon-based field-effect transistors (FETs). The use of wide-bandgap materials offers unprecedented potential for performance improvements at both the device and system levels. Enhancement-mode GaN power FETs are now a reality, with several major semiconductor manufacturers already launching products on the market. The most mature GaN device concept employed by the vast majority of participants is the pGaN normally-off concept. Currently, the fabrication of normally-off pGaN power FETs typically follows two approaches. The primary difference lies in the fabrication strategy for the metal / pGaN interface. The two possible approaches are: i) ohmic interface; and ii) Schottky interface. While the Schottky approach can significantly reduce DC gate current, it suffers from two major drawbacks: unstable threshold voltage and poor gate reliability. Summary of the Invention

[0003] The object of the present invention is to provide a GaN power transistor solution that does not have the above-mentioned disadvantages (i.e., unstable threshold voltage and poor gate reliability), or at least to provide a GaN power transistor solution with significantly reduced problems of unstable threshold voltage and poor gate reliability.

[0004] This object is achieved by the features of the independent claim. Further implementations are apparent from the dependent claims, the description and the drawings.

[0005] The embodiments of the present invention provide a specific set of guiding principles for optimizing a Schottky gate module of a p-gate of a GaN power transistor.

[0006] Specifically, the present invention will provide a set of precise relationships between different sizes and doping concentrations of pGaN gate modules, optimize overall performance and solve the main problems of prior art pGaN Schottky gates, namely, unstable threshold voltage and poor gate reliability.

[0007] In the present invention, a fully depleted pGaN Schottky gate scheme is proposed, which can be achieved by appropriately adjusting the geometry of the pGaN gate with respect to a specific p-type doping concentration, for example by magnesium doping, but can also be achieved using any other doping.

[0008] In tests conducted with different parameters, the results show that the guiding principles optimization strategy for pGaN Schottky gate modules can be summarized as follows:

[0009] (1) pGaN thickness < 65nm

[0010] (2) p-type doping concentration: [1e18cm -3 to 1e19cm -3 ]

[0011] (3) Metal type of metal gate: Al, Ti, TiN, Au, Pd, Ni, W or any combination thereof in a stacked manner

[0012] This paper proposes a new pGaN Schottky gate module concept for enhancement-mode GaN-based power transistors, which can achieve the following advantages: normally-off operation; stable threshold voltage, suppressing dynamic instability (which is a characteristic of traditional pGaN Schottky gate approaches); and improved gate reliability due to significantly reduced peak electric fields at the metal / pGaN interface and in the pGaN bulk.

[0013] To describe the present invention in detail, the following terms, abbreviations and symbols will be used:

[0014] GaN Gallium Nitride

[0015] FET Field Effect Transistor

[0016] pGaN p-type doped GaN

[0017] AlGaN aluminum gallium nitride

[0018] 2DEG two-dimensional electron gas

[0019] HV High voltage (working), for example >600V

[0020] MV Medium Voltage (working), e.g. 200-600V

[0021] V TH Threshold voltage

[0022] TDDB Time Dependent Dielectric Breakdown

[0023] In the present invention, two methods for fabricating the metal / pGaN interface are described: an Ohmic interface method and a Schottky interface method.

[0024] In the ohmic interface approach, the interface between the metal gate and the pGaN surface is nearly ideal. This translates into a high DC current to maintain device operation in the on-state, but also complicates the drive strategy and significantly increases drive losses.

[0025] The ohmic interface approach has the following advantages: (i) the pGaN node is neatly connected to the gate metal terminal, so the device is less susceptible to V TH (ii) high reliability: when a large DC current flows through the gate, the gate breaks due to thermal runaway; (iii) a large number of holes are injected from the gate to improve the dynamic effect.

[0026] However, the ohmic interface approach has the following disadvantages: (i) a large amount of hole injection buffer requires a negative external gate voltage; (ii) hole accumulation may lead to tail current; (iii) a dedicated driving scheme is required: current-driven gate driver, external RC network; (iv) large DC gate current leads to driving losses; and it limits the scalability of the concept to high voltage (400-600V) and large R DSON (>30mOhm).

[0027] In the Schottky interface approach, a reverse-biased Schottky diode is inserted in parallel with the pn-pGaN / AlGaN diode. This can significantly reduce the DC gate current.

[0028] The Schottky interface approach has the following advantages: (i) the pGaN node is separated from the gate terminal by a reverse-biased Schottky diode; (ii) the V TH (iii) Low DC current means more difficult to optimize dynamic effects due to the smaller number of holes injected into the buffer; (iv) Gate modules disconnect via TDDB mechanisms (e.g., oxides in Si-MOS devices); (v) Dynamic effects, gate reliability, and V TH Stability is difficult to interact with each other.

[0029] However, the Schottky interface approach has the following disadvantages: (i) the approach allows for a self-aligned gate concept, resulting in the best figure of merit (FOM) (low C GS and C GD ); (ii) there is essentially no DC gate current; (iii) the method allows the use of standard drive schemes, such as voltage drive methods, without external RC networks; (iv) the concept can be used for HV and MV operation; (v) the concept allows the device to be extended to very low R DSON .

[0030] The present invention focuses on providing optimization guidelines for the Schottky interface method to overcome the above shortcomings.

[0031] According to a first aspect, the present invention relates to a gallium nitride (GaN) power transistor, comprising: a buffer layer; a barrier layer deposited on the buffer layer, wherein a gate region is formed on top of the barrier layer; a p-type doped gallium nitride (GaN) layer deposited on the barrier layer at the gate region; and a metal gate layer deposited on top of the p-type doped GaN layer, wherein the metal gate layer contacts the p-type doped GaN layer to form a Schottky barrier; wherein the thickness of the p-type doped GaN layer, the metal type of the metal gate layer, and the p-type doping concentration of the p-type doped GaN layer are based on the known relationship between the thickness of the pGaN Schottky gate depletion region and the p-type doping concentration and the gate metal type.

[0032] This type of GaN power transistor offers a new pGaN Schottky gate module concept for enhancement-mode GaN-based power transistors, which enables the following advantages: normally-off operation; stable threshold voltage, suppressing dynamic instabilities (which are a characteristic of traditional pGaN Schottky gate approaches); and improved gate reliability due to significantly reduced peak electric fields at the metal / pGaN interface and in the pGaN bulk.

[0033] In an exemplary implementation of the GaN power transistor, the thickness of the p-type doped GaN layer is less than 65 nanometers.

[0034] This provides the following advantages: the thickness of the p-type doped GaN layer affects the choice of etching process used to define the gate region. The thin layer of p-type doped GaN allows for better definition of the gate region by photolithography. Another advantage is that minimizing the pGaN layer can increase device transconductance (gm). In addition, the device threshold voltage increases with increasing pGaN thickness. Therefore, the thickness of the p-type doped GaN layer is less than 65 nanometers so that the threshold voltage of the transistor remains stable.

[0035] In an exemplary implementation of the GaN power transistor, the metal gate layer is made of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stacked manner.

[0036] This offers the advantage that the different properties of these metals, such as electrical conductivity, current carrying capacity, robustness, durability, acid resistance, electrical properties, etc., can be advantageously utilized.

[0037] In an exemplary implementation of the GaN power transistor, the p-type doping concentration of the p-type doped GaN layer is between 1e18 cm -3 to 1e19cm -3 within the range.

[0038] When the p-type doping concentration of the p-type doped GaN layer is within this range, the hole tunneling event injected from the metal layer into the pGaN layer is significantly attenuated. Using a p-type doping concentration within this range can significantly reduce the static gate current when a positive voltage is applied to the gate.

[0039] In an exemplary implementation of the GaN power transistor, the p-type doped GaN layer is fully depleted during operation of the GaN power transistor.

[0040] When the p-type doped GaN layer is fully depleted, the transistor can operate with optimized performance, high gate reliability, and no threshold voltage instability.

[0041] In an exemplary implementation of the GaN power transistor, the known relationship of the pGaN Schottky gate depletion region thickness with respect to the p-type doping concentration and the gate metal type is based on a predetermined data set that enables stable operation of the GaN power transistor.

[0042] By using, for example, Figure 4 The predetermined data set described in the foregoing can optimize the overall performance of the GaN power transistor.

[0043] In an exemplary implementation of the GaN power transistor, the predetermined data set enables the GaN power transistor to achieve optimal (or improved) operating performance in terms of static performance, dynamic performance, and gate reliability.

[0044] Due to the significant reduction in the peak electric field at the metal / pGaN interface, such GaN power transistors can achieve optimal (or improved) operating performance with a stable threshold voltage in normally-off operation, suppress dynamic instability and improve gate reliability.

[0045] In an exemplary implementation of the GaN power transistor, the GaN power transistor is configured to enable normally-off operation.

[0046] This offers the advantage that the normally-off transistor can ensure safe operation, for example in power electronics systems.

[0047] In an exemplary implementation of the GaN power transistor, the p-type doped GaN layer and the metal gate layer are defined only in the gate region of the barrier layer by photolithography.

[0048] This offers the advantage that the manufacturing process can be precisely implemented and GaN power transistors with high gate reliability can be manufactured.

[0049] In an exemplary implementation of the GaN power transistor, the buffer layer includes a GaN layer or an aluminum gallium nitride (AlGaN) layer.

[0050] The buffer layer comprising GaN or AlGaN improves the electron mobility of the transistor, further reduces the reverse leakage current in the transistor, and improves the on-off ratio of the transistor.

[0051] In an exemplary implementation of the GaN power transistor, the barrier layer includes an AlGaN layer.

[0052] Transistors having such blocking layers exhibit improved RF characteristics and DC performance.

[0053] In an exemplary implementation of the GaN power transistor, the buffer layer is formed on at least one transition layer, and the transition layer is formed on a silicon substrate.

[0054] This type of power transistor has improved gate leakage current reduction.

[0055] According to a second aspect, the present invention relates to a metal-semiconductor junction of a gallium nitride (GaN) power transistor, the metal-semiconductor junction comprising: a p-type doped GaN layer; a metal gate layer deposited on top of the p-type doped GaN layer; wherein the metal gate layer contacts the p-type doped GaN layer to form a Schottky barrier, and the p-type doping concentration of the p-type doped GaN layer is between 1e18 cm -3 to 1e19cm -3 within the range.

[0056] The metal-semiconductor junction of this type of GaN power transistor offers the following advantages: normally-off operation; stable threshold voltage, suppressing dynamic instabilities that are a characteristic of traditional pGaN Schottky gate approaches; and improved gate reliability due to significantly reduced peak electric fields at the metal / pGaN interface and in the pGaN bulk.

[0057] When the p-type doping concentration of the p-type doped GaN layer is within the above range, the hole tunneling event injected from the metal layer into the pGaN layer is significantly attenuated. Using the p-type doping concentration within this range can significantly reduce the static gate current when a positive voltage is applied to the gate.

[0058] In an exemplary implementation of the metal-semiconductor junction, the p-type doped GaN layer has a thickness less than 65 nanometers.

[0059] This provides the following advantages: the thickness of the p-type doped GaN layer affects the choice of etching process used to define the gate region. The thin layer of p-type doped GaN allows for better definition of the gate region by photolithography. Another advantage is that minimizing the pGaN layer can increase device transconductance (gm). In addition, the device threshold voltage increases with increasing pGaN thickness. Therefore, the thickness of the p-type doped GaN layer is less than 65 nanometers so that the threshold voltage of the transistor remains stable.

[0060] In an exemplary implementation of the metal-semiconductor junction, the metal gate layer is made of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stacked manner.

[0061] This offers the advantage that the different properties of these metals, such as electrical conductivity, current carrying capacity, robustness, durability, acid resistance, electrical properties, etc., can be advantageously utilized. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Other embodiments of the present invention will be described with reference to the following drawings, in which:

[0063] Figure 1 The design of a GaN power transistor 100 with a Schottky barrier provided by a first example is shown;

[0064] Figure 2 The design of a GaN power transistor 200 with a Schottky barrier provided by the second example is shown;

[0065] Figure 3 An equivalent circuit design 300 of a gate module of a GaN power transistor with a Schottky barrier provided by the present invention is shown;

[0066] Figure 4 An example of the design guideline for the Schottky interface of the depletion region with a doping concentration of 400 or more provided by the present invention is shown;

[0067] Figure 5 An exemplary performance simulation 500 showing pGaN Schottky gate threshold voltage stability as a function of stress time is shown;

[0068] Figure 6 An example design of a metal-semiconductor junction 700 of a GaN power transistor is shown. DETAILED DESCRIPTION

[0069] The following is a detailed description of the present invention in conjunction with the accompanying drawings, which form a part of the description and illustrate specific aspects of the present invention by way of illustration. It should be understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not intended to be limiting, and the scope of the present invention is defined by the appended claims.

[0070] It is understood that comments related to a described method also apply to a corresponding device or system for performing the method, and vice versa. For example, if a specific method step is described, the corresponding device may include a unit for performing the described method step, even if such a unit is not explicitly described or shown in the drawings. In addition, it should be understood that unless otherwise explicitly stated, the features of the various exemplary aspects described herein may be combined with each other.

[0071] The semiconductor devices and apparatus described herein can be implemented in wireless communication schemes, particularly those based on 5G. The semiconductor devices described can be used to manufacture integrated circuits and / or power semiconductors and can be manufactured using a variety of technologies. For example, the semiconductor devices can be used in logic integrated circuits, analog integrated circuits, mixed-signal integrated circuits, optical circuits, memory circuits, and / or integrated passive components.

[0072] The Schottky barrier described in this invention is an electron barrier formed at a metal-semiconductor junction. The Schottky barrier exhibits rectifying properties, making it suitable for use as a diode. A key characteristic of a Schottky barrier is its height. This height depends on the combination of metal and semiconductor. Not all metal-semiconductor junctions form rectifying Schottky barriers; metal-semiconductor junctions that conduct current bidirectionally without rectification (perhaps because their Schottky barriers are too low) are called ohmic contacts.

[0073] Figure 1 A design of a GaN power transistor 100 with a Schottky barrier is shown as a first example.

[0074] The GaN power transistor 100 includes: a buffer layer 110; a barrier layer 111 deposited on the buffer layer 110, wherein a gate region 112 is formed on top of the barrier layer 111; a p-type doped GaN layer 113 deposited on the barrier layer 111 at the gate region 112; and a metal gate layer 114 deposited on top of the p-type doped GaN layer 113, wherein the metal gate layer 114 contacts the p-type doped GaN layer 113 to form a Schottky barrier 115. The thickness of the p-type doped GaN layer 113, the metal type of the metal gate layer 114, and the p-type doping concentration of the p-type doped GaN layer 113 are based on known relationships between the pGaN Schottky gate depletion region thickness 401, the p-type doping concentration 402, and the gate metal type, for example. Figure 4 The relationship 400 is shown in FIG.

[0075] A source (S) metal layer 120 and a drain (D) metal layer 121 may be formed on the sides of the barrier layer 111. The source metal layer 120 and the drain metal layer 121 may be separated from the pGaN layer 113 and the metal gate layer 114 by the barrier layer 111. The source metal layer 120 and the drain metal layer 121 may extend to the same height as the barrier layer 111 and thus extend to a level lower than the metal gate layer 114.

[0076] The buffer layer 110 may include a GaN layer or an aluminum gallium nitride (AlGaN) layer, and the barrier layer 111 may include an AlGaN layer.

[0077] In one example of the transistor 100 , the thickness of the p-type doped GaN layer 113 may be less than 65 nanometers.

[0078] In an example of the transistor 100 , the metal gate layer 114 may be made of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stacked manner.

[0079] In an example of the transistor 100, the p-type doping concentration of the p-type doped GaN layer 113 may be 1e18 cm -3 to 1e19cm -3 within the range.

[0080] In one example of the transistor 100 , the p-type doped GaN layer 113 may be fully depleted during operation of the GaN power transistor 100 .

[0081] In one example of the transistor 100, the pGaN Schottky gate depletion region thickness 401 is proportional to the known relationship between the p-type doping concentration 402 and the gate metal type (e.g., Figure 4 The relationship 400 shown in FIG. 4 may be based on a predetermined data set (eg, Figure 4 Data set 403 shown in ).

[0082] In one example of the transistor 100 , the predetermined data set enables the GaN power transistor 100 to achieve optimal (or improved) operating performance in terms of static performance, dynamic performance, and gate reliability.

[0083] In tests conducted with different parameters, the results show that the dataset suitable for pGaN Schottky gate modules can be summarized as follows:

[0084] (1) pGaN thickness < 65nm

[0085] (2) p-type doping concentration: [1e18cm -3 to 1e19cm -3 ]

[0086] (3) Metal type of metal gate: Al, Ti, TiN, Au, Pd, Ni, W or any combination thereof in a stacked manner

[0087] In one example of the transistor 100 , the transistor 100 may be configured to enable normally-off operation.

[0088] In an example of the transistor 100 , the p-type doped GaN layer 113 and the metal gate layer 114 may be defined only in the gate region of the barrier layer 111 by photolithography.

[0089] In one example of the transistor 100, the buffer layer 110 may be formed on at least one transition layer (eg, Figure 2 202, 203) shown in the example of FIG, the transition layer is formed on a silicon substrate (eg, Figure 2 On a substrate 201) as shown in the example.

[0090] Figure 2 The design of a GaN power transistor 200 with a Schottky barrier is shown as a second example.

[0091] The GaN power transistor 200 can be used in combination with Figure 1 A similar design of transistor 100 is described.

[0092] The GaN power transistor 100 includes a buffer layer 110; a barrier layer 111 deposited on the buffer layer 110, wherein a gate region 112 is formed on top of the barrier layer 111; a p-type doped GaN layer 113 deposited on the barrier layer 111 at the gate region 112; and a metal gate layer 114 deposited on top of the p-type doped GaN layer 113, wherein the metal gate layer 114 contacts the p-type doped GaN layer 113 to form a Schottky barrier 115. The buffer layer 110 is formed on a transition layer 203, which is formed on a nucleation layer 202. The nucleation layer 202 is formed on the silicon substrate 201.

[0093] The thickness of the p-type doped GaN layer 113 , the metal type of the metal gate layer 114 , and the p-type doping concentration of the p-type doped GaN layer 113 are based on the known relationship between the pGaN Schottky gate depletion region thickness 401 and the p-type doping concentration 302 and the gate metal type, e.g. Figure 4 The relationship 400 is shown in FIG.

[0094] A source (S) metal layer 120 and a drain (D) metal layer 121 may be formed on the side of the barrier layer 111. The source metal layer 120 and the drain metal layer 121 may be separated from the pGaN layer 113 and the metal gate layer 114 by a passivation layer 204. The source metal layer 120 and the drain metal layer 121 may extend to the same height as the metal gate layer 114. Alternatively, for example, according to Figure 1 In the design shown in FIG, the source metal layer 120 and the drain metal layer 121 may extend to a level lower than the metal gate layer 114 .

[0095] The buffer layer 110 may include a GaN layer or an aluminum gallium nitride (AlGaN) layer, and the barrier layer 111 may include an AlGaN layer.

[0096] In an example of the transistor 200 , the thickness of the p-type doped GaN layer 113 may be less than 65 nanometers.

[0097] In an example of the transistor 200 , the metal gate layer 114 may be made of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stacked manner.

[0098] In an example of the transistor 200, the p-type doping concentration of the p-type doped GaN layer 113 may be 1e18 cm -3 to 1e19cm -3 within the range.

[0099] In one example of the transistor 200 , the p-type doped GaN layer 113 may be fully depleted during operation of the GaN power transistor 100 .

[0100] In one example of the transistor 200 , the pGaN Schottky gate depletion region thickness 401 is proportional to the known relationship between the p-type doping concentration 402 and the gate metal type (e.g., Figure 3 The relationship 400 shown in FIG. 4 may be based on a predetermined data set (eg, Figure 4 Data set 403 shown in ).

[0101] In one example of the transistor 200 , the predetermined data set enables the GaN power transistor 100 to achieve optimal (or improved) operating performance in terms of static performance, dynamic performance, and gate reliability.

[0102] In tests conducted with different parameters, the results show that the dataset suitable for pGaN Schottky gate modules can be summarized as follows:

[0103] (1) pGaN thickness < 65nm

[0104] (2) p-type doping concentration: [1e18cm -3 to 1e19cm -3 ]

[0105] (3) Metal type of metal gate: Al, Ti, TiN, Au, Pd, Ni, W or any combination thereof in a stacked manner

[0106] In one example of the transistor 200 , the transistor 200 may be configured to enable normally-off operation.

[0107] In an example of the transistor 200 , the p-type doped GaN layer 113 and the metal gate layer 114 may be defined only in the gate region of the barrier layer 111 by photolithography.

[0108] Figure 3 An equivalent circuit design 300 of a gate module of a GaN power transistor with a Schottky barrier provided by the present invention is shown.

[0109] exist Figure 3 In the Schottky approach shown, a reverse biased Schottky diode 302 is inserted in series with the pn-pGaN / AlGaN diode 301, as shown in the driving scheme 300b. This can significantly reduce the DC gate current, as shown in FIG. Figure 3 The equivalent circuit 300a shows a parallel capacitor C WThe reverse biased Schottky diode 302 and the parallel capacitor C p The pn-pGaN / AlGaN diodes 301 are connected in series.

[0110] Threshold voltage instabilities (positive and negative) are observed in the Schottky approach, which can make the device more susceptible to spurious turn-on effects (for negative V TH drift) or reduce the on-state resistance of the device (for positive V TH For example, the threshold voltage dynamic behavior of a pGaN Schottky gate can be observed under a positive stress voltage applied to the gate.

[0111] Weak gate robustness and time-dependent dielectric breakdown (TDDB) behavior similar to gate dielectric breakdown in traditional silicon-based power devices have also been observed for the Schottky approach. Several theories have been proposed to explain the gate failure mechanism, with one possible root cause being impact ionization within the depletion region of the reverse-biased Schottky diode, triggered by electrons injected from the AlGaN barrier into the pGaN layer. Measurements of the electric field distribution within the pGaN layer under a positive voltage applied to the gate indicate that the maximum electric field is located at the metal / pGaN interface.

[0112] Today, most Schottky-gate pGaN approaches rely on very high doping concentrations (>5e19 cm -3 The typical thickness of the pGaN layer is usually between 80 nm and 250 nm. The p-type doping concentration can be extracted by conventional SIM profile measurement.

[0113] Studies have shown that hole depletion and accumulation (time-dependent and geometry-dependent) can lead to unstable threshold voltages. In addition, the use of very high doping concentrations in the pGaN layer results in a very narrow depletion region at the metal / pGaN interface. The main disadvantage of this approach is that the electric field in the narrow depletion region reaches very high values ​​(~5-10MV / cm), which seriously affects the overall reliability of the gate. It is believed that the high electric field in the depletion region causes electrons injected from the 2DEG to be rapidly accelerated into the pGaN layer. These accelerated electrons may promote carrier multiplication through impact ionization effects and the presence of a large number of high-energy carriers, which is believed to cause damage (percolation path) at the metal / pGaN interface, ultimately compromising the overall reliability of the gate.

[0114] Over the past few years, several attempts have been made to improve the gate reliability of pGaN gate modules and mitigate the threshold voltage instability of pGaN Schottky gates. For example, a direct relationship has been observed between the static DC gate current and the overall reliability of the gate. Unfortunately, due to the presence of a large number of floating holes in the pGaN layer that can be injected into the AlGaN barrier and / or recombine with electrons injected into the pGaN layer from the 2DEG without being replenished by the metal gate, a reduction in the static gate current translates into higher threshold voltage instability.

[0115] Based on the above reasons, the present invention proposes a solution for overcoming the above shortcomings of the pGaN Schottky gate module, which include: large instability of positive and negative threshold voltages; and poor gate reliability.

[0116] This invention provides a specific set of guidelines for optimizing Schottky gate modules for p-type GaN power transistors. This invention provides a precise set of relationships between different pGaN gate module dimensions and doping concentrations that optimize overall performance and address key challenges of state-of-the-art pGaN Schottky gates, namely threshold voltage instability and gate reliability. A fully depleted pGaN Schottky gate solution can be achieved by appropriately tailoring the pGaN gate geometry to a specific p-type doping concentration, such as through magnesium doping, but can also be achieved using any other doping method.

[0117] As mentioned above Figure 1 and Figure 2 As mentioned, a guiding principle optimization strategy for pGaN Schottky gate modules may include one or more of the following features:

[0118] (1) pGaN thickness < 65nm

[0119] (2) p-type doping concentration: [1e18cm -3 to 1e19cm -3 ]

[0120] (3) Metal type of metal gate: Al, Ti, TiN, Au, Pd, Ni, W or any combination thereof in a stacked manner

[0121] Figure 4 An example of the design guideline for the Schottky interface of the depletion region with a doping concentration above 400 provided by the present invention is shown.

[0122] exist Figure 4 In the example, such as Figure 1 、 Figure 2 and Figure 6The thickness of the depletion region at the metal / pGaN interface between layers 114 and 113 shown in FIG is shown as a function of the p-type doping concentration, for example for Mg used as the doping element. However, any other doping element can also be used. The bold, signed line 410 defines the extension of the depletion region formed at the interface between the metal gate layer 114 and the underlying p-type doped GaN layer 113 as a function of the p-type doping concentration for the particular metal type of the pGaN layer 113 and the metal gate layer 114. Figure 4 Also shown is the dependence of the depletion region on the metal type of the metal gate layer 114 , which is used to form a Schottky interface 115 with the underlying pGaN layer 113 .

[0123] Figure 4 Also shown are a horizontal line B and a vertical line A. These lines represent the safe operating area boundary and the depletion region line of the Schottky pGaN gate module. Specifically, horizontal line A represents the threshold p-type doping concentration, below which hole tunneling events injected from the metal layer into the pGaN layer are severely attenuated. Lowering the p-type doping concentration below this threshold also significantly reduces the quiescent gate current under positive voltage applied to the gate.

[0124] On the other hand, the vertical line B represents the maximum thickness of the pGaN layer 113 recommended to optimize the operating performance of the pGaN Schottky gate module. This maximum thickness is selected based on the following three main guiding principles:

[0125] 1) pGaN etching process optimization: The metal gate layer 114 and the p-type doped GaN layer 113 must be confined to the gate region 112 by photolithography. Typically, some masking steps are performed on the metal gate layer 114 and the p-type doped GaN layer 113 before the etching step. The etching must be carefully controlled to selectively stop at the pGaN / AlGaN barrier interface 113, 111. If this etching step is not properly controlled, unnecessary etching of the AlGaN barrier 111 may occur, resulting in degraded device performance. The p-type GaN thickness may also affect the choice of etching process.

[0126] 2) Transconductance optimization: In order to improve the device transconductance (gm), the pGaN layer 113 must be minimized.

[0127] 3) Threshold voltage: The device threshold voltage increases with the increase of pGaN thickness.

[0128] Based on the following gate module optimization guidelines, the present invention provides the following device dimensions and doping concentration ranges that enable optimal (or improved) performance of pGaN Schottky gate modules. Optimal (or improved) performance is defined in terms of static performance (threshold voltage, gate current), dynamic performance (dynamic threshold voltage), and (last but not least) improved gate reliability.

[0129] Specifically, Figure 4 The simulated performance of a pGaN Schottky gate is shown as a function of the voltage applied to the gate and for different values ​​of the p-type doping concentration used in the pGaN layer 113. It can be observed how, according to the guidelines given below, reducing the p-type doping concentration suppresses the instability of the dynamic threshold voltage and simultaneously achieves a sharp reduction in the peak electric field at the metal / pGaN interface 114, 113. This reduction in the peak electric field translates into a direct improvement in the overall reliability of the gate module. Indeed, it is believed that the primary cause of Schottky pGaN gate breakdown is triggered by impact ionization events, which are promoted and sustained by the high electric field in the Schottky depletion region.

[0130] The depletion region also depends on the metal type of the metal gate.

[0131] The results show that the gradual reduction of the p-type doping concentration of the pGaN layer 113 and the geometric optimization of the gate module can bring significant advantages in terms of threshold voltage instability and peak electric field reduction of the pGaN layer.

[0132] The guiding principles and optimization strategy applicable to pGaN Schottky gate modules can be summarized as follows:

[0133] 1. pGaN thickness < 65nm

[0134] 2. p-type doping concentration: [1e18cm -3 to 1e19cm -3 ]

[0135] 3. Metal type of metal gate: Al, Ti, TiN, Au, Pd, Ni, W or any combination thereof in a stacked manner

[0136] Figure 4 An exemplary data set 403 is shown that follows these guidelines.

[0137] Figure 5 An exemplary performance simulation 500 of pGaN Schottky gate threshold voltage stability 501 as a function of stress time 502 is shown.

[0138] The first graph 510 shows the performance of a pGaN Schottky gate designed according to the guidelines described in the present invention, i.e., pGaN thickness: <65nm; p-type doping concentration: between [1e18cm -3 to 1e19cm -3 ]; Metal gate type: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stacked manner. The threshold voltage of the gate is very stable, even for a long stress time 502.

[0139] The second graph 511 shows the performance of another pGaN Schottky gate designed strictly according to the above guidelines. The threshold voltage shown in graph 511 is also quite stable, with only slight instabilities after a longer stress time 502.

[0140] The third and fourth graphs 512 and 513 were not designed according to the guiding principles of the present invention, but rather use a general design that relies on very high doping concentrations (>5e19 cm -3 ) and pGaN layer thicknesses between 80nm and 250nm. The threshold voltages of Figures 512 and 513 exhibit unstable behavior from the beginning.

[0141] Figure 6 FIG. 6 shows a design of a metal-semiconductor junction 600 of a GaN power transistor provided as an example. For example, the metal-semiconductor junction 600 may be Figure 1 The GaN power transistor 100 shown in or Figure 2 The GaN power transistor 200 shown in FIG.

[0142] The metal-semiconductor junction 600 includes: a p-type doped GaN layer 113; a metal gate layer 114, which is deposited on top of the p-type doped GaN layer 113. The metal gate layer 114 contacts the p-type doped GaN layer 113 to form a Schottky barrier 115. The p-type doping concentration of the p-type doped GaN layer (113) is between 1e18cm -3 to 1e19cm -3 within the range.

[0143] The thickness of the p-type doped GaN layer 113 may be less than 65 nanometers.

[0144] The metal gate layer 114 may be made of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stacked manner.

[0145] The thickness of the p-type doped GaN layer 113, the metal type of the metal gate layer 114, and the p-type doping concentration of the p-type doped GaN layer 113 can be based on the known relationship 400 of the pGaN Schottky gate depletion region thickness 401 relative to the p-type doping concentration 402 and the gate metal type, such as Figure 4 As shown and combined with the above Figure 1 and Figure 2 As stated.

[0146] Although specific features or aspects of the present invention may have been disclosed in conjunction with only one of several implementations, such features or aspects may be combined with one or more features or aspects in other implementations as needed or advantageous for any given or specific application. In addition, to the extent that the terms "include," "have," "have," or other variations of these terms are used in the detailed description or claims, such terms are similar to the term "comprising" in that they all mean to include. Similarly, the terms "exemplary," "for example," and "such as" are intended to be examples only, not best or optimal. The terms "coupled" and "connected," and their derivatives, may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical or electrical contact, or whether they are not in direct contact with each other.

[0147] Although specific aspects have been illustrated and described herein, it will be appreciated by those skilled in the art that various alternative and / or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific aspects discussed herein.

[0148] Although elements in the above claims are listed in a specific order with corresponding labels, these elements do not have to be limited to being implemented in that specific order unless the claim recitation otherwise implies a specific order for implementing some or all of these elements.

[0149] Through the above enlightenment, it is obvious to those skilled in the art that many substitutions, modifications and variations exist. Of course, it is readily apparent to those skilled in the art that, in addition to the applications described herein, there are numerous other applications of the present invention. Although embodiments of the present invention have been described with reference to one or more specific embodiments, it will be appreciated by those skilled in the art that many changes may be made to the embodiments without departing from the scope of the embodiments of the present invention. Therefore, it should be understood that, as long as it is within the scope of the appended claims and their equivalents, the present invention may be practiced in a manner different from that specifically described herein.

Claims

1. A gallium nitride power transistor (100), characterized in that: include: a buffer layer (110); a barrier layer (111) deposited on the buffer layer (110), wherein a gate region (112) is formed on top of the barrier layer (111); a p-type doped gallium nitride layer (113) deposited on the barrier layer (111) at the gate region (112); a metal gate layer (114) deposited on top of the p-type doped GaN layer (113), wherein the metal gate layer (114) contacts the p-type doped GaN layer (113) to form a Schottky barrier (115); wherein the thickness of the p-type doped GaN layer (113), the metal type of the metal gate layer (114), and the p-type doping concentration of the p-type doped GaN layer (113) are based on a known relationship (400) between the thickness (401) of the pGaN Schottky gate depletion region and the p-type doping concentration (402) and the gate metal type; The thickness of the p-type doped GaN layer (113) is less than 65 nanometers; The metal gate layer (114) is made of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W or any combination thereof in a stacked manner; The p-type doping concentration of the p-type doped GaN layer (113) is 1e18 cm -3 to 1e19cm -3 within the range.

2. The gallium nitride power transistor (100) according to claim 1, characterized in that The p-type doped GaN layer (113) is completely depleted during operation of the GaN power transistor (100).

3. The gallium nitride power transistor (100) according to claim 1 or 2, characterized in that The known relationship (400) of the pGaN Schottky gate depletion region thickness (401) to the p-type doping concentration (402) and the gate metal type is based on a predetermined data set (403) that enables stable operation of the GaN power transistor (100).

4. The gallium nitride power transistor (100) according to claim 3, characterized in that The predetermined data set (403) enables the GaN power transistor (100) to achieve optimal operating performance in terms of static performance, dynamic performance and gate reliability.

5. The gallium nitride power transistor (100) according to claim 1 or 2, characterized in that Used to enable normally-off operation.

6. The gallium nitride power transistor (100) according to claim 1 or 2, characterized in that The p-type doped GaN layer (113) and the metal gate layer (114) are limited only in the gate region of the barrier layer (111) by photolithography.

7. The gallium nitride power transistor (100) according to claim 1 or 2, characterized in that The buffer layer (110) includes a GaN layer or an aluminum gallium nitride layer.

8. The gallium nitride power transistor (100) according to claim 1 or 2, characterized in that The barrier layer (111) includes an AlGaN layer.

9. The gallium nitride power transistor (100) according to claim 1 or 2, characterized in that: The buffer layer (110) is formed on at least one transition layer (202, 203), and the transition layer (202, 203) is formed on a silicon substrate (201).

10. A metal-semiconductor junction (600) of a gallium nitride power transistor (100), characterized in that: The metal-semiconductor junction (600) is provided in a gate region (112) on top of a barrier layer (111), and the barrier layer (111) is deposited on a buffer layer (110); The metal-semiconductor junction (600) comprises: A p-type doped GaN layer (113) is deposited on the gate region (112); a metal gate layer (114) deposited on top of the p-type doped GaN layer (113); wherein the metal gate layer (114) contacts the p-type doped GaN layer (113) to form a Schottky barrier (115); The p-type doping concentration of the p-type doped GaN layer (113) is 1e18 cm -3 to 1e19cm -3 within the scope; The thickness of the p-type doped GaN layer (113) is less than 65 nanometers; The metal gate layer (114) is made of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W or any combination thereof in a stacked manner.

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