An ADC self-calibration based low temperature drift bandgap reference circuit

Abstract

The application discloses a low-temperature-drift bandgap reference based on ADC self-calibration, comprising a bandgap reference core circuit BGR, a programmable resistance array PRA, an analog-to-digital converter ADC, a temperature drift extraction circuit TDE and a feedback control circuit FBC; wherein the bandgap reference core circuit is used for generating a sampling reference voltage and an output reference voltage; the analog-to-digital converter is used for collecting the sampling reference voltage and quantizing; the temperature drift extraction circuit is used for extracting the change direction and size of the quantized reference voltage when the temperature change causes the sampling reference voltage to change and the quantized reference voltage output by the analog-to-digital converter changes, and generating a monitoring signal; the feedback control circuit is used for calculating a new control code according to the current control code and the monitoring signal; the programmable resistance array is used for adjusting the gating branch according to the control code output by the feedback control circuit to change the size of the load resistance, so as to adjust the output reference voltage, so that the output reference voltage remains constant.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of integrated circuits, and particularly relates to a low-temperature-drift bandgap reference circuit based on ADC self-calibration. BACKGROUND

[0002] The bandgap reference is widely used in analog circuits, digital circuits and mixed signal circuits, such as operational amplifiers, A / D converters, phase-locked loops and power converters, due to its high precision and temperature independence. The precision of the bandgap reference plays a crucial role in the performance of the subsequent circuits. For example, the bandgap reference circuit is used in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), which require high-precision reference voltages to provide high-resolution and high-speed data conversion. Therefore, the design of a high-precision low-temperature-drift bandgap reference circuit has become a problem of great concern.

[0003] Due to the second-order temperature characteristics of the transistor, the temperature drift of the conventional bandgap reference is difficult to be very low, and therefore some high-order curvature compensation techniques and segmented linear compensation techniques are proposed. However, the system is unstable, and the performance of the system under various PVT (process voltage temperature) cannot be guaranteed, often requiring trimming, which increases the cost and reduces the yield. SUMMARY

[0004] In order to solve the above problems in the prior art, the application provides a low-temperature-drift bandgap reference circuit based on ADC self-calibration. The technical problem to be solved by the application is solved by the following technical scheme:

[0005] A low-temperature-drift bandgap reference circuit based on ADC self-calibration, comprising:

[0006] a bandgap reference core circuit BGR, a programmable resistance array PRA, an analog-to-digital converter ADC, a temperature drift extraction circuit TDE and a feedback control circuit FBC; wherein,

[0007] the bandgap reference core circuit BGR is used to generate a sampling reference voltage and an output reference voltage;

[0008] the analog-to-digital converter ADC is used to collect the sampling reference voltage and quantize, and output the quantized reference voltage as a quantization result;

[0009] the temperature drift extraction circuit TDE is used to extract the change direction and size of the quantized reference voltage when the PVT changes cause the sampling reference voltage to change, and the quantized reference voltage output by the analog-to-digital converter ADC changes, and generate a monitoring signal;

[0010] the feedback control circuit FBC is used to calculate a new control code according to the current control code and the monitoring signal.

[0011] The programmable resistance array PRA is used to adjust the gating branch according to the control code output by the feedback control circuit FBC to change the size of the load resistance, so as to adjust the output reference voltage, so that the output reference voltage remains constant.

[0012] In an embodiment of the present application, the bandgap reference core circuit BGR comprises:

[0013] The operational amplifier, the transistor Q1, the transistor Q2, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the MOS tube M1, the MOS tube M2, the MOS tube M3, and the MOS tube M4; wherein,

[0014] The inverting input terminal of the operational amplifier is connected to node X, the non-inverting input terminal of the operational amplifier is connected to node Y, and the output terminal of the operational amplifier is connected to the first node;

[0015] The base of the transistor Q1 is connected to the base of the transistor Q2, the emitter of the transistor Q1 is connected to node X, and the collector of the transistor Q1 is connected to ground;

[0016] The emitter of the transistor Q2 is connected to the resistor R1, and the collector of the transistor Q2 is connected to ground;

[0017] One end of the resistor R1 is connected to the emitter of the transistor Q2, and the other end is connected to node Y;

[0018] One end of the resistor R2 is connected to node X, and the other end is connected to ground;

[0019] One end of the resistor R3 is connected to node Y, and the other end is connected to ground;

[0020] One end of the resistor R4 is connected to the drain of the MOS tube M3, and the other end is connected to ground;

[0021] The gate of the MOS tube M1 is connected to the first node, the source of the MOS tube M1 is connected to VDD, and the drain of the MOS tube M1 is connected to node X;

[0022] The gate of the MOS tube M2 is connected to the first node, the source of the MOS tube M2 is connected to VDD, and the drain of the MOS tube M2 is connected to node Y;

[0023] The gate of the MOS tube M3 is connected to the first node, the source of the MOS tube M3 is connected to VDD, and the drain of the MOS tube M3 is connected to the resistor R4;

[0024] The gate of the MOS tube M4 is connected to the first node, the source of the MOS tube M4 is connected to VDD, and the drain of the MOS tube M4 is connected to the programmable resistance array PRA.

[0025] In one embodiment of the present application, the bandgap reference core circuit BGR draws a sampling reference voltage between the drain of MOS transistor M3 and resistor R4, and draws an output reference voltage between the drain of MOS transistor M4 and the programmable resistance array PRA.

[0026] In one embodiment of the present application, the temperature drift extraction circuit TDE comprises:

[0027] The D flip-flop DFF1, the first complement calculation module complement1, the adder add1, the second complement calculation module complement2 and the selector sel; wherein,

[0028] The input end of the D flip-flop DFF1 receives the quantization result of the last time of the analog-to-digital converter ADC, and the output end of the D flip-flop DFF1 is connected to the input end of the first complement calculation module complement1.

[0029] The output end of the first complement calculation module complement1 is connected to the first input end of the adder add1.

[0030] The second input end of the adder add1 receives the quantization result of the current time of the analog-to-digital converter ADC, the first output end of the adder add1 is connected to the input end of the second complement calculation module complement2 and the second input end of the selector sel, and the second output end of the adder add1 is connected to the third input end of the selector sel.

[0031] The output end of the second complement calculation module complement2 is connected to the first input end of the selector sel.

[0032] The output end of the selector sel is connected to the input end of the OR gate in the feedback control circuit FBC, the first input end of the adder add2 and the first input end of the subtractor min, respectively.

[0033] In one embodiment of the present application, in the temperature drift extraction circuit TDE, the D flip-flop DFF1 saves the quantization result of the last time; the first complement calculation module complement1 takes the complement of the quantization result saved by the D flip-flop DFF1; the adder add1 adds the complement of the quantization result of the last time output by the first complement calculation module complement1 and the quantization result of the current time to output the sign bit and the sum result, and completes the subtraction operation; and the second complement calculation module complement2 outputs the complement of the sum result.

[0034] In one embodiment of the present application, in the temperature drift extraction circuit TDE, the selection module sel selects the corresponding result according to the sign bit output by the adder add1, if the sign bit is positive, the selection module sel outputs the sum result as the output digital code; if the sign bit is negative, the selection module sel outputs the complement of the sum result as the output digital code.

[0035] In one embodiment of the present application, the feedback control circuit FBC comprises:

[0036] The adder add2, the subtractor min, the OR gate OR, the D flip-flop DFF2 and the binary code thermometer code converter T_B; wherein,

[0037] The first input terminal of the adder add2 is connected with the output terminal of the selector sel in the temperature drift extraction circuit TDE, the second input terminal of the adder add2 is connected with the output terminal of the D flip-flop DFF2 in the feedback control circuit FBC, the third input terminal of the adder add2 receives the sign bit output by the adder add1 in the temperature drift extraction circuit TDE, and the output terminal of the adder add2 is connected with the second input terminal of the D flip-flop DFF2 in the feedback control circuit FBC;

[0038] The first input terminal of the subtractor min is connected with the output terminal of the selector sel in the temperature drift extraction circuit TDE, the second input terminal of the subtractor min is connected with the output terminal of the D flip-flop DFF2 in the feedback control circuit FBC, the third input terminal of the subtractor min receives the sign bit output by the adder add1 in the temperature drift extraction circuit TDE, and the output terminal of the subtractor min is connected with the second input terminal of the D flip-flop DFF2 in the feedback control circuit FBC;

[0039] The input terminal of the OR gate OR is connected with the output terminal of the selector sel in the temperature drift extraction circuit TDE, and the output terminal of the OR gate OR is connected with the first input terminal of the D flip-flop DFF2 in the feedback control circuit FBC;

[0040] The output terminal of the D flip-flop DFF2 is connected with the input terminal of the binary code thermometer code converter T_B;

[0041] The output terminal of the binary code thermometer code converter T_B is connected with the programmable resistance array PRA.

[0042] In one embodiment of the present application, in the feedback control circuit FBC, when the sign bit output by the temperature drift extraction circuit TDE is positive, the digital code output by the current D flip-flop DFF2 is added to the monitoring signal output by the temperature drift extraction circuit TDE using the adder add2 to calculate the output processing result; when the sign bit output by the temperature drift extraction circuit TDE is negative, the digital code output by the current D flip-flop DFF2 is subtracted from the monitoring signal output by the temperature drift extraction circuit TDE using the subtractor min to calculate the output processing result.

[0043] In one embodiment of the present application, in the feedback control circuit FBC, the D flip-flop DFF2 and the OR gate OR are combined, when the OR gate OR detects that the monitoring signal output by the temperature drift extraction circuit TDE changes, the control word of the D flip-flop DFF2 is valid, and the D flip-flop transmits the processing result to the input end of the binary code thermometer code converter T_B to prevent changes in the operation process from affecting the output result of the binary code thermometer code converter T_B.

[0044] Advantages of the present application:

[0045] 1. The ADC sub-calibration output reference voltage scheme proposed in the present application abstracts the work from analyzing the temperature characteristics of the bandgap reference internal triode, so that the ADC can detect changes in the sampling reference voltage and adjust the corresponding resistance through the feedback control circuit FBC, thereby suppressing changes in the output reference voltage. Regardless of PVT changes, the output reference voltage will remain unchanged, greatly improving system stability, eliminating the need for subsequent trimming, reducing costs, and improving yield.

[0046] 2. The present application adopts an innovative temperature drift extraction circuit, and the TDE module can cover all cases of bandgap sampling reference voltage changes, and control the output reference voltage to remain within a small range through the feedback control circuit. The TDE module uses the principle of complement operation, and the circuit structure is relatively simple, which can handle all change cases with one circuit mode, saving area and power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 The present application provides a low-temperature drift bandgap reference circuit based on ADC self-calibration.

[0048] Figure 2 The present application provides a bandgap reference core circuit BGR.

[0049] Figure 3 The present application provides a temperature drift extraction circuit TDE.

[0050] Figure 4A structural diagram of the feedback control circuit FBC provided by the embodiment of the present application is shown in the figure.

[0051] Figure 5 A circuit diagram of the programmable resistance array PRA provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0053] The low-temperature-drift bandgap reference circuit based on ADC self-calibration provided by the embodiment of the present application comprises:

[0054] a bandgap reference core circuit BGR, a programmable resistance array PRA, an analog-to-digital converter ADC, a temperature drift extraction circuit TDE, and a feedback control circuit FBC; wherein,

[0055] The bandgap reference core circuit BGR is configured to generate a sampling reference voltage and an output reference voltage.

[0056] The analog-to-digital converter ADC is configured to collect the sampling reference voltage and quantize the sampling reference voltage, and output the quantized reference voltage as a quantization result.

[0057] The temperature drift extraction circuit TDE is configured to extract a change direction and a size of the quantized reference voltage when the PVT variation causes the sampling reference voltage to change and the quantized reference voltage output by the analog-to-digital converter ADC changes, and generate a monitoring signal.

[0058] The feedback control circuit FBC is configured to calculate a new control code according to the current control code and the monitoring signal.

[0059] The programmable resistance array PRA is configured to adjust a gating branch according to the control code output by the feedback control circuit FBC to change the size of the load resistance, so as to adjust the output reference voltage, so that the output reference voltage remains constant.

[0060] The architecture diagram of the low-temperature-drift bandgap reference circuit based on ADC self-calibration is shown in the figure. Figure 1As shown, the working process of the following is briefly described: the bandgap reference core circuit BGR generates two reference voltages, the sampling reference voltage V refs The reference input of the calibrated ADC is provided for calibration, V ref The output reference voltage after calibration. The calibrated ADC samples V refs and quantizes, when the reference voltage V refs changes due to PVT changes, the ADC quantization result D out changes, the temperature drift extraction circuit TDE extracts the change direction and size of D out , generates output Q, the feedback control circuit FBC obtains the new control code k+1 according to the current control code k and the output Q of the temperature drift extraction circuit TDE, and thus selects the resistance array PRA to calibrate the output reference voltage V ref of the bandgap reference core circuit BGR.

[0061] For the sake of clear architecture, the following describes each part in the ADC self-calibration based low temperature drift bandgap reference circuit.

[0062] The bandgap reference core circuit BGR

[0063] The bandgap reference core circuit BGR as Figure 2 shown, comprises:

[0064] an operational amplifier, a transistor Q1, a transistor Q2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, and a MOS transistor M4; wherein,

[0065] the inverting input terminal of the operational amplifier is connected to node X, the non-inverting input terminal of the operational amplifier is connected to node Y, and the output terminal of the operational amplifier is connected to the first node;

[0066] the base of the transistor Q1 is connected to the base of the transistor Q2 and then grounded, the emitter of the transistor Q1 is connected to node X, and the collector of the transistor Q1 is grounded;

[0067] the emitter of the transistor Q2 is connected to the resistor R1, and the collector of the transistor Q2 is grounded;

[0068] one end of the resistor R1 is connected to the emitter of the transistor Q2, and the other end is connected to node Y;

[0069] one end of the resistor R2 is connected to node X, and the other end is connected to ground;

[0070] one end of the resistor R3 is connected to node Y, and the other end is connected to ground;

[0071] one end of the resistor R4 is connected to the drain of the MOS transistor M3, and the other end is connected to ground;

[0072] The gate of the MOS transistor M1 is connected to the first node, the source of the MOS transistor M1 is connected to VDD, and the drain of the MOS transistor M1 is connected to node X;

[0073] The gate of the MOS transistor M2 is connected to the first node, the source of the MOS transistor M2 is connected to VDD, and the drain of the MOS transistor M2 is connected to node Y;

[0074] The gate of the MOS transistor M3 is connected to the first node, the source of the MOS transistor M3 is connected to VDD, and the drain of the MOS transistor M3 is connected to resistor R4.

[0075] The gate of the MOS transistor M4 is connected to the first node, the source of the MOS transistor M4 is connected to VDD, and the drain of the MOS transistor M4 is connected to the programmable resistance array PRA.

[0076] The bandgap reference core circuit BGR draws a sampling reference voltage between the drain of the MOS transistor M3 and the resistor R4, and draws an output reference voltage between the drain of the MOS transistor M4 and the programmable resistance array PRA.

[0077] Specifically, initially, V refs and V ref are equal, and the control code k The gating, the reference voltage value is:

[0078] V refs = V ref = V ref0 = I ref *R S +R i

[0079] In the formula, V ref0 is the initial reference voltage, I ref is the reference current, R S is the resistance value of the series resistance R S in the programmable resistance array PRA, and R i represents the resistance value of the i (i=1, 2, 3...63) resistor in the programmable resistance array PRA.

[0080] The bandgap reference core circuit BGR adds the voltage with negative temperature coefficient and positive temperature coefficient to realize the removal of the temperature influence and realize the working voltage close to 0 temperature coefficient. It can be expressed by mathematical method as follows:

[0081] V ref =a1V1+a2V2

[0082] In the formula, V1 is the positive temperature coefficient voltage, V2 is the negative temperature coefficient voltage, and a1 and a2 are the corresponding coefficients.

[0083] In the application, the bandgap reference circuit realized by the resistance ratio is suitable.

[0084] In Figure 2 : the current flowing through R1 in the bandgap reference core circuit BGR is proportional to the voltage V BE of the transistor, which is a negative temperature coefficient, and the current flowing through R3 is proportional to the voltage change ΔV BE of the transistor, which is a positive temperature coefficient, and the proportion of the positive and negative temperature coefficients is adjusted by using R1 and R3, thereby generating a reference current independent of temperature. The output reference voltage is determined by the load resistance R4 and the PRA.

[0085] Analog-to-digital converter ADC

[0086] The analog-to-digital converter adopts a low-power high-precision analog-to-digital converter, and the analog-to-digital converter provides a quantization result greater than 14 bits at low frequency to detect the slight change of the reference voltage.

[0087] The analog-to-digital converter collects and quantizes the sampling reference voltage, and outputs the quantized reference voltage as the quantization result, and the quantization result of the ADC is D out .

[0088] Taking temperature change in PVT as an example, when the temperature changes, the reference voltage changes as follows:

[0089] V refs = V ref0 + ΔV = (I ref + ΔI) * R S + R i

[0090] In the formula, ΔV is the voltage change, and ΔI is the current change.

[0091] The quantization result of the ADC is D out + N, wherein N is the change amount of the quantization result.

[0092] The temperature drift extraction circuit TDE

[0093] The temperature drift extraction circuit TDE, as shown in the figure, comprises: Figure 3 A D flip-flop DFF1, a first complement calculation module complement1, an adder add1, a second complement calculation module complement2, and a selector sel; wherein,

[0094] The input end of the D flip-flop DFF1 receives the quantization result of the last time of the analog-to-digital converter ADC, and the output end of the D flip-flop DFF1 is connected to the input end of the first complement calculation module complement1.

[0095] The output end of the first complement calculation module complement1 is connected to the first input end of the adder add1.

[0096] The second input end of the adder add1 receives the quantization result of the current time of the analog-to-digital converter ADC, the first output end of the adder add1 is connected to the input end of the second complement calculation module complement2, and simultaneously connected to the second input end of the selector sel, and the second output end of the adder add1 is connected to the third input end of the selector sel.

[0097] The output end of the second complement calculation module complement2 is connected to the first input end of the selector sel.

[0098] The output end of the selector sel is respectively connected to the input end of the OR gate in the feedback control circuit FBC, the first input end of the adder add2, and the first input end of the subtracter min.

[0099] Principle of the temperature drift extraction circuit TDE: The temperature drift extraction circuit TDE extracts the change of the quantization result of the ADC, obtains the change direction and size of the reference voltage, and uses positive and negative to represent the change direction of the reference voltage.

[0100]

[0101] ​The temperature drift extraction circuit TDE extracts the size and sign of the variation N, the feedback control circuit FBC updates the control code according to the size and sign of N, and the k+i+N branch selects the output reference voltage to be calibrated as:

[0102] V ref =(I ref +ΔI)*(R S +R i+N )

[0103] Wherein, R i+N is the resistance value of the i+Nth resistor.

[0104] In the temperature drift extraction circuit TDE, the D flip-flop DFF1 stores the last quantization result, the first complement calculation module complement1 takes the complement of the quantization result stored by the D flip-flop DFF1, the adder add1 adds the complement of the last quantization result output by the first complement calculation module complement1 and the current quantization result to output the sign bit and the sum result, and completes the subtraction operation, and the second complement calculation module complement2 outputs the complement of the sum result.

[0105] The last sampling result is stored by the D flip-flop, the current quantization result and the last quantization result are subtracted, a sign bit and a subtraction result absolute value are generated, if the current quantization result is greater than the last quantization result, the sign bit is positive, and the subtraction result is output, if the current quantization result is less than the last quantization result, the sign bit is negative, and the negative of the subtraction result is output. That is, the size and direction of the reference voltage variation are obtained.

[0106] In the temperature drift extraction circuit TDE, the selection module sel selects the corresponding result according to the sign bit output by the adder add1, if the sign bit is positive, the selection module sel outputs the sum result as the output monitoring signal, if the sign bit is negative, the selection module sel outputs the complement of the sum result as the output monitoring signal.

[0107] Specific implementation: since the reference voltage variation caused by temperature change is very small, the ADC quantization result variation is in the low bit, so the subsequent digital processing module can adopt the low bit quantization result. Here, the low 6 bits are used for illustration. The last quantization result DT<5:0> is taken to obtain the complement DTc<5:0>. The current quantization result D<5:0> is added to obtain the sign bit S and the sum result O<5:0>, and the subtraction operation is completed. If S is positive, it indicates that the result is positive, and the subtractor result is the sum result O<5:0>; if S is negative, it indicates that the result is negative, and the subtractor result is the complement Oc<5:0> of the sum result.

[0108] The feedback control circuit FBC

[0109] The feedback control circuit FBC, as shown in Figure 4 comprises:

[0110] an adder add2, a subtractor min, an OR gate OR, a D flip-flop DFF2, and a binary code thermometer code converter T_B; wherein,

[0111] an output terminal of the selector sel in the temperature drift extraction circuit TDE is connected to a first input terminal of the adder add2, an output terminal of the D flip-flop DFF2 in the feedback control circuit FBC is connected to a second input terminal of the adder add2, a sign bit output by the adder add1 in the temperature drift extraction circuit TDE is received by a third input terminal of the adder add2, and an output terminal of the adder add2 is connected to a second input terminal of the D flip-flop DFF2 in the feedback control circuit FBC;

[0112] an output terminal of the selector sel in the temperature drift extraction circuit TDE is connected to a first input terminal of the subtractor min, an output terminal of the D flip-flop DFF2 in the feedback control circuit FBC is connected to a second input terminal of the subtractor min, a sign bit output by the adder add1 in the temperature drift extraction circuit TDE is received by a third input terminal of the subtractor min, and an output terminal of the subtractor min is connected to a second input terminal of the D flip-flop DFF2 in the feedback control circuit FBC;

[0113] an output terminal of the selector sel in the temperature drift extraction circuit TDE is connected to an input terminal of the OR gate OR, and an output terminal of the OR gate OR is connected to a first input terminal of the D flip-flop DFF2 in the feedback control circuit FBC;

[0114] an output terminal of the D flip-flop DFF2 is connected to an input terminal of the binary code thermometer code converter T_B;

[0115] an output terminal of the binary code thermometer code converter T_B is connected to the programmable resistance array PRA.

[0116] Principle of the feedback control circuit FBC: the monitoring signal output by the temperature drift extraction circuit TDE is converted into a control code for controlling the programmable resistance array.

[0117] When the sign bit output by the temperature drift extraction circuit TDE is positive, the digital code output by the current D flip-flop DFF2 is added to the monitoring signal output by the temperature drift extraction circuit TDE using the adder add2, and a processing result is output; when the sign bit output by the temperature drift extraction circuit TDE is negative, the digital code output by the current D flip-flop DFF2 is subtracted from the monitoring signal output by the temperature drift extraction circuit TDE using the subtractor min, and a processing result is output.

[0118] When the sign bit of the output of the temperature drift extraction circuit TDE is positive, the current digital code F<5:0> is added to the monitoring signal Q<5:0> output by the temperature drift extraction circuit TDE using the adder add2 to obtain the digital code C<5:0>; when the sign bit is negative, the current digital code F<5:0> is subtracted from the monitoring signal Q<5:0> using the subtracter min to obtain the digital code C<5:0>.

[0119] In the feedback control circuit FBC, the D flip-flop DFF2 and the OR gate OR are combined, when the OR gate OR detects that the monitoring signal output by the temperature drift extraction circuit TDE changes, the control word of the D flip-flop DFF2 is valid, and the D flip-flop transmits the processing result to the input end of the binary code thermometer code converter T_B to prevent changes in the operation process from affecting the output result of the binary code thermometer code converter T_B.

[0120] The feedback control circuit FBC detects the change of the monitoring signal Q<5:0> using the OR gate OR, when the monitoring signal Q<5:0> changes, the D flip-flop DFF2 clock control word T is valid, and the D flip-flop DFF2 transmits the operation result C<5:0> to F<5:0>, and outputs the control code k<63:1> after the binary to thermometer code module.

[0121] Programmable resistance array PRA

[0122] The programmable resistance array PRA, as shown in Figure 5 The control code k<63:1> generated by the temperature drift extraction circuit selects different branches to adjust the resistance, so as to adjust the output reference voltage, so that the output reference voltage remains constant.

[0123] When the reference current increases, the resistance of the selected branch decreases, so that the output reference voltage remains unchanged. Conversely.

[0124] The embodiment of the present application has the following advantages:

[0125] 1、The scheme of the ADC sub-calibration output reference voltage proposed in the present application abstracts the work from analyzing the temperature characteristics of the bandgap reference internal transistor, so that the ADC can detect the change when the sampling reference voltage changes, and adjust the corresponding resistance through the feedback control circuit FBC, so as to suppress the change of the output reference voltage. Regardless of the change of PVT (process voltage temperature), the output reference voltage will remain unchanged, the system stability is greatly improved, and subsequent trimming is not required, which reduces the cost and improves the yield.

[0126] 2、The application adopts an innovative temperature drift extraction circuit, the TDE module can cover all cases of band gap sampling reference voltage variation, the output reference voltage is controlled to keep in a small range through a feedback control circuit. The TDE module uses the principle of complement operation, the circuit structure is relatively simple, all change cases can be processed by one circuit mode, the area and power consumption are saved.

[0127] In addition, the terms "first", "second", etc. are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or an indicated number of technical features. Thus, features defined with "first", "second" can include one or more such features explicitly or implicitly. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0128] The above only describes the preferred embodiments of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A low-temperature drift bandgap reference circuit based on ADC self-calibration, characterized in that, include: The system includes a bandgap reference core circuit (BGR), a programmable resistor array (PRA), an analog-to-digital converter (ADC), a temperature drift extraction circuit (TDE), and a feedback control circuit (FBC); among these components... The bandgap reference core circuit BGR is used to generate the sampling reference voltage and the output reference voltage. The analog-to-digital converter (ADC) is used to acquire the sampled reference voltage and quantize it, and output the quantized reference voltage as the quantization result. The temperature drift extraction circuit (TDE) is used to extract the direction and magnitude of the change in the quantized reference voltage when a change in the PVT causes a change in the sampling reference voltage, and consequently a change in the quantized reference voltage output by the analog-to-digital converter (ADC), thereby generating a monitoring signal. The temperature drift extraction circuit (TDE) includes: The system consists of a D flip-flop (DFF1), a first two's complement calculation module (complement1), an adder (add1), a second two's complement calculation module (complement2), and a selector (sel). The input of the D flip-flop DFF1 receives the quantization result of the previous ADC, and the output of the D flip-flop DFF1 is connected to the input of the first complement calculation module complement1. The output of the first complement calculation module complement1 is connected to the first input of the adder add1; The second input of adder add1 receives the quantization result of the analog-to-digital converter ADC in the current iteration. The first output of adder add1 is connected to the input of the second complement calculation module complement2 and the second input of selector sel. The second output of adder add1 is connected to the third input of selector sel. The output of the second complement calculation module complement2 is connected to the first input of the selector sel; The output of the selector sel is connected to the input of the OR gate, the first input of the adder add2, and the first input of the subtractor min in the feedback control circuit FBC. The feedback control circuit FBC is used to calculate and output a new control code based on the current control code and the monitoring signal; The programmable resistor array PRA is used to adjust the selected branch according to the control code output by the feedback control circuit FBC to change the value of the load resistance, thereby adjusting the output reference voltage so that the output reference voltage remains constant.

2. The low-temperature drift bandgap reference circuit based on ADC self-calibration according to claim 1, characterized in that, The bandgap reference core circuit BGR includes: Operational amplifier, transistors Q1 and Q2, resistors R1, R2, R3, and R4, MOSFETs M1, M2, M3, and M4; among them, The inverting input of the operational amplifier is connected to node X, the non-inverting input of the operational amplifier is connected to node Y, and the output of the operational amplifier is connected to the first node. The base of transistor Q1 is connected to the base of transistor Q2 and then grounded. The emitter of transistor Q1 is connected to node X. The collector of transistor Q1 is grounded. The emitter of transistor Q2 is connected to resistor R1, and the collector of transistor Q2 is grounded. One end of resistor R1 is connected to the emitter of transistor Q2, and the other end is connected to node Y; One end of resistor R2 is connected to node X, and the other end is grounded; One end of resistor R3 is connected to node Y, and the other end is grounded; One end of resistor R4 is connected to the drain of MOSFET M3, and the other end is grounded; The gate of MOS transistor M1 is connected to the first node, the source of MOS transistor M1 is connected to VDD, and the drain of MOS transistor M1 is connected to the node X. The gate of MOS transistor M2 is connected to the first node, the source of MOS transistor M2 is connected to VDD, and the drain of MOS transistor M2 is connected to the node Y. The gate of MOSFET M3 is connected to the first node, the source of MOSFET M3 is connected to VDD, and the drain of MOSFET M3 is connected to the resistor R4. The gate of MOSFET M4 is connected to the first node, the source of MOSFET M4 is connected to VDD, and the drain of MOSFET M4 is connected to the programmable resistor array PRA.

3. The low-temperature drift bandgap reference circuit based on ADC self-calibration according to claim 2, characterized in that, The bandgap reference core circuit BGR draws out the sampling reference voltage between the drain of the MOS transistor M3 and the resistor R4; and draws out the output reference voltage between the drain of the MOS transistor M4 and the programmable resistor array PRA.

4. The low-temperature drift bandgap reference circuit based on ADC self-calibration according to claim 1, characterized in that, In the temperature drift extraction circuit TDE, the D flip-flop DFF1 stores the previous quantization result; the first complement calculation module complement1 takes the complement of the quantization result stored in the D flip-flop DFF1; the adder add1 adds the complement of the previous quantization result output by the first complement calculation module complement1 and the current quantization result to output the sign bit sum, thus completing the subtraction operation. The second complement calculation module complement2 outputs the complement of the summation result.

5. The low-temperature drift bandgap reference circuit based on ADC self-calibration according to claim 4, characterized in that, In the temperature drift extraction circuit TDE, the selector sel selects the corresponding output result according to the sign bit of the adder add1. If the sign bit is positive, the selector sel outputs the summation result as the output digital code. If the sign bit is negative, the selector sel outputs the two's complement of the summation result as the output numeric code.

6. The low-temperature drift bandgap reference circuit based on ADC self-calibration according to claim 5, characterized in that, The feedback control circuit FBC includes: Adder add2, subtractor min, OR gate, D flip-flop DFF2, and binary code thermometer code converter T_B; among them, The first input terminal of adder add2 is connected to the output terminal of selector sel in the temperature drift extraction circuit TDE, the second input terminal of adder add2 is connected to the output terminal of D flip-flop DFF2 in the feedback control circuit FBC, the third input terminal of adder add2 receives the sign bit output by add1 in the temperature drift extraction circuit TDE, and the output terminal of add2 is connected to the second input terminal of D flip-flop DFF2 in the feedback control circuit FBC; The first input terminal of the subtractor min is connected to the output terminal of the selector sel in the temperature drift extraction circuit TDE, the second input terminal of the subtractor min is connected to the output terminal of the D flip-flop DFF2 in the feedback control circuit FBC, the third input terminal of the subtractor min receives the sign bit output by the adder add1 in the temperature drift extraction circuit TDE, and the output terminal of the subtractor min is connected to the second input terminal of the D flip-flop DFF2 in the feedback control circuit FBC. The input of the OR gate is connected to the output of the selector sel in the temperature drift extraction circuit TDE, and the output of the OR gate is connected to the first input of the D flip-flop DFF2 in the feedback control circuit FBC. The output of the D flip-flop DFF2 is connected to the input of the binary code thermometer code converter T_B; The output of the binary code thermometer code converter T_B is connected to the programmable resistor array PRA.

7. The low-temperature drift bandgap reference circuit based on ADC self-calibration according to claim 6, characterized in that, In the feedback control circuit FBC, when the sign bit of the output of the temperature drift extraction circuit TDE is positive, the adder add2 is used to add the digital code output by the current D flip-flop DFF2 and the monitoring signal output by the temperature drift extraction circuit TDE to calculate and output the processing result; when the sign bit of the output of the temperature drift extraction circuit TDE is negative, the subtractor min is used to subtract the monitoring signal output by the temperature drift extraction circuit TDE from the digital code output by the current D flip-flop DFF2 to calculate and output the processing result.

8. The low-temperature drift bandgap reference circuit based on ADC self-calibration according to claim 7, characterized in that, In the feedback control circuit FBC, the D flip-flop DFF2 and the OR gate are combined. When the OR gate detects a change in the monitoring signal output by the temperature drift extraction circuit TDE, the control word of the D flip-flop DFF2 is valid. The D flip-flop transmits the processing result to the input of the binary code thermometer code converter T_B to prevent changes during the operation from affecting the output result of the binary code thermometer code converter T_B.

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