An in-situ compensation method for hardware accuracy issues in Skip Structure deep neural networks

Abstract

This invention discloses an in-situ compensation method for the hardware accuracy problem of Skip Structure deep neural networks, belonging to the field of memristor technology. The in-situ compensation method includes S1, determining the correlation coefficient of the compensation equation; S2, testing the relationship between the correlation coefficient and the output error; S3, performing data fitting based on the test data obtained in S2, and establishing the compensation equation; S4, when the array outputs the results, using the compensation equation established in S3 to perform in-situ compensation on the output results. The compensation method of this invention can solve the accuracy degradation problem caused by the layer-by-layer accumulation of errors when implementing Skip Structure deep neural networks with memristor arrays, thus having a significant optimization effect on the hardware implementation of skip structure neural networks.

Description

Technical Field

[0001] This invention belongs to the field of memristor technology, specifically relating to an in-situ compensation method for the hardware accuracy problem of Skip Structure deep neural networks. Background Technology

[0002] Deep neural networks have developed rapidly and have been applied in fields such as image recognition, speech recognition, and natural language processing. As the number of network layers increases, deep neural networks acquire more information and extract richer features. However, excessively deep neural networks suffer from gradient explosion and vanishing gradient problems, leading to errors during training and testing. To address this issue, Residual Networks (ResNet), proposed in 2015, uses a skip connection mechanism to directly transfer features from shallow layers to deeper layers, solving the gradient explosion and vanishing gradient problems. DenseNet (Densely connected convolutional networks) proposes an even denser connection mechanism than ResNet, further improving ResNet's feature reuse capability. Each layer receives additional input from all preceding layers and passes its own feature map to all subsequent layers. DenseNet achieves superior performance compared to ResNet with fewer parameters and lower computational costs. Following ResNet and DenseNet, better networks based on the Skip Connection concept, such as ResNeXt, DenseNet-B, and DenseNet-C, have been proposed. We collectively refer to them as Skip Structure deep neural networks.

[0003] While skip-structure deep neural networks offer significant advantages, their hardware implementation using memristor arrays inevitably presents challenges due to hardware non-ideals. Limited by the immature manufacturing technology of memristors, they are typically susceptible to interference from non-ideal factors such as write nonlinearity, inter-device variations, and periodicity. These non-ideal factors can lead to severe error aggregation in skip-structure deep neural networks, ultimately resulting in a significant decrease in prediction accuracy. Therefore, addressing the problem of error accumulation is the primary challenge in implementing skip-structure deep neural networks using memristor arrays. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide an in-situ compensation method for the hardware accuracy problem of Skip Structure deep neural networks. This method solves the accuracy degradation problem caused by the cumulative error of memristor arrays when implementing Skip Structure deep neural networks, and optimizes the hardware implementation of skip structure neural networks.

[0005] The objective of this invention can be achieved through the following technical solutions:

[0006] An in-situ compensation method for hardware accuracy issues in Skip Structure deep neural networks includes the following steps;

[0007] S1, determine the correlation coefficient of the compensation equation;

[0008] S2, tests the relationship between the correlation coefficient and the output error;

[0009] S3. Based on the test data obtained in S2, perform data fitting and establish a compensation equation;

[0010] S4 uses the compensation equation established in S3 to perform in-situ compensation on the output results when the array outputs.

[0011] Furthermore, in S1, based on the experiment: as the input voltage V increases, the number of array rows n turned on... row The change in the value of the memristor resistor R will have different effects on the array output. The preliminary determination is that the compensation equation should be related to the input voltage V and the number of array rows n. row It is also related to the value of the memristor resistance R.

[0012] Furthermore, in S2, the input voltage V and the number of array rows n to be enabled are determined by designing and executing a test plan. row And the influence of the memristor resistance value R on the array output error; the specific steps include:

[0013] S21, Set a fixed step size and test how the output error increases with the number of array rows n as the input voltage increases. row The relationship between the resistance value R of the memristor;

[0014] S22, set a fixed step size, and test the output error as the memristor resistance R increases, with the number of array rows n turned on. row The relationship between the input voltage magnitude V and the input voltage.

[0015] Furthermore, in S21, the specific test steps are as follows:

[0016] S211, Input voltage V input Set to 0.03V, input voltage is fixed and increased in steps of V.step Set to 0.03V, memristor resistance value is fixed, increase step size R. step Set to 5KΩ;

[0017] S212, the memristor resistance R is set to 5KΩ;

[0018] S213, the number of rows to open in the array is n row Set to 1;

[0019] S214, Measure the actual array output current I under the current parameter settings. actual and ideal output current I ideal And calculate the error I between the two. error =I ideal -I actual Increment the number of rows to be enabled in the array by 1.

[0020] S215, determine whether the current number of open rows of the array exceeds the maximum number of open rows of the array, 32; if the number of open rows of the array does not exceed the maximum number of open rows of the array, proceed to S214, otherwise proceed to S216;

[0021] S216, according to a fixed step size R step Increase the resistance of the memristor once;

[0022] S217: Determine if the current memristor resistance is greater than the upper limit of 50KΩ. If the memristor resistance does not exceed the upper limit, proceed to S213; otherwise, proceed to S218.

[0023] S218, according to a fixed step size V step Increase the input voltage once;

[0024] S219: Determine if the current input voltage is greater than the upper limit of input voltage by 0.3V; if the input voltage does not exceed the upper limit of input voltage, proceed to S212; otherwise, end the test.

[0025] Furthermore, the specific test steps in S22 are as follows:

[0026] S221, the memristor resistance R is set to 5KΩ, the input voltage is fixed and the step size V is increased. step Set to 0.001V, memristor resistance value is fixed, incremented by step size R. step Set to 5KΩ;

[0027] S222, Input voltage V input Set to 0.001V;

[0028] S223, the number of rows to open in the array is n row Set to 1;

[0029] S224, Measure the actual array output current I under the current parameter settings. actual and ideal output current I ideal And calculate the error I between the two. error =I ideal -I actual Increment the number of rows to be enabled in the array by 1.

[0030] S225, determine whether the current number of open rows of the array exceeds the maximum number of open rows of the array, 32; if the number of open rows of the array does not exceed the maximum number of open rows of the array, proceed to S224, otherwise proceed to S226;

[0031] S226, according to a fixed step size V step Increase the input voltage once;

[0032] S227: Determine if the current input voltage is greater than the upper limit of the input voltage by 0.2V; if the input voltage does not exceed the upper limit of the input voltage, proceed to S223; otherwise, proceed to S228.

[0033] S228, according to a fixed step size R step Increase the resistance of the memristor once;

[0034] S229: Determine if the current memristor resistance is greater than the upper limit of 50KΩ. If the memristor resistance is not greater than the upper limit, proceed to S222; otherwise, end the test.

[0035] Furthermore, in S3, based on the data measured in S2, the most suitable fitting method for the two sets of data is selected, and linear and nonlinear fittings are performed on them respectively, to obtain the output error corresponding to the linear and nonlinear fittings in relation to the input voltage V and the number of array rows n. row And the relationship between the resistance value R of the memristor.

[0036] 7. The in-situ compensation method for the hardware accuracy problem of Skip Structure deep neural networks according to claim 6, characterized in that the compensation equation includes four in-situ compensation schemes, namely:

[0037] The first compensation scheme: only perform linear compensation on the output;

[0038] The second compensation scheme: only perform nonlinear compensation on the output;

[0039] The third compensation scheme is to compensate the output, with the compensation value being the average of the linear and nonlinear compensations.

[0040] The fourth compensation scheme: compensate the output, and the compensation value is the result of solving the ordinary differential equation after linear compensation and nonlinear compensation.

[0041] Furthermore, the steps for establishing the compensation equation are as follows:

[0042] S31, Determine the ideal output I of the array ideal Array actual output I actual and compensation value M compensation The relationship between I and ideal =I actual +M compensation ;

[0043] S32, based on the data measured in S21, with array output error I error Let n be the number of rows to open in the array, and let n be the number of rows to open in the array. row Using the memristor resistance R and input voltage V as independent variables, a nonlinear fitting was performed to obtain the array output error I when the memristor resistance R and input voltage V took different values. error Nonlinear relationship between input voltage V and Let the compensation value That is, to complete the establishment of the nonlinear compensation equation;

[0044] S33, based on the data measured in S22, with array output error I error Using the input voltage V as the independent variable and applying linear fitting, the memristor resistance R and the number of array rows n are obtained. row The array output error I varies depending on the value of I. error Linear relationship between input voltage V and Let the compensation value That is, to complete the establishment of the linear compensation equation;

[0045] S34, take the average of the linear compensation value and the nonlinear compensation value, that is, let the compensation value... Complete the establishment of the third compensation equation;

[0046] S35, solve the ordinary differential equations for linear and nonlinear compensation, and let the compensation value... Complete the establishment of the fourth compensation equation;

[0047] The final compensation equation is:

[0048]

[0049] Furthermore, in S4, the four in-situ compensation schemes determined in S3 are used to compensate the output current. By comparing the output error of the array before and after compensation, it is determined that the present invention has the effect of optimizing the problem of large output error in the hardware implementation of the skip-type deep neural network.

[0050] An in-situ compensation system for the hardware accuracy problem of Skip Structure deep neural networks includes:

[0051] Coefficient confirmation unit: used to determine the correlation coefficients of the compensation equation;

[0052] Test unit: Used to test the relationship between the correlation coefficient and the output error;

[0053] Equation establishment unit: Based on the test data obtained from the test unit, perform data fitting and establish compensation equations;

[0054] Compensation Unit: When the array outputs results, the compensation equation established in the equation establishment unit is used to perform in-situ compensation on the output results.

[0055] The beneficial effects of this invention are:

[0056] The compensation method of this invention can solve the problem of accuracy degradation caused by the accumulation of errors in the implementation of Skip Structure deep neural networks using memristor arrays, thus greatly optimizing the hardware implementation of skip structure neural networks. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a schematic diagram of the in-situ compensation method of the present invention;

[0059] Figure 2 This is a flowchart illustrating the data testing scheme of the present invention;

[0060] Figure 3 This is a flowchart illustrating the second data testing scheme of the present invention;

[0061] Figure 4 This is a schematic diagram illustrating the process of establishing the compensation equation of the present invention. Detailed Implementation

[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] like Figure 1 As shown, an in-situ compensation method for the hardware accuracy problem of Skip Structure deep neural networks includes the following steps:

[0064] S1, determine the correlation coefficient of the compensation equation;

[0065] In this step, the present invention is based on the phenomenon observed in experiments, namely, as the input voltage V and the number of array rows n are turned on... row The change in the value of the memristor resistor R will have different effects on the array output. The preliminary determination is that the compensation equation should be related to the input voltage V and the number of array rows n. row It is also related to the value of the memristor resistance R.

[0066] S2, tests the relationship between the correlation coefficient and the output error;

[0067] By designing and executing a test plan, the input voltage V and the number of array rows n to be enabled were determined. row And the relationship between the memristor resistance value R and the array output error;

[0068] S21, with a fixed step size of 0.03V, this invention tested the output error as the input voltage increased from 0.03V to 0.3V, and how it varied with the number of array rows n. row The relationship between the memristor's resistance value R and the test procedure is as follows: Figure 2 As shown;

[0069] The specific testing steps are as follows:

[0070] S211, Input voltage V input Set to 0.03V, input voltage is fixed and increased in steps of V. step Set to 0.03V, memristor resistance value is fixed, increase step size R. step Set to 5KΩ.

[0071] S212, the memristor resistance R is set to 5KΩ.

[0072] S213, the number of rows to open in the array is n row Set to 1.

[0073] S214, Measure the actual array output current I under the current parameter settings. actual and ideal output current I ideal And calculate the error I between the two. error =I ideal -I actual Increment the number of rows to be enabled in the array by 1.

[0074] S215, determine whether the current number of open rows of the array exceeds the maximum number of open rows of the array, which is 32. If the number of open rows of the array does not exceed the maximum number of open rows of the array, proceed to S214; otherwise, proceed to S216.

[0075] S216, according to a fixed step size R step Increase the resistance of the memristor once.

[0076] S217 checks if the current memristor resistance is greater than the upper limit of 50KΩ. If the memristor resistance is not greater than the upper limit, proceed to S213; otherwise, proceed to S218.

[0077] S218, according to a fixed step size V step Increase the input voltage once.

[0078] S219: Determine if the current input voltage is greater than the upper limit of 0.3V. If the input voltage does not exceed the upper limit, proceed to S212; otherwise, end the test.

[0079] S22, with a fixed step size of 5KΩ, this invention tested the output error as the memristor resistance R increased from 5KΩ to 50KΩ, depending on the number of array rows n. row The relationship between the input voltage magnitude V and the test procedure is as follows: Figure 3 As shown;

[0080] The specific testing steps are as follows:

[0081] S221, the memristor resistance R is set to 5KΩ, the input voltage is fixed and the step size V is increased. step Set to 0.001V, memristor resistance value is fixed, incremented by step size R. step Set to 5KΩ.

[0082] S222, Input voltage V input Set to 0.001V.

[0083] S223, the number of rows to open in the array is n row Set to 1.

[0084] S224, Measure the actual array output current I under the current parameter settings. actual and ideal output current I ideal And calculate the error I between the two. error =I ideal -I actual Increment the number of rows to be enabled in the array by 1.

[0085] S225, determine whether the current number of open rows of the array exceeds the maximum number of open rows of the array, which is 32. If the number of open rows of the array does not exceed the maximum number of open rows of the array, proceed to S224; otherwise, proceed to S226.

[0086] S226, according to a fixed step size V step Increase the input voltage once.

[0087] S227: Determine if the current input voltage is greater than the upper limit of 0.2V. If the input voltage does not exceed the upper limit, proceed to S223; otherwise, proceed to S228.

[0088] S228, according to a fixed step size R step Increase the resistance of the memristor once.

[0089] S229 checks if the current memristor resistance is greater than the upper limit of 50KΩ. If the memristor resistance is not greater than the upper limit, proceed to S222; otherwise, end the test.

[0090] S3. Based on the test data obtained in S2, perform data fitting and establish a compensation equation;

[0091] like Figure 4 As shown, based on the data measured by S2, the most suitable fitting method for the two sets of data is selected, and linear and nonlinear fitting are performed respectively. The output error corresponding to linear and nonlinear fitting is obtained in relation to the input voltage V and the number of array rows n. row And the relationship between the resistance value R of the memristor;

[0092] The compensation equation includes four in-situ compensation schemes, namely:

[0093] The first compensation scheme: only perform linear compensation on the output;

[0094] The second compensation scheme: only perform nonlinear compensation on the output;

[0095] The third compensation scheme is to compensate the output, with the compensation value being the average of the linear and nonlinear compensations.

[0096] The fourth compensation scheme: compensate the output, and the compensation value is the result of solving the ordinary differential equation after linear compensation and nonlinear compensation.

[0097] The specific steps for establishing the compensation equation are as follows:

[0098] S31, Determine the ideal output I of the array ideal Array actual output I actual and compensation value M compensation The relationship between I and ideal =I actual +M compensation ;

[0099] S32, based on the data measured in S21, with array output error I errorLet n be the number of rows to open in the array, and let n be the number of rows to open in the array. row Using the memristor resistance R and input voltage V as independent variables, a nonlinear fitting was performed to obtain the array output error I when the memristor resistance R and input voltage V took different values. error Nonlinear relationship between input voltage V and Let the compensation value That is, to complete the establishment of the nonlinear compensation equation;

[0100] S33, based on the data measured in S22, with array output error I error Using the input voltage V as the independent variable and applying linear fitting, the memristor resistance R and the number of array rows n are obtained. row The array output error I varies depending on the value of I. error Linear relationship between input voltage V and Let the compensation value That is, to complete the establishment of the linear compensation equation;

[0101] S34, take the average of the linear compensation value and the nonlinear compensation value, that is, let the compensation value... Complete the establishment of the third compensation equation;

[0102] S35, solve the ordinary differential equations for linear and nonlinear compensation, and let the compensation value... Complete the establishment of the fourth compensation equation;

[0103] The final compensation equation is:

[0104]

[0105] S4, when the array outputs the results, uses the four compensation equations established in S3 to perform in-situ compensation on the output results;

[0106] The output current was compensated using the four in-situ compensation schemes determined by S3. By comparing the output error of the array before and after compensation, it was determined that the present invention has the effect of optimizing the large output error of the jump-type deep neural network in hardware implementation.

[0107] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0108] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. An in-situ compensation method for hardware accuracy issues in Skip Structure deep neural networks, characterized in that, Includes the following steps; S1, determine the correlation coefficient of the compensation equation; S2, tests the relationship between the correlation coefficient and the output error; S3. Based on the test data obtained in S2, perform data fitting and establish a compensation equation; S4, when the array outputs the results, uses the compensation equation established in S3 to perform in-situ compensation on the output results; In S1, based on the experiment: as the input voltage V and the number of array rows n are turned on... row The change in the value of the memristor resistor R will have different effects on the array output. The preliminary determination is that the compensation equation should be related to the input voltage V and the number of array rows n. row And it is related to the value of the memristor resistance R; In S2, the input voltage V and the number of array rows n to be enabled are determined by designing and executing a test plan. row And the influence of the memristor resistance value R on the array output error; the specific steps include: S21, Set a fixed step size and test how the output error increases with the number of array rows n as the input voltage increases. row The relationship between the resistance value R of the memristor; S22, set a fixed step size, and test the output error as the memristor resistance R increases, with the number of array rows n turned on. row The relationship between the input voltage magnitude V and the input voltage magnitude V; In S3, based on the data measured in S2, the most suitable fitting method for the two sets of data is selected, and linear and nonlinear fittings are performed respectively. The output error corresponding to the linear and nonlinear fittings is obtained in relation to the input voltage V and the number of array rows n. row And the relationship between the resistance value R of the memristor.

2. The in-situ compensation method for the hardware accuracy problem of Skip Structure deep neural networks according to claim 1, characterized in that, In S21, the specific test steps are as follows: S211, Input voltage V input Set to 0.03V, input voltage is fixed and increased in steps of V. step Set to 0.03V, memristor resistance value is fixed, increase step size R. step Set to 5KΩ; S212, the memristor resistance R is set to 5KΩ; S213, the number of rows to open in the array is n row Set to 1; S214, Measure the actual array output current I under the current parameter settings. actual and ideal output current I ideal And calculate the error I between the two. error =I ideal -I actual Increment the number of rows to be enabled in the array by 1. S215, determine whether the current number of open rows of the array exceeds the maximum number of open rows of the array, 32; if the number of open rows of the array does not exceed the maximum number of open rows of the array, proceed to S214, otherwise proceed to S216. S216, according to a fixed step size R step Increase the resistance of the memristor once; S217: Determine if the current memristor resistance is greater than the upper limit of 50KΩ. If the memristor resistance does not exceed the upper limit, proceed to S213; otherwise, proceed to S218. S218, according to a fixed step size V step Increase the input voltage once; S219: Determine if the current input voltage is greater than the upper limit of input voltage by 0.3V; if the input voltage does not exceed the upper limit of input voltage, proceed to S212; otherwise, end the test.

3. The in-situ compensation method for the hardware accuracy problem of Skip Structure deep neural networks according to claim 1, characterized in that, The specific test steps in S22 are as follows: S221, the memristor resistance R is set to 5KΩ, the input voltage is fixed and the step size V is increased. step Set to 0.001V, memristor resistance value is fixed, incremented by step size R. step Set to 5KΩ; S222, Input voltage V input Set to 0.001V; S223, the number of rows to open in the array is n row Set to 1; S224, Measure the actual array output current I under the current parameter settings. actual and ideal output current I ideal And calculate the error I between the two. error =I ideal -I actual Increment the number of rows to be enabled in the array by 1. S225, determine whether the current number of open rows of the array exceeds the maximum number of open rows of the array, 32; if the number of open rows of the array does not exceed the maximum number of open rows of the array, proceed to S224, otherwise proceed to S226; S226, according to a fixed step size V step Increase the input voltage once; S227: Determine if the current input voltage is greater than the upper limit of the input voltage by 0.2V; if the input voltage does not exceed the upper limit of the input voltage, proceed to S223; otherwise, proceed to S228. S228, according to a fixed step size R step Increase the resistance of the memristor once; S229: Determine if the current memristor resistance is greater than the upper limit of 50KΩ. If the memristor resistance is not greater than the upper limit, proceed to S222; otherwise, end the test.

4. The in-situ compensation method for the hardware accuracy problem of Skip Structure deep neural networks according to claim 1, characterized in that, The compensation equation includes four in-situ compensation schemes, namely: The first compensation scheme: only perform linear compensation on the output; The second compensation scheme: only perform nonlinear compensation on the output; The third compensation scheme is to compensate the output, with the compensation value being the average of the linear and nonlinear compensations. The fourth compensation scheme: compensate the output, and the compensation value is the result of solving the ordinary differential equation after linear compensation and nonlinear compensation.

5. The in-situ compensation method for the hardware accuracy problem of Skip Structure deep neural networks according to claim 4, characterized in that, The steps for establishing the compensation equation are as follows: S31, Determine the ideal output I of the array ideal Array actual output I actual and compensation value M compensation The relationship between I and ideal =I actual +M compensation ; S32, based on the data measured in S21, with array output error I error Let n be the number of rows to open in the array, and let n be the number of rows to open in the array. row Using the memristor resistance R and input voltage V as independent variables, a nonlinear fitting was performed to obtain the array output error I when the memristor resistance R and input voltage V took different values. error Nonlinear relationship between input voltage V and Let the compensation value Among them, a (V,R) b (V,R) and c (V,R) These are three coefficients determined by the array input voltage V and the memristor resistance R, which complete the establishment of the nonlinear compensation equation; S33, based on the data measured in S22, with array output error I error Using the input voltage V as the independent variable and applying linear fitting, the memristor resistance R and the number of array rows n are obtained. row The array output error I varies depending on the value of I. error Linear relationship between input voltage V and input voltage V Let the compensation value in, and It is determined by the number of open rows n of the array row The two coefficients determined by the memristor resistance value R are used to establish the linear compensation equation. S34, take the average of the linear compensation value and the nonlinear compensation value, that is, let the compensation value... Complete the establishment of the third compensation equation; S35, solve the ordinary differential equations for linear and nonlinear compensation, and let the compensation value... Among them, p and q are two coefficients obtained by solving the ordinary differential equation, which complete the establishment of the fourth compensation equation; The final compensation equation is: Where x and y are the nonlinear compensations, respectively. and linear compensation The coefficient, the specific value of which is determined by the compensation scheme.

6. The in-situ compensation method for the hardware accuracy problem of Skip Structure deep neural networks according to claim 5, characterized in that, In S4, the four in-situ compensation schemes determined in S3 are used to compensate the output current. By comparing the output error of the array before and after compensation, the effect of optimizing the large output error of the jump-type deep neural network in hardware implementation is determined.

7. An in-situ compensation system for the hardware accuracy problem of Skip Structure deep neural networks, comprising performing the in-situ compensation method according to any one of claims 1-6, characterized in that, include: Coefficient confirmation unit: used to determine the correlation coefficients of the compensation equation; Test unit: Used to test the relationship between the correlation coefficient and the output error; Equation establishment unit: Based on the test data obtained from the test unit, perform data fitting and establish compensation equations; Compensation Unit: When the array outputs results, the compensation equation established in the equation establishment unit is used to perform in-situ compensation on the output results.

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