Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a first substrate, the first substrate including opposite first and second surfaces, and having a first ion in the first substrate, the first ion having a first concentration; forming a first epitaxial layer on the first surface of the first substrate, the first epitaxial layer having a second ion, the second ion having a second concentration, the second concentration being less than the first concentration; forming a second epitaxial layer on the first epitaxial layer and a third epitaxial layer on the second epitaxial layer, the second epitaxial layer having a third ion, the third ion having a third concentration, the third epitaxial layer having a fourth ion, the fourth ion having a fourth concentration, the fourth concentration being less than the third concentration; thinning the first substrate from the second surface of the first substrate until the surface of the second epitaxial layer is exposed. The present invention can meet the requirements for fabricating the substrate of the semiconductor structure while ensuring the thickness uniformity of thinning, which is beneficial to improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to a method for forming a semiconductor structure. Background Art

[0002] An image sensor can be used to sense radiation (e.g., optical radiation, including but not limited to visible light, infrared light, ultraviolet light, etc.). Image sensors can be classified into back-illuminated (BSI) image sensors and front-illuminated (FSI) image sensors according to the way they receive radiation.

[0003] A BSI image sensor can receive radiation from its back surface. Different from an FSI image sensor, in a BSI image sensor, components such as wirings that may affect radiation reception are basically located on the front surface of the substrate, and light enters from the back surface of the substrate.

[0004] For a BSI image sensor, it is generally formed by the following steps currently: growing an epitaxial layer on a substrate, fabricating a photosensing device (e.g., a photodiode) on the epitaxial layer, and then removing the substrate from the back surface, where the epitaxial layer is used as a stop layer for substrate removal. However, in the case of fabricating a BSI image sensor using a substrate and the epitaxial layer on the substrate, only a part of the low-doped epitaxial layer will be finally retained, affecting the performance of the finally formed image sensor.

[0005] Therefore, a method for forming a semiconductor structure is needed, which can realize a structure with a low-doped epitaxial layer and a high-doped substrate. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which is beneficial to improving the performance of the finally formed semiconductor structure.

[0007] To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a first substrate, the first substrate including opposite first and second surfaces, and the first substrate having first ions with a first concentration therein; forming a first epitaxial layer on the first surface of the first substrate, the first epitaxial layer having second ions with a second concentration therein, the second concentration being less than the first concentration; forming a second epitaxial layer and a third epitaxial layer located on the second epitaxial layer on the first epitaxial layer, the second epitaxial layer having third ions with a third concentration therein, the third epitaxial layer having fourth ions with a fourth concentration therein, the fourth concentration being less than the third concentration; thinning the first substrate from the second surface of the first substrate until the surface of the second epitaxial layer is exposed.

[0008] Optionally, the steps of the thinning process include: etching the first substrate from the second surface of the first substrate until the surface of the first epitaxial layer is exposed; planarizing the first epitaxial layer until the surface of the second epitaxial layer is exposed.

[0009] Optionally, the etching process is wet etching; the process parameters of the wet etching process include: the etching solution includes an HNA solution, and the HNA solution is a mixed solution formed by hydrofluoric acid, nitric acid, and acetic acid.

[0010] Optionally, the planarization process is chemical mechanical polishing; the process parameters of the chemical mechanical polishing include: selecting a SiO2 polishing solution, and the polishing time is 50 to 100 seconds.

[0011] Optionally, the conduction types of the first ion and the second ion are opposite.

[0012] Optionally, the conduction types of the third ion and the fourth ion are the same.

[0013] Optionally, the first ion is a P-type ion; the P-type ion includes one or more of boron ions, indium ions, and gallium ions.

[0014] Optionally, the second ion is an N-type ion; the N-type ion includes one or more of phosphorus ions, arsenic ions, and antimony ions.

[0015] Optionally, the third ion is a P-type ion; the fourth ion is a P-type ion; the P-type ion includes one or more of boron ions, indium ions, and gallium ions.

[0016] Optionally, the range of the first concentration is 2E18 to 5E18 atoms / cm 3 。

[0017] Optionally, the range of the second concentration is 5E12 to 1E15 atoms / cm 3 。

[0018] Optionally, the range of the third concentration is 6E17 to 5E18 atoms / cm 3 。

[0019] Optionally, the range of the fourth concentration is 1E13 to 2E14 atoms / cm 3 。

[0020] Optionally, the thickness range of the first epitaxial layer is 1 to 3 micrometers.

[0021] Optionally, the thickness range of the second epitaxial layer is 1 to 5 micrometers.

[0022] Optionally, the thickness range of the third epitaxial layer is 4 to 10 microns.

[0023] Optionally, the third epitaxial layer includes a third surface facing away from the second epitaxial layer. Before thinning the first substrate, it further includes: forming a plurality of photoelectric doping regions in the third epitaxial layer; forming a first dielectric layer covering the third surface of the third epitaxial layer and the photoelectric doping regions; and forming an electrical interconnection structure in the first dielectric layer.

[0024] Optionally, after forming the interconnection layer, it further includes: providing a second substrate; bonding the first surface of the first substrate to the second substrate.

[0025] Optionally, the second epitaxial layer includes a fourth surface in contact with the first epitaxial layer. After thinning the first substrate, it further includes: forming a second dielectric layer on the fourth surface of the second epitaxial layer; forming a through hole in the second dielectric layer, the second epitaxial layer, and the third epitaxial layer to expose the first dielectric layer; forming a contact hole at the bottom of the through hole and in the first dielectric layer to expose the electrical interconnection structure; and forming a conductive layer in the through hole and the contact hole.

[0026] Optionally, it further includes: forming a plurality of filter films on the second dielectric layer and lenses on the filter films.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] A first epitaxial layer is formed on the first surface of the first substrate, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The second concentration of the second ions in the first epitaxial layer is less than the first concentration of the first ions in the first substrate, and the third concentration of the third ions in the second epitaxial layer is greater than the fourth concentration of the fourth ions in the third epitaxial layer. Thinning the first substrate from the second surface of the first substrate, due to the ion concentration difference between the first epitaxial layer and the first substrate, the thinning process will first stop at the first epitaxial layer, which can control the thickness uniformity of the thinning process. Subsequently, continue thinning until the surface of the second epitaxial layer is exposed, making the second epitaxial layer a flat surface; and the thinning process removes the first substrate and the first epitaxial layer, retaining the second epitaxial layer and the third epitaxial layer, and the third concentration is greater than the fourth concentration. Subsequently, after forming pixel units in the third epitaxial layer, when a reverse bias voltage is applied during the operation of the pixel units, due to the presence of the second epitaxial layer, it can prevent the formed depletion region from diffusing to the interface of the thinning process, while improving the thickness uniformity of the thinning process, and meeting the substrate requirements for manufacturing an image sensor, which is beneficial to the performance of the finally formed semiconductor structure.

[0029] Further, the first ion and the second ion have opposite conduction types. By forming a first epitaxial layer having an opposite conduction type to that of the first substrate, the boundary between the first substrate and the first epitaxial layer can be made clearer, avoiding the boundary from becoming blurred due to ion diffusion during some heat treatment processes, so that the first epitaxial layer can better serve as an etch stop layer. Description of the Drawings

[0030] Figures 1 to 8 Schematic diagrams corresponding to the steps of the method for forming a semiconductor structure in an embodiment of the present invention. Detailed Embodiments

[0031] As can be seen from the background art, the specific method for forming a BSI image sensor currently includes:

[0032] Providing a first substrate, the first substrate includes opposite first and second surfaces, and the first substrate has a first ion therein, and the ion has a first concentration; forming an epitaxial layer on the first surface, the epitaxial layer includes opposite third and fourth surfaces, the fourth surface of the epitaxial layer is in contact with the first surface of the first substrate, the epitaxial layer has a second ion therein, and the second ion has a second concentration, and the second concentration is less than the first concentration; forming a plurality of pixel units isolated from each other, a dielectric layer covering the third surface of the epitaxial layer and the pixel units, and an interconnect layer located in the dielectric layer on the third surface of the epitaxial layer, wherein each pixel unit includes a light-emitting diode and a plurality of MOS transistors; providing a second substrate, bonding the second substrate to the first substrate in the first surface direction, and then flipping the second substrate so that the second surface of the first substrate faces upward; thinning the first substrate from the second surface of the first substrate.

[0033] Currently, the thinning process of the first substrate usually uses the method of using the epitaxial layer as an etch stop layer. Since the thinning rate is very sensitive to the ion concentration, when thinning to the concentration gradient layer, the thinning rate will drop suddenly, so that the thinning stops at the junction of the first substrate and the epitaxial layer. Using the thinning process stopped by the epitaxial layer will eventually completely remove the first substrate, and there will be many lattice defects at the interface where the thinning stops, that is, the fourth surface of the epitaxial layer. When the finally formed image sensor is working, a reverse bias voltage will be applied to the light-emitting diode. Therefore, a depletion region will be formed in the epitaxial layer. When the applied reverse bias voltage is relatively large, the depletion region will extend to the lattice defects on the fourth surface of the epitaxial layer, resulting in the generation of dark current, which is not conducive to the performance of the image sensor.

[0034] If, in order to prevent the depletion region from extending to the interface where the thinning process stops, it is desired to retain a portion of the first substrate with a relatively high ion concentration without using an epitaxial layer stop thinning process, when thinning the first substrate, it is necessary to independently control the thinning stop interface, which easily causes a problem of poor thickness uniformity of the remaining first substrate after thinning, and will also affect the performance of the sensor.

[0035] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure. A first epitaxial layer, a second epitaxial layer located on the first epitaxial layer, and a third epitaxial layer located on the second epitaxial layer are formed on a first substrate. The second concentration of the second ions in the first epitaxial layer is less than the first concentration of the first ions in the first substrate, and the third concentration of the third ions in the second epitaxial layer is greater than the fourth concentration of the fourth ions in the third epitaxial layer. When thinning the first substrate, on the one hand, due to the ion concentration difference between the first epitaxial layer and the first substrate, the thinning process will first stop at the junction between the first epitaxial layer and the first substrate, and then continue the thinning process until the surface of the second epitaxial layer is exposed, which is beneficial to controlling the uniformity of the thinning thickness; on the other hand, the second epitaxial layer and the third epitaxial layer are still retained after the thinning process, and the third concentration is greater than the fourth concentration. Subsequently, after forming pixel units in the third epitaxial layer, when a reverse bias voltage is applied during the operation of the pixel units, due to the presence of the second epitaxial layer with a relatively large ion concentration, the formed depletion region can be prevented from extending to the lattice defects at the thinning process interface, reducing the generation of dark current, thereby being beneficial to improving the performance of the semiconductor structure.

[0036] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0037] Refer to Figure 1 , a first substrate 100 is provided. The first substrate 100 includes opposite first surface 101 and second surface 102, and the first substrate 100 has first ions with a first concentration.

[0038] The first substrate 100 may be a silicon substrate, or a germanium, germanium-silicon, gallium arsenide substrate, or silicon-on-insulator substrate. Those skilled in the art can select the substrate type according to needs. Therefore, the type of the first substrate should not be a feature that limits the protection scope of the present invention. In this embodiment, the first substrate 10 is a silicon substrate.

[0039] In this embodiment, the first substrate 100 is P-type doped, that is, the first ions are P-type ions; the P-type ions include one or more of boron ions, indium ions, and gallium ions.

[0040] The range of the first concentration of the first ions is 2E18~5E18atoms / cm 3 .

[0041] The thickness range of the first substrate 100 is 725 - 775 microns; the thickness of the first substrate 100 is the general thickness of the substrate in conventional semiconductor processes.

[0042] Reference Figure 2 , a first epitaxial layer 110 is formed on the first surface 101 of the first substrate 100. The first epitaxial layer 110 contains second ions, the second ions have a second concentration, and the second concentration is less than the first concentration.

[0043] The range of the second concentration of the second ions is 5E12 - 1E15 atoms / cm 3 .

[0044] In this embodiment, the second concentration is less than the first concentration, and there is a concentration difference at the junction of the first epitaxial layer 110 and the first substrate 100. When the first substrate 100 is thinned from the second surface 102 later, the first substrate 100 is first etched. Since the etching rate is sensitive to the ion concentration, the etching rate will drop sharply in the ion concentration gradient layer, so that the thinning first stops at the junction of the first epitaxial layer 110 and the first substrate 100, thereby controlling the uniformity of the thinning thickness.

[0045] In this embodiment, the second ions and the first ions have opposite conductivity types; the reason for the second ions and the first ions to have opposite conductivity types is that it can make the boundary between the first epitaxial layer 110 and the first substrate 100 clearer, avoiding the boundary becoming blurred due to ion diffusion during some heat treatment processes. When the first substrate 100 is thinned later, the first epitaxial layer 110 can better serve as an etch stop layer.

[0046] In this embodiment, if the first ions are P-type ions, then the second ions are N-type ions; the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.

[0047] In other embodiments, the second ions and the first ions can also have the same conductivity type.

[0048] In this embodiment, the first epitaxial layer 110 is formed by an epitaxial growth process.

[0049] The thickness range of the first epitaxial layer 110 is 1 to 3 micrometers; if the thickness of the first epitaxial layer 110 is greater than 3 micrometers, a concentration gradient layer may be formed by the second ions in the first epitaxial layer 110, which is not conducive to the stopping of the etching process in the subsequent thinning process; if the thickness of the first epitaxial layer 110 is less than 1 micrometer, over-polishing is likely to occur during the planarization process in the subsequent thinning process, damaging the second epitaxial layer 120.

[0050] Reference Figure 3 , a second epitaxial layer 120 is formed on the first epitaxial layer 110 and a third epitaxial layer 130 is formed on the second epitaxial layer 120. The second epitaxial layer 120 contains a third ion, the third ion has a third concentration, the third epitaxial layer 130 has a fourth ion, the fourth ion has a fourth concentration, and the fourth concentration is less than the third concentration.

[0051] The range of the third concentration is 6E17 to 5E18 atoms / cm 3 ; the range of the fourth concentration is 1E13 to 2E14 atoms / cm 3 .

[0052] In this embodiment, the third ion and the fourth ion have the same conductivity type, and the third ion, the fourth ion and the first ion have the same conductivity type.

[0053] In this embodiment, the third ion is a P-type ion; the fourth ion is a P-type ion; the P-type ion includes one or several of boron ions, indium ions, and gallium ions.

[0054] In this embodiment, the reason for continuously forming the second epitaxial layer 120 and the third epitaxial layer 130 on the first epitaxial layer 110 is that after the first substrate 100 is thinned, the first substrate 100 and the first epitaxial layer 110 will be removed until the surface of the second epitaxial layer 120 is exposed. The remaining second epitaxial layer 120 and the third epitaxial layer 130 serve as the substrate for forming the semiconductor structure, and the third concentration is greater than the fourth concentration, meeting the substrate requirements for manufacturing the image sensor and being conducive to improving the performance of the formed semiconductor structure.

[0055] In this embodiment, the second epitaxial layer 120 and the third epitaxial layer 130 are formed by an epitaxial growth process.

[0056] The thickness range of the second epitaxial layer 120 is 1 to 5 micrometers; the thickness range of the third epitaxial layer 130 is 4 to 10 micrometers; the thicknesses of the second epitaxial layer 120 and the third epitaxial layer 130 can be selected according to specific actual situations.

[0057] The third epitaxial layer 130 includes a third surface 131 that faces away from the second epitaxial layer 120; the second epitaxial layer 120 includes a fourth surface 121 that contacts the first epitaxial layer 110.

[0058] Reference Figure 4 , after forming the third epitaxial layer 130, a plurality of photo-doped regions 210 are formed within the third epitaxial layer 130. Adjacent photo-doped regions 210 are isolated by a shallow trench isolation structure 240.

[0059] In this embodiment, it further includes: forming a first dielectric layer 220 that covers the third surface 131 of the third epitaxial layer 130 and the photo-doped regions.

[0060] In this embodiment, it further includes: forming a logic circuit (not shown) within the first dielectric layer 220, the logic circuit includes MOS transistors and an electrical interconnect structure 230 electrically connected to the MOS transistors, and electrical signals in the MOS transistors are transmitted through the electrical interconnect structure 230.

[0061] In this embodiment, the method for forming the photo-doped regions 210 includes:

[0062] forming a patterned layer (not shown) on the third surface 131 of the third epitaxial layer 130, the patterned layer exposing a part of the third surface 131 of the third epitaxial layer 130; performing ion implantation using the patterned layer as a mask to form photo-doped regions 210 within the third epitaxial layer 130.

[0063] The doping type of the photo-doped regions 210 is opposite to the doping type of the third epitaxial layer 130. For example, if the third epitaxial layer 130 is P-type doped, the first doped region is N-type doped, or vice versa. In this way, a PN junction is formed between the first doped region and the third epitaxial layer 130 in a direction perpendicular to the third surface 131 of the third epitaxial layer 130, forming a photodiode.

[0064] In this embodiment, the electrical interconnect structure 230 includes a plurality of stacked interconnect metal layers and a plug layer (not shown in the figure) connecting adjacent two interconnect metal layers, where the interconnect metal layers are located above the shallow trench isolation structure 240. The method for forming the electrical interconnect structure 230 is well-known to those skilled in the art and will not be elaborated here.

[0065] Reference Figure 5 , providing a second substrate 300, bonding the second substrate 300 to the first substrate 100 in the direction of the first surface 101, and flipping the first substrate 100 so that the second surface 102 faces upward. The bonding method can be eutectic bonding or any other welding process feasible in semiconductor processes.

[0066] After flipping the first substrate 100, the first substrate 100 is thinned from the second surface 102. Specifically, the steps of the thinning process include:

[0067] Reference Figure 6 , the first substrate 100 is etched from the second surface 102 of the first substrate 100 until the surface of the first epitaxial layer 110 is exposed.

[0068] In this embodiment, the etching process is a wet etching process; the process parameters of the wet etching process include: the etching solution includes an HNA solution, and the HNA solution is a mixed solution formed by hydrofluoric acid, nitric acid, and acetic acid.

[0069] In this embodiment, since there is an ion concentration difference between the first epitaxial layer 110 and the first substrate 100, and the wet etching is very sensitive to the ion concentration, the etching rate will drop suddenly at the concentration change, so the first epitaxial layer 110 serves as an etching stop layer during the wet etching process, which can stop the wet etching at the junction of the first substrate 100 and the first epitaxial layer 110, improving the uniformity of the thinning thickness.

[0070] Reference Figure 7 , continue to planarize the first epitaxial layer 110 until the surface of the second epitaxial layer 120 is exposed.

[0071] In this embodiment, the planarization process is chemical mechanical polishing; the process parameters of the chemical mechanical polishing include: using SiO2 polishing liquid, and the polishing time is 50 - 100 seconds.

[0072] In this embodiment, chemical mechanical polishing is beneficial to further improve the thickness uniformity of the thinning process.

[0073] In this embodiment, the thickness of the chemical mechanical polishing is the thickness of the first epitaxial layer 110, and the thickness range of the first epitaxial layer 110 is 1 - 3 microns; if the thickness of the first epitaxial layer 110 is greater than 3 microns, a concentration gradient layer may be formed by the second ions in the first epitaxial layer 110, which is not conducive to the stop of the etching process; if the thickness of the first epitaxial layer 110 is less than 1 micron, the requirement of uniformity cannot be met during chemical mechanical polishing, and over-polishing is likely to occur, damaging the second epitaxial layer 120.

[0074] In this embodiment, after planarizing the first epitaxial layer 110, ensuring that the exposed surface of the second epitaxial layer 120 is flat is beneficial to the performance of the finally formed semiconductor structure.

[0075] In this embodiment, after the planarization process of the first epitaxial layer 110, the following steps are further included: treating the surface of the exposed second epitaxial layer 120 with a TMAH solution, which can make the crystal orientation of silicon on the surface of the second epitaxial layer 120 consistent, and is beneficial to further improving the flatness of the surface of the second epitaxial layer 120 after the thinning process.

[0076] In this embodiment, after the thinning process of the first substrate 100, the first substrate 100 and the first epitaxial layer 110 are removed, and the second epitaxial layer 120 and the third epitaxial layer 130 are retained. Pixel units are formed on the third surface 131 of the third epitaxial layer 130. During the operation of the finally formed semiconductor structure, a reverse bias voltage is applied to the photodiode, so that a depletion region is formed in the third epitaxial layer 130. If the applied reverse bias voltage is large, the depletion region is likely to expand. By retaining the second epitaxial layer 120 with a relatively high ion concentration, the expansion of the depletion region can be inhibited, and the depletion region is prevented from expanding to the processed interface, where dark current is generated at the interface defects of the thinning process, which is beneficial to the performance of the finally formed semiconductor structure.

[0077] Reference Figure 8 , after the thinning process, a second dielectric layer 250 is formed on the fourth surface 121 of the second epitaxial layer 120. The second dielectric layer covers the fourth surface 121 of the second epitaxial layer 120 to protect the fourth surface 121 of the second epitaxial layer 120.

[0078] In this embodiment, the second dielectric layer 250 is a single-layer structure, including a silicon oxide layer, a silicon nitride layer, or other feasible dielectric materials.

[0079] In other embodiments, the second dielectric layer 250 is a stacked structure, including a silicon oxide layer and a silicon nitride layer located on the silicon oxide layer.

[0080] Continue to refer to Figure 8 , a conductive plug 251 is formed in the second dielectric layer 250, the second epitaxial layer 120, and the third epitaxial layer 130. The conductive plug 251 is electrically connected to the interconnect metal layer in the electrical interconnect structure 230.

[0081] In this embodiment, the step of forming the conductive plug 251 includes: forming a through hole (not shown in the figure) in the second dielectric layer 250, the second epitaxial layer 120, and the third epitaxial layer 130. The through hole is located above the interconnect metal layer in the electrical interconnect structure 230 in the first dielectric layer 220 and exposes the first dielectric layer 220; forming a contact hole (not shown in the figure) at the bottom of the through hole and in the first dielectric layer 220 to expose the interconnect metal layer in the electrical interconnect structure 230; and forming a conductive layer in the through hole and the contact hole.

[0082] In this embodiment, the steps of forming the conductive layer include: forming a conductive material (not shown) on the second dielectric layer 250 and in the through holes and contact holes, the conductive material filling the through holes and contact holes and covering the second dielectric layer 250, the conductive material being used to form the conductive layer subsequently; using photolithography and dry etching processes to remove the conductive material outside the through holes, and the remaining conductive material in the through holes and contact holes serves as the conductive layer.

[0083] In this embodiment, the conductive plug 251 functions as an electrical connection, transmitting the electrical signals in the electrical interconnection structure 230 on the third surface 131 of the third epitaxial layer 130 to the peripheral circuit.

[0084] Continue to refer to Figure 8 , a plurality of filter films 410 are formed on the second dielectric layer 250 and lenses 420 are located on the filter films 410. The filter films 410 are aligned one-to-one with the pixel units 210 in a direction perpendicular to the third surface 131 of the third epitaxial layer 130 to ensure that incident light can be accurately captured.

[0085] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a first substrate, the first substrate including opposite first and second surfaces, and having a first ion within the first substrate, the first ion having a first concentration; Forming a first epitaxial layer on the first surface of the first substrate, the first epitaxial layer having a second ion within it, the second ion having a second concentration, the second concentration being less than the first concentration; forming a second epitaxial layer on the first epitaxial layer and a third epitaxial layer on the second epitaxial layer, the second epitaxial layer having a third ion within it, the third ion having a third concentration, the third epitaxial layer having a fourth ion within it, the fourth ion having a fourth concentration, the fourth concentration being less than the third concentration; Thinning the first substrate from the second surface of the first substrate until the surface of the second epitaxial layer is exposed.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The steps of the thinning process include: etching the first substrate from the second surface of the first substrate until the surface of the first epitaxial layer is exposed; planarizing the first epitaxial layer until the surface of the second epitaxial layer is exposed.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The etching process is wet etching; the process parameters of the wet etching process include: the etching solution includes an HNA solution, and the HNA solution is a mixed solution formed by hydrofluoric acid, nitric acid, and acetic acid.

4. The method for forming a semiconductor structure according to claim 2, characterized in that, The planarizing process is chemical mechanical polishing; the process parameters of the chemical mechanical polishing include: selecting a SiO2 polishing solution, and the polishing time is 50 - 100 seconds.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The first ion and the second ion have opposite conduction types.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The third ion and the fourth ion have the same conduction type.

7. The method for forming a semiconductor structure according to claim 5, characterized in that, The first ion is a P-type ion; the P-type ion includes one or several of boron ions, indium ions, and gallium ions.

8. The method for forming a semiconductor structure according to claim 5, characterized in that, The second ion is an N-type ion; the N-type ion includes one or several of phosphorus ions, arsenic ions, and antimony ions.

9. The method for forming a semiconductor structure according to claim 6, characterized in that, The third ion is a P-type ion; the fourth ion is a P-type ion; the P-type ion includes one or several of boron ions, indium ions, and gallium ions.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, The range of the first concentration is 2E18 to 5E18 atoms / cm 3 .

11. The method for forming a semiconductor structure according to claim 1, characterized in that, The range of the second concentration is 5E12 to 1E15 atoms / cm 3 .

12. The method for forming a semiconductor structure according to claim 1, characterized in that, The range of the third concentration is 6E17 to 5E18 atoms / cm 3 .

13. The method for forming a semiconductor structure according to claim 1, characterized in that, The range of the fourth concentration is 1E13 to 2E14 atoms / cm 3 .

14. The method for forming a semiconductor structure according to claim 1, characterized in that, The thickness range of the first epitaxial layer is 1 - 3 microns.

15. The method for forming a semiconductor structure according to claim 1, characterized in that, The thickness range of the second epitaxial layer is 1 - 5 microns.

16. The method for forming a semiconductor structure according to claim 1, characterized in that, The thickness range of the third epitaxial layer is 4 - 10 microns.

17. The method for forming a semiconductor structure according to claim 1, characterized in that, The third epitaxial layer includes a third surface facing away from the second epitaxial layer. Before thinning the first substrate, it further includes: forming a plurality of optoelectronic doping regions within the third epitaxial layer; forming a first dielectric layer covering the third surface of the third epitaxial layer and the optoelectronic doping regions; forming an electrical interconnection structure within the first dielectric layer.

18. The method for forming a semiconductor structure according to claim 17, wherein, After forming the electrical interconnection structure, it further includes: providing a second substrate; bonding the first surface of the first substrate to the second substrate.

19. The method for forming a semiconductor structure according to claim 18, wherein, The second epitaxial layer includes a fourth surface, and the fourth surface is in contact with the first epitaxial layer. After the first substrate is thinned, it further includes: forming a second dielectric layer on the fourth surface of the second epitaxial layer; forming a through hole in the second dielectric layer, the second epitaxial layer, and the third epitaxial layer, and the through hole exposes the first dielectric layer; forming a contact hole at the bottom of the through hole and in the first dielectric layer to expose the electrical interconnection structure; and forming a conductive layer in the through hole and the contact hole.

20. The method for forming a semiconductor structure according to claim 19, wherein, It further includes: forming a plurality of optical filters on the second dielectric layer and a lens on the optical filters.

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