A device for measuring flicker noise of MOS devices

Abstract

The present invention discloses a device for measuring flicker noise of MOS devices. An input bias drive circuit provides a DC bias voltage to a MOS transistor to be tested so that the MOS transistor to be tested is in a linear working region. The input bias drive circuit includes a gate drive branch that provides a DC bias voltage to the gate of the MOS transistor to be tested; the gate drive branch includes a capacitor voltage divider unit composed of a plurality of capacitors connected in series to ground, and a switch five; the switch five is a single-pole multi-throw switch, and the plurality of throws are respectively connected to different positions in the capacitor voltage divider unit, and different closed states of the switch five provide different gate voltage values ​​for the gate of the MOS transistor to be tested. A back-end noise signal processing circuit is connected to the target position of the MOS transistor to be tested, and is used to measure and analyze the flicker noise of the target position of the MOS transistor to be tested. The present invention can stabilize the gate voltage and reduce the influence of gate flicker noise and other noise inputs on the entire test system.

Description

Technical Field

[0001] The present invention relates to a measuring circuit for a semiconductor device, in particular to a measuring circuit for a MOS device. Background Art

[0002] Flicker noise is a type of electronic noise with a power spectral density of 1 / f, where f represents frequency. Flicker noise is an important tool for evaluating the performance of electronic components. In addition to testing in a low-noise environment, improving test methods to achieve more accurate measurements is crucial.

[0003] MOS devices refer to metal–oxide–semiconductor field-effect transistors (MOSFETs). Flicker noise in MOS devices is particularly important. Existing methods for measuring flicker noise in MOS devices mainly include the following three methods.

[0004] The first method is direct measurement, which determines the quality of MOS transistors by directly measuring their flicker noise. This method can provide a detailed assessment of MOS transistor quality, but it requires very expensive measurement instruments and a long testing process, resulting in high measurement costs and time.

[0005] The second method is an indirect detection method based on current noise. This method uses the total current noise in the MOS transistor to infer the flicker noise level. This method is more economical than direct measurement, but it cannot provide complete information about MOS transistor parameters, such as the output impedance of the MOS transistor.

[0006] The third method is the indirect derivation method, which infers the flicker noise level from the MOS transistor. For example, when performing power spectral density analysis, the flicker noise level is inferred by comparing the noise level in the frequency band related to the MOS transistor. The results of this method are relatively inaccurate. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a circuit that can accurately measure the flicker noise of a MOS device, and is superior to a direct measurement method in terms of measurement cost and time consumption.

[0008] To solve the above-mentioned technical problems, the present invention discloses a device for measuring flicker noise of MOS devices, comprising a MOS transistor to be measured, an input bias drive circuit, and a back-end noise signal processing circuit. The input bias drive circuit provides a DC bias voltage to the MOS transistor to be measured, so that the MOS transistor to be measured is in a linear operating region; the input bias drive circuit includes a gate drive branch that provides a DC bias voltage to the gate of the MOS transistor to be measured; the gate drive branch includes a capacitor voltage divider unit composed of multiple capacitors connected in series to ground, and a switch five; the switch five is a single-pole, multi-throw switch, with multiple throws connected to different positions in the capacitor voltage divider unit, and different closed states of the switch five provide different gate voltage values ​​for the gate of the MOS transistor to be measured. The back-end noise signal processing circuit is connected to the target position of the MOS transistor to be tested and is used to measure and analyze the flicker noise at the target position of the MOS transistor to be tested; the back-end noise signal processing circuit includes a DC block, a low-noise current preamplifier and a dynamic signal analyzer connected in sequence; the DC block is used to isolate the target position of the MOS transistor to be tested from other parts of the circuit; the low-noise current preamplifier converts the voltage signal at the target position of the MOS transistor to be tested into a corresponding current signal and amplifies the current signal at the target position; the dynamic signal analyzer collects the amplified current signal at the target position, samples the input signal, and analyzes and automatically measures the flicker noise signal.

[0009] Furthermore, when the target position is the drain or the gate, the source of the MOS transistor to be tested is grounded; the input bias driving circuit further includes a drain driving branch for providing a DC bias voltage to the drain of the MOS transistor to be tested.

[0010] Furthermore, the gate drive branch includes a gate power supply, switch 1, a capacitor voltage divider unit, switch 5, and switch 2, which are connected in sequence and ultimately connected to the target position of the MOS transistor to be tested; switch 1 is a single-pole double-throw switch, which is either connected to the gate power supply or to resistor 1; resistor 1 is grounded, providing a capacitor discharge channel for each capacitor in the capacitor voltage divider unit; switch 2 is a single-pole single-throw switch, which determines whether to provide a gate bias voltage to the gate of the MOS transistor to be tested.

[0011] Furthermore, capacitor four is connected in parallel with the gate power supply to provide filtering for the gate power supply.

[0012] Furthermore, the drain drive branch includes a drain power supply, a third switch, an inductor first, and a fourth switch, which are connected in sequence and ultimately connected to the drain of the MOS transistor under test. The first inductor is used to stabilize the power input and filter high-frequency noise. The fourth switch is a single-pole double-throw switch, connected to either the drain of the MOS transistor under test or a parallel unit of a second resistor and a sixth capacitor. The parallel unit of the second resistor and the sixth capacitor is grounded to reduce the stabilization time of the first inductor when the fourth switch is disconnected from the drain of the MOS transistor under test and then reconnected. Alternatively, the fourth switch can be replaced with a single-pole single-throw switch, in which case the parallel unit of the second resistor and the sixth capacitor is eliminated.

[0013] Furthermore, capacitor five is connected in parallel with the drain power supply to provide filtering for the drain power supply.

[0014] Furthermore, when the target position is the source, the drain of the MOS transistor to be tested is grounded; the input bias driving circuit further includes a source driving branch for providing a DC bias voltage to the source of the MOS transistor to be tested.

[0015] Furthermore, the source drive branch includes a source power supply, switch 3, inductor 1, and switch 4, which are connected in sequence and ultimately connected to the source of the MOS transistor under test. Inductor 1 is used to stabilize the power input and filter high-frequency noise. Switch 4 is a single-pole double-throw switch, connected to either the drain of the MOS transistor under test or the parallel unit of resistor 2 and capacitor 6. The parallel unit of resistor 2 and capacitor 6 is grounded to reduce the stabilization time of inductor 1 when switch 4 is disconnected from the source of the MOS transistor under test and then reconnected. Alternatively, switch 4 can be replaced with a single-pole single-throw switch, in which case the parallel unit of resistor 2 and capacitor 6 is deleted.

[0016] Furthermore, the dynamic signal analyzer removes or smoothes the mains frequency.

[0017] Furthermore, each switching element adopts a relay, and the closing and opening of each switching element are automatically controlled by any one or more of SoC, FPGA, single-chip microcomputer, host computer, and PC, so as to test the flicker noise of the MOS device under dynamic switching conditions and test the flicker noise value generated by the MOS device at different switching frequencies.

[0018] The flicker noise measurement device proposed in the present invention uses a capacitor voltage divider to provide a bias voltage for the gate of the MOS transistor to be tested, which can stabilize the gate voltage and reduce the influence of gate flicker noise and other noise inputs on the entire test system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural diagram of embodiment 1 of the device for measuring flicker noise of MOS devices proposed by the present invention.

[0020] Figure 2 It is a structural diagram of a second embodiment of the apparatus for measuring flicker noise of a MOS device proposed by the present invention.

[0021] Figure 3 1 is a schematic structural diagram of a third embodiment of the apparatus for measuring flicker noise of a MOS device proposed by the present invention.

[0022] Explanation of the reference numerals in the figure: 10 is the input bias drive circuit 1, 15 is the input bias drive circuit 2, 20 is the back-end noise signal processing circuit, M1 is the MOS transistor to be tested, Vgs is the gate power supply, Vds is the drain power supply, Vss is the source power supply, SW1 to SW5 are switches, C1 to C6 are capacitors, R1 to R2 are resistors, L1 is an inductor, B1 is a DC block, A1 is a low-noise current preamplifier, and A2 is a dynamic signal analyzer. DETAILED DESCRIPTION

[0023] See also Figure 1 This is a first embodiment of the device for measuring flicker noise of a MOS device proposed by the present invention, which is used to measure the flicker noise of the drain of a MOS transistor. The first embodiment of the measuring device includes a MOS transistor M1 to be tested, an input bias drive circuit 10, and a back-end noise signal processing circuit 20. The source of the MOS transistor M1 to be tested is grounded. The input bias drive circuit 10 provides a suitable DC bias voltage to the gate and drain of the MOS transistor M1 to be tested, so that the MOS transistor M1 to be tested is in the linear operating region to obtain the optimal test effect. The input bias drive circuit 10 includes a gate drive branch that provides a bias for the gate of the MOS transistor M1 to be tested, and a drain drive branch that provides a bias for the drain of the MOS transistor M1 to be tested. The back-end noise signal processing circuit 20 is connected to the drain of the MOS transistor M1 to be tested, and is used to measure and analyze the flicker noise of the drain of the MOS transistor M1 to be tested.

[0024] The gate drive branch includes a gate power supply Vgs, a switch SW1, a capacitor voltage divider unit, a switch SW5, and a switch SW2 connected in sequence, and finally connected to the gate of the MOS transistor M1 to be measured. The gate power supply Vgs preferably uses a lithium battery or other low-noise power supply. The temperature drift, noise and other performance of the lithium battery are very good, and can largely avoid external interference for measuring flicker noise. Capacitor C4 is connected in parallel with the gate power supply Vgs to provide filtering for the gate power supply Vgs; capacitor C4 can also be replaced with other components for filtering or stabilizing the input power supply. Switch SW1 is, for example, a single-pole double-throw (SPDT) switch, or connected to the gate power supply Vgs, or connected to resistor R1. Resistor R1 is, for example, a large resistor. When switch SW1 is connected to resistor R1, the grounded resistor R1 provides a capacitor discharge channel for each capacitor in the capacitor voltage divider unit to avoid excessive internal loss of each capacitor. The capacitor voltage divider unit is composed of multiple capacitors connected in series, Figure 1 In the example, three capacitors C1, C2, and C3 are connected in series and then grounded. One end of the multiple capacitors in series is connected to the single pole of switch 1 SW1, and the other end is grounded. Switch 5 SW5 is, for example, a single-pole double-throw switch, connected between capacitor 1 C1 and capacitor 2 C2, or between capacitor 2 C2 and capacitor 3 C3. By selecting capacitors of different numbers and capacitance values ​​to form the capacitor voltage divider unit, and selecting different single-pole multiple-throw forms of switch 5 SW5, the position of the capacitor voltage divider unit, and the switch state, a variety of different gate voltage values ​​can be provided for the gate of the MOS transistor M1 to be tested. Switch 2 SW2 is, for example, a single-pole single-throw (SPST) switch. In the initial state, switch 2 SW2 is disconnected, and switch 1 SW1 is connected to the gate power supply Vgs. The gate power supply Vgs charges the capacitors in the capacitor voltage divider unit, and the voltage distributed across each capacitor is inversely proportional to its capacitance, and then reaches a steady state. The appropriate gate voltage value is obtained by the switching state of switch 5 SW5. Then, switch SW2 closes, and the gate drive branch begins providing gate drive voltage to the gate of the MOS transistor M1 under test. The capacitors in the capacitor voltage divider continuously charge and discharge under the power of the gate power supply Vgs, maintaining a steady state and suppressing oscillations in the gate drive branch, eliminating noise.

[0025] The drain drive branch includes a drain power supply Vds, a third switch SW3, an inductor L1, and a fourth switch SW4, which are connected in sequence and ultimately connected to the drain of the MOS transistor M1 to be tested. The drain power supply Vds is preferably a lithium battery or other low-noise power supply. A fifth capacitor C5 is connected in parallel with the drain power supply Vds to provide filtering for the drain power supply Vds; the fifth capacitor C5 can also be replaced with other components for filtering or stabilizing the input power supply. The third switch SW3 is, for example, a single-pole single-throw switch. The first inductor L1 is, for example, a large inductor, which mainly serves to stabilize the power input and filter high-frequency noise. The first inductor L1 can also be replaced with other components that filter high-frequency noise and stabilize the power input. The fourth switch SW4 is, for example, a single-pole double-throw switch, which is either connected to the drain of the MOS transistor M1 to be tested or to the parallel unit of the second resistor R2 and the sixth capacitor C6. In the initial state, switch 3 SW3 is closed, and switch 4 SW4 is connected to the drain of the MOS transistor M1 under test. After a certain charging time, the drain drive branch reaches stability, providing a certain drain drive voltage to the drain of the MOS transistor M1 under test. The magnitude of the drain drive voltage can be adjusted by adjusting the drain power supply Vds. When the DC bias voltage to the drain of the MOS transistor M1 under test needs to be disconnected, that is, when the MOS transistor M1 under test needs to be disconnected, switch 4 SW4 is connected to the parallel unit of resistor 2 R2 and capacitor 6 C6. The parallel unit of resistor 2 R2 and capacitor 6 C6 is grounded. This reserves a power supply circuit for the drain drive branch. This can reduce the stabilization time of inductor 1 L1 to a certain extent when the MOS transistor M1 under test next needs to use the drain bias voltage, that is, when switch 4 SW4 is reconnected to the drain of the MOS transistor M1 under test. Switch SW4 can also be changed to a single-pole single-throw switch. In this case, the parallel unit of resistor R2 and capacitor C6 is removed. When the DC bias voltage of the drain of the MOS transistor M1 under test needs to be disconnected, switch SW4 is opened. When the drain bias voltage of the MOS transistor M1 under test needs to be applied next time, switch SW4 is closed. However, inductor L1 requires a certain amount of stabilization time.

[0026] The back-end noise signal processing circuit 20 includes a DC block B1, a low-noise current preamplifier A1, and a dynamic signal analyzer A2, which are connected in sequence. The DC block B1 is used to isolate the drain voltage of the MOS transistor M1 under test from the rest of the circuit. The DC block B1 transmits the drain voltage signal of the MOS transistor M1 under test. The low-noise current preamplifier A1 converts the drain voltage signal of the MOS transistor M1 under test into a corresponding current signal. It also sets a gain to amplify the performance of the noise signal (in the first embodiment, the drain current of the MOS transistor M1 under test) to facilitate subsequent measurement and processing by the dynamic signal analyzer A2. During signal amplification and measurement, any noise is amplified. If a conventional amplifier is used for signal amplification, some unnecessary high-frequency noise may be amplified, thereby affecting the measurement results. Therefore, a low-noise current preamplifier A1 is required to reduce the system noise level and improve the signal-to-noise ratio. The low-noise current preamplifier A1 has the advantages of low noise, high gain, and high bandwidth. Dynamic signal analyzer A2 collects data containing flicker noise (in Example 1, this refers to the amplified drain current of the MOS transistor M1 under test) and samples the input signal to achieve more accurate analysis and automated measurement of the flicker noise signal. If dynamic signal analyzer A2 is set to an appropriate range and bandwidth, the number of sampling points is increased and averaged. By collecting multiple data points and averaging them, the impact of random noise can be reduced, thereby obtaining more accurate flicker noise measurement results. Flicker noise refers to a type of random noise whose spectral density typically exhibits a distinct peak. For flicker noise in the drain of a MOS device, its peak typically occurs around 1 Hz. The calculation method for flicker noise may vary depending on the application scenario and specific circuit, but generally involves power spectral density data at 1 Hz. Therefore, when calculating the flicker noise in the drain of the MOS transistor M1 under test, dynamic signal analyzer A2 records the power spectral density data at 1 Hz and uses it as a reference point for subsequent noise analysis. At the same time, the dynamic signal analyzer A2 can remove or smooth the frequency of the mains (industrial frequency AC power) (50Hz for China). Optionally, the low-noise current preamplifier A1 and the dynamic signal analyzer A2 can be connected to a PC for control, thereby performing relevant information processing on the noise signal.

[0027] See also Figure 2This is the second embodiment of the device for measuring the flicker noise of a MOS device proposed by the present invention, which is used to measure the flicker noise of the gate of a MOS transistor. The second embodiment of the measuring device includes a MOS transistor M1 to be measured, an input bias driving circuit 10, and a back-end noise signal processing circuit 20. The source of the MOS transistor M1 to be measured is grounded. The input bias driving circuit 10 provides a suitable DC bias voltage to the gate and drain of the MOS transistor M1 to be measured so that the MOS transistor M1 to be measured is in the linear operating region. The circuit structure of the input bias driving circuit 10 is exactly the same as that of the first embodiment. The circuit structure of the back-end noise signal processing circuit 20 is exactly the same as that of the first embodiment, except that the back-end noise signal processing circuit 20 is connected to the gate of the MOS transistor M1 to be measured and is used to measure and analyze the flicker noise of the gate of the MOS transistor M1 to be measured.

[0028] See also Figure 3 This is the third embodiment of the device for measuring the flicker noise of a MOS device proposed by the present invention, which is used to measure the flicker noise of the source of a MOS transistor. The third embodiment of the measuring device includes a MOS transistor M1 to be measured, an input bias driving circuit 2 15, and a back-end noise signal processing circuit 20. The drain of the MOS transistor M1 to be measured is grounded. The input bias driving circuit 2 15 provides a suitable DC bias voltage to the gate and source of the MOS transistor M1 to be measured, so that the MOS transistor M1 to be measured is in the linear working area. The circuit structure of the back-end noise signal processing circuit 20 is exactly the same as that of the first embodiment, except that the back-end noise signal processing circuit 20 is connected to the source of the MOS transistor M1 to be measured, and is used to measure and analyze the flicker noise of the source of the MOS transistor M1 to be measured.

[0029] The second input bias drive circuit 15 includes a gate drive branch that provides bias for the gate of the MOS transistor M1 under test, and a source drive branch that provides bias for the source of the MOS transistor M1 under test. The gate drive branch in the second input bias drive circuit 15 has the same circuit structure and connection location to the MOS transistor M1 under test as the gate drive branch in the first input bias drive circuit 10. The source drive branch in the second input bias drive circuit 15 has the same circuit structure as the drain drive branch in the first input bias drive circuit 10, except that the drain power supply Vds is replaced by the source power supply Vss, and the connection location to the MOS transistor M1 under test is different. The source drive branch in the second input bias drive circuit 15 is connected to the source of the MOS transistor M1 under test. The drain drive branch in the first input bias drive circuit 10 is connected to the drain of the MOS transistor M1 under test.

[0030] Compared with the existing device for measuring flicker noise of MOS devices, the present invention has the following beneficial effects.

[0031] First, the three embodiments of the present invention provide two input bias drive circuits 10 and 15, both of which include the same gate drive branch. (1) The gate drive branch uses a capacitor voltage divider to provide a drive voltage to the gate of the MOS transistor M1 to be tested, and the gate drive voltage value is stable and adjustable. MOS devices are voltage-controlled devices. Traditionally, a resistor voltage divider is used to provide a gate bias drive voltage. A capacitor voltage divider is more stable for providing a gate drive voltage. (2) The flicker noise of a capacitor is mainly charge noise and dielectric noise, while the flicker noise of a resistor is mainly thermal noise. Due to differences in internal structure and physical properties, the flicker noise of a capacitor is generally smaller than that of a resistor. Compared with the traditional resistor voltage divider, the capacitor voltage divider also significantly improves the performance and stability of the entire system. (3) Flicker noise is a noise model in a DC circuit. Flicker noise mainly comes from the perturbation of carriers, and is mainly characterized by low frequency and DC. When the gate voltage changes, the electron concentration will change, thereby affecting the perturbation of carriers and further affecting the flicker noise. The present invention adopts a capacitor voltage division method in the gate driving branch to reduce the influence of gate flicker noise and other noise inputs on the flicker noise of the MOS device to be measured.

[0032] Second, while conventional circuits for measuring flicker noise in MOS devices can only measure at a single location, the present invention employs multiple switching elements in a measurement device, enabling rapid changes in the flicker noise measurement location of the MOS transistor M1 under test, either manually or automatically. For example, by simply changing the location of one throw of switch SW4 connected to the MOS transistor M1 under test and simultaneously changing the input power supply, the drain drive branch in Example 1 can be replaced with the source drive branch in Example 3. This provides multiple flexible methods for measuring flicker noise under different test conditions, enabling accurate flicker noise assessment at different locations on a MOS device.

[0033] The present invention can be used to measure the flicker noise of the drain of MOS devices, which is Figure 1 The present invention can also be used to test the flicker noise of the drain of a MOS device under different drain voltages when the gate drive voltage is constant. Figure 1 In the first embodiment of the measuring device shown, this is achieved by changing the value of the drain power supply Vds.

[0034] The present invention can be used to measure the flicker noise of the gate of MOS devices, which is Figure 2 The present invention can also be used to test the flicker noise of the gate of a MOS device under different gate voltages when the drain drive voltage is constant. Figure 2In the second embodiment of the measuring device shown, different gate drive voltage values ​​are obtained by switching the switch state of the fifth switch SW5, and / or changing the position of the switch fifth SW5 connected to the capacitor voltage divider unit, and / or changing the voltage value of the gate power supply Vgs, that is, the gate voltage scanning method.

[0035] The present invention can be used to measure the flicker noise of the source of MOS devices, which is Figure 3 The present invention can also be used to test the flicker noise of the source of MOS devices under different source voltages when the gate drive voltage is constant. Figure 3 In the third embodiment of the measuring device shown, this is achieved by changing the value of the source power supply Vss.

[0036] Third, each switching element in the present invention can be a high-performance relay. In this case, the SoC (system on chip), FPGA (field-programmable gate array), single-chip microcomputer (MCU, also known as microcontroller), host computer, PC, etc. can be programmed according to a certain logic to automatically control the closing and opening of each switch, thereby realizing the test of the flicker noise of the MOS device under dynamic switching conditions, and the value of the flicker noise generated by the MOS device at different switching frequencies can be tested. Using hardware triggering to change the switch state has a shorter delay than software triggering. For example, to measure the flicker noise in the switching state of the MOS device, PWM (pulse width modulation) can be used to drive each switch, which can be set by the SoC. Figures 1 to 3 The switching frequency of the second switch SW2 is measured to measure the change of flicker noise under different switching frequencies.

[0037] Fourth, (1) Compared with the direct measurement method, the present invention does not require the use of expensive measuring instruments for measuring the flicker noise of MOS devices, and the measurement cost is low and the measurement time is short. (2) Compared with the indirect detection method based on current noise, the present invention can obtain more MOS transistor parameter information. For example, by analyzing the power spectral density (PSD) of the flicker noise, the drain resistance (Rd) of the MOS transistor can be calculated. According to the internal structural characteristics of the MOS transistor and the amplitude and frequency response of the flicker noise, the gate capacitance (Cg) of the MOS transistor can be calculated by analyzing the PSD and the linearization model. By analyzing the time domain waveform and change rate of the flicker noise, the field effect mobility of the MOS transistor can be calculated. By analyzing the PSD and the linearization model, the cutoff frequency of the MOS transistor can be calculated. The source-drain residual capacitance, reverse leakage current, etc. of the MOS transistor can also be calculated. (3) Compared with the indirect derivation method, the present invention has more accurate measurement results for the flicker noise of MOS devices.

[0038] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A device for measuring flicker noise of a MOS device, characterized in that: It includes a MOS transistor to be tested, an input bias driving circuit and a back-end noise signal processing circuit; The input bias drive circuit provides a DC bias voltage to the MOS transistor under test so that the MOS transistor under test is in a linear operating region; the input bias drive circuit includes a gate drive branch that provides a DC bias voltage to the gate of the MOS transistor under test; the gate drive branch includes a capacitor voltage divider unit composed of multiple capacitors connected in series to ground, and a switch five; the switch five is a single-pole multi-throw switch, wherein the multiple throws are respectively connected to different positions in the capacitor voltage divider unit, and different closed states of the switch five provide different gate voltage values ​​for the gate of the MOS transistor under test; The back-end noise signal processing circuit is connected to the target position of the MOS transistor to be tested, and is used to measure and analyze the flicker noise of the target position of the MOS transistor to be tested; The back-end noise signal processing circuit includes a DC block, a low-noise current preamplifier and a dynamic signal analyzer connected in sequence; The DC block is used to isolate the target position of the MOS transistor to be tested from the rest of the circuit; the low-noise current preamplifier converts the voltage signal at the target position of the MOS transistor to a corresponding current signal and amplifies the current signal at the target position; The dynamic signal analyzer collects the amplified current signal at the target position, samples the input signal, and analyzes and automatically measures the flicker noise signal.

2. The device for measuring flicker noise of a MOS device according to claim 1, wherein: When the target position is the drain or the gate, the source of the MOS transistor to be tested is grounded; the input bias driving circuit also includes a drain driving branch for providing a DC bias voltage to the drain of the MOS transistor to be tested.

3. The device for measuring flicker noise of a MOS device according to claim 2, wherein: The gate drive branch includes a gate power supply, switch 1, a capacitor voltage divider unit, switch 5, and switch 2, which are connected in sequence and ultimately connected to the target position of the MOS transistor to be tested; switch 1 is a single-pole double-throw switch, which is either connected to the gate power supply or to resistor 1; resistor 1 is grounded, providing a capacitor discharge channel for each capacitor in the capacitor voltage divider unit; Switch 2 is a single-pole single-throw switch that determines whether to provide a gate bias voltage to the gate of the MOS transistor to be tested.

4. The device for measuring flicker noise of a MOS device according to claim 3, wherein: Capacitor four is connected in parallel with the gate power supply to provide filtering for the gate power supply.

5. The device for measuring flicker noise of a MOS device according to claim 2, wherein: The drain driving branch includes a drain power supply, a third switch, an inductor, and a fourth switch connected in sequence, and finally connected to the drain of the MOS transistor to be tested; the inductor is used to stabilize the power input and filter high-frequency noise; Switch 4 is a single-pole double-throw switch connected either to the drain of the MOS transistor under test or to the parallel unit of resistor 2 and capacitor 6; the parallel unit of resistor 2 and capacitor 6 is grounded and is used to reduce the settling time of inductor 1 when switch 4 is disconnected from the drain of the MOS transistor under test and then reconnected. Alternatively, switch four is changed to a single-pole single-throw switch, and the parallel unit of resistor two and capacitor six is ​​deleted.

6. The device for measuring flicker noise of a MOS device according to claim 5, wherein: Capacitor five is connected in parallel with the drain power supply to provide filtering for the drain power supply.

7. The device for measuring flicker noise of a MOS device according to claim 1, wherein: When the target position is the source, the drain of the MOS transistor to be tested is grounded; the input bias driving circuit further includes a source driving branch for providing a DC bias voltage to the source of the MOS transistor to be tested.

8. The device for measuring flicker noise of a MOS device according to claim 7, wherein: The source driving branch includes a source power supply, a third switch, an inductor, and a fourth switch connected in sequence, and is finally connected to the source of the MOS transistor to be tested; Inductor 1 is used to stabilize power input and filter high-frequency noise; Switch 4 is a single-pole double-throw switch connected either to the drain of the MOS transistor under test or to the parallel unit of resistor 2 and capacitor 6; the parallel unit of resistor 2 and capacitor 6 is grounded and is used to reduce the settling time of inductor 1 when switch 4 is disconnected from the source of the MOS transistor under test and then reconnected. Alternatively, switch four is changed to a single-pole single-throw switch, and the parallel unit of resistor two and capacitor six is ​​deleted.

9. The device for measuring flicker noise of a MOS device according to claim 1, wherein: The dynamic signal analyzer removes or smoothes the mains frequency.

10. The device for measuring flicker noise of a MOS device according to claim 1, wherein: Each switching element uses a relay, and the closing and opening of each switching element are automatically controlled by any one or more of SoC, FPGA, single-chip microcomputer, host computer, and PC, so as to test the flicker noise of MOS devices under dynamic switching conditions and the flicker noise value generated by MOS devices at different switching frequencies.

Images