A high-speed rail-to-rail self-biased voltage follower

Abstract

The present invention relates to a high-speed rail-to-rail self-biased voltage follower, comprising: a PMOS input circuit, an NMOS input circuit, a voltage clamp, and a mutual bias circuit. This high-speed rail-to-rail self-biased voltage follower can accurately track changes in input voltage at high speed to generate a rail-to-rail output signal. It also uses a self-biased design to provide a bias voltage for the input circuit, eliminating the need for an additional input bias voltage and reducing the complexity of the voltage design. The present invention can be widely used in single-inductor bipolar output or isolated gate drive circuits with rapidly changing positive and negative voltages or voltage rails, providing stable and accurate voltage tracking for the circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a high-speed rail-to-rail self-biased voltage follower. Background Art

[0002] The voltage follower is an indispensable basic building block in power electronic circuits and is widely used in DC / DC circuits and gate drive circuits. Its function is to read the input voltage and output the same voltage, thereby isolating and enhancing the driving capability.

[0003] Current voltage followers primarily utilize a common-source connection, which results in a threshold voltage loss and prevents accurate voltage tracking. To achieve precise tracking without threshold loss, a unity-gain circuit based on an op amp is typically employed. This input clamping of the op amp eliminates the threshold loss, enabling accurate voltage tracking. However, this approach also presents corresponding problems: First, its tracking capability is severely limited by the bandwidth and gain of the op amp. For input voltages with fast frequency changes, a unity-gain voltage follower based on an op amp cannot respond quickly. Second, for rail-to-rail inputs, a voltage follower based on this connection cannot achieve rail-to-rail voltage tracking due to the limited input range of the op amp. Third, an additional bias voltage is required for op amp-based voltage followers to operate. For isolated drive circuits, the power supply and ground potentials are floating, making it difficult to provide a suitable bias current, making this architecture unsuitable.

[0004] Therefore, the existing voltage follower has a slow tracking frequency, cannot achieve rail-to-rail input and output, and requires an additional bias circuit. Its application scenarios are very limited, and it does not have wide adaptability and excellent voltage tracking performance. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a high-speed rail-to-rail self-biased voltage follower. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a high-speed rail-to-rail self-biased voltage follower comprising: a PMOS input circuit, an NMOS input circuit, a voltage clamping and mutual biasing circuit; wherein the PMOS input circuit and the NMOS input circuit form a rail-to-rail complementary input; the voltage clamping and mutual biasing circuit provides an adaptive bias voltage, a clamping input, and an output voltage for the PMOS input circuit and the NMOS input circuit;

[0007] The PMOS input circuit is used for input voltage ranging from GND to VDD-2V THPWhen the input voltage is within the specified range, the regulating voltage is generated according to the voltage difference between the input voltage and the output voltage to adjust the working parameters or state of the component so that the input voltage is equal to the output voltage;

[0008] The NMOS input circuit is used for the input voltage at 2V THN When the input voltage reaches VDD, the regulated voltage is generated according to the voltage difference between the input voltage and the output voltage to adjust the operating parameters or state of the component so that the input voltage is equal to the output voltage.

[0009] The voltage clamping and mutual biasing circuit is used to maintain the output voltage always equal to the input voltage, and provide corresponding bias voltages for the PMOS input circuit and the NMOS input circuit respectively through its own current mirror;

[0010] Among them, V THP is the threshold voltage of the PMOS tube, V THN is the threshold voltage of the NMOS tube.

[0011] Optionally, the PMOS input circuit includes a first MOS transistor M1, a sixth MOS transistor M6, a seventh MOS transistor M7, a twelfth MOS transistor M12, and a thirteenth MOS transistor M13;

[0012] The source of the first MOS transistor M1 is connected to the power supply VDD, the gate serves as a VPBLAS voltage terminal, which is connected to other VPBLAS voltage terminals, and the drain is connected to the drain of the sixth MOS transistor M6 and the source of the seventh MOS transistor M7. The gate of the sixth MOS transistor M6 serves as an input voltage terminal SENSE, which is connected to other input voltage terminals SENSE. The drain of the sixth MOS transistor M6 is connected to the drain of the thirteenth MOS transistor M13 and serves as a VCTRLP voltage terminal, which is connected to other VCTRLP voltage terminals. The gate of the seventh MOS transistor M7 serves as an output voltage terminal HOLD, which is connected to other output voltage terminals HOLD. The drain of the seventh MOS transistor M7 is connected to the gates of the twelfth MOS transistor M12 and the thirteenth MOS transistor M13. The sources of the twelfth MOS transistor M12 and the thirteenth MOS transistor M13 are grounded GND.

[0013] Optionally, the NMOS input circuit includes a second MOS transistor M2, a third MOS transistor M3, a fifth MOS transistor M5, an eighth MOS transistor M8, and an eleventh MOS transistor M11;

[0014] The source of the second MOS transistor M2 and the source of the third MOS transistor M3 are both connected to the power supply VDD; the gate of the second MOS transistor M2 is connected to the gate of the third MOS transistor M3, the drain of the third MOS transistor M3, and the drain of the fifth MOS transistor M5; the drain of the third MOS transistor M3 is connected to the drain of the eighth MOS transistor M8; the source of the fifth MOS transistor M5 and the source of the eighth MOS transistor M8 are both connected to the drain of the eleventh MOS transistor M11; the gate of the fifth MOS transistor M5 serves as the output voltage terminal HOLD, which is connected to other output voltage terminals HOLD; the gate of the eighth MOS transistor M8 serves as the input voltage terminal SENSE, which is connected to other input voltage terminals SENSE; the source of the eleventh MOS transistor M11 is grounded GND, and the gate serves as the VNBLAS voltage terminal, which is connected to other VNBLAS voltage terminals.

[0015] Optionally, the voltage clamping and mutual biasing circuit includes a fourth MOS transistor M4, a ninth MOS transistor M9, a tenth MOS transistor M10, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, and a sixteenth MOS transistor M16;

[0016] Among them, the gate and drain of the fourth MOS transistor M4 and the source of the tenth MOS transistor M10 are connected together and serve as the VPBLAS voltage terminal, which is connected to other VPBLAS voltage terminals; the source of the fourth MOS transistor M4 and the source of the ninth MOS transistor M9 are both connected to the power supply VDD; the gate of the ninth MOS transistor M9 is connected to the gate of the fifteenth MOS transistor M15 and serves as the VCTRLN voltage terminal, which is connected to other VCTRLN voltage terminals; the drain of the ninth MOS transistor M9 is connected to the tenth MOS transistor M10 and serves as the output The voltage terminal HOLD is connected to other output voltage terminals HOLD; the source of the fifteenth MOS transistor M15 is connected to the drain of the fourteenth MOS transistor M14 and the gate of the fourteenth MOS transistor M14, and serves as a VNBLAS voltage terminal, which is connected to other VNBLAS voltage terminals; the gate of the tenth MOS transistor M10 is connected to the sixteenth MOS transistor M16, and serves as a VCTRLP voltage terminal, which is connected to other VCTRLP voltage terminals; the sources of the fourteenth MOS transistor M14 and the sixteenth MOS transistor M16 are both grounded GND.

[0017] Beneficial effects of the present invention:

[0018] The high-speed rail-to-rail self-biased voltage follower circuit of the present invention can achieve high-frequency precise voltage following and is no longer limited by the performance of the operational amplifier; it can achieve rail-to-rail voltage input and output tracking without threshold loss; in addition, since a self-biased structure is used to provide a bias voltage for the input circuit, this circuit does not need to provide an additional bias voltage and can operate in circuits where the power supply voltage and ground voltage fluctuate rapidly. Therefore, the present invention can be widely used in various scenarios of DC / DC converters and isolated drive circuits.

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a unity-gain voltage follower composed of a second-order op amp clamp, which is commonly used in current DC / DC technology.

[0021] Figure 2 An overall circuit diagram of a high-speed rail-to-rail self-biased voltage follower circuit provided by an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of actual operation simulation of the high-speed rail-to-rail self-biased voltage follower circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0024] like Figure 1 As shown, Figure 1 This is a unity-gain voltage follower composed of a second-order op amp clamp, commonly used in current DC / DC technology. Its working principle is to achieve high-precision following through the high gain of the op amp. The principle is as follows: when the input SENSE voltage increases, the current flowing through M5a decreases, and the current flowing through M4a increases. Since M4a and M5a have the same gate bias and the same on-resistance, the drain voltage of M5a decreases, causing the gate voltage of M6a to decrease, and the degree of M6a's opening to decrease. Therefore, the HOLD voltage increases, following the voltage change of SENSE, forming negative feedback. However, since the clamping performance of this circuit depends entirely on the gain and bandwidth of the op amp, it often does not have sufficient speed to follow changes in the input voltage when processing high-frequency changing signals. At the same time, the op amp has a range of input common-mode voltage. For PMOS input op amps, if the input common-mode voltage is too high, the op amp will fail, making it impossible to achieve voltage following. In addition, this circuit requires an external bias voltage. In the case of floating voltage levels, such as in SIBO circuits and isolated gate drive circuits, this structure cannot be used because it cannot generate a stable bias circuit for the floating voltage, which has limitations.

[0025] like Figure 2 As shown, the present invention provides a high-speed rail-to-rail self-biased voltage follower comprising: a PMOS input circuit, an NMOS input circuit, a voltage clamping and mutual biasing circuit; wherein the PMOS input circuit and the NMOS input circuit form a rail-to-rail complementary input; the voltage clamping and mutual biasing circuit provides an adaptive bias voltage, a clamping input, and an output voltage for the PMOS input circuit and the NMOS input circuit;

[0026] The PMOS input circuit is used for input voltage ranging from GND to VDD-2V THP When the input voltage is within the specified range, the regulating voltage is generated according to the voltage difference between the input voltage and the output voltage to adjust the working parameters or state of the component so that the input voltage is equal to the output voltage;

[0027] The NMOS input circuit is used for the input voltage at 2V THN When the input voltage reaches VDD, the regulated voltage is generated according to the voltage difference between the input voltage and the output voltage to adjust the operating parameters or state of the component so that the input voltage is equal to the output voltage.

[0028] The voltage clamping and mutual biasing circuit is used to maintain the output voltage always equal to the input voltage, and provide corresponding bias voltages for the PMOS input circuit and the NMOS input circuit respectively through its own current mirror;

[0029] Among them, V THP is the threshold voltage of the PMOS tube, V THN is the threshold voltage of the NMOS transistor. The threshold voltage is a fixed value when the parameters of the MOS transistor are determined.

[0030] The circuit components and connection methods of the invented high-speed rail-to-rail self-biased voltage follower circuit are described as follows:

[0031] The PMOS input circuit includes a first MOS transistor M1, a sixth MOS transistor M6, a seventh MOS transistor M7, a twelfth MOS transistor M12, and a thirteenth MOS transistor M13; the NMOS input circuit includes a second MOS transistor M2, a third MOS transistor M3, a fifth MOS transistor M5, an eighth MOS transistor M8, and an eleventh MOS transistor M11; the voltage clamping and mutual biasing circuit includes a fourth MOS transistor M4, a ninth MOS transistor M9, a tenth MOS transistor M10, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, and a sixteenth MOS transistor M16;

[0032] The source of the first MOS transistor M1, the source of the second MOS transistor M2, the source of the fourth MOS transistor M4 and the source of the ninth MOS transistor M9 are all connected to the input power supply terminal V DDThe source of the eleventh MOS transistor M11, the source of the twelfth MOS transistor M12, the source of the thirteenth MOS transistor M13, the source of the fourteenth MOS transistor M14 and the source of the sixteenth MOS transistor M16 are all connected to the ground end;

[0033] The gate of the first MOS transistor M1 is connected to the gate and drain of the fourth MOS transistor M4 and the source of the tenth MOS transistor M10; the drain of the first MOS transistor M1 is connected to the source of the sixth MOS transistor M6 and the source of the seventh MOS transistor M7; the gate of the second MOS transistor M2 is connected to the gate and drain of the third MOS transistor M3 and the drain of the eighth MOS transistor M8; the drain of the second MOS transistor M2 is connected to the drain of the fifth MOS transistor M5, the gate of the ninth MOS transistor M9, and the gate VCTRLN of the fifteenth MOS transistor M15; the gate of the fifth MOS transistor M5 is connected to the gate of the sixth MOS transistor M6 and the input terminal SENSE of the high-speed rail-to-rail self-bias voltage follower; the source of the fifth MOS transistor M5 is connected to the source of the eighth MOS transistor M8, the gate of the eleventh MOS transistor M9, and the gate VCTRLN of the fifteenth MOS transistor M15. The drain of the sixth MOS transistor M6 is connected to the drain of the twelfth MOS transistor M12, the gate of the tenth MOS transistor M10, and the gate VCTRLP of the sixteenth MOS transistor M16; the gate of the seventh MOS transistor M7 is connected to the gate of the eighth MOS transistor M8, the drain of the ninth MOS transistor M9, the drain of the tenth MOS transistor M10, the drain of the fifteenth MOS transistor M15, and the drain of the sixteenth MOS transistor M16, and is connected to the output terminal HOLD of the high-speed rail-to-rail self-bias voltage follower; the drain of the seventh MOS transistor M7 is connected to the gate of the twelfth MOS transistor M12, the gate and drain of the thirteenth MOS transistor M13; the gate of the eleventh MOS transistor M11 is connected to the gate and drain of the fourteenth MOS transistor M14, and the source of the fifteenth MOS transistor M15.

[0034] The overall principle of the high-speed rail-to-rail self-biased voltage follower circuit of the present invention is described below:

[0035] M1, M6, M7, M12 and M13 form a PMOS input circuit for inputting GND to VDD-2V THP The input voltage generates a corresponding voltage response. After the circuit is powered on, when the input voltage is GND to VDD-2V THPWhen M6 and M7 are within the normal operating range, a corresponding voltage is generated at the drain of M12 based on the voltage values of SENSE and HOLD, which in turn adjusts the gate voltages of M10 and M16, thereby changing the magnitude of the HOLD voltage and forcing HOLD to equal SENSE. Taking the case where SENSE is greater than HOLD as an example, the current flowing through M7 is greater than the current of M6, so the voltage of VCTRLP decreases, and thus the gate voltages of M16 and M10 decrease. The open degree of M16 decreases, and the open degree of M10 increases, causing VHOLD to rise and gradually approach SENSE, forming a negative feedback.

[0036] M2, M3, M5, M8 and M11 form an NMOS input circuit for inputting 2V THN The input voltage to VDD generates a corresponding voltage response. After the circuit is powered on, when the input voltage is 2V THN When the voltage of SENSE and HOLD is within the range of VDD, M5 and M8 are in the normal working range. The corresponding voltage is generated at the drain end of M2 according to the voltage value of SENSE and HOLD, and then the gate voltage of M9 and M15 is adjusted, thereby changing the size of HOLD voltage and forcing HOLD to be equal to SENSE. The analysis of negative feedback is the same as above.

[0037] M4, M9, M10, M14, M15, and M16 form a voltage clamp and mutual bias circuit to ensure that the output voltage HOLD is always equal to the input voltage SENSE. These circuits, through the output-stage MOS transistors M4 and M14, form a current mirror structure, providing corresponding bias voltages for the PMOS and NMOS input circuits, respectively. When the circuit is operating normally, M4, through a common diode connection, is always in the saturation region and provides a suitable operating voltage for M1. M14, through a common diode connection, is always in the saturation region and provides a suitable operating voltage for M11.

[0038] See Figure 3 , Figure 3 The schematic diagram of the actual working simulation comparison between the high-speed rail-to-rail self-biased voltage follower circuit provided in an embodiment of the present invention and the voltage follower based on a unity-gain operational amplifier and a non-rail-to-rail voltage follower is shown. The power supply voltage VDD is 5V and the ground level is 0V. It can be seen that for the rail-to-rail input voltage with high frequency changes, the voltage follower hold3 based on the unity-gain operational amplifier cannot quickly track the input voltage sense and cannot process the rail-to-rail input signal; the non-rail-to-rail voltage follower hold2 cannot process the rail-to-rail input voltage, and circuit failure may occur due to the input voltage exceeding the common-mode input range; while the high-speed rail-to-rail self-biased voltage follower circuit hold1 provided by the present invention can accurately and quickly follow the input voltage changes.

[0039] This example provides a high-speed rail-to-rail self-biased voltage follower, comprising a PMOS input circuit, an NMOS input circuit, a voltage clamp and mutual bias circuit, and a compensation circuit. This high-speed rail-to-rail self-biased voltage follower can accurately track input voltage changes at high speed to generate a rail-to-rail output signal. Its self-biasing design eliminates the need for an additional input bias voltage, reducing the complexity of voltage design. It can be widely used in single-inductor bipolar output or isolated gate drive circuits with rapidly changing positive and negative voltages or voltage rails, providing stable and accurate voltage tracking.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0041] Although the present application is described herein with reference to various embodiments, those skilled in the art will be able to understand and implement other variations of the disclosed embodiments in practicing the claimed application by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0042] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A high-speed rail-to-rail self-biased voltage follower, characterized in that: include: A PMOS input circuit, an NMOS input circuit, a voltage clamp and mutual bias circuit; wherein the PMOS input circuit and the NMOS input circuit form a rail-to-rail complementary input; the voltage clamp and mutual bias circuit provides an adaptive bias voltage, a clamp input, and an output voltage for the PMOS input circuit and the NMOS input circuit; The PMOS input circuit is used for input voltage ranging from GND to VDD-2V THP When the input voltage is within the specified range, the regulating voltage is generated according to the voltage difference between the input voltage and the output voltage to adjust the working parameters or state of the component so that the input voltage is equal to the output voltage; The NMOS input circuit is used for the input voltage at 2V THN When the input voltage reaches VDD, the regulated voltage is generated according to the voltage difference between the input voltage and the output voltage to adjust the operating parameters or state of the component so that the input voltage is equal to the output voltage. The voltage clamping and mutual biasing circuit is used to maintain the output voltage always equal to the input voltage, and provide corresponding bias voltages for the PMOS input circuit and the NMOS input circuit respectively through its own current mirror; Among them, V THP is the threshold voltage of the PMOS tube, V THN is the threshold voltage of the NMOS tube.

2. The high-speed rail-to-rail self-biased voltage follower according to claim 1, characterized in that: The PMOS input circuit comprises a first MOS transistor (M1), a sixth MOS transistor (M6), a seventh MOS transistor (M7), a twelfth MOS transistor (M12), and a thirteenth MOS transistor (M13); The source of the first MOS tube (M1) is connected to a power supply (VDD), the gate serves as a VPBLAS voltage terminal, which is connected to other VPBLAS voltage terminals, and the drain is connected to the drain of the sixth MOS tube (M6) and the source of the seventh MOS tube (M7); the gate of the sixth MOS tube (M6) serves as an input voltage terminal (SENSE), which is connected to other input voltage terminals (SENSE); the drain of the sixth MOS tube (M6) is connected to the drain of the thirteenth MOS tube (M13), and serves as a VCTRLP voltage terminal, which is connected to other VCTRLP voltage terminals; the gate of the seventh MOS tube (M7) serves as an output voltage terminal (HOLD), which is connected to other output voltage terminals (HOLD); the drain of the seventh MOS tube (M7) is connected to the gates of the twelfth MOS tube (M12) and the thirteenth MOS tube (M13); and the sources of the twelfth MOS tube (M12) and the thirteenth MOS tube (M13) are grounded (GND).

3. The high-speed rail-to-rail self-biased voltage follower according to claim 1, characterized in that: The NMOS input circuit includes a second MOS transistor (M2), a third MOS transistor (M3), a fifth MOS transistor (M5), an eighth MOS transistor (M8), and an eleventh MOS transistor (M11); The source of the second MOS tube (M2) and the source of the third MOS tube (M3) are both connected to the power supply (VDD); the gate of the second MOS tube (M2) is connected to the gate of the third MOS tube (M3), the drain of the third MOS tube (M3), and the drain of the fifth MOS tube (M5); the drain of the third MOS tube (M3) serves as a VCTRLN voltage terminal and is connected to other VCTRLN voltage terminals; The drain of the third MOS tube (M3) is connected to the drain of the eighth MOS tube (M8); the source of the fifth MOS tube (M5) and the source of the eighth MOS tube (M8) are both connected to the drain of the eleventh MOS tube (M11); the gate of the fifth MOS tube (M5) serves as an output voltage terminal (HOLD), which is connected to other output voltage terminals (HOLD); the gate of the eighth MOS tube (M8) serves as an input voltage terminal (SENSE), which is connected to other input voltage terminals (SENSE); the source of the eleventh MOS tube (M11) is grounded (GND), and the gate serves as a VNBLAS voltage terminal, which is connected to other VNBLAS voltage terminals.

4. The high-speed rail-to-rail self-biased voltage follower according to claim 1, characterized in that: The voltage clamping and mutual biasing circuit includes a fourth MOS transistor (M4), a ninth MOS transistor (M9), a tenth MOS transistor (M10), a fourteenth MOS transistor (M14), a fifteenth MOS transistor (M15), and a sixteenth MOS transistor (M16); The gate and drain of the fourth MOS tube (M4) and the source of the tenth MOS tube (M10) are connected together and serve as a VPBLAS voltage terminal, which is connected to other VPBLAS voltage terminals; the source of the fourth MOS tube (M4) and the source of the ninth MOS tube (M9) are both connected to a power supply (VDD); the gate of the ninth MOS tube (M9) is connected to the gate of the fifteenth MOS tube (M15) and serves as a VCTRLN voltage terminal, which is connected to other VCTRLN voltage terminals; the drain of the ninth MOS tube (M9) is connected to the tenth MOS tube (M10) and serves as an output voltage. The source of the fifteenth MOS transistor (M15) is connected to the drain of the fourteenth MOS transistor (M14) and the gate of the fourteenth MOS transistor (M14), and serves as a VNBLAS voltage terminal, which is connected to other VNBLAS voltage terminals; the gate of the tenth MOS transistor (M10) is connected to the sixteenth MOS transistor (M16), and serves as a VCTRLP voltage terminal, which is connected to other VCTRLP voltage terminals; the sources of the fourteenth MOS transistor (M14) and the sixteenth MOS transistor (M16) are both grounded (GND).

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